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Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w21 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<21>, q : UInt<21>, flip en : UInt<1>}
reg cdc_reg : UInt<21>, clock
when io.en :
connect cdc_reg, io.d
connect io.q, cdc_reg | module ClockCrossingReg_w21( // @[SynchronizerReg.scala:191:7]
input clock, // @[SynchronizerReg.scala:191:7]
input reset, // @[SynchronizerReg.scala:191:7]
input [20:0] io_d, // @[SynchronizerReg.scala:195:14]
output [20:0] io_q, // @[SynchronizerReg.scala:195:14]
input io_en // @[SynchronizerReg.scala:195:14]
);
wire [20:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7]
wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7]
wire [20:0] io_q_0; // @[SynchronizerReg.scala:191:7]
reg [20:0] cdc_reg; // @[SynchronizerReg.scala:201:76]
assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge clock) begin // @[SynchronizerReg.scala:191:7]
if (io_en_0) // @[SynchronizerReg.scala:191:7]
cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge)
assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC :
input clock : Clock
input reset : Reset
output auto : { flip in_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}
invalidate nodeIn_1.e.bits.sink
invalidate nodeIn_1.e.valid
invalidate nodeIn_1.e.ready
invalidate nodeIn_1.d.bits.corrupt
invalidate nodeIn_1.d.bits.data
invalidate nodeIn_1.d.bits.denied
invalidate nodeIn_1.d.bits.sink
invalidate nodeIn_1.d.bits.source
invalidate nodeIn_1.d.bits.size
invalidate nodeIn_1.d.bits.param
invalidate nodeIn_1.d.bits.opcode
invalidate nodeIn_1.d.valid
invalidate nodeIn_1.d.ready
invalidate nodeIn_1.c.bits.corrupt
invalidate nodeIn_1.c.bits.data
invalidate nodeIn_1.c.bits.address
invalidate nodeIn_1.c.bits.source
invalidate nodeIn_1.c.bits.size
invalidate nodeIn_1.c.bits.param
invalidate nodeIn_1.c.bits.opcode
invalidate nodeIn_1.c.valid
invalidate nodeIn_1.c.ready
invalidate nodeIn_1.b.bits.corrupt
invalidate nodeIn_1.b.bits.data
invalidate nodeIn_1.b.bits.mask
invalidate nodeIn_1.b.bits.address
invalidate nodeIn_1.b.bits.source
invalidate nodeIn_1.b.bits.size
invalidate nodeIn_1.b.bits.param
invalidate nodeIn_1.b.bits.opcode
invalidate nodeIn_1.b.valid
invalidate nodeIn_1.b.ready
invalidate nodeIn_1.a.bits.corrupt
invalidate nodeIn_1.a.bits.data
invalidate nodeIn_1.a.bits.mask
invalidate nodeIn_1.a.bits.address
invalidate nodeIn_1.a.bits.source
invalidate nodeIn_1.a.bits.size
invalidate nodeIn_1.a.bits.param
invalidate nodeIn_1.a.bits.opcode
invalidate nodeIn_1.a.valid
invalidate nodeIn_1.a.ready
wire nodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}
invalidate nodeIn_2.e.bits.sink
invalidate nodeIn_2.e.valid
invalidate nodeIn_2.e.ready
invalidate nodeIn_2.d.bits.corrupt
invalidate nodeIn_2.d.bits.data
invalidate nodeIn_2.d.bits.denied
invalidate nodeIn_2.d.bits.sink
invalidate nodeIn_2.d.bits.source
invalidate nodeIn_2.d.bits.size
invalidate nodeIn_2.d.bits.param
invalidate nodeIn_2.d.bits.opcode
invalidate nodeIn_2.d.valid
invalidate nodeIn_2.d.ready
invalidate nodeIn_2.c.bits.corrupt
invalidate nodeIn_2.c.bits.data
invalidate nodeIn_2.c.bits.address
invalidate nodeIn_2.c.bits.source
invalidate nodeIn_2.c.bits.size
invalidate nodeIn_2.c.bits.param
invalidate nodeIn_2.c.bits.opcode
invalidate nodeIn_2.c.valid
invalidate nodeIn_2.c.ready
invalidate nodeIn_2.b.bits.corrupt
invalidate nodeIn_2.b.bits.data
invalidate nodeIn_2.b.bits.mask
invalidate nodeIn_2.b.bits.address
invalidate nodeIn_2.b.bits.source
invalidate nodeIn_2.b.bits.size
invalidate nodeIn_2.b.bits.param
invalidate nodeIn_2.b.bits.opcode
invalidate nodeIn_2.b.valid
invalidate nodeIn_2.b.ready
invalidate nodeIn_2.a.bits.corrupt
invalidate nodeIn_2.a.bits.data
invalidate nodeIn_2.a.bits.mask
invalidate nodeIn_2.a.bits.address
invalidate nodeIn_2.a.bits.source
invalidate nodeIn_2.a.bits.size
invalidate nodeIn_2.a.bits.param
invalidate nodeIn_2.a.bits.opcode
invalidate nodeIn_2.a.valid
invalidate nodeIn_2.a.ready
wire nodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}
invalidate nodeIn_3.e.bits.sink
invalidate nodeIn_3.e.valid
invalidate nodeIn_3.e.ready
invalidate nodeIn_3.d.bits.corrupt
invalidate nodeIn_3.d.bits.data
invalidate nodeIn_3.d.bits.denied
invalidate nodeIn_3.d.bits.sink
invalidate nodeIn_3.d.bits.source
invalidate nodeIn_3.d.bits.size
invalidate nodeIn_3.d.bits.param
invalidate nodeIn_3.d.bits.opcode
invalidate nodeIn_3.d.valid
invalidate nodeIn_3.d.ready
invalidate nodeIn_3.c.bits.corrupt
invalidate nodeIn_3.c.bits.data
invalidate nodeIn_3.c.bits.address
invalidate nodeIn_3.c.bits.source
invalidate nodeIn_3.c.bits.size
invalidate nodeIn_3.c.bits.param
invalidate nodeIn_3.c.bits.opcode
invalidate nodeIn_3.c.valid
invalidate nodeIn_3.c.ready
invalidate nodeIn_3.b.bits.corrupt
invalidate nodeIn_3.b.bits.data
invalidate nodeIn_3.b.bits.mask
invalidate nodeIn_3.b.bits.address
invalidate nodeIn_3.b.bits.source
invalidate nodeIn_3.b.bits.size
invalidate nodeIn_3.b.bits.param
invalidate nodeIn_3.b.bits.opcode
invalidate nodeIn_3.b.valid
invalidate nodeIn_3.b.ready
invalidate nodeIn_3.a.bits.corrupt
invalidate nodeIn_3.a.bits.data
invalidate nodeIn_3.a.bits.mask
invalidate nodeIn_3.a.bits.address
invalidate nodeIn_3.a.bits.source
invalidate nodeIn_3.a.bits.size
invalidate nodeIn_3.a.bits.param
invalidate nodeIn_3.a.bits.opcode
invalidate nodeIn_3.a.valid
invalidate nodeIn_3.a.ready
wire nodeIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}
invalidate nodeIn_4.e.bits.sink
invalidate nodeIn_4.e.valid
invalidate nodeIn_4.e.ready
invalidate nodeIn_4.d.bits.corrupt
invalidate nodeIn_4.d.bits.data
invalidate nodeIn_4.d.bits.denied
invalidate nodeIn_4.d.bits.sink
invalidate nodeIn_4.d.bits.source
invalidate nodeIn_4.d.bits.size
invalidate nodeIn_4.d.bits.param
invalidate nodeIn_4.d.bits.opcode
invalidate nodeIn_4.d.valid
invalidate nodeIn_4.d.ready
invalidate nodeIn_4.c.bits.corrupt
invalidate nodeIn_4.c.bits.data
invalidate nodeIn_4.c.bits.address
invalidate nodeIn_4.c.bits.source
invalidate nodeIn_4.c.bits.size
invalidate nodeIn_4.c.bits.param
invalidate nodeIn_4.c.bits.opcode
invalidate nodeIn_4.c.valid
invalidate nodeIn_4.c.ready
invalidate nodeIn_4.b.bits.corrupt
invalidate nodeIn_4.b.bits.data
invalidate nodeIn_4.b.bits.mask
invalidate nodeIn_4.b.bits.address
invalidate nodeIn_4.b.bits.source
invalidate nodeIn_4.b.bits.size
invalidate nodeIn_4.b.bits.param
invalidate nodeIn_4.b.bits.opcode
invalidate nodeIn_4.b.valid
invalidate nodeIn_4.b.ready
invalidate nodeIn_4.a.bits.corrupt
invalidate nodeIn_4.a.bits.data
invalidate nodeIn_4.a.bits.mask
invalidate nodeIn_4.a.bits.address
invalidate nodeIn_4.a.bits.source
invalidate nodeIn_4.a.bits.size
invalidate nodeIn_4.a.bits.param
invalidate nodeIn_4.a.bits.opcode
invalidate nodeIn_4.a.valid
invalidate nodeIn_4.a.ready
inst monitor of TLMonitor
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
inst monitor_1 of TLMonitor_1
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.e.bits.sink, nodeIn_1.e.bits.sink
connect monitor_1.io.in.e.valid, nodeIn_1.e.valid
connect monitor_1.io.in.e.ready, nodeIn_1.e.ready
connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, nodeIn_1.d.valid
connect monitor_1.io.in.d.ready, nodeIn_1.d.ready
connect monitor_1.io.in.c.bits.corrupt, nodeIn_1.c.bits.corrupt
connect monitor_1.io.in.c.bits.data, nodeIn_1.c.bits.data
connect monitor_1.io.in.c.bits.address, nodeIn_1.c.bits.address
connect monitor_1.io.in.c.bits.source, nodeIn_1.c.bits.source
connect monitor_1.io.in.c.bits.size, nodeIn_1.c.bits.size
connect monitor_1.io.in.c.bits.param, nodeIn_1.c.bits.param
connect monitor_1.io.in.c.bits.opcode, nodeIn_1.c.bits.opcode
connect monitor_1.io.in.c.valid, nodeIn_1.c.valid
connect monitor_1.io.in.c.ready, nodeIn_1.c.ready
connect monitor_1.io.in.b.bits.corrupt, nodeIn_1.b.bits.corrupt
connect monitor_1.io.in.b.bits.data, nodeIn_1.b.bits.data
connect monitor_1.io.in.b.bits.mask, nodeIn_1.b.bits.mask
connect monitor_1.io.in.b.bits.address, nodeIn_1.b.bits.address
connect monitor_1.io.in.b.bits.source, nodeIn_1.b.bits.source
connect monitor_1.io.in.b.bits.size, nodeIn_1.b.bits.size
connect monitor_1.io.in.b.bits.param, nodeIn_1.b.bits.param
connect monitor_1.io.in.b.bits.opcode, nodeIn_1.b.bits.opcode
connect monitor_1.io.in.b.valid, nodeIn_1.b.valid
connect monitor_1.io.in.b.ready, nodeIn_1.b.ready
connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, nodeIn_1.a.valid
connect monitor_1.io.in.a.ready, nodeIn_1.a.ready
inst monitor_2 of TLMonitor_2
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.e.bits.sink, nodeIn_2.e.bits.sink
connect monitor_2.io.in.e.valid, nodeIn_2.e.valid
connect monitor_2.io.in.e.ready, nodeIn_2.e.ready
connect monitor_2.io.in.d.bits.corrupt, nodeIn_2.d.bits.corrupt
connect monitor_2.io.in.d.bits.data, nodeIn_2.d.bits.data
connect monitor_2.io.in.d.bits.denied, nodeIn_2.d.bits.denied
connect monitor_2.io.in.d.bits.sink, nodeIn_2.d.bits.sink
connect monitor_2.io.in.d.bits.source, nodeIn_2.d.bits.source
connect monitor_2.io.in.d.bits.size, nodeIn_2.d.bits.size
connect monitor_2.io.in.d.bits.param, nodeIn_2.d.bits.param
connect monitor_2.io.in.d.bits.opcode, nodeIn_2.d.bits.opcode
connect monitor_2.io.in.d.valid, nodeIn_2.d.valid
connect monitor_2.io.in.d.ready, nodeIn_2.d.ready
connect monitor_2.io.in.c.bits.corrupt, nodeIn_2.c.bits.corrupt
connect monitor_2.io.in.c.bits.data, nodeIn_2.c.bits.data
connect monitor_2.io.in.c.bits.address, nodeIn_2.c.bits.address
connect monitor_2.io.in.c.bits.source, nodeIn_2.c.bits.source
connect monitor_2.io.in.c.bits.size, nodeIn_2.c.bits.size
connect monitor_2.io.in.c.bits.param, nodeIn_2.c.bits.param
connect monitor_2.io.in.c.bits.opcode, nodeIn_2.c.bits.opcode
connect monitor_2.io.in.c.valid, nodeIn_2.c.valid
connect monitor_2.io.in.c.ready, nodeIn_2.c.ready
connect monitor_2.io.in.b.bits.corrupt, nodeIn_2.b.bits.corrupt
connect monitor_2.io.in.b.bits.data, nodeIn_2.b.bits.data
connect monitor_2.io.in.b.bits.mask, nodeIn_2.b.bits.mask
connect monitor_2.io.in.b.bits.address, nodeIn_2.b.bits.address
connect monitor_2.io.in.b.bits.source, nodeIn_2.b.bits.source
connect monitor_2.io.in.b.bits.size, nodeIn_2.b.bits.size
connect monitor_2.io.in.b.bits.param, nodeIn_2.b.bits.param
connect monitor_2.io.in.b.bits.opcode, nodeIn_2.b.bits.opcode
connect monitor_2.io.in.b.valid, nodeIn_2.b.valid
connect monitor_2.io.in.b.ready, nodeIn_2.b.ready
connect monitor_2.io.in.a.bits.corrupt, nodeIn_2.a.bits.corrupt
connect monitor_2.io.in.a.bits.data, nodeIn_2.a.bits.data
connect monitor_2.io.in.a.bits.mask, nodeIn_2.a.bits.mask
connect monitor_2.io.in.a.bits.address, nodeIn_2.a.bits.address
connect monitor_2.io.in.a.bits.source, nodeIn_2.a.bits.source
connect monitor_2.io.in.a.bits.size, nodeIn_2.a.bits.size
connect monitor_2.io.in.a.bits.param, nodeIn_2.a.bits.param
connect monitor_2.io.in.a.bits.opcode, nodeIn_2.a.bits.opcode
connect monitor_2.io.in.a.valid, nodeIn_2.a.valid
connect monitor_2.io.in.a.ready, nodeIn_2.a.ready
inst monitor_3 of TLMonitor_3
connect monitor_3.clock, clock
connect monitor_3.reset, reset
connect monitor_3.io.in.e.bits.sink, nodeIn_3.e.bits.sink
connect monitor_3.io.in.e.valid, nodeIn_3.e.valid
connect monitor_3.io.in.e.ready, nodeIn_3.e.ready
connect monitor_3.io.in.d.bits.corrupt, nodeIn_3.d.bits.corrupt
connect monitor_3.io.in.d.bits.data, nodeIn_3.d.bits.data
connect monitor_3.io.in.d.bits.denied, nodeIn_3.d.bits.denied
connect monitor_3.io.in.d.bits.sink, nodeIn_3.d.bits.sink
connect monitor_3.io.in.d.bits.source, nodeIn_3.d.bits.source
connect monitor_3.io.in.d.bits.size, nodeIn_3.d.bits.size
connect monitor_3.io.in.d.bits.param, nodeIn_3.d.bits.param
connect monitor_3.io.in.d.bits.opcode, nodeIn_3.d.bits.opcode
connect monitor_3.io.in.d.valid, nodeIn_3.d.valid
connect monitor_3.io.in.d.ready, nodeIn_3.d.ready
connect monitor_3.io.in.c.bits.corrupt, nodeIn_3.c.bits.corrupt
connect monitor_3.io.in.c.bits.data, nodeIn_3.c.bits.data
connect monitor_3.io.in.c.bits.address, nodeIn_3.c.bits.address
connect monitor_3.io.in.c.bits.source, nodeIn_3.c.bits.source
connect monitor_3.io.in.c.bits.size, nodeIn_3.c.bits.size
connect monitor_3.io.in.c.bits.param, nodeIn_3.c.bits.param
connect monitor_3.io.in.c.bits.opcode, nodeIn_3.c.bits.opcode
connect monitor_3.io.in.c.valid, nodeIn_3.c.valid
connect monitor_3.io.in.c.ready, nodeIn_3.c.ready
connect monitor_3.io.in.b.bits.corrupt, nodeIn_3.b.bits.corrupt
connect monitor_3.io.in.b.bits.data, nodeIn_3.b.bits.data
connect monitor_3.io.in.b.bits.mask, nodeIn_3.b.bits.mask
connect monitor_3.io.in.b.bits.address, nodeIn_3.b.bits.address
connect monitor_3.io.in.b.bits.source, nodeIn_3.b.bits.source
connect monitor_3.io.in.b.bits.size, nodeIn_3.b.bits.size
connect monitor_3.io.in.b.bits.param, nodeIn_3.b.bits.param
connect monitor_3.io.in.b.bits.opcode, nodeIn_3.b.bits.opcode
connect monitor_3.io.in.b.valid, nodeIn_3.b.valid
connect monitor_3.io.in.b.ready, nodeIn_3.b.ready
connect monitor_3.io.in.a.bits.corrupt, nodeIn_3.a.bits.corrupt
connect monitor_3.io.in.a.bits.data, nodeIn_3.a.bits.data
connect monitor_3.io.in.a.bits.mask, nodeIn_3.a.bits.mask
connect monitor_3.io.in.a.bits.address, nodeIn_3.a.bits.address
connect monitor_3.io.in.a.bits.source, nodeIn_3.a.bits.source
connect monitor_3.io.in.a.bits.size, nodeIn_3.a.bits.size
connect monitor_3.io.in.a.bits.param, nodeIn_3.a.bits.param
connect monitor_3.io.in.a.bits.opcode, nodeIn_3.a.bits.opcode
connect monitor_3.io.in.a.valid, nodeIn_3.a.valid
connect monitor_3.io.in.a.ready, nodeIn_3.a.ready
inst monitor_4 of TLMonitor_4
connect monitor_4.clock, clock
connect monitor_4.reset, reset
connect monitor_4.io.in.e.bits.sink, nodeIn_4.e.bits.sink
connect monitor_4.io.in.e.valid, nodeIn_4.e.valid
connect monitor_4.io.in.e.ready, nodeIn_4.e.ready
connect monitor_4.io.in.d.bits.corrupt, nodeIn_4.d.bits.corrupt
connect monitor_4.io.in.d.bits.data, nodeIn_4.d.bits.data
connect monitor_4.io.in.d.bits.denied, nodeIn_4.d.bits.denied
connect monitor_4.io.in.d.bits.sink, nodeIn_4.d.bits.sink
connect monitor_4.io.in.d.bits.source, nodeIn_4.d.bits.source
connect monitor_4.io.in.d.bits.size, nodeIn_4.d.bits.size
connect monitor_4.io.in.d.bits.param, nodeIn_4.d.bits.param
connect monitor_4.io.in.d.bits.opcode, nodeIn_4.d.bits.opcode
connect monitor_4.io.in.d.valid, nodeIn_4.d.valid
connect monitor_4.io.in.d.ready, nodeIn_4.d.ready
connect monitor_4.io.in.c.bits.corrupt, nodeIn_4.c.bits.corrupt
connect monitor_4.io.in.c.bits.data, nodeIn_4.c.bits.data
connect monitor_4.io.in.c.bits.address, nodeIn_4.c.bits.address
connect monitor_4.io.in.c.bits.source, nodeIn_4.c.bits.source
connect monitor_4.io.in.c.bits.size, nodeIn_4.c.bits.size
connect monitor_4.io.in.c.bits.param, nodeIn_4.c.bits.param
connect monitor_4.io.in.c.bits.opcode, nodeIn_4.c.bits.opcode
connect monitor_4.io.in.c.valid, nodeIn_4.c.valid
connect monitor_4.io.in.c.ready, nodeIn_4.c.ready
connect monitor_4.io.in.b.bits.corrupt, nodeIn_4.b.bits.corrupt
connect monitor_4.io.in.b.bits.data, nodeIn_4.b.bits.data
connect monitor_4.io.in.b.bits.mask, nodeIn_4.b.bits.mask
connect monitor_4.io.in.b.bits.address, nodeIn_4.b.bits.address
connect monitor_4.io.in.b.bits.source, nodeIn_4.b.bits.source
connect monitor_4.io.in.b.bits.size, nodeIn_4.b.bits.size
connect monitor_4.io.in.b.bits.param, nodeIn_4.b.bits.param
connect monitor_4.io.in.b.bits.opcode, nodeIn_4.b.bits.opcode
connect monitor_4.io.in.b.valid, nodeIn_4.b.valid
connect monitor_4.io.in.b.ready, nodeIn_4.b.ready
connect monitor_4.io.in.a.bits.corrupt, nodeIn_4.a.bits.corrupt
connect monitor_4.io.in.a.bits.data, nodeIn_4.a.bits.data
connect monitor_4.io.in.a.bits.mask, nodeIn_4.a.bits.mask
connect monitor_4.io.in.a.bits.address, nodeIn_4.a.bits.address
connect monitor_4.io.in.a.bits.source, nodeIn_4.a.bits.source
connect monitor_4.io.in.a.bits.size, nodeIn_4.a.bits.size
connect monitor_4.io.in.a.bits.param, nodeIn_4.a.bits.param
connect monitor_4.io.in.a.bits.opcode, nodeIn_4.a.bits.opcode
connect monitor_4.io.in.a.valid, nodeIn_4.a.valid
connect monitor_4.io.in.a.ready, nodeIn_4.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate x1_nodeOut.e.bits.sink
invalidate x1_nodeOut.e.valid
invalidate x1_nodeOut.e.ready
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.c.bits.corrupt
invalidate x1_nodeOut.c.bits.data
invalidate x1_nodeOut.c.bits.address
invalidate x1_nodeOut.c.bits.source
invalidate x1_nodeOut.c.bits.size
invalidate x1_nodeOut.c.bits.param
invalidate x1_nodeOut.c.bits.opcode
invalidate x1_nodeOut.c.valid
invalidate x1_nodeOut.c.ready
invalidate x1_nodeOut.b.bits.corrupt
invalidate x1_nodeOut.b.bits.data
invalidate x1_nodeOut.b.bits.mask
invalidate x1_nodeOut.b.bits.address
invalidate x1_nodeOut.b.bits.source
invalidate x1_nodeOut.b.bits.size
invalidate x1_nodeOut.b.bits.param
invalidate x1_nodeOut.b.bits.opcode
invalidate x1_nodeOut.b.valid
invalidate x1_nodeOut.b.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
wire x1_nodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate x1_nodeOut_1.e.bits.sink
invalidate x1_nodeOut_1.e.valid
invalidate x1_nodeOut_1.e.ready
invalidate x1_nodeOut_1.d.bits.corrupt
invalidate x1_nodeOut_1.d.bits.data
invalidate x1_nodeOut_1.d.bits.denied
invalidate x1_nodeOut_1.d.bits.sink
invalidate x1_nodeOut_1.d.bits.source
invalidate x1_nodeOut_1.d.bits.size
invalidate x1_nodeOut_1.d.bits.param
invalidate x1_nodeOut_1.d.bits.opcode
invalidate x1_nodeOut_1.d.valid
invalidate x1_nodeOut_1.d.ready
invalidate x1_nodeOut_1.c.bits.corrupt
invalidate x1_nodeOut_1.c.bits.data
invalidate x1_nodeOut_1.c.bits.address
invalidate x1_nodeOut_1.c.bits.source
invalidate x1_nodeOut_1.c.bits.size
invalidate x1_nodeOut_1.c.bits.param
invalidate x1_nodeOut_1.c.bits.opcode
invalidate x1_nodeOut_1.c.valid
invalidate x1_nodeOut_1.c.ready
invalidate x1_nodeOut_1.b.bits.corrupt
invalidate x1_nodeOut_1.b.bits.data
invalidate x1_nodeOut_1.b.bits.mask
invalidate x1_nodeOut_1.b.bits.address
invalidate x1_nodeOut_1.b.bits.source
invalidate x1_nodeOut_1.b.bits.size
invalidate x1_nodeOut_1.b.bits.param
invalidate x1_nodeOut_1.b.bits.opcode
invalidate x1_nodeOut_1.b.valid
invalidate x1_nodeOut_1.b.ready
invalidate x1_nodeOut_1.a.bits.corrupt
invalidate x1_nodeOut_1.a.bits.data
invalidate x1_nodeOut_1.a.bits.mask
invalidate x1_nodeOut_1.a.bits.address
invalidate x1_nodeOut_1.a.bits.source
invalidate x1_nodeOut_1.a.bits.size
invalidate x1_nodeOut_1.a.bits.param
invalidate x1_nodeOut_1.a.bits.opcode
invalidate x1_nodeOut_1.a.valid
invalidate x1_nodeOut_1.a.ready
wire x1_nodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate x1_nodeOut_2.e.bits.sink
invalidate x1_nodeOut_2.e.valid
invalidate x1_nodeOut_2.e.ready
invalidate x1_nodeOut_2.d.bits.corrupt
invalidate x1_nodeOut_2.d.bits.data
invalidate x1_nodeOut_2.d.bits.denied
invalidate x1_nodeOut_2.d.bits.sink
invalidate x1_nodeOut_2.d.bits.source
invalidate x1_nodeOut_2.d.bits.size
invalidate x1_nodeOut_2.d.bits.param
invalidate x1_nodeOut_2.d.bits.opcode
invalidate x1_nodeOut_2.d.valid
invalidate x1_nodeOut_2.d.ready
invalidate x1_nodeOut_2.c.bits.corrupt
invalidate x1_nodeOut_2.c.bits.data
invalidate x1_nodeOut_2.c.bits.address
invalidate x1_nodeOut_2.c.bits.source
invalidate x1_nodeOut_2.c.bits.size
invalidate x1_nodeOut_2.c.bits.param
invalidate x1_nodeOut_2.c.bits.opcode
invalidate x1_nodeOut_2.c.valid
invalidate x1_nodeOut_2.c.ready
invalidate x1_nodeOut_2.b.bits.corrupt
invalidate x1_nodeOut_2.b.bits.data
invalidate x1_nodeOut_2.b.bits.mask
invalidate x1_nodeOut_2.b.bits.address
invalidate x1_nodeOut_2.b.bits.source
invalidate x1_nodeOut_2.b.bits.size
invalidate x1_nodeOut_2.b.bits.param
invalidate x1_nodeOut_2.b.bits.opcode
invalidate x1_nodeOut_2.b.valid
invalidate x1_nodeOut_2.b.ready
invalidate x1_nodeOut_2.a.bits.corrupt
invalidate x1_nodeOut_2.a.bits.data
invalidate x1_nodeOut_2.a.bits.mask
invalidate x1_nodeOut_2.a.bits.address
invalidate x1_nodeOut_2.a.bits.source
invalidate x1_nodeOut_2.a.bits.size
invalidate x1_nodeOut_2.a.bits.param
invalidate x1_nodeOut_2.a.bits.opcode
invalidate x1_nodeOut_2.a.valid
invalidate x1_nodeOut_2.a.ready
wire x1_nodeOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate x1_nodeOut_3.e.bits.sink
invalidate x1_nodeOut_3.e.valid
invalidate x1_nodeOut_3.e.ready
invalidate x1_nodeOut_3.d.bits.corrupt
invalidate x1_nodeOut_3.d.bits.data
invalidate x1_nodeOut_3.d.bits.denied
invalidate x1_nodeOut_3.d.bits.sink
invalidate x1_nodeOut_3.d.bits.source
invalidate x1_nodeOut_3.d.bits.size
invalidate x1_nodeOut_3.d.bits.param
invalidate x1_nodeOut_3.d.bits.opcode
invalidate x1_nodeOut_3.d.valid
invalidate x1_nodeOut_3.d.ready
invalidate x1_nodeOut_3.c.bits.corrupt
invalidate x1_nodeOut_3.c.bits.data
invalidate x1_nodeOut_3.c.bits.address
invalidate x1_nodeOut_3.c.bits.source
invalidate x1_nodeOut_3.c.bits.size
invalidate x1_nodeOut_3.c.bits.param
invalidate x1_nodeOut_3.c.bits.opcode
invalidate x1_nodeOut_3.c.valid
invalidate x1_nodeOut_3.c.ready
invalidate x1_nodeOut_3.b.bits.corrupt
invalidate x1_nodeOut_3.b.bits.data
invalidate x1_nodeOut_3.b.bits.mask
invalidate x1_nodeOut_3.b.bits.address
invalidate x1_nodeOut_3.b.bits.source
invalidate x1_nodeOut_3.b.bits.size
invalidate x1_nodeOut_3.b.bits.param
invalidate x1_nodeOut_3.b.bits.opcode
invalidate x1_nodeOut_3.b.valid
invalidate x1_nodeOut_3.b.ready
invalidate x1_nodeOut_3.a.bits.corrupt
invalidate x1_nodeOut_3.a.bits.data
invalidate x1_nodeOut_3.a.bits.mask
invalidate x1_nodeOut_3.a.bits.address
invalidate x1_nodeOut_3.a.bits.source
invalidate x1_nodeOut_3.a.bits.size
invalidate x1_nodeOut_3.a.bits.param
invalidate x1_nodeOut_3.a.bits.opcode
invalidate x1_nodeOut_3.a.valid
invalidate x1_nodeOut_3.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect auto.out_2, x1_nodeOut_1
connect auto.out_3, x1_nodeOut_2
connect auto.out_4, x1_nodeOut_3
connect nodeIn, auto.in_0
connect nodeIn_1, auto.in_1
connect nodeIn_2, auto.in_2
connect nodeIn_3, auto.in_3
connect nodeIn_4, auto.in_4
inst noc of ProtocolNoC
connect noc.clock, clock
connect noc.reset, reset
connect noc.io.protocol.`0`.in.`0`, nodeIn
connect noc.io.protocol.`0`.in.`1`, nodeIn_1
connect noc.io.protocol.`0`.in.`2`, nodeIn_2
connect noc.io.protocol.`0`.in.`3`, nodeIn_3
connect noc.io.protocol.`0`.in.`4`, nodeIn_4
connect noc.io.protocol.`0`.out.`0`.d, nodeOut.d
connect nodeOut.a.bits, noc.io.protocol.`0`.out.`0`.a.bits
connect nodeOut.a.valid, noc.io.protocol.`0`.out.`0`.a.valid
connect noc.io.protocol.`0`.out.`0`.a.ready, nodeOut.a.ready
connect x1_nodeOut.e.bits, noc.io.protocol.`0`.out.`1`.e.bits
connect x1_nodeOut.e.valid, noc.io.protocol.`0`.out.`1`.e.valid
connect noc.io.protocol.`0`.out.`1`.e.ready, x1_nodeOut.e.ready
connect noc.io.protocol.`0`.out.`1`.d, x1_nodeOut.d
connect x1_nodeOut.c.bits, noc.io.protocol.`0`.out.`1`.c.bits
connect x1_nodeOut.c.valid, noc.io.protocol.`0`.out.`1`.c.valid
connect noc.io.protocol.`0`.out.`1`.c.ready, x1_nodeOut.c.ready
connect noc.io.protocol.`0`.out.`1`.b, x1_nodeOut.b
connect x1_nodeOut.a.bits, noc.io.protocol.`0`.out.`1`.a.bits
connect x1_nodeOut.a.valid, noc.io.protocol.`0`.out.`1`.a.valid
connect noc.io.protocol.`0`.out.`1`.a.ready, x1_nodeOut.a.ready
connect x1_nodeOut_1.e.bits, noc.io.protocol.`0`.out.`2`.e.bits
connect x1_nodeOut_1.e.valid, noc.io.protocol.`0`.out.`2`.e.valid
connect noc.io.protocol.`0`.out.`2`.e.ready, x1_nodeOut_1.e.ready
connect noc.io.protocol.`0`.out.`2`.d, x1_nodeOut_1.d
connect x1_nodeOut_1.c.bits, noc.io.protocol.`0`.out.`2`.c.bits
connect x1_nodeOut_1.c.valid, noc.io.protocol.`0`.out.`2`.c.valid
connect noc.io.protocol.`0`.out.`2`.c.ready, x1_nodeOut_1.c.ready
connect noc.io.protocol.`0`.out.`2`.b, x1_nodeOut_1.b
connect x1_nodeOut_1.a.bits, noc.io.protocol.`0`.out.`2`.a.bits
connect x1_nodeOut_1.a.valid, noc.io.protocol.`0`.out.`2`.a.valid
connect noc.io.protocol.`0`.out.`2`.a.ready, x1_nodeOut_1.a.ready
connect x1_nodeOut_2.e.bits, noc.io.protocol.`0`.out.`3`.e.bits
connect x1_nodeOut_2.e.valid, noc.io.protocol.`0`.out.`3`.e.valid
connect noc.io.protocol.`0`.out.`3`.e.ready, x1_nodeOut_2.e.ready
connect noc.io.protocol.`0`.out.`3`.d, x1_nodeOut_2.d
connect x1_nodeOut_2.c.bits, noc.io.protocol.`0`.out.`3`.c.bits
connect x1_nodeOut_2.c.valid, noc.io.protocol.`0`.out.`3`.c.valid
connect noc.io.protocol.`0`.out.`3`.c.ready, x1_nodeOut_2.c.ready
connect noc.io.protocol.`0`.out.`3`.b, x1_nodeOut_2.b
connect x1_nodeOut_2.a.bits, noc.io.protocol.`0`.out.`3`.a.bits
connect x1_nodeOut_2.a.valid, noc.io.protocol.`0`.out.`3`.a.valid
connect noc.io.protocol.`0`.out.`3`.a.ready, x1_nodeOut_2.a.ready
connect x1_nodeOut_3.e.bits, noc.io.protocol.`0`.out.`4`.e.bits
connect x1_nodeOut_3.e.valid, noc.io.protocol.`0`.out.`4`.e.valid
connect noc.io.protocol.`0`.out.`4`.e.ready, x1_nodeOut_3.e.ready
connect noc.io.protocol.`0`.out.`4`.d, x1_nodeOut_3.d
connect x1_nodeOut_3.c.bits, noc.io.protocol.`0`.out.`4`.c.bits
connect x1_nodeOut_3.c.valid, noc.io.protocol.`0`.out.`4`.c.valid
connect noc.io.protocol.`0`.out.`4`.c.ready, x1_nodeOut_3.c.ready
connect noc.io.protocol.`0`.out.`4`.b, x1_nodeOut_3.b
connect x1_nodeOut_3.a.bits, noc.io.protocol.`0`.out.`4`.a.bits
connect x1_nodeOut_3.a.valid, noc.io.protocol.`0`.out.`4`.a.valid
connect noc.io.protocol.`0`.out.`4`.a.ready, x1_nodeOut_3.a.ready | module TLNoC( // @[Tilelink.scala:546:25]
input clock, // @[Tilelink.scala:546:25]
input reset, // @[Tilelink.scala:546:25]
output auto_in_4_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_4_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_4_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_4_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_4_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_4_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_4_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_4_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_4_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_4_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_4_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_4_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_4_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_4_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_4_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_4_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_4_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_4_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_4_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_4_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_4_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_4_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_4_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_3_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_3_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_3_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_3_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_3_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_3_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_3_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_2_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_2_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_2_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_2_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_2_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_2_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_2_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_1_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_4_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_4_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_4_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_4_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_4_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_4_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_4_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_4_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_4_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_4_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_4_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_4_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_4_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_4_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_4_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_3_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_3_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_3_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_3_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_3_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_3_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_2_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_2_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_2_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_2_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_2_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_2_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _noc_io_protocol_0_in_4_a_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_4_b_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_4_b_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_4_b_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_4_b_bits_size; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_4_b_bits_source; // @[Tilelink.scala:561:21]
wire [31:0] _noc_io_protocol_0_in_4_b_bits_address; // @[Tilelink.scala:561:21]
wire [7:0] _noc_io_protocol_0_in_4_b_bits_mask; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_4_b_bits_corrupt; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_4_c_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_4_d_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_4_d_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_4_d_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_4_d_bits_size; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_4_d_bits_source; // @[Tilelink.scala:561:21]
wire [4:0] _noc_io_protocol_0_in_4_d_bits_sink; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_4_d_bits_denied; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_4_d_bits_corrupt; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_4_e_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_3_a_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_3_b_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_3_b_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_3_b_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_3_b_bits_size; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_3_b_bits_source; // @[Tilelink.scala:561:21]
wire [31:0] _noc_io_protocol_0_in_3_b_bits_address; // @[Tilelink.scala:561:21]
wire [7:0] _noc_io_protocol_0_in_3_b_bits_mask; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_3_b_bits_corrupt; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_3_c_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_3_d_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_3_d_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_3_d_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_3_d_bits_size; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_3_d_bits_source; // @[Tilelink.scala:561:21]
wire [4:0] _noc_io_protocol_0_in_3_d_bits_sink; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_3_d_bits_denied; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_3_d_bits_corrupt; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_3_e_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_2_a_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_2_b_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_2_b_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_2_b_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_2_b_bits_size; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_2_b_bits_source; // @[Tilelink.scala:561:21]
wire [31:0] _noc_io_protocol_0_in_2_b_bits_address; // @[Tilelink.scala:561:21]
wire [7:0] _noc_io_protocol_0_in_2_b_bits_mask; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_2_b_bits_corrupt; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_2_c_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_2_d_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_2_d_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_2_d_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_2_d_bits_size; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_2_d_bits_source; // @[Tilelink.scala:561:21]
wire [4:0] _noc_io_protocol_0_in_2_d_bits_sink; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_2_d_bits_denied; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_2_d_bits_corrupt; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_2_e_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_1_a_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_1_b_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_1_b_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_1_b_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_1_b_bits_size; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_1_b_bits_source; // @[Tilelink.scala:561:21]
wire [31:0] _noc_io_protocol_0_in_1_b_bits_address; // @[Tilelink.scala:561:21]
wire [7:0] _noc_io_protocol_0_in_1_b_bits_mask; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_1_b_bits_corrupt; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_1_c_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_1_d_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_1_d_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_1_d_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_1_d_bits_size; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_1_d_bits_source; // @[Tilelink.scala:561:21]
wire [4:0] _noc_io_protocol_0_in_1_d_bits_sink; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_1_d_bits_denied; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_1_d_bits_corrupt; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_1_e_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_0_a_ready; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_0_d_valid; // @[Tilelink.scala:561:21]
wire [2:0] _noc_io_protocol_0_in_0_d_bits_opcode; // @[Tilelink.scala:561:21]
wire [1:0] _noc_io_protocol_0_in_0_d_bits_param; // @[Tilelink.scala:561:21]
wire [3:0] _noc_io_protocol_0_in_0_d_bits_size; // @[Tilelink.scala:561:21]
wire [4:0] _noc_io_protocol_0_in_0_d_bits_source; // @[Tilelink.scala:561:21]
wire [4:0] _noc_io_protocol_0_in_0_d_bits_sink; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_0_d_bits_denied; // @[Tilelink.scala:561:21]
wire _noc_io_protocol_0_in_0_d_bits_corrupt; // @[Tilelink.scala:561:21]
TLMonitor monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_noc_io_protocol_0_in_0_a_ready), // @[Tilelink.scala:561:21]
.io_in_a_valid (auto_in_0_a_valid),
.io_in_a_bits_opcode (auto_in_0_a_bits_opcode),
.io_in_a_bits_param (auto_in_0_a_bits_param),
.io_in_a_bits_size (auto_in_0_a_bits_size),
.io_in_a_bits_source (auto_in_0_a_bits_source),
.io_in_a_bits_address (auto_in_0_a_bits_address),
.io_in_a_bits_mask (auto_in_0_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt),
.io_in_d_ready (auto_in_0_d_ready),
.io_in_d_valid (_noc_io_protocol_0_in_0_d_valid), // @[Tilelink.scala:561:21]
.io_in_d_bits_opcode (_noc_io_protocol_0_in_0_d_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_d_bits_param (_noc_io_protocol_0_in_0_d_bits_param), // @[Tilelink.scala:561:21]
.io_in_d_bits_size (_noc_io_protocol_0_in_0_d_bits_size), // @[Tilelink.scala:561:21]
.io_in_d_bits_source (_noc_io_protocol_0_in_0_d_bits_source), // @[Tilelink.scala:561:21]
.io_in_d_bits_sink (_noc_io_protocol_0_in_0_d_bits_sink), // @[Tilelink.scala:561:21]
.io_in_d_bits_denied (_noc_io_protocol_0_in_0_d_bits_denied), // @[Tilelink.scala:561:21]
.io_in_d_bits_corrupt (_noc_io_protocol_0_in_0_d_bits_corrupt) // @[Tilelink.scala:561:21]
); // @[Nodes.scala:27:25]
TLMonitor_1 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_noc_io_protocol_0_in_1_a_ready), // @[Tilelink.scala:561:21]
.io_in_a_valid (auto_in_1_a_valid),
.io_in_a_bits_opcode (auto_in_1_a_bits_opcode),
.io_in_a_bits_param (auto_in_1_a_bits_param),
.io_in_a_bits_size (auto_in_1_a_bits_size),
.io_in_a_bits_source (auto_in_1_a_bits_source),
.io_in_a_bits_address (auto_in_1_a_bits_address),
.io_in_a_bits_mask (auto_in_1_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt),
.io_in_b_ready (auto_in_1_b_ready),
.io_in_b_valid (_noc_io_protocol_0_in_1_b_valid), // @[Tilelink.scala:561:21]
.io_in_b_bits_opcode (_noc_io_protocol_0_in_1_b_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_b_bits_param (_noc_io_protocol_0_in_1_b_bits_param), // @[Tilelink.scala:561:21]
.io_in_b_bits_size (_noc_io_protocol_0_in_1_b_bits_size), // @[Tilelink.scala:561:21]
.io_in_b_bits_source (_noc_io_protocol_0_in_1_b_bits_source), // @[Tilelink.scala:561:21]
.io_in_b_bits_address (_noc_io_protocol_0_in_1_b_bits_address), // @[Tilelink.scala:561:21]
.io_in_b_bits_mask (_noc_io_protocol_0_in_1_b_bits_mask), // @[Tilelink.scala:561:21]
.io_in_b_bits_corrupt (_noc_io_protocol_0_in_1_b_bits_corrupt), // @[Tilelink.scala:561:21]
.io_in_c_ready (_noc_io_protocol_0_in_1_c_ready), // @[Tilelink.scala:561:21]
.io_in_c_valid (auto_in_1_c_valid),
.io_in_c_bits_opcode (auto_in_1_c_bits_opcode),
.io_in_c_bits_param (auto_in_1_c_bits_param),
.io_in_c_bits_size (auto_in_1_c_bits_size),
.io_in_c_bits_source (auto_in_1_c_bits_source),
.io_in_c_bits_address (auto_in_1_c_bits_address),
.io_in_c_bits_corrupt (auto_in_1_c_bits_corrupt),
.io_in_d_ready (auto_in_1_d_ready),
.io_in_d_valid (_noc_io_protocol_0_in_1_d_valid), // @[Tilelink.scala:561:21]
.io_in_d_bits_opcode (_noc_io_protocol_0_in_1_d_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_d_bits_param (_noc_io_protocol_0_in_1_d_bits_param), // @[Tilelink.scala:561:21]
.io_in_d_bits_size (_noc_io_protocol_0_in_1_d_bits_size), // @[Tilelink.scala:561:21]
.io_in_d_bits_source (_noc_io_protocol_0_in_1_d_bits_source), // @[Tilelink.scala:561:21]
.io_in_d_bits_sink (_noc_io_protocol_0_in_1_d_bits_sink), // @[Tilelink.scala:561:21]
.io_in_d_bits_denied (_noc_io_protocol_0_in_1_d_bits_denied), // @[Tilelink.scala:561:21]
.io_in_d_bits_corrupt (_noc_io_protocol_0_in_1_d_bits_corrupt), // @[Tilelink.scala:561:21]
.io_in_e_ready (_noc_io_protocol_0_in_1_e_ready), // @[Tilelink.scala:561:21]
.io_in_e_valid (auto_in_1_e_valid),
.io_in_e_bits_sink (auto_in_1_e_bits_sink)
); // @[Nodes.scala:27:25]
TLMonitor_1 monitor_2 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_noc_io_protocol_0_in_2_a_ready), // @[Tilelink.scala:561:21]
.io_in_a_valid (auto_in_2_a_valid),
.io_in_a_bits_opcode (auto_in_2_a_bits_opcode),
.io_in_a_bits_param (auto_in_2_a_bits_param),
.io_in_a_bits_size (auto_in_2_a_bits_size),
.io_in_a_bits_source (auto_in_2_a_bits_source),
.io_in_a_bits_address (auto_in_2_a_bits_address),
.io_in_a_bits_mask (auto_in_2_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_2_a_bits_corrupt),
.io_in_b_ready (auto_in_2_b_ready),
.io_in_b_valid (_noc_io_protocol_0_in_2_b_valid), // @[Tilelink.scala:561:21]
.io_in_b_bits_opcode (_noc_io_protocol_0_in_2_b_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_b_bits_param (_noc_io_protocol_0_in_2_b_bits_param), // @[Tilelink.scala:561:21]
.io_in_b_bits_size (_noc_io_protocol_0_in_2_b_bits_size), // @[Tilelink.scala:561:21]
.io_in_b_bits_source (_noc_io_protocol_0_in_2_b_bits_source), // @[Tilelink.scala:561:21]
.io_in_b_bits_address (_noc_io_protocol_0_in_2_b_bits_address), // @[Tilelink.scala:561:21]
.io_in_b_bits_mask (_noc_io_protocol_0_in_2_b_bits_mask), // @[Tilelink.scala:561:21]
.io_in_b_bits_corrupt (_noc_io_protocol_0_in_2_b_bits_corrupt), // @[Tilelink.scala:561:21]
.io_in_c_ready (_noc_io_protocol_0_in_2_c_ready), // @[Tilelink.scala:561:21]
.io_in_c_valid (auto_in_2_c_valid),
.io_in_c_bits_opcode (auto_in_2_c_bits_opcode),
.io_in_c_bits_param (auto_in_2_c_bits_param),
.io_in_c_bits_size (auto_in_2_c_bits_size),
.io_in_c_bits_source (auto_in_2_c_bits_source),
.io_in_c_bits_address (auto_in_2_c_bits_address),
.io_in_c_bits_corrupt (auto_in_2_c_bits_corrupt),
.io_in_d_ready (auto_in_2_d_ready),
.io_in_d_valid (_noc_io_protocol_0_in_2_d_valid), // @[Tilelink.scala:561:21]
.io_in_d_bits_opcode (_noc_io_protocol_0_in_2_d_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_d_bits_param (_noc_io_protocol_0_in_2_d_bits_param), // @[Tilelink.scala:561:21]
.io_in_d_bits_size (_noc_io_protocol_0_in_2_d_bits_size), // @[Tilelink.scala:561:21]
.io_in_d_bits_source (_noc_io_protocol_0_in_2_d_bits_source), // @[Tilelink.scala:561:21]
.io_in_d_bits_sink (_noc_io_protocol_0_in_2_d_bits_sink), // @[Tilelink.scala:561:21]
.io_in_d_bits_denied (_noc_io_protocol_0_in_2_d_bits_denied), // @[Tilelink.scala:561:21]
.io_in_d_bits_corrupt (_noc_io_protocol_0_in_2_d_bits_corrupt), // @[Tilelink.scala:561:21]
.io_in_e_ready (_noc_io_protocol_0_in_2_e_ready), // @[Tilelink.scala:561:21]
.io_in_e_valid (auto_in_2_e_valid),
.io_in_e_bits_sink (auto_in_2_e_bits_sink)
); // @[Nodes.scala:27:25]
TLMonitor_1 monitor_3 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_noc_io_protocol_0_in_3_a_ready), // @[Tilelink.scala:561:21]
.io_in_a_valid (auto_in_3_a_valid),
.io_in_a_bits_opcode (auto_in_3_a_bits_opcode),
.io_in_a_bits_param (auto_in_3_a_bits_param),
.io_in_a_bits_size (auto_in_3_a_bits_size),
.io_in_a_bits_source (auto_in_3_a_bits_source),
.io_in_a_bits_address (auto_in_3_a_bits_address),
.io_in_a_bits_mask (auto_in_3_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_3_a_bits_corrupt),
.io_in_b_ready (auto_in_3_b_ready),
.io_in_b_valid (_noc_io_protocol_0_in_3_b_valid), // @[Tilelink.scala:561:21]
.io_in_b_bits_opcode (_noc_io_protocol_0_in_3_b_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_b_bits_param (_noc_io_protocol_0_in_3_b_bits_param), // @[Tilelink.scala:561:21]
.io_in_b_bits_size (_noc_io_protocol_0_in_3_b_bits_size), // @[Tilelink.scala:561:21]
.io_in_b_bits_source (_noc_io_protocol_0_in_3_b_bits_source), // @[Tilelink.scala:561:21]
.io_in_b_bits_address (_noc_io_protocol_0_in_3_b_bits_address), // @[Tilelink.scala:561:21]
.io_in_b_bits_mask (_noc_io_protocol_0_in_3_b_bits_mask), // @[Tilelink.scala:561:21]
.io_in_b_bits_corrupt (_noc_io_protocol_0_in_3_b_bits_corrupt), // @[Tilelink.scala:561:21]
.io_in_c_ready (_noc_io_protocol_0_in_3_c_ready), // @[Tilelink.scala:561:21]
.io_in_c_valid (auto_in_3_c_valid),
.io_in_c_bits_opcode (auto_in_3_c_bits_opcode),
.io_in_c_bits_param (auto_in_3_c_bits_param),
.io_in_c_bits_size (auto_in_3_c_bits_size),
.io_in_c_bits_source (auto_in_3_c_bits_source),
.io_in_c_bits_address (auto_in_3_c_bits_address),
.io_in_c_bits_corrupt (auto_in_3_c_bits_corrupt),
.io_in_d_ready (auto_in_3_d_ready),
.io_in_d_valid (_noc_io_protocol_0_in_3_d_valid), // @[Tilelink.scala:561:21]
.io_in_d_bits_opcode (_noc_io_protocol_0_in_3_d_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_d_bits_param (_noc_io_protocol_0_in_3_d_bits_param), // @[Tilelink.scala:561:21]
.io_in_d_bits_size (_noc_io_protocol_0_in_3_d_bits_size), // @[Tilelink.scala:561:21]
.io_in_d_bits_source (_noc_io_protocol_0_in_3_d_bits_source), // @[Tilelink.scala:561:21]
.io_in_d_bits_sink (_noc_io_protocol_0_in_3_d_bits_sink), // @[Tilelink.scala:561:21]
.io_in_d_bits_denied (_noc_io_protocol_0_in_3_d_bits_denied), // @[Tilelink.scala:561:21]
.io_in_d_bits_corrupt (_noc_io_protocol_0_in_3_d_bits_corrupt), // @[Tilelink.scala:561:21]
.io_in_e_ready (_noc_io_protocol_0_in_3_e_ready), // @[Tilelink.scala:561:21]
.io_in_e_valid (auto_in_3_e_valid),
.io_in_e_bits_sink (auto_in_3_e_bits_sink)
); // @[Nodes.scala:27:25]
TLMonitor_1 monitor_4 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_noc_io_protocol_0_in_4_a_ready), // @[Tilelink.scala:561:21]
.io_in_a_valid (auto_in_4_a_valid),
.io_in_a_bits_opcode (auto_in_4_a_bits_opcode),
.io_in_a_bits_param (auto_in_4_a_bits_param),
.io_in_a_bits_size (auto_in_4_a_bits_size),
.io_in_a_bits_source (auto_in_4_a_bits_source),
.io_in_a_bits_address (auto_in_4_a_bits_address),
.io_in_a_bits_mask (auto_in_4_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_4_a_bits_corrupt),
.io_in_b_ready (auto_in_4_b_ready),
.io_in_b_valid (_noc_io_protocol_0_in_4_b_valid), // @[Tilelink.scala:561:21]
.io_in_b_bits_opcode (_noc_io_protocol_0_in_4_b_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_b_bits_param (_noc_io_protocol_0_in_4_b_bits_param), // @[Tilelink.scala:561:21]
.io_in_b_bits_size (_noc_io_protocol_0_in_4_b_bits_size), // @[Tilelink.scala:561:21]
.io_in_b_bits_source (_noc_io_protocol_0_in_4_b_bits_source), // @[Tilelink.scala:561:21]
.io_in_b_bits_address (_noc_io_protocol_0_in_4_b_bits_address), // @[Tilelink.scala:561:21]
.io_in_b_bits_mask (_noc_io_protocol_0_in_4_b_bits_mask), // @[Tilelink.scala:561:21]
.io_in_b_bits_corrupt (_noc_io_protocol_0_in_4_b_bits_corrupt), // @[Tilelink.scala:561:21]
.io_in_c_ready (_noc_io_protocol_0_in_4_c_ready), // @[Tilelink.scala:561:21]
.io_in_c_valid (auto_in_4_c_valid),
.io_in_c_bits_opcode (auto_in_4_c_bits_opcode),
.io_in_c_bits_param (auto_in_4_c_bits_param),
.io_in_c_bits_size (auto_in_4_c_bits_size),
.io_in_c_bits_source (auto_in_4_c_bits_source),
.io_in_c_bits_address (auto_in_4_c_bits_address),
.io_in_c_bits_corrupt (auto_in_4_c_bits_corrupt),
.io_in_d_ready (auto_in_4_d_ready),
.io_in_d_valid (_noc_io_protocol_0_in_4_d_valid), // @[Tilelink.scala:561:21]
.io_in_d_bits_opcode (_noc_io_protocol_0_in_4_d_bits_opcode), // @[Tilelink.scala:561:21]
.io_in_d_bits_param (_noc_io_protocol_0_in_4_d_bits_param), // @[Tilelink.scala:561:21]
.io_in_d_bits_size (_noc_io_protocol_0_in_4_d_bits_size), // @[Tilelink.scala:561:21]
.io_in_d_bits_source (_noc_io_protocol_0_in_4_d_bits_source), // @[Tilelink.scala:561:21]
.io_in_d_bits_sink (_noc_io_protocol_0_in_4_d_bits_sink), // @[Tilelink.scala:561:21]
.io_in_d_bits_denied (_noc_io_protocol_0_in_4_d_bits_denied), // @[Tilelink.scala:561:21]
.io_in_d_bits_corrupt (_noc_io_protocol_0_in_4_d_bits_corrupt), // @[Tilelink.scala:561:21]
.io_in_e_ready (_noc_io_protocol_0_in_4_e_ready), // @[Tilelink.scala:561:21]
.io_in_e_valid (auto_in_4_e_valid),
.io_in_e_bits_sink (auto_in_4_e_bits_sink)
); // @[Nodes.scala:27:25]
ProtocolNoC noc ( // @[Tilelink.scala:561:21]
.clock (clock),
.reset (reset),
.io_protocol_0_in_4_a_ready (_noc_io_protocol_0_in_4_a_ready),
.io_protocol_0_in_4_a_valid (auto_in_4_a_valid),
.io_protocol_0_in_4_a_bits_opcode (auto_in_4_a_bits_opcode),
.io_protocol_0_in_4_a_bits_param (auto_in_4_a_bits_param),
.io_protocol_0_in_4_a_bits_size (auto_in_4_a_bits_size),
.io_protocol_0_in_4_a_bits_source (auto_in_4_a_bits_source),
.io_protocol_0_in_4_a_bits_address (auto_in_4_a_bits_address),
.io_protocol_0_in_4_a_bits_mask (auto_in_4_a_bits_mask),
.io_protocol_0_in_4_a_bits_data (auto_in_4_a_bits_data),
.io_protocol_0_in_4_a_bits_corrupt (auto_in_4_a_bits_corrupt),
.io_protocol_0_in_4_b_ready (auto_in_4_b_ready),
.io_protocol_0_in_4_b_valid (_noc_io_protocol_0_in_4_b_valid),
.io_protocol_0_in_4_b_bits_opcode (_noc_io_protocol_0_in_4_b_bits_opcode),
.io_protocol_0_in_4_b_bits_param (_noc_io_protocol_0_in_4_b_bits_param),
.io_protocol_0_in_4_b_bits_size (_noc_io_protocol_0_in_4_b_bits_size),
.io_protocol_0_in_4_b_bits_source (_noc_io_protocol_0_in_4_b_bits_source),
.io_protocol_0_in_4_b_bits_address (_noc_io_protocol_0_in_4_b_bits_address),
.io_protocol_0_in_4_b_bits_mask (_noc_io_protocol_0_in_4_b_bits_mask),
.io_protocol_0_in_4_b_bits_data (auto_in_4_b_bits_data),
.io_protocol_0_in_4_b_bits_corrupt (_noc_io_protocol_0_in_4_b_bits_corrupt),
.io_protocol_0_in_4_c_ready (_noc_io_protocol_0_in_4_c_ready),
.io_protocol_0_in_4_c_valid (auto_in_4_c_valid),
.io_protocol_0_in_4_c_bits_opcode (auto_in_4_c_bits_opcode),
.io_protocol_0_in_4_c_bits_param (auto_in_4_c_bits_param),
.io_protocol_0_in_4_c_bits_size (auto_in_4_c_bits_size),
.io_protocol_0_in_4_c_bits_source (auto_in_4_c_bits_source),
.io_protocol_0_in_4_c_bits_address (auto_in_4_c_bits_address),
.io_protocol_0_in_4_c_bits_data (auto_in_4_c_bits_data),
.io_protocol_0_in_4_c_bits_corrupt (auto_in_4_c_bits_corrupt),
.io_protocol_0_in_4_d_ready (auto_in_4_d_ready),
.io_protocol_0_in_4_d_valid (_noc_io_protocol_0_in_4_d_valid),
.io_protocol_0_in_4_d_bits_opcode (_noc_io_protocol_0_in_4_d_bits_opcode),
.io_protocol_0_in_4_d_bits_param (_noc_io_protocol_0_in_4_d_bits_param),
.io_protocol_0_in_4_d_bits_size (_noc_io_protocol_0_in_4_d_bits_size),
.io_protocol_0_in_4_d_bits_source (_noc_io_protocol_0_in_4_d_bits_source),
.io_protocol_0_in_4_d_bits_sink (_noc_io_protocol_0_in_4_d_bits_sink),
.io_protocol_0_in_4_d_bits_denied (_noc_io_protocol_0_in_4_d_bits_denied),
.io_protocol_0_in_4_d_bits_data (auto_in_4_d_bits_data),
.io_protocol_0_in_4_d_bits_corrupt (_noc_io_protocol_0_in_4_d_bits_corrupt),
.io_protocol_0_in_4_e_ready (_noc_io_protocol_0_in_4_e_ready),
.io_protocol_0_in_4_e_valid (auto_in_4_e_valid),
.io_protocol_0_in_4_e_bits_sink (auto_in_4_e_bits_sink),
.io_protocol_0_in_3_a_ready (_noc_io_protocol_0_in_3_a_ready),
.io_protocol_0_in_3_a_valid (auto_in_3_a_valid),
.io_protocol_0_in_3_a_bits_opcode (auto_in_3_a_bits_opcode),
.io_protocol_0_in_3_a_bits_param (auto_in_3_a_bits_param),
.io_protocol_0_in_3_a_bits_size (auto_in_3_a_bits_size),
.io_protocol_0_in_3_a_bits_source (auto_in_3_a_bits_source),
.io_protocol_0_in_3_a_bits_address (auto_in_3_a_bits_address),
.io_protocol_0_in_3_a_bits_mask (auto_in_3_a_bits_mask),
.io_protocol_0_in_3_a_bits_data (auto_in_3_a_bits_data),
.io_protocol_0_in_3_a_bits_corrupt (auto_in_3_a_bits_corrupt),
.io_protocol_0_in_3_b_ready (auto_in_3_b_ready),
.io_protocol_0_in_3_b_valid (_noc_io_protocol_0_in_3_b_valid),
.io_protocol_0_in_3_b_bits_opcode (_noc_io_protocol_0_in_3_b_bits_opcode),
.io_protocol_0_in_3_b_bits_param (_noc_io_protocol_0_in_3_b_bits_param),
.io_protocol_0_in_3_b_bits_size (_noc_io_protocol_0_in_3_b_bits_size),
.io_protocol_0_in_3_b_bits_source (_noc_io_protocol_0_in_3_b_bits_source),
.io_protocol_0_in_3_b_bits_address (_noc_io_protocol_0_in_3_b_bits_address),
.io_protocol_0_in_3_b_bits_mask (_noc_io_protocol_0_in_3_b_bits_mask),
.io_protocol_0_in_3_b_bits_data (auto_in_3_b_bits_data),
.io_protocol_0_in_3_b_bits_corrupt (_noc_io_protocol_0_in_3_b_bits_corrupt),
.io_protocol_0_in_3_c_ready (_noc_io_protocol_0_in_3_c_ready),
.io_protocol_0_in_3_c_valid (auto_in_3_c_valid),
.io_protocol_0_in_3_c_bits_opcode (auto_in_3_c_bits_opcode),
.io_protocol_0_in_3_c_bits_param (auto_in_3_c_bits_param),
.io_protocol_0_in_3_c_bits_size (auto_in_3_c_bits_size),
.io_protocol_0_in_3_c_bits_source (auto_in_3_c_bits_source),
.io_protocol_0_in_3_c_bits_address (auto_in_3_c_bits_address),
.io_protocol_0_in_3_c_bits_data (auto_in_3_c_bits_data),
.io_protocol_0_in_3_c_bits_corrupt (auto_in_3_c_bits_corrupt),
.io_protocol_0_in_3_d_ready (auto_in_3_d_ready),
.io_protocol_0_in_3_d_valid (_noc_io_protocol_0_in_3_d_valid),
.io_protocol_0_in_3_d_bits_opcode (_noc_io_protocol_0_in_3_d_bits_opcode),
.io_protocol_0_in_3_d_bits_param (_noc_io_protocol_0_in_3_d_bits_param),
.io_protocol_0_in_3_d_bits_size (_noc_io_protocol_0_in_3_d_bits_size),
.io_protocol_0_in_3_d_bits_source (_noc_io_protocol_0_in_3_d_bits_source),
.io_protocol_0_in_3_d_bits_sink (_noc_io_protocol_0_in_3_d_bits_sink),
.io_protocol_0_in_3_d_bits_denied (_noc_io_protocol_0_in_3_d_bits_denied),
.io_protocol_0_in_3_d_bits_data (auto_in_3_d_bits_data),
.io_protocol_0_in_3_d_bits_corrupt (_noc_io_protocol_0_in_3_d_bits_corrupt),
.io_protocol_0_in_3_e_ready (_noc_io_protocol_0_in_3_e_ready),
.io_protocol_0_in_3_e_valid (auto_in_3_e_valid),
.io_protocol_0_in_3_e_bits_sink (auto_in_3_e_bits_sink),
.io_protocol_0_in_2_a_ready (_noc_io_protocol_0_in_2_a_ready),
.io_protocol_0_in_2_a_valid (auto_in_2_a_valid),
.io_protocol_0_in_2_a_bits_opcode (auto_in_2_a_bits_opcode),
.io_protocol_0_in_2_a_bits_param (auto_in_2_a_bits_param),
.io_protocol_0_in_2_a_bits_size (auto_in_2_a_bits_size),
.io_protocol_0_in_2_a_bits_source (auto_in_2_a_bits_source),
.io_protocol_0_in_2_a_bits_address (auto_in_2_a_bits_address),
.io_protocol_0_in_2_a_bits_mask (auto_in_2_a_bits_mask),
.io_protocol_0_in_2_a_bits_data (auto_in_2_a_bits_data),
.io_protocol_0_in_2_a_bits_corrupt (auto_in_2_a_bits_corrupt),
.io_protocol_0_in_2_b_ready (auto_in_2_b_ready),
.io_protocol_0_in_2_b_valid (_noc_io_protocol_0_in_2_b_valid),
.io_protocol_0_in_2_b_bits_opcode (_noc_io_protocol_0_in_2_b_bits_opcode),
.io_protocol_0_in_2_b_bits_param (_noc_io_protocol_0_in_2_b_bits_param),
.io_protocol_0_in_2_b_bits_size (_noc_io_protocol_0_in_2_b_bits_size),
.io_protocol_0_in_2_b_bits_source (_noc_io_protocol_0_in_2_b_bits_source),
.io_protocol_0_in_2_b_bits_address (_noc_io_protocol_0_in_2_b_bits_address),
.io_protocol_0_in_2_b_bits_mask (_noc_io_protocol_0_in_2_b_bits_mask),
.io_protocol_0_in_2_b_bits_data (auto_in_2_b_bits_data),
.io_protocol_0_in_2_b_bits_corrupt (_noc_io_protocol_0_in_2_b_bits_corrupt),
.io_protocol_0_in_2_c_ready (_noc_io_protocol_0_in_2_c_ready),
.io_protocol_0_in_2_c_valid (auto_in_2_c_valid),
.io_protocol_0_in_2_c_bits_opcode (auto_in_2_c_bits_opcode),
.io_protocol_0_in_2_c_bits_param (auto_in_2_c_bits_param),
.io_protocol_0_in_2_c_bits_size (auto_in_2_c_bits_size),
.io_protocol_0_in_2_c_bits_source (auto_in_2_c_bits_source),
.io_protocol_0_in_2_c_bits_address (auto_in_2_c_bits_address),
.io_protocol_0_in_2_c_bits_data (auto_in_2_c_bits_data),
.io_protocol_0_in_2_c_bits_corrupt (auto_in_2_c_bits_corrupt),
.io_protocol_0_in_2_d_ready (auto_in_2_d_ready),
.io_protocol_0_in_2_d_valid (_noc_io_protocol_0_in_2_d_valid),
.io_protocol_0_in_2_d_bits_opcode (_noc_io_protocol_0_in_2_d_bits_opcode),
.io_protocol_0_in_2_d_bits_param (_noc_io_protocol_0_in_2_d_bits_param),
.io_protocol_0_in_2_d_bits_size (_noc_io_protocol_0_in_2_d_bits_size),
.io_protocol_0_in_2_d_bits_source (_noc_io_protocol_0_in_2_d_bits_source),
.io_protocol_0_in_2_d_bits_sink (_noc_io_protocol_0_in_2_d_bits_sink),
.io_protocol_0_in_2_d_bits_denied (_noc_io_protocol_0_in_2_d_bits_denied),
.io_protocol_0_in_2_d_bits_data (auto_in_2_d_bits_data),
.io_protocol_0_in_2_d_bits_corrupt (_noc_io_protocol_0_in_2_d_bits_corrupt),
.io_protocol_0_in_2_e_ready (_noc_io_protocol_0_in_2_e_ready),
.io_protocol_0_in_2_e_valid (auto_in_2_e_valid),
.io_protocol_0_in_2_e_bits_sink (auto_in_2_e_bits_sink),
.io_protocol_0_in_1_a_ready (_noc_io_protocol_0_in_1_a_ready),
.io_protocol_0_in_1_a_valid (auto_in_1_a_valid),
.io_protocol_0_in_1_a_bits_opcode (auto_in_1_a_bits_opcode),
.io_protocol_0_in_1_a_bits_param (auto_in_1_a_bits_param),
.io_protocol_0_in_1_a_bits_size (auto_in_1_a_bits_size),
.io_protocol_0_in_1_a_bits_source (auto_in_1_a_bits_source),
.io_protocol_0_in_1_a_bits_address (auto_in_1_a_bits_address),
.io_protocol_0_in_1_a_bits_mask (auto_in_1_a_bits_mask),
.io_protocol_0_in_1_a_bits_data (auto_in_1_a_bits_data),
.io_protocol_0_in_1_a_bits_corrupt (auto_in_1_a_bits_corrupt),
.io_protocol_0_in_1_b_ready (auto_in_1_b_ready),
.io_protocol_0_in_1_b_valid (_noc_io_protocol_0_in_1_b_valid),
.io_protocol_0_in_1_b_bits_opcode (_noc_io_protocol_0_in_1_b_bits_opcode),
.io_protocol_0_in_1_b_bits_param (_noc_io_protocol_0_in_1_b_bits_param),
.io_protocol_0_in_1_b_bits_size (_noc_io_protocol_0_in_1_b_bits_size),
.io_protocol_0_in_1_b_bits_source (_noc_io_protocol_0_in_1_b_bits_source),
.io_protocol_0_in_1_b_bits_address (_noc_io_protocol_0_in_1_b_bits_address),
.io_protocol_0_in_1_b_bits_mask (_noc_io_protocol_0_in_1_b_bits_mask),
.io_protocol_0_in_1_b_bits_data (auto_in_1_b_bits_data),
.io_protocol_0_in_1_b_bits_corrupt (_noc_io_protocol_0_in_1_b_bits_corrupt),
.io_protocol_0_in_1_c_ready (_noc_io_protocol_0_in_1_c_ready),
.io_protocol_0_in_1_c_valid (auto_in_1_c_valid),
.io_protocol_0_in_1_c_bits_opcode (auto_in_1_c_bits_opcode),
.io_protocol_0_in_1_c_bits_param (auto_in_1_c_bits_param),
.io_protocol_0_in_1_c_bits_size (auto_in_1_c_bits_size),
.io_protocol_0_in_1_c_bits_source (auto_in_1_c_bits_source),
.io_protocol_0_in_1_c_bits_address (auto_in_1_c_bits_address),
.io_protocol_0_in_1_c_bits_data (auto_in_1_c_bits_data),
.io_protocol_0_in_1_c_bits_corrupt (auto_in_1_c_bits_corrupt),
.io_protocol_0_in_1_d_ready (auto_in_1_d_ready),
.io_protocol_0_in_1_d_valid (_noc_io_protocol_0_in_1_d_valid),
.io_protocol_0_in_1_d_bits_opcode (_noc_io_protocol_0_in_1_d_bits_opcode),
.io_protocol_0_in_1_d_bits_param (_noc_io_protocol_0_in_1_d_bits_param),
.io_protocol_0_in_1_d_bits_size (_noc_io_protocol_0_in_1_d_bits_size),
.io_protocol_0_in_1_d_bits_source (_noc_io_protocol_0_in_1_d_bits_source),
.io_protocol_0_in_1_d_bits_sink (_noc_io_protocol_0_in_1_d_bits_sink),
.io_protocol_0_in_1_d_bits_denied (_noc_io_protocol_0_in_1_d_bits_denied),
.io_protocol_0_in_1_d_bits_data (auto_in_1_d_bits_data),
.io_protocol_0_in_1_d_bits_corrupt (_noc_io_protocol_0_in_1_d_bits_corrupt),
.io_protocol_0_in_1_e_ready (_noc_io_protocol_0_in_1_e_ready),
.io_protocol_0_in_1_e_valid (auto_in_1_e_valid),
.io_protocol_0_in_1_e_bits_sink (auto_in_1_e_bits_sink),
.io_protocol_0_in_0_a_ready (_noc_io_protocol_0_in_0_a_ready),
.io_protocol_0_in_0_a_valid (auto_in_0_a_valid),
.io_protocol_0_in_0_a_bits_opcode (auto_in_0_a_bits_opcode),
.io_protocol_0_in_0_a_bits_param (auto_in_0_a_bits_param),
.io_protocol_0_in_0_a_bits_size (auto_in_0_a_bits_size),
.io_protocol_0_in_0_a_bits_source (auto_in_0_a_bits_source),
.io_protocol_0_in_0_a_bits_address (auto_in_0_a_bits_address),
.io_protocol_0_in_0_a_bits_mask (auto_in_0_a_bits_mask),
.io_protocol_0_in_0_a_bits_data (auto_in_0_a_bits_data),
.io_protocol_0_in_0_a_bits_corrupt (auto_in_0_a_bits_corrupt),
.io_protocol_0_in_0_d_ready (auto_in_0_d_ready),
.io_protocol_0_in_0_d_valid (_noc_io_protocol_0_in_0_d_valid),
.io_protocol_0_in_0_d_bits_opcode (_noc_io_protocol_0_in_0_d_bits_opcode),
.io_protocol_0_in_0_d_bits_param (_noc_io_protocol_0_in_0_d_bits_param),
.io_protocol_0_in_0_d_bits_size (_noc_io_protocol_0_in_0_d_bits_size),
.io_protocol_0_in_0_d_bits_source (_noc_io_protocol_0_in_0_d_bits_source),
.io_protocol_0_in_0_d_bits_sink (_noc_io_protocol_0_in_0_d_bits_sink),
.io_protocol_0_in_0_d_bits_denied (_noc_io_protocol_0_in_0_d_bits_denied),
.io_protocol_0_in_0_d_bits_data (auto_in_0_d_bits_data),
.io_protocol_0_in_0_d_bits_corrupt (_noc_io_protocol_0_in_0_d_bits_corrupt),
.io_protocol_0_out_4_a_ready (auto_out_4_a_ready),
.io_protocol_0_out_4_a_valid (auto_out_4_a_valid),
.io_protocol_0_out_4_a_bits_opcode (auto_out_4_a_bits_opcode),
.io_protocol_0_out_4_a_bits_param (auto_out_4_a_bits_param),
.io_protocol_0_out_4_a_bits_size (auto_out_4_a_bits_size),
.io_protocol_0_out_4_a_bits_source (auto_out_4_a_bits_source),
.io_protocol_0_out_4_a_bits_address (auto_out_4_a_bits_address),
.io_protocol_0_out_4_a_bits_mask (auto_out_4_a_bits_mask),
.io_protocol_0_out_4_a_bits_data (auto_out_4_a_bits_data),
.io_protocol_0_out_4_a_bits_corrupt (auto_out_4_a_bits_corrupt),
.io_protocol_0_out_4_b_ready (auto_out_4_b_ready),
.io_protocol_0_out_4_b_valid (auto_out_4_b_valid),
.io_protocol_0_out_4_b_bits_param (auto_out_4_b_bits_param),
.io_protocol_0_out_4_b_bits_source (auto_out_4_b_bits_source),
.io_protocol_0_out_4_b_bits_address (auto_out_4_b_bits_address),
.io_protocol_0_out_4_c_ready (auto_out_4_c_ready),
.io_protocol_0_out_4_c_valid (auto_out_4_c_valid),
.io_protocol_0_out_4_c_bits_opcode (auto_out_4_c_bits_opcode),
.io_protocol_0_out_4_c_bits_param (auto_out_4_c_bits_param),
.io_protocol_0_out_4_c_bits_size (auto_out_4_c_bits_size),
.io_protocol_0_out_4_c_bits_source (auto_out_4_c_bits_source),
.io_protocol_0_out_4_c_bits_address (auto_out_4_c_bits_address),
.io_protocol_0_out_4_c_bits_data (auto_out_4_c_bits_data),
.io_protocol_0_out_4_c_bits_corrupt (auto_out_4_c_bits_corrupt),
.io_protocol_0_out_4_d_ready (auto_out_4_d_ready),
.io_protocol_0_out_4_d_valid (auto_out_4_d_valid),
.io_protocol_0_out_4_d_bits_opcode (auto_out_4_d_bits_opcode),
.io_protocol_0_out_4_d_bits_param (auto_out_4_d_bits_param),
.io_protocol_0_out_4_d_bits_size (auto_out_4_d_bits_size),
.io_protocol_0_out_4_d_bits_source (auto_out_4_d_bits_source),
.io_protocol_0_out_4_d_bits_sink (auto_out_4_d_bits_sink),
.io_protocol_0_out_4_d_bits_denied (auto_out_4_d_bits_denied),
.io_protocol_0_out_4_d_bits_data (auto_out_4_d_bits_data),
.io_protocol_0_out_4_d_bits_corrupt (auto_out_4_d_bits_corrupt),
.io_protocol_0_out_4_e_valid (auto_out_4_e_valid),
.io_protocol_0_out_4_e_bits_sink (auto_out_4_e_bits_sink),
.io_protocol_0_out_3_a_ready (auto_out_3_a_ready),
.io_protocol_0_out_3_a_valid (auto_out_3_a_valid),
.io_protocol_0_out_3_a_bits_opcode (auto_out_3_a_bits_opcode),
.io_protocol_0_out_3_a_bits_param (auto_out_3_a_bits_param),
.io_protocol_0_out_3_a_bits_size (auto_out_3_a_bits_size),
.io_protocol_0_out_3_a_bits_source (auto_out_3_a_bits_source),
.io_protocol_0_out_3_a_bits_address (auto_out_3_a_bits_address),
.io_protocol_0_out_3_a_bits_mask (auto_out_3_a_bits_mask),
.io_protocol_0_out_3_a_bits_data (auto_out_3_a_bits_data),
.io_protocol_0_out_3_a_bits_corrupt (auto_out_3_a_bits_corrupt),
.io_protocol_0_out_3_b_ready (auto_out_3_b_ready),
.io_protocol_0_out_3_b_valid (auto_out_3_b_valid),
.io_protocol_0_out_3_b_bits_param (auto_out_3_b_bits_param),
.io_protocol_0_out_3_b_bits_source (auto_out_3_b_bits_source),
.io_protocol_0_out_3_b_bits_address (auto_out_3_b_bits_address),
.io_protocol_0_out_3_c_ready (auto_out_3_c_ready),
.io_protocol_0_out_3_c_valid (auto_out_3_c_valid),
.io_protocol_0_out_3_c_bits_opcode (auto_out_3_c_bits_opcode),
.io_protocol_0_out_3_c_bits_param (auto_out_3_c_bits_param),
.io_protocol_0_out_3_c_bits_size (auto_out_3_c_bits_size),
.io_protocol_0_out_3_c_bits_source (auto_out_3_c_bits_source),
.io_protocol_0_out_3_c_bits_address (auto_out_3_c_bits_address),
.io_protocol_0_out_3_c_bits_data (auto_out_3_c_bits_data),
.io_protocol_0_out_3_c_bits_corrupt (auto_out_3_c_bits_corrupt),
.io_protocol_0_out_3_d_ready (auto_out_3_d_ready),
.io_protocol_0_out_3_d_valid (auto_out_3_d_valid),
.io_protocol_0_out_3_d_bits_opcode (auto_out_3_d_bits_opcode),
.io_protocol_0_out_3_d_bits_param (auto_out_3_d_bits_param),
.io_protocol_0_out_3_d_bits_size (auto_out_3_d_bits_size),
.io_protocol_0_out_3_d_bits_source (auto_out_3_d_bits_source),
.io_protocol_0_out_3_d_bits_sink (auto_out_3_d_bits_sink),
.io_protocol_0_out_3_d_bits_denied (auto_out_3_d_bits_denied),
.io_protocol_0_out_3_d_bits_data (auto_out_3_d_bits_data),
.io_protocol_0_out_3_d_bits_corrupt (auto_out_3_d_bits_corrupt),
.io_protocol_0_out_3_e_valid (auto_out_3_e_valid),
.io_protocol_0_out_3_e_bits_sink (auto_out_3_e_bits_sink),
.io_protocol_0_out_2_a_ready (auto_out_2_a_ready),
.io_protocol_0_out_2_a_valid (auto_out_2_a_valid),
.io_protocol_0_out_2_a_bits_opcode (auto_out_2_a_bits_opcode),
.io_protocol_0_out_2_a_bits_param (auto_out_2_a_bits_param),
.io_protocol_0_out_2_a_bits_size (auto_out_2_a_bits_size),
.io_protocol_0_out_2_a_bits_source (auto_out_2_a_bits_source),
.io_protocol_0_out_2_a_bits_address (auto_out_2_a_bits_address),
.io_protocol_0_out_2_a_bits_mask (auto_out_2_a_bits_mask),
.io_protocol_0_out_2_a_bits_data (auto_out_2_a_bits_data),
.io_protocol_0_out_2_a_bits_corrupt (auto_out_2_a_bits_corrupt),
.io_protocol_0_out_2_b_ready (auto_out_2_b_ready),
.io_protocol_0_out_2_b_valid (auto_out_2_b_valid),
.io_protocol_0_out_2_b_bits_param (auto_out_2_b_bits_param),
.io_protocol_0_out_2_b_bits_source (auto_out_2_b_bits_source),
.io_protocol_0_out_2_b_bits_address (auto_out_2_b_bits_address),
.io_protocol_0_out_2_c_ready (auto_out_2_c_ready),
.io_protocol_0_out_2_c_valid (auto_out_2_c_valid),
.io_protocol_0_out_2_c_bits_opcode (auto_out_2_c_bits_opcode),
.io_protocol_0_out_2_c_bits_param (auto_out_2_c_bits_param),
.io_protocol_0_out_2_c_bits_size (auto_out_2_c_bits_size),
.io_protocol_0_out_2_c_bits_source (auto_out_2_c_bits_source),
.io_protocol_0_out_2_c_bits_address (auto_out_2_c_bits_address),
.io_protocol_0_out_2_c_bits_data (auto_out_2_c_bits_data),
.io_protocol_0_out_2_c_bits_corrupt (auto_out_2_c_bits_corrupt),
.io_protocol_0_out_2_d_ready (auto_out_2_d_ready),
.io_protocol_0_out_2_d_valid (auto_out_2_d_valid),
.io_protocol_0_out_2_d_bits_opcode (auto_out_2_d_bits_opcode),
.io_protocol_0_out_2_d_bits_param (auto_out_2_d_bits_param),
.io_protocol_0_out_2_d_bits_size (auto_out_2_d_bits_size),
.io_protocol_0_out_2_d_bits_source (auto_out_2_d_bits_source),
.io_protocol_0_out_2_d_bits_sink (auto_out_2_d_bits_sink),
.io_protocol_0_out_2_d_bits_denied (auto_out_2_d_bits_denied),
.io_protocol_0_out_2_d_bits_data (auto_out_2_d_bits_data),
.io_protocol_0_out_2_d_bits_corrupt (auto_out_2_d_bits_corrupt),
.io_protocol_0_out_2_e_valid (auto_out_2_e_valid),
.io_protocol_0_out_2_e_bits_sink (auto_out_2_e_bits_sink),
.io_protocol_0_out_1_a_ready (auto_out_1_a_ready),
.io_protocol_0_out_1_a_valid (auto_out_1_a_valid),
.io_protocol_0_out_1_a_bits_opcode (auto_out_1_a_bits_opcode),
.io_protocol_0_out_1_a_bits_param (auto_out_1_a_bits_param),
.io_protocol_0_out_1_a_bits_size (auto_out_1_a_bits_size),
.io_protocol_0_out_1_a_bits_source (auto_out_1_a_bits_source),
.io_protocol_0_out_1_a_bits_address (auto_out_1_a_bits_address),
.io_protocol_0_out_1_a_bits_mask (auto_out_1_a_bits_mask),
.io_protocol_0_out_1_a_bits_data (auto_out_1_a_bits_data),
.io_protocol_0_out_1_a_bits_corrupt (auto_out_1_a_bits_corrupt),
.io_protocol_0_out_1_b_ready (auto_out_1_b_ready),
.io_protocol_0_out_1_b_valid (auto_out_1_b_valid),
.io_protocol_0_out_1_b_bits_param (auto_out_1_b_bits_param),
.io_protocol_0_out_1_b_bits_source (auto_out_1_b_bits_source),
.io_protocol_0_out_1_b_bits_address (auto_out_1_b_bits_address),
.io_protocol_0_out_1_c_ready (auto_out_1_c_ready),
.io_protocol_0_out_1_c_valid (auto_out_1_c_valid),
.io_protocol_0_out_1_c_bits_opcode (auto_out_1_c_bits_opcode),
.io_protocol_0_out_1_c_bits_param (auto_out_1_c_bits_param),
.io_protocol_0_out_1_c_bits_size (auto_out_1_c_bits_size),
.io_protocol_0_out_1_c_bits_source (auto_out_1_c_bits_source),
.io_protocol_0_out_1_c_bits_address (auto_out_1_c_bits_address),
.io_protocol_0_out_1_c_bits_data (auto_out_1_c_bits_data),
.io_protocol_0_out_1_c_bits_corrupt (auto_out_1_c_bits_corrupt),
.io_protocol_0_out_1_d_ready (auto_out_1_d_ready),
.io_protocol_0_out_1_d_valid (auto_out_1_d_valid),
.io_protocol_0_out_1_d_bits_opcode (auto_out_1_d_bits_opcode),
.io_protocol_0_out_1_d_bits_param (auto_out_1_d_bits_param),
.io_protocol_0_out_1_d_bits_size (auto_out_1_d_bits_size),
.io_protocol_0_out_1_d_bits_source (auto_out_1_d_bits_source),
.io_protocol_0_out_1_d_bits_sink (auto_out_1_d_bits_sink),
.io_protocol_0_out_1_d_bits_denied (auto_out_1_d_bits_denied),
.io_protocol_0_out_1_d_bits_data (auto_out_1_d_bits_data),
.io_protocol_0_out_1_d_bits_corrupt (auto_out_1_d_bits_corrupt),
.io_protocol_0_out_1_e_valid (auto_out_1_e_valid),
.io_protocol_0_out_1_e_bits_sink (auto_out_1_e_bits_sink),
.io_protocol_0_out_0_a_ready (auto_out_0_a_ready),
.io_protocol_0_out_0_a_valid (auto_out_0_a_valid),
.io_protocol_0_out_0_a_bits_opcode (auto_out_0_a_bits_opcode),
.io_protocol_0_out_0_a_bits_param (auto_out_0_a_bits_param),
.io_protocol_0_out_0_a_bits_size (auto_out_0_a_bits_size),
.io_protocol_0_out_0_a_bits_source (auto_out_0_a_bits_source),
.io_protocol_0_out_0_a_bits_address (auto_out_0_a_bits_address),
.io_protocol_0_out_0_a_bits_mask (auto_out_0_a_bits_mask),
.io_protocol_0_out_0_a_bits_data (auto_out_0_a_bits_data),
.io_protocol_0_out_0_a_bits_corrupt (auto_out_0_a_bits_corrupt),
.io_protocol_0_out_0_d_ready (auto_out_0_d_ready),
.io_protocol_0_out_0_d_valid (auto_out_0_d_valid),
.io_protocol_0_out_0_d_bits_opcode (auto_out_0_d_bits_opcode),
.io_protocol_0_out_0_d_bits_param (auto_out_0_d_bits_param),
.io_protocol_0_out_0_d_bits_size (auto_out_0_d_bits_size),
.io_protocol_0_out_0_d_bits_source (auto_out_0_d_bits_source),
.io_protocol_0_out_0_d_bits_sink (auto_out_0_d_bits_sink),
.io_protocol_0_out_0_d_bits_denied (auto_out_0_d_bits_denied),
.io_protocol_0_out_0_d_bits_data (auto_out_0_d_bits_data),
.io_protocol_0_out_0_d_bits_corrupt (auto_out_0_d_bits_corrupt)
); // @[Tilelink.scala:561:21]
assign auto_in_4_a_ready = _noc_io_protocol_0_in_4_a_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_b_valid = _noc_io_protocol_0_in_4_b_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_b_bits_opcode = _noc_io_protocol_0_in_4_b_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_b_bits_param = _noc_io_protocol_0_in_4_b_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_b_bits_size = _noc_io_protocol_0_in_4_b_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_b_bits_source = _noc_io_protocol_0_in_4_b_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_b_bits_address = _noc_io_protocol_0_in_4_b_bits_address; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_b_bits_mask = _noc_io_protocol_0_in_4_b_bits_mask; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_b_bits_corrupt = _noc_io_protocol_0_in_4_b_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_c_ready = _noc_io_protocol_0_in_4_c_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_d_valid = _noc_io_protocol_0_in_4_d_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_d_bits_opcode = _noc_io_protocol_0_in_4_d_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_d_bits_param = _noc_io_protocol_0_in_4_d_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_d_bits_size = _noc_io_protocol_0_in_4_d_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_d_bits_source = _noc_io_protocol_0_in_4_d_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_d_bits_sink = _noc_io_protocol_0_in_4_d_bits_sink; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_d_bits_denied = _noc_io_protocol_0_in_4_d_bits_denied; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_d_bits_corrupt = _noc_io_protocol_0_in_4_d_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_4_e_ready = _noc_io_protocol_0_in_4_e_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_a_ready = _noc_io_protocol_0_in_3_a_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_b_valid = _noc_io_protocol_0_in_3_b_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_b_bits_opcode = _noc_io_protocol_0_in_3_b_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_b_bits_param = _noc_io_protocol_0_in_3_b_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_b_bits_size = _noc_io_protocol_0_in_3_b_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_b_bits_source = _noc_io_protocol_0_in_3_b_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_b_bits_address = _noc_io_protocol_0_in_3_b_bits_address; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_b_bits_mask = _noc_io_protocol_0_in_3_b_bits_mask; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_b_bits_corrupt = _noc_io_protocol_0_in_3_b_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_c_ready = _noc_io_protocol_0_in_3_c_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_d_valid = _noc_io_protocol_0_in_3_d_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_d_bits_opcode = _noc_io_protocol_0_in_3_d_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_d_bits_param = _noc_io_protocol_0_in_3_d_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_d_bits_size = _noc_io_protocol_0_in_3_d_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_d_bits_source = _noc_io_protocol_0_in_3_d_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_d_bits_sink = _noc_io_protocol_0_in_3_d_bits_sink; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_d_bits_denied = _noc_io_protocol_0_in_3_d_bits_denied; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_d_bits_corrupt = _noc_io_protocol_0_in_3_d_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_3_e_ready = _noc_io_protocol_0_in_3_e_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_a_ready = _noc_io_protocol_0_in_2_a_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_b_valid = _noc_io_protocol_0_in_2_b_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_b_bits_opcode = _noc_io_protocol_0_in_2_b_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_b_bits_param = _noc_io_protocol_0_in_2_b_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_b_bits_size = _noc_io_protocol_0_in_2_b_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_b_bits_source = _noc_io_protocol_0_in_2_b_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_b_bits_address = _noc_io_protocol_0_in_2_b_bits_address; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_b_bits_mask = _noc_io_protocol_0_in_2_b_bits_mask; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_b_bits_corrupt = _noc_io_protocol_0_in_2_b_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_c_ready = _noc_io_protocol_0_in_2_c_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_d_valid = _noc_io_protocol_0_in_2_d_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_d_bits_opcode = _noc_io_protocol_0_in_2_d_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_d_bits_param = _noc_io_protocol_0_in_2_d_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_d_bits_size = _noc_io_protocol_0_in_2_d_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_d_bits_source = _noc_io_protocol_0_in_2_d_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_d_bits_sink = _noc_io_protocol_0_in_2_d_bits_sink; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_d_bits_denied = _noc_io_protocol_0_in_2_d_bits_denied; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_d_bits_corrupt = _noc_io_protocol_0_in_2_d_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_2_e_ready = _noc_io_protocol_0_in_2_e_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_a_ready = _noc_io_protocol_0_in_1_a_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_b_valid = _noc_io_protocol_0_in_1_b_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_b_bits_opcode = _noc_io_protocol_0_in_1_b_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_b_bits_param = _noc_io_protocol_0_in_1_b_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_b_bits_size = _noc_io_protocol_0_in_1_b_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_b_bits_source = _noc_io_protocol_0_in_1_b_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_b_bits_address = _noc_io_protocol_0_in_1_b_bits_address; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_b_bits_mask = _noc_io_protocol_0_in_1_b_bits_mask; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_b_bits_corrupt = _noc_io_protocol_0_in_1_b_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_c_ready = _noc_io_protocol_0_in_1_c_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_d_valid = _noc_io_protocol_0_in_1_d_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_d_bits_opcode = _noc_io_protocol_0_in_1_d_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_d_bits_param = _noc_io_protocol_0_in_1_d_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_d_bits_size = _noc_io_protocol_0_in_1_d_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_d_bits_source = _noc_io_protocol_0_in_1_d_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_d_bits_sink = _noc_io_protocol_0_in_1_d_bits_sink; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_d_bits_denied = _noc_io_protocol_0_in_1_d_bits_denied; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_d_bits_corrupt = _noc_io_protocol_0_in_1_d_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_1_e_ready = _noc_io_protocol_0_in_1_e_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_a_ready = _noc_io_protocol_0_in_0_a_ready; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_d_valid = _noc_io_protocol_0_in_0_d_valid; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_d_bits_opcode = _noc_io_protocol_0_in_0_d_bits_opcode; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_d_bits_param = _noc_io_protocol_0_in_0_d_bits_param; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_d_bits_size = _noc_io_protocol_0_in_0_d_bits_size; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_d_bits_source = _noc_io_protocol_0_in_0_d_bits_source; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_d_bits_sink = _noc_io_protocol_0_in_0_d_bits_sink; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_d_bits_denied = _noc_io_protocol_0_in_0_d_bits_denied; // @[Tilelink.scala:546:25, :561:21]
assign auto_in_0_d_bits_corrupt = _noc_io_protocol_0_in_0_d_bits_corrupt; // @[Tilelink.scala:546:25, :561:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_447 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_447( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_9ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip routers_ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, routers_source_nodes_out_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_9
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0
connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1
connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2
connect routers.auto.dest_nodes_in_3, auto.routers_dest_nodes_in_3
connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free
connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return
connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit
connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free
connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return
connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit
connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free
connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return
connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit
connect routers.auto.source_nodes_out_3.vc_free, auto.routers_source_nodes_out_3.vc_free
connect routers.auto.source_nodes_out_3.credit_return, auto.routers_source_nodes_out_3.credit_return
connect auto.routers_source_nodes_out_3.flit, routers.auto.source_nodes_out_3.flit
connect routers.auto.ingress_nodes_in, auto.routers_ingress_nodes_in
connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits
connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid
connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready
connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits
connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid
connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLSplitACDxBENoC_acd_router_9ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_9 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3),
.auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3),
.auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_flit_ready (auto_routers_ingress_nodes_in_flit_ready),
.auto_ingress_nodes_in_flit_valid (auto_routers_ingress_nodes_in_flit_valid),
.auto_ingress_nodes_in_flit_bits_head (auto_routers_ingress_nodes_in_flit_bits_head),
.auto_ingress_nodes_in_flit_bits_tail (auto_routers_ingress_nodes_in_flit_bits_tail),
.auto_ingress_nodes_in_flit_bits_payload (auto_routers_ingress_nodes_in_flit_bits_payload),
.auto_ingress_nodes_in_flit_bits_egress_id (auto_routers_ingress_nodes_in_flit_bits_egress_id),
.auto_source_nodes_out_3_flit_0_valid (auto_routers_source_nodes_out_3_flit_0_valid),
.auto_source_nodes_out_3_flit_0_bits_head (auto_routers_source_nodes_out_3_flit_0_bits_head),
.auto_source_nodes_out_3_flit_0_bits_tail (auto_routers_source_nodes_out_3_flit_0_bits_tail),
.auto_source_nodes_out_3_flit_0_bits_payload (auto_routers_source_nodes_out_3_flit_0_bits_payload),
.auto_source_nodes_out_3_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_3_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_3_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_3_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_3_credit_return (auto_routers_source_nodes_out_3_credit_return),
.auto_source_nodes_out_3_vc_free (auto_routers_source_nodes_out_3_vc_free),
.auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid),
.auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head),
.auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail),
.auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload),
.auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return),
.auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free),
.auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),
.auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),
.auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),
.auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),
.auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),
.auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),
.auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),
.auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),
.auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),
.auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),
.auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),
.auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),
.auto_dest_nodes_in_3_flit_0_valid (auto_routers_dest_nodes_in_3_flit_0_valid),
.auto_dest_nodes_in_3_flit_0_bits_head (auto_routers_dest_nodes_in_3_flit_0_bits_head),
.auto_dest_nodes_in_3_flit_0_bits_tail (auto_routers_dest_nodes_in_3_flit_0_bits_tail),
.auto_dest_nodes_in_3_flit_0_bits_payload (auto_routers_dest_nodes_in_3_flit_0_bits_payload),
.auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_3_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_3_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_3_credit_return (auto_routers_dest_nodes_in_3_credit_return),
.auto_dest_nodes_in_3_vc_free (auto_routers_dest_nodes_in_3_vc_free),
.auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid),
.auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head),
.auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail),
.auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload),
.auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return),
.auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free),
.auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),
.auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),
.auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),
.auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),
.auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),
.auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),
.auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),
.auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),
.auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),
.auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),
.auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),
.auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_28 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_28
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_28
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h14))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_9 :
connect states[0].g, UInt<3>(0h2)
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_12 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_13 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_14 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_15 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_16 :
connect states[7].g, UInt<3>(0h2)
node _T_17 = and(io.router_req.ready, io.router_req.valid)
when _T_17 :
node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_18, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_29 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_30 = and(io.router_req.ready, io.router_req.valid)
when _T_30 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_32 = or(_T_31, vcalloc_vals[2])
node _T_33 = or(_T_32, vcalloc_vals[3])
node _T_34 = or(_T_33, vcalloc_vals[4])
node _T_35 = or(_T_34, vcalloc_vals[5])
node _T_36 = or(_T_35, vcalloc_vals[6])
node _T_37 = or(_T_36, vcalloc_vals[7])
when _T_37 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8]
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35
node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459)
node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460)
node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461)
node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462)
node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463)
node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464)
node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465)
wire _io_vcalloc_req_bits_WIRE_36 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472
connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477)
node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478)
node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479)
node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480)
wire _io_vcalloc_req_bits_WIRE_37 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487
connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495)
wire _io_vcalloc_req_bits_WIRE_38 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38
wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504)
node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505)
node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506)
node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507)
node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508)
node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509)
node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510)
wire _io_vcalloc_req_bits_WIRE_40 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517
connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40
node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519)
node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520)
node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521)
node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522)
node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523)
node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524)
node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525)
wire _io_vcalloc_req_bits_WIRE_41 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532
connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41
node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534)
node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535)
node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536)
node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537)
node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538)
node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539)
node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540)
wire _io_vcalloc_req_bits_WIRE_42 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547
connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42
node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549)
node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550)
node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551)
node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552)
node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553)
node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554)
node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555)
wire _io_vcalloc_req_bits_WIRE_43 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562
connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43
node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564)
node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565)
node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566)
node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567)
node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568)
node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569)
node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570)
wire _io_vcalloc_req_bits_WIRE_44 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577
connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_38 = bits(vcalloc_sel, 0, 0)
node _T_39 = and(vcalloc_vals[0], _T_38)
node _T_40 = and(_T_39, io.vcalloc_req.ready)
when _T_40 :
connect states[0].g, UInt<3>(0h3)
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_41 = bits(vcalloc_sel, 1, 1)
node _T_42 = and(vcalloc_vals[1], _T_41)
node _T_43 = and(_T_42, io.vcalloc_req.ready)
when _T_43 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_44 = bits(vcalloc_sel, 2, 2)
node _T_45 = and(vcalloc_vals[2], _T_44)
node _T_46 = and(_T_45, io.vcalloc_req.ready)
when _T_46 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_47 = bits(vcalloc_sel, 3, 3)
node _T_48 = and(vcalloc_vals[3], _T_47)
node _T_49 = and(_T_48, io.vcalloc_req.ready)
when _T_49 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_50 = bits(vcalloc_sel, 4, 4)
node _T_51 = and(vcalloc_vals[4], _T_50)
node _T_52 = and(_T_51, io.vcalloc_req.ready)
when _T_52 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_53 = bits(vcalloc_sel, 5, 5)
node _T_54 = and(vcalloc_vals[5], _T_53)
node _T_55 = and(_T_54, io.vcalloc_req.ready)
when _T_55 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_56 = bits(vcalloc_sel, 6, 6)
node _T_57 = and(vcalloc_vals[6], _T_56)
node _T_58 = and(_T_57, io.vcalloc_req.ready)
when _T_58 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_59 = bits(vcalloc_sel, 7, 7)
node _T_60 = and(vcalloc_vals[7], _T_59)
node _T_61 = and(_T_60, io.vcalloc_req.ready)
when _T_61 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_62 :
node _T_63 = bits(vcalloc_sel, 0, 0)
when _T_63 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_64 = eq(states[0].g, UInt<3>(0h2))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_64, UInt<1>(0h1), "") : assert_3
node _T_68 = bits(vcalloc_sel, 1, 1)
when _T_68 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_69 = eq(states[1].g, UInt<3>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_69, UInt<1>(0h1), "") : assert_4
node _T_73 = bits(vcalloc_sel, 2, 2)
when _T_73 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_74 = eq(states[2].g, UInt<3>(0h2))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = bits(vcalloc_sel, 3, 3)
when _T_78 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_79 = eq(states[3].g, UInt<3>(0h2))
node _T_80 = asUInt(reset)
node _T_81 = eq(_T_80, UInt<1>(0h0))
when _T_81 :
node _T_82 = eq(_T_79, UInt<1>(0h0))
when _T_82 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_79, UInt<1>(0h1), "") : assert_6
node _T_83 = bits(vcalloc_sel, 4, 4)
when _T_83 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_84 = eq(states[4].g, UInt<3>(0h2))
node _T_85 = asUInt(reset)
node _T_86 = eq(_T_85, UInt<1>(0h0))
when _T_86 :
node _T_87 = eq(_T_84, UInt<1>(0h0))
when _T_87 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_84, UInt<1>(0h1), "") : assert_7
node _T_88 = bits(vcalloc_sel, 5, 5)
when _T_88 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[5].g, UInt<3>(0h3)
node _T_89 = eq(states[5].g, UInt<3>(0h2))
node _T_90 = asUInt(reset)
node _T_91 = eq(_T_90, UInt<1>(0h0))
when _T_91 :
node _T_92 = eq(_T_89, UInt<1>(0h0))
when _T_92 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_89, UInt<1>(0h1), "") : assert_8
node _T_93 = bits(vcalloc_sel, 6, 6)
when _T_93 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[6].g, UInt<3>(0h3)
node _T_94 = eq(states[6].g, UInt<3>(0h2))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = bits(vcalloc_sel, 7, 7)
when _T_98 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[7].g, UInt<3>(0h3)
node _T_99 = eq(states[7].g, UInt<3>(0h2))
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_99, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_89
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0])
node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4])
node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6])
node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail)
when _T_104 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
node credit_available_lo_lo_8 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi_8 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi_8 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_lo_9 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node credit_available_lo_hi_9 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4])
node credit_available_hi_hi_9 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6])
node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11)
node credit_available_lo_lo_10 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node credit_available_lo_hi_10 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4])
node credit_available_hi_hi_10 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_lo_11 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0])
node credit_available_lo_hi_11 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4])
node credit_available_hi_hi_11 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13)
node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11)
node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15)
node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16)
node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18)
node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16)
node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18)
node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19)
node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20)
node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail)
when _T_106 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_16 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_16 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_16 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20)
node credit_available_lo_lo_17 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_17 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4])
node credit_available_hi_hi_17 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21)
node credit_available_lo_lo_18 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_18 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4])
node credit_available_hi_hi_18 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22)
node credit_available_lo_lo_19 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0])
node credit_available_lo_hi_19 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4])
node credit_available_hi_hi_19 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6])
node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23)
node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22)
node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24)
node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24)
node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28)
node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27)
node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29)
node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29)
node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31)
node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail)
when _T_108 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_24 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_24 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_24 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30)
node credit_available_lo_lo_25 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_25 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4])
node credit_available_hi_hi_25 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6])
node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31)
node credit_available_lo_lo_26 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_26 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4])
node credit_available_hi_hi_26 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6])
node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32)
node credit_available_lo_lo_27 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0])
node credit_available_lo_hi_27 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4])
node credit_available_hi_hi_27 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6])
node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33)
node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33)
node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35)
node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36)
node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37)
node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38)
node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38)
node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40)
node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39)
node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42)
node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail)
when _T_110 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_32 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_32 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_32 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40)
node credit_available_lo_lo_33 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_33 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_33 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41)
node credit_available_lo_lo_34 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_34 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_34 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42)
node credit_available_lo_lo_35 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0])
node credit_available_lo_hi_35 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2])
node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4])
node credit_available_hi_hi_35 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6])
node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43)
node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44)
node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44)
node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45)
node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46)
node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48)
node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49)
node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51)
node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49)
node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53)
node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail)
when _T_112 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_40 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_40 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_40 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50)
node credit_available_lo_lo_41 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_41 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_41 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51)
node credit_available_lo_lo_42 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_42 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42)
node credit_available_hi_lo_42 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_42 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42)
node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52)
node credit_available_lo_lo_43 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0])
node credit_available_lo_hi_43 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2])
node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43)
node credit_available_hi_lo_43 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4])
node credit_available_hi_hi_43 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6])
node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43)
node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53)
node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55)
node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57)
node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54)
node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44)
node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44)
node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55)
node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45)
node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45)
node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56)
node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46)
node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46)
node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57)
node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47)
node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47)
node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58)
node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60)
node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62)
node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59)
node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64)
node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail)
when _T_114 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_48 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_48 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48)
node credit_available_hi_lo_48 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_48 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48)
node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60)
node credit_available_lo_lo_49 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_49 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49)
node credit_available_hi_lo_49 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_49 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49)
node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61)
node credit_available_lo_lo_50 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_50 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50)
node credit_available_hi_lo_50 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_50 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50)
node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62)
node credit_available_lo_lo_51 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0])
node credit_available_lo_hi_51 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2])
node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51)
node credit_available_hi_lo_51 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4])
node credit_available_hi_hi_51 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6])
node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51)
node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63)
node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66)
node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68)
node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64)
node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52)
node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52)
node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65)
node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53)
node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53)
node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66)
node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54)
node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54)
node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67)
node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55)
node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55)
node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68)
node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71)
node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73)
node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69)
node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75)
node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail)
when _T_116 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_56 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_56 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_70 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56)
node credit_available_hi_lo_56 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_56 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_70 = cat(credit_available_hi_hi_56, credit_available_hi_lo_56)
node _credit_available_T_77 = cat(credit_available_hi_70, credit_available_lo_70)
node credit_available_lo_lo_57 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_57 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_71 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57)
node credit_available_hi_lo_57 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_57 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_71 = cat(credit_available_hi_hi_57, credit_available_hi_lo_57)
node _credit_available_T_78 = cat(credit_available_hi_71, credit_available_lo_71)
node credit_available_lo_lo_58 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_58 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_72 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58)
node credit_available_hi_lo_58 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_58 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_72 = cat(credit_available_hi_hi_58, credit_available_hi_lo_58)
node _credit_available_T_79 = cat(credit_available_hi_72, credit_available_lo_72)
node credit_available_lo_lo_59 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0])
node credit_available_lo_hi_59 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2])
node credit_available_lo_73 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59)
node credit_available_hi_lo_59 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4])
node credit_available_hi_hi_59 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6])
node credit_available_hi_73 = cat(credit_available_hi_hi_59, credit_available_hi_lo_59)
node _credit_available_T_80 = cat(credit_available_hi_73, credit_available_lo_73)
node credit_available_lo_74 = cat(_credit_available_T_78, _credit_available_T_77)
node credit_available_hi_74 = cat(_credit_available_T_80, _credit_available_T_79)
node _credit_available_T_81 = cat(credit_available_hi_74, credit_available_lo_74)
node credit_available_lo_lo_60 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_60 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_75 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60)
node credit_available_hi_lo_60 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_60 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_75 = cat(credit_available_hi_hi_60, credit_available_hi_lo_60)
node _credit_available_T_82 = cat(credit_available_hi_75, credit_available_lo_75)
node credit_available_lo_lo_61 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_61 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_76 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61)
node credit_available_hi_lo_61 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_61 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_76 = cat(credit_available_hi_hi_61, credit_available_hi_lo_61)
node _credit_available_T_83 = cat(credit_available_hi_76, credit_available_lo_76)
node credit_available_lo_lo_62 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_62 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_77 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62)
node credit_available_hi_lo_62 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_62 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_77 = cat(credit_available_hi_hi_62, credit_available_hi_lo_62)
node _credit_available_T_84 = cat(credit_available_hi_77, credit_available_lo_77)
node credit_available_lo_lo_63 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_63 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_78 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63)
node credit_available_hi_lo_63 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_63 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_78 = cat(credit_available_hi_hi_63, credit_available_hi_lo_63)
node _credit_available_T_85 = cat(credit_available_hi_78, credit_available_lo_78)
node credit_available_lo_79 = cat(_credit_available_T_83, _credit_available_T_82)
node credit_available_hi_79 = cat(_credit_available_T_85, _credit_available_T_84)
node _credit_available_T_86 = cat(credit_available_hi_79, credit_available_lo_79)
node _credit_available_T_87 = and(_credit_available_T_81, _credit_available_T_86)
node credit_available_7 = neq(_credit_available_T_87, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail)
when _T_118 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
wire _vc_sel_WIRE_27 : UInt<1>[8]
node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369)
node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370)
node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371)
node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372)
node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373)
node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375)
wire _vc_sel_WIRE_28 : UInt<1>
connect _vc_sel_WIRE_28, _vc_sel_T_382
connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28
node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384)
node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385)
node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386)
node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387)
node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388)
node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389)
node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390)
wire _vc_sel_WIRE_29 : UInt<1>
connect _vc_sel_WIRE_29, _vc_sel_T_397
connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29
node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399)
node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400)
node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401)
node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402)
node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403)
node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404)
node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405)
wire _vc_sel_WIRE_30 : UInt<1>
connect _vc_sel_WIRE_30, _vc_sel_T_412
connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30
node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414)
node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415)
node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416)
node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417)
node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418)
node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419)
node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420)
wire _vc_sel_WIRE_31 : UInt<1>
connect _vc_sel_WIRE_31, _vc_sel_T_427
connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31
node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429)
node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430)
node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431)
node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432)
node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433)
node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434)
node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435)
wire _vc_sel_WIRE_32 : UInt<1>
connect _vc_sel_WIRE_32, _vc_sel_T_442
connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32
node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444)
node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445)
node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446)
node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447)
node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448)
node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449)
node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450)
wire _vc_sel_WIRE_33 : UInt<1>
connect _vc_sel_WIRE_33, _vc_sel_T_457
connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33
node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459)
node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460)
node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461)
node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462)
node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463)
node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464)
node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465)
wire _vc_sel_WIRE_34 : UInt<1>
connect _vc_sel_WIRE_34, _vc_sel_T_472
connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34
node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474)
node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475)
node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476)
node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477)
node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478)
node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479)
node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480)
wire _vc_sel_WIRE_35 : UInt<1>
connect _vc_sel_WIRE_35, _vc_sel_T_487
connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35
connect vc_sel.`3`, _vc_sel_WIRE_27
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2])
node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3])
node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4])
node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5])
node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6])
node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2])
node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3)
node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4])
node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6])
node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3)
node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9)
node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4)
node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0)
node _virt_channel_T_25 = orr(virt_channel_hi_10)
node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10)
node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2)
node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0)
node _virt_channel_T_27 = orr(virt_channel_hi_11)
node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11)
node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1)
node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29)
node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30)
node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0))
node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33)
node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34)
node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_38
node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_119 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[0], UInt<1>(0h0)
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`0`[3], UInt<1>(0h0)
connect states[0].vc_sel.`0`[4], UInt<1>(0h0)
connect states[0].vc_sel.`0`[5], UInt<1>(0h0)
connect states[0].vc_sel.`0`[6], UInt<1>(0h0)
connect states[0].vc_sel.`0`[7], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[2], UInt<1>(0h0)
connect states[0].vc_sel.`1`[3], UInt<1>(0h0)
connect states[0].vc_sel.`1`[4], UInt<1>(0h0)
connect states[0].vc_sel.`1`[5], UInt<1>(0h0)
connect states[0].vc_sel.`1`[6], UInt<1>(0h0)
connect states[0].vc_sel.`1`[7], UInt<1>(0h0)
connect states[0].vc_sel.`3`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[1], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`0`[3], UInt<1>(0h0)
connect states[1].vc_sel.`0`[4], UInt<1>(0h0)
connect states[1].vc_sel.`0`[5], UInt<1>(0h0)
connect states[1].vc_sel.`0`[6], UInt<1>(0h0)
connect states[1].vc_sel.`0`[7], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[1], UInt<1>(0h0)
connect states[1].vc_sel.`1`[2], UInt<1>(0h0)
connect states[1].vc_sel.`1`[3], UInt<1>(0h0)
connect states[1].vc_sel.`1`[4], UInt<1>(0h0)
connect states[1].vc_sel.`1`[5], UInt<1>(0h0)
connect states[1].vc_sel.`1`[6], UInt<1>(0h0)
connect states[1].vc_sel.`1`[7], UInt<1>(0h0)
connect states[1].vc_sel.`3`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[4], UInt<1>(0h0)
connect states[2].vc_sel.`0`[5], UInt<1>(0h0)
connect states[2].vc_sel.`0`[6], UInt<1>(0h0)
connect states[2].vc_sel.`0`[7], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`1`[3], UInt<1>(0h0)
connect states[2].vc_sel.`1`[4], UInt<1>(0h0)
connect states[2].vc_sel.`1`[5], UInt<1>(0h0)
connect states[2].vc_sel.`1`[6], UInt<1>(0h0)
connect states[2].vc_sel.`1`[7], UInt<1>(0h0)
connect states[2].vc_sel.`3`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[3], UInt<1>(0h0)
connect states[3].vc_sel.`0`[4], UInt<1>(0h0)
connect states[3].vc_sel.`0`[5], UInt<1>(0h0)
connect states[3].vc_sel.`0`[6], UInt<1>(0h0)
connect states[3].vc_sel.`0`[7], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[1], UInt<1>(0h0)
connect states[3].vc_sel.`1`[2], UInt<1>(0h0)
connect states[3].vc_sel.`1`[3], UInt<1>(0h0)
connect states[3].vc_sel.`1`[4], UInt<1>(0h0)
connect states[3].vc_sel.`1`[5], UInt<1>(0h0)
connect states[3].vc_sel.`1`[6], UInt<1>(0h0)
connect states[3].vc_sel.`1`[7], UInt<1>(0h0)
connect states[3].vc_sel.`3`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[6], UInt<1>(0h0)
connect states[4].vc_sel.`0`[7], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`1`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[4], UInt<1>(0h0)
connect states[4].vc_sel.`3`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[4], UInt<1>(0h0)
connect states[5].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[6], UInt<1>(0h0)
connect states[5].vc_sel.`0`[7], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[1], UInt<1>(0h0)
connect states[5].vc_sel.`1`[2], UInt<1>(0h0)
connect states[5].vc_sel.`1`[3], UInt<1>(0h0)
connect states[5].vc_sel.`1`[4], UInt<1>(0h0)
connect states[5].vc_sel.`3`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[4], UInt<1>(0h0)
connect states[6].vc_sel.`0`[5], UInt<1>(0h0)
connect states[6].vc_sel.`0`[6], UInt<1>(0h0)
connect states[6].vc_sel.`0`[7], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[1], UInt<1>(0h0)
connect states[6].vc_sel.`1`[2], UInt<1>(0h0)
connect states[6].vc_sel.`1`[3], UInt<1>(0h0)
connect states[6].vc_sel.`1`[4], UInt<1>(0h0)
connect states[6].vc_sel.`3`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[4], UInt<1>(0h0)
connect states[7].vc_sel.`0`[5], UInt<1>(0h0)
connect states[7].vc_sel.`0`[6], UInt<1>(0h0)
connect states[7].vc_sel.`0`[7], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[1], UInt<1>(0h0)
connect states[7].vc_sel.`1`[2], UInt<1>(0h0)
connect states[7].vc_sel.`1`[3], UInt<1>(0h0)
connect states[7].vc_sel.`1`[4], UInt<1>(0h0)
connect states[7].vc_sel.`3`[0], UInt<1>(0h0)
node _T_120 = asUInt(reset)
when _T_120 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_28( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module PE :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_56 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_72
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_56( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_72 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_7 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_263
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_7( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_263 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_141 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1)
node _T_45 = and(io.wakeup_ports[2].valid, _T_44)
when _T_45 :
connect p1, UInt<1>(0h1)
node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2)
node _T_47 = and(io.wakeup_ports[2].valid, _T_46)
when _T_47 :
connect p2, UInt<1>(0h1)
node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3)
node _T_49 = and(io.wakeup_ports[2].valid, _T_48)
when _T_49 :
connect p3, UInt<1>(0h1)
node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1)
node _T_51 = and(io.wakeup_ports[3].valid, _T_50)
when _T_51 :
connect p1, UInt<1>(0h1)
node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2)
node _T_53 = and(io.wakeup_ports[3].valid, _T_52)
when _T_53 :
connect p2, UInt<1>(0h1)
node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3)
node _T_55 = and(io.wakeup_ports[3].valid, _T_54)
when _T_55 :
connect p3, UInt<1>(0h1)
node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1)
node _T_57 = and(io.wakeup_ports[4].valid, _T_56)
when _T_57 :
connect p1, UInt<1>(0h1)
node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2)
node _T_59 = and(io.wakeup_ports[4].valid, _T_58)
when _T_59 :
connect p2, UInt<1>(0h1)
node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3)
node _T_61 = and(io.wakeup_ports[4].valid, _T_60)
when _T_61 :
connect p3, UInt<1>(0h1)
node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1)
node _T_63 = and(io.wakeup_ports[5].valid, _T_62)
when _T_63 :
connect p1, UInt<1>(0h1)
node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2)
node _T_65 = and(io.wakeup_ports[5].valid, _T_64)
when _T_65 :
connect p2, UInt<1>(0h1)
node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3)
node _T_67 = and(io.wakeup_ports[5].valid, _T_66)
when _T_67 :
connect p3, UInt<1>(0h1)
node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1)
node _T_69 = and(io.wakeup_ports[6].valid, _T_68)
when _T_69 :
connect p1, UInt<1>(0h1)
node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2)
node _T_71 = and(io.wakeup_ports[6].valid, _T_70)
when _T_71 :
connect p2, UInt<1>(0h1)
node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3)
node _T_73 = and(io.wakeup_ports[6].valid, _T_72)
when _T_73 :
connect p3, UInt<1>(0h1)
node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_75 = and(io.pred_wakeup_port.valid, _T_74)
when _T_75 :
connect ppred, UInt<1>(0h1)
node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82)
node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
when _T_85 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_86, UInt<1>(0h1), "") : assert_4
node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90)
node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_93 = and(_T_91, _T_92)
when _T_93 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_94, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect next_state, UInt<2>(0h0)
node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_100 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_101 = eq(state, UInt<2>(0h1))
when _T_101 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_102 = eq(state, UInt<2>(0h2))
when _T_102 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_103 = eq(state, UInt<2>(0h2))
when _T_103 :
node _T_104 = and(p1, p2)
node _T_105 = and(_T_104, ppred)
when _T_105 :
skip
else :
node _T_106 = and(p1, ppred)
when _T_106 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_107 = and(p2, ppred)
when _T_107 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_141( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e8_s24_i32_6 :
input clock : Clock
input reset : Reset
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node magGeOne = bits(rawIn.sExp, 8, 8)
node posExp = bits(rawIn.sExp, 7, 0)
node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0))
node _magJustBelowOne_T_1 = andr(posExp)
node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1)
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _shiftedSig_T = bits(rawIn.sig, 22, 0)
node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T)
node _shiftedSig_T_2 = bits(rawIn.sExp, 4, 0)
node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0))
node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3)
node _alignedSig_T = shr(shiftedSig, 22)
node _alignedSig_T_1 = bits(shiftedSig, 21, 0)
node _alignedSig_T_2 = orr(_alignedSig_T_1)
node alignedSig = cat(_alignedSig_T, _alignedSig_T_2)
node _unroundedInt_T = shr(alignedSig, 2)
node unroundedInt = or(UInt<32>(0h0), _unroundedInt_T)
node _common_inexact_T = bits(alignedSig, 1, 0)
node _common_inexact_T_1 = orr(_common_inexact_T)
node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0))
node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2)
node _roundIncr_near_even_T = bits(alignedSig, 2, 1)
node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T)
node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0)
node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2)
node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3)
node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4)
node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0)
node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6)
node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7)
node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8)
node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1)
node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T)
node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne)
node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even)
node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag)
node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1)
node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd)
node _roundIncr_T_4 = and(rawIn.sign, common_inexact)
node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4)
node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5)
node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0))
node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact)
node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8)
node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9)
node _complUnroundedInt_T = not(unroundedInt)
node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt)
node _roundedInt_T = xor(roundIncr, rawIn.sign)
node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1))
node _roundedInt_T_2 = tail(_roundedInt_T_1, 1)
node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt)
node _roundedInt_T_4 = and(roundingMode_odd, common_inexact)
node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4)
node magGeOne_atOverflowEdge = eq(posExp, UInt<5>(0h1f))
node _roundCarryBut2_T = bits(unroundedInt, 29, 0)
node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T)
node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr)
node _common_overflow_T = geq(posExp, UInt<6>(0h20))
node _common_overflow_T_1 = bits(unroundedInt, 30, 0)
node _common_overflow_T_2 = orr(_common_overflow_T_1)
node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr)
node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3)
node _common_overflow_T_5 = eq(posExp, UInt<5>(0h1e))
node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2)
node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6)
node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7)
node _common_overflow_T_9 = bits(unroundedInt, 30, 30)
node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9)
node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2)
node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11)
node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12)
node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13)
node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0))
node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign)
node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr)
node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17)
node invalidExc = or(rawIn.isNaN, rawIn.isInf)
node _overflow_T = eq(invalidExc, UInt<1>(0h0))
node overflow = and(_overflow_T, common_overflow)
node _inexact_T = eq(invalidExc, UInt<1>(0h0))
node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0))
node _inexact_T_2 = and(_inexact_T, _inexact_T_1)
node inexact = and(_inexact_T_2, common_inexact)
node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0))
node excSign = and(_excSign_T, rawIn.sign)
node _excOut_T = eq(io.signedOut, excSign)
node _excOut_T_1 = mux(_excOut_T, UInt<32>(0h80000000), UInt<1>(0h0))
node _excOut_T_2 = eq(excSign, UInt<1>(0h0))
node _excOut_T_3 = mux(_excOut_T_2, UInt<31>(0h7fffffff), UInt<1>(0h0))
node excOut = or(_excOut_T_1, _excOut_T_3)
node _io_out_T = or(invalidExc, common_overflow)
node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt)
connect io.out, _io_out_T_1
node _io_intExceptionFlags_T = cat(invalidExc, overflow)
node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact)
connect io.intExceptionFlags, _io_intExceptionFlags_T_1 | module RecFNToIN_e8_s24_i32_6( // @[RecFNToIN.scala:46:7]
input clock, // @[RecFNToIN.scala:46:7]
input reset, // @[RecFNToIN.scala:46:7]
input [32:0] io_in, // @[RecFNToIN.scala:49:16]
output [31:0] io_out, // @[RecFNToIN.scala:49:16]
output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7]
wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53]
wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53]
wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53]
wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53]
wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53]
wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35]
wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28]
wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49]
wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27]
wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31]
wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13]
wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27]
wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41]
wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7]
wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7]
wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18]
wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52]
wire [31:0] io_out_0; // @[RecFNToIN.scala:46:7]
wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27]
wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47]
wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}]
wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}]
wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27]
wire [54:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16]
wire [32:0] _alignedSig_T = shiftedSig[54:22]; // @[RecFNToIN.scala:83:49, :89:20]
wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51]
wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}]
wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}]
wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52]
wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}]
wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50]
wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64]
wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39]
wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}]
wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}]
wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39]
wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}]
wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}]
wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}]
wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}]
wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}]
wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}]
wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26]
wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35]
wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56]
wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}]
wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}]
wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}]
wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61]
wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23]
wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46]
wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}]
wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45]
wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23]
wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31]
wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31]
wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31]
wire [31:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11]
wire magGeOne_atOverflowEdge = posExp == 8'h1F; // @[RecFNToIN.scala:62:28, :110:43]
wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38]
wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}]
wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}]
wire _common_overflow_T = |(posExp[7:5]); // @[RecFNToIN.scala:62:28, :116:21]
wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42]
wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}]
wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}]
wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64]
wire _common_overflow_T_5 = posExp == 8'h1E; // @[RecFNToIN.scala:62:28, :122:38]
wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}]
wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60]
wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24]
wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42]
wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42]
wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57]
wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20]
wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36]
wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20]
wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}]
wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20]
wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35]
wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}]
wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}]
wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27]
wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}]
wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13]
wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}]
wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12]
wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30]
assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}]
assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18]
wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40]
assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}]
assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52]
assign io_out = io_out_0; // @[RecFNToIN.scala:46:7]
assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_50 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
node _T_9 = or(_T_8, prs1_wakeups_4)
when _T_9 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3)
node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3)
node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_11 = or(_T_10, prs1_rebusys_2)
node _T_12 = or(_T_11, prs1_rebusys_3)
node _T_13 = or(_T_12, prs1_rebusys_4)
node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = or(_T_13, _T_15)
node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_20 = or(_T_19, prs2_wakeups_2)
node _T_21 = or(_T_20, prs2_wakeups_3)
node _T_22 = or(_T_21, prs2_wakeups_4)
when _T_22 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3)
node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3)
node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_24 = or(_T_23, prs2_rebusys_2)
node _T_25 = or(_T_24, prs2_rebusys_3)
node _T_26 = or(_T_25, prs2_rebusys_4)
node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_28 = neq(_T_27, UInt<1>(0h0))
node _T_29 = or(_T_26, _T_28)
node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_31 = and(_T_29, _T_30)
when _T_31 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_33 = or(_T_32, prs3_wakeups_2)
node _T_34 = or(_T_33, prs3_wakeups_3)
node _T_35 = or(_T_34, prs3_wakeups_4)
when _T_35 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3)
node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_37 = and(io.pred_wakeup_port.valid, _T_36)
when _T_37 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_40 = and(slot_valid, slot_uop.iw_issued)
when _T_40 :
connect next_valid, rebusied | module IssueSlot_50( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_314 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_314( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_9 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_9( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_148 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_165
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_148( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_165 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_205 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_205( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[8]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6])
node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = and(_T_11, _T_24)
node _T_89 = and(_T_88, _T_37)
node _T_90 = and(_T_89, _T_50)
node _T_91 = and(_T_90, _T_63)
node _T_92 = and(_T_91, _T_71)
node _T_93 = and(_T_92, _T_79)
node _T_94 = and(_T_93, _T_87)
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_94, UInt<1>(0h1), "") : assert_1
node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_98 :
node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_103 = shr(io.in.a.bits.source, 2)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_106 = and(_T_104, _T_105)
node _T_107 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_108 = and(_T_106, _T_107)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_109 = shr(io.in.a.bits.source, 2)
node _T_110 = eq(_T_109, UInt<1>(0h1))
node _T_111 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_112 = and(_T_110, _T_111)
node _T_113 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_114 = and(_T_112, _T_113)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_115 = shr(io.in.a.bits.source, 2)
node _T_116 = eq(_T_115, UInt<2>(0h2))
node _T_117 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_118 = and(_T_116, _T_117)
node _T_119 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_120 = and(_T_118, _T_119)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_121 = shr(io.in.a.bits.source, 2)
node _T_122 = eq(_T_121, UInt<2>(0h3))
node _T_123 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_124 = and(_T_122, _T_123)
node _T_125 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_130 = or(_T_102, _T_108)
node _T_131 = or(_T_130, _T_114)
node _T_132 = or(_T_131, _T_120)
node _T_133 = or(_T_132, _T_126)
node _T_134 = or(_T_133, _T_127)
node _T_135 = or(_T_134, _T_128)
node _T_136 = or(_T_135, _T_129)
node _T_137 = and(_T_101, _T_136)
node _T_138 = or(UInt<1>(0h0), _T_137)
node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_140 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<13>(0h1000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = and(_T_139, _T_144)
node _T_146 = or(UInt<1>(0h0), _T_145)
node _T_147 = and(_T_138, _T_146)
node _T_148 = asUInt(reset)
node _T_149 = eq(_T_148, UInt<1>(0h0))
when _T_149 :
node _T_150 = eq(_T_147, UInt<1>(0h0))
when _T_150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_147, UInt<1>(0h1), "") : assert_2
node _T_151 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_152 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_153 = and(_T_151, _T_152)
node _T_154 = or(UInt<1>(0h0), _T_153)
node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_156 = cvt(_T_155)
node _T_157 = and(_T_156, asSInt(UInt<13>(0h1000)))
node _T_158 = asSInt(_T_157)
node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0)))
node _T_160 = and(_T_154, _T_159)
node _T_161 = or(UInt<1>(0h0), _T_160)
node _T_162 = and(UInt<1>(0h0), _T_161)
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_162, UInt<1>(0h1), "") : assert_3
node _T_166 = asUInt(reset)
node _T_167 = eq(_T_166, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(source_ok, UInt<1>(0h0))
when _T_168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_169 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_169, UInt<1>(0h1), "") : assert_5
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(is_aligned, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_176 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_176, UInt<1>(0h1), "") : assert_7
node _T_180 = not(io.in.a.bits.mask)
node _T_181 = eq(_T_180, UInt<1>(0h0))
node _T_182 = asUInt(reset)
node _T_183 = eq(_T_182, UInt<1>(0h0))
when _T_183 :
node _T_184 = eq(_T_181, UInt<1>(0h0))
when _T_184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_181, UInt<1>(0h1), "") : assert_8
node _T_185 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_185, UInt<1>(0h1), "") : assert_9
node _T_189 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_189 :
node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_192 = and(_T_190, _T_191)
node _T_193 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_194 = shr(io.in.a.bits.source, 2)
node _T_195 = eq(_T_194, UInt<1>(0h0))
node _T_196 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_197 = and(_T_195, _T_196)
node _T_198 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_199 = and(_T_197, _T_198)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_200 = shr(io.in.a.bits.source, 2)
node _T_201 = eq(_T_200, UInt<1>(0h1))
node _T_202 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_203 = and(_T_201, _T_202)
node _T_204 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_205 = and(_T_203, _T_204)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_206 = shr(io.in.a.bits.source, 2)
node _T_207 = eq(_T_206, UInt<2>(0h2))
node _T_208 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_209 = and(_T_207, _T_208)
node _T_210 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_211 = and(_T_209, _T_210)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_212 = shr(io.in.a.bits.source, 2)
node _T_213 = eq(_T_212, UInt<2>(0h3))
node _T_214 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_215 = and(_T_213, _T_214)
node _T_216 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_220 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_221 = or(_T_193, _T_199)
node _T_222 = or(_T_221, _T_205)
node _T_223 = or(_T_222, _T_211)
node _T_224 = or(_T_223, _T_217)
node _T_225 = or(_T_224, _T_218)
node _T_226 = or(_T_225, _T_219)
node _T_227 = or(_T_226, _T_220)
node _T_228 = and(_T_192, _T_227)
node _T_229 = or(UInt<1>(0h0), _T_228)
node _T_230 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_231 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = and(_T_230, _T_235)
node _T_237 = or(UInt<1>(0h0), _T_236)
node _T_238 = and(_T_229, _T_237)
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(_T_238, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_238, UInt<1>(0h1), "") : assert_10
node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_244 = and(_T_242, _T_243)
node _T_245 = or(UInt<1>(0h0), _T_244)
node _T_246 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = and(_T_245, _T_250)
node _T_252 = or(UInt<1>(0h0), _T_251)
node _T_253 = and(UInt<1>(0h0), _T_252)
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_253, UInt<1>(0h1), "") : assert_11
node _T_257 = asUInt(reset)
node _T_258 = eq(_T_257, UInt<1>(0h0))
when _T_258 :
node _T_259 = eq(source_ok, UInt<1>(0h0))
when _T_259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_260 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_260, UInt<1>(0h1), "") : assert_13
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(is_aligned, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_267 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_267, UInt<1>(0h1), "") : assert_15
node _T_271 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_272 = asUInt(reset)
node _T_273 = eq(_T_272, UInt<1>(0h0))
when _T_273 :
node _T_274 = eq(_T_271, UInt<1>(0h0))
when _T_274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_271, UInt<1>(0h1), "") : assert_16
node _T_275 = not(io.in.a.bits.mask)
node _T_276 = eq(_T_275, UInt<1>(0h0))
node _T_277 = asUInt(reset)
node _T_278 = eq(_T_277, UInt<1>(0h0))
when _T_278 :
node _T_279 = eq(_T_276, UInt<1>(0h0))
when _T_279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_276, UInt<1>(0h1), "") : assert_17
node _T_280 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_281 = asUInt(reset)
node _T_282 = eq(_T_281, UInt<1>(0h0))
when _T_282 :
node _T_283 = eq(_T_280, UInt<1>(0h0))
when _T_283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_280, UInt<1>(0h1), "") : assert_18
node _T_284 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_284 :
node _T_285 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_286 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_287 = and(_T_285, _T_286)
node _T_288 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_289 = shr(io.in.a.bits.source, 2)
node _T_290 = eq(_T_289, UInt<1>(0h0))
node _T_291 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_292 = and(_T_290, _T_291)
node _T_293 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_294 = and(_T_292, _T_293)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_295 = shr(io.in.a.bits.source, 2)
node _T_296 = eq(_T_295, UInt<1>(0h1))
node _T_297 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_298 = and(_T_296, _T_297)
node _T_299 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_300 = and(_T_298, _T_299)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_301 = shr(io.in.a.bits.source, 2)
node _T_302 = eq(_T_301, UInt<2>(0h2))
node _T_303 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_304 = and(_T_302, _T_303)
node _T_305 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_306 = and(_T_304, _T_305)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_307 = shr(io.in.a.bits.source, 2)
node _T_308 = eq(_T_307, UInt<2>(0h3))
node _T_309 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_310 = and(_T_308, _T_309)
node _T_311 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_312 = and(_T_310, _T_311)
node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_315 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_316 = or(_T_288, _T_294)
node _T_317 = or(_T_316, _T_300)
node _T_318 = or(_T_317, _T_306)
node _T_319 = or(_T_318, _T_312)
node _T_320 = or(_T_319, _T_313)
node _T_321 = or(_T_320, _T_314)
node _T_322 = or(_T_321, _T_315)
node _T_323 = and(_T_287, _T_322)
node _T_324 = or(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_324, UInt<1>(0h1), "") : assert_19
node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_329 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_330 = and(_T_328, _T_329)
node _T_331 = or(UInt<1>(0h0), _T_330)
node _T_332 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = and(_T_331, _T_336)
node _T_338 = or(UInt<1>(0h0), _T_337)
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_338, UInt<1>(0h1), "") : assert_20
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(source_ok, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_345 = asUInt(reset)
node _T_346 = eq(_T_345, UInt<1>(0h0))
when _T_346 :
node _T_347 = eq(is_aligned, UInt<1>(0h0))
when _T_347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_348 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_349 = asUInt(reset)
node _T_350 = eq(_T_349, UInt<1>(0h0))
when _T_350 :
node _T_351 = eq(_T_348, UInt<1>(0h0))
when _T_351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_348, UInt<1>(0h1), "") : assert_23
node _T_352 = eq(io.in.a.bits.mask, mask)
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_352, UInt<1>(0h1), "") : assert_24
node _T_356 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_356, UInt<1>(0h1), "") : assert_25
node _T_360 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_360 :
node _T_361 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_362 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_365 = shr(io.in.a.bits.source, 2)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_368 = and(_T_366, _T_367)
node _T_369 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_370 = and(_T_368, _T_369)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_371 = shr(io.in.a.bits.source, 2)
node _T_372 = eq(_T_371, UInt<1>(0h1))
node _T_373 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_374 = and(_T_372, _T_373)
node _T_375 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_376 = and(_T_374, _T_375)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_377 = shr(io.in.a.bits.source, 2)
node _T_378 = eq(_T_377, UInt<2>(0h2))
node _T_379 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_380 = and(_T_378, _T_379)
node _T_381 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_382 = and(_T_380, _T_381)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_383 = shr(io.in.a.bits.source, 2)
node _T_384 = eq(_T_383, UInt<2>(0h3))
node _T_385 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_386 = and(_T_384, _T_385)
node _T_387 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_388 = and(_T_386, _T_387)
node _T_389 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_390 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_391 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_392 = or(_T_364, _T_370)
node _T_393 = or(_T_392, _T_376)
node _T_394 = or(_T_393, _T_382)
node _T_395 = or(_T_394, _T_388)
node _T_396 = or(_T_395, _T_389)
node _T_397 = or(_T_396, _T_390)
node _T_398 = or(_T_397, _T_391)
node _T_399 = and(_T_363, _T_398)
node _T_400 = or(UInt<1>(0h0), _T_399)
node _T_401 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_402 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_403 = and(_T_401, _T_402)
node _T_404 = or(UInt<1>(0h0), _T_403)
node _T_405 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_406 = cvt(_T_405)
node _T_407 = and(_T_406, asSInt(UInt<13>(0h1000)))
node _T_408 = asSInt(_T_407)
node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0)))
node _T_410 = and(_T_404, _T_409)
node _T_411 = or(UInt<1>(0h0), _T_410)
node _T_412 = and(_T_400, _T_411)
node _T_413 = asUInt(reset)
node _T_414 = eq(_T_413, UInt<1>(0h0))
when _T_414 :
node _T_415 = eq(_T_412, UInt<1>(0h0))
when _T_415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_412, UInt<1>(0h1), "") : assert_26
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(source_ok, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(is_aligned, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_422 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_422, UInt<1>(0h1), "") : assert_29
node _T_426 = eq(io.in.a.bits.mask, mask)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_426, UInt<1>(0h1), "") : assert_30
node _T_430 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_430 :
node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_432 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_435 = shr(io.in.a.bits.source, 2)
node _T_436 = eq(_T_435, UInt<1>(0h0))
node _T_437 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_438 = and(_T_436, _T_437)
node _T_439 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_440 = and(_T_438, _T_439)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_441 = shr(io.in.a.bits.source, 2)
node _T_442 = eq(_T_441, UInt<1>(0h1))
node _T_443 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_444 = and(_T_442, _T_443)
node _T_445 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_446 = and(_T_444, _T_445)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_447 = shr(io.in.a.bits.source, 2)
node _T_448 = eq(_T_447, UInt<2>(0h2))
node _T_449 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_450 = and(_T_448, _T_449)
node _T_451 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_452 = and(_T_450, _T_451)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_453 = shr(io.in.a.bits.source, 2)
node _T_454 = eq(_T_453, UInt<2>(0h3))
node _T_455 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_456 = and(_T_454, _T_455)
node _T_457 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_461 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_462 = or(_T_434, _T_440)
node _T_463 = or(_T_462, _T_446)
node _T_464 = or(_T_463, _T_452)
node _T_465 = or(_T_464, _T_458)
node _T_466 = or(_T_465, _T_459)
node _T_467 = or(_T_466, _T_460)
node _T_468 = or(_T_467, _T_461)
node _T_469 = and(_T_433, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_472 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_473 = and(_T_471, _T_472)
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_476 = cvt(_T_475)
node _T_477 = and(_T_476, asSInt(UInt<13>(0h1000)))
node _T_478 = asSInt(_T_477)
node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0)))
node _T_480 = and(_T_474, _T_479)
node _T_481 = or(UInt<1>(0h0), _T_480)
node _T_482 = and(_T_470, _T_481)
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_482, UInt<1>(0h1), "") : assert_31
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(source_ok, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(is_aligned, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_492, UInt<1>(0h1), "") : assert_34
node _T_496 = not(mask)
node _T_497 = and(io.in.a.bits.mask, _T_496)
node _T_498 = eq(_T_497, UInt<1>(0h0))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_498, UInt<1>(0h1), "") : assert_35
node _T_502 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_502 :
node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_504 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_505 = and(_T_503, _T_504)
node _T_506 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<1>(0h0))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<1>(0h1))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_519 = shr(io.in.a.bits.source, 2)
node _T_520 = eq(_T_519, UInt<2>(0h2))
node _T_521 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_522 = and(_T_520, _T_521)
node _T_523 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_524 = and(_T_522, _T_523)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_525 = shr(io.in.a.bits.source, 2)
node _T_526 = eq(_T_525, UInt<2>(0h3))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_530 = and(_T_528, _T_529)
node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_533 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_534 = or(_T_506, _T_512)
node _T_535 = or(_T_534, _T_518)
node _T_536 = or(_T_535, _T_524)
node _T_537 = or(_T_536, _T_530)
node _T_538 = or(_T_537, _T_531)
node _T_539 = or(_T_538, _T_532)
node _T_540 = or(_T_539, _T_533)
node _T_541 = and(_T_505, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_544 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = and(_T_543, _T_548)
node _T_550 = or(UInt<1>(0h0), _T_549)
node _T_551 = and(_T_542, _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_551, UInt<1>(0h1), "") : assert_36
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(source_ok, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_558 = asUInt(reset)
node _T_559 = eq(_T_558, UInt<1>(0h0))
when _T_559 :
node _T_560 = eq(is_aligned, UInt<1>(0h0))
when _T_560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_561 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(_T_561, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_561, UInt<1>(0h1), "") : assert_39
node _T_565 = eq(io.in.a.bits.mask, mask)
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(_T_565, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_565, UInt<1>(0h1), "") : assert_40
node _T_569 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_569 :
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_572 = and(_T_570, _T_571)
node _T_573 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_574 = shr(io.in.a.bits.source, 2)
node _T_575 = eq(_T_574, UInt<1>(0h0))
node _T_576 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_577 = and(_T_575, _T_576)
node _T_578 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_579 = and(_T_577, _T_578)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_580 = shr(io.in.a.bits.source, 2)
node _T_581 = eq(_T_580, UInt<1>(0h1))
node _T_582 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_583 = and(_T_581, _T_582)
node _T_584 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_585 = and(_T_583, _T_584)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_586 = shr(io.in.a.bits.source, 2)
node _T_587 = eq(_T_586, UInt<2>(0h2))
node _T_588 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_589 = and(_T_587, _T_588)
node _T_590 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_591 = and(_T_589, _T_590)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_592 = shr(io.in.a.bits.source, 2)
node _T_593 = eq(_T_592, UInt<2>(0h3))
node _T_594 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_595 = and(_T_593, _T_594)
node _T_596 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_597 = and(_T_595, _T_596)
node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_601 = or(_T_573, _T_579)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_591)
node _T_604 = or(_T_603, _T_597)
node _T_605 = or(_T_604, _T_598)
node _T_606 = or(_T_605, _T_599)
node _T_607 = or(_T_606, _T_600)
node _T_608 = and(_T_572, _T_607)
node _T_609 = or(UInt<1>(0h0), _T_608)
node _T_610 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_611 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_612 = cvt(_T_611)
node _T_613 = and(_T_612, asSInt(UInt<13>(0h1000)))
node _T_614 = asSInt(_T_613)
node _T_615 = eq(_T_614, asSInt(UInt<1>(0h0)))
node _T_616 = and(_T_610, _T_615)
node _T_617 = or(UInt<1>(0h0), _T_616)
node _T_618 = and(_T_609, _T_617)
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_618, UInt<1>(0h1), "") : assert_41
node _T_622 = asUInt(reset)
node _T_623 = eq(_T_622, UInt<1>(0h0))
when _T_623 :
node _T_624 = eq(source_ok, UInt<1>(0h0))
when _T_624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_625 = asUInt(reset)
node _T_626 = eq(_T_625, UInt<1>(0h0))
when _T_626 :
node _T_627 = eq(is_aligned, UInt<1>(0h0))
when _T_627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_628 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_628, UInt<1>(0h1), "") : assert_44
node _T_632 = eq(io.in.a.bits.mask, mask)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_632, UInt<1>(0h1), "") : assert_45
node _T_636 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_636 :
node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_638 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_639 = and(_T_637, _T_638)
node _T_640 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_641 = shr(io.in.a.bits.source, 2)
node _T_642 = eq(_T_641, UInt<1>(0h0))
node _T_643 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_644 = and(_T_642, _T_643)
node _T_645 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_646 = and(_T_644, _T_645)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_647 = shr(io.in.a.bits.source, 2)
node _T_648 = eq(_T_647, UInt<1>(0h1))
node _T_649 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_650 = and(_T_648, _T_649)
node _T_651 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_652 = and(_T_650, _T_651)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_653 = shr(io.in.a.bits.source, 2)
node _T_654 = eq(_T_653, UInt<2>(0h2))
node _T_655 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_656 = and(_T_654, _T_655)
node _T_657 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_658 = and(_T_656, _T_657)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_659 = shr(io.in.a.bits.source, 2)
node _T_660 = eq(_T_659, UInt<2>(0h3))
node _T_661 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_662 = and(_T_660, _T_661)
node _T_663 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_664 = and(_T_662, _T_663)
node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_666 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_667 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_668 = or(_T_640, _T_646)
node _T_669 = or(_T_668, _T_652)
node _T_670 = or(_T_669, _T_658)
node _T_671 = or(_T_670, _T_664)
node _T_672 = or(_T_671, _T_665)
node _T_673 = or(_T_672, _T_666)
node _T_674 = or(_T_673, _T_667)
node _T_675 = and(_T_639, _T_674)
node _T_676 = or(UInt<1>(0h0), _T_675)
node _T_677 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = and(_T_677, _T_682)
node _T_684 = or(UInt<1>(0h0), _T_683)
node _T_685 = and(_T_676, _T_684)
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(_T_685, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_685, UInt<1>(0h1), "") : assert_46
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(source_ok, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(is_aligned, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_695 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_696 = asUInt(reset)
node _T_697 = eq(_T_696, UInt<1>(0h0))
when _T_697 :
node _T_698 = eq(_T_695, UInt<1>(0h0))
when _T_698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_695, UInt<1>(0h1), "") : assert_49
node _T_699 = eq(io.in.a.bits.mask, mask)
node _T_700 = asUInt(reset)
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(_T_699, UInt<1>(0h0))
when _T_702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_699, UInt<1>(0h1), "") : assert_50
node _T_703 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_703, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_707 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_707, UInt<1>(0h1), "") : assert_52
node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_35 = shr(io.in.d.bits.source, 2)
node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0))
node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_41 = shr(io.in.d.bits.source, 2)
node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1))
node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_47 = shr(io.in.d.bits.source, 2)
node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2))
node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_53 = shr(io.in.d.bits.source, 2)
node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3))
node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[8]
connect _source_ok_WIRE_1[0], _source_ok_T_34
connect _source_ok_WIRE_1[1], _source_ok_T_40
connect _source_ok_WIRE_1[2], _source_ok_T_46
connect _source_ok_WIRE_1[3], _source_ok_T_52
connect _source_ok_WIRE_1[4], _source_ok_T_58
connect _source_ok_WIRE_1[5], _source_ok_T_59
connect _source_ok_WIRE_1[6], _source_ok_T_60
connect _source_ok_WIRE_1[7], _source_ok_T_61
node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2])
node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3])
node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6])
node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_711 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(source_ok_1, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_715 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_715, UInt<1>(0h1), "") : assert_54
node _T_719 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_719, UInt<1>(0h1), "") : assert_55
node _T_723 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_724 = asUInt(reset)
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(_T_723, UInt<1>(0h0))
when _T_726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_723, UInt<1>(0h1), "") : assert_56
node _T_727 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_727, UInt<1>(0h1), "") : assert_57
node _T_731 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_731 :
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(source_ok_1, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(sink_ok, UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_738 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_739 = asUInt(reset)
node _T_740 = eq(_T_739, UInt<1>(0h0))
when _T_740 :
node _T_741 = eq(_T_738, UInt<1>(0h0))
when _T_741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_738, UInt<1>(0h1), "") : assert_60
node _T_742 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_742, UInt<1>(0h1), "") : assert_61
node _T_746 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_T_746, UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_746, UInt<1>(0h1), "") : assert_62
node _T_750 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_750, UInt<1>(0h1), "") : assert_63
node _T_754 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(_T_755, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_755, UInt<1>(0h1), "") : assert_64
node _T_759 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_759 :
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(source_ok_1, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(sink_ok, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_766 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_767 = asUInt(reset)
node _T_768 = eq(_T_767, UInt<1>(0h0))
when _T_768 :
node _T_769 = eq(_T_766, UInt<1>(0h0))
when _T_769 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_766, UInt<1>(0h1), "") : assert_67
node _T_770 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(_T_770, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_770, UInt<1>(0h1), "") : assert_68
node _T_774 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_774, UInt<1>(0h1), "") : assert_69
node _T_778 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_779 = or(_T_778, io.in.d.bits.corrupt)
node _T_780 = asUInt(reset)
node _T_781 = eq(_T_780, UInt<1>(0h0))
when _T_781 :
node _T_782 = eq(_T_779, UInt<1>(0h0))
when _T_782 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_779, UInt<1>(0h1), "") : assert_70
node _T_783 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_784 = or(UInt<1>(0h0), _T_783)
node _T_785 = asUInt(reset)
node _T_786 = eq(_T_785, UInt<1>(0h0))
when _T_786 :
node _T_787 = eq(_T_784, UInt<1>(0h0))
when _T_787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_784, UInt<1>(0h1), "") : assert_71
node _T_788 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_788 :
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(source_ok_1, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_792 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(_T_792, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_792, UInt<1>(0h1), "") : assert_73
node _T_796 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_796, UInt<1>(0h1), "") : assert_74
node _T_800 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_801, UInt<1>(0h1), "") : assert_75
node _T_805 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_805 :
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(source_ok_1, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_809 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_809, UInt<1>(0h1), "") : assert_77
node _T_813 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_814 = or(_T_813, io.in.d.bits.corrupt)
node _T_815 = asUInt(reset)
node _T_816 = eq(_T_815, UInt<1>(0h0))
when _T_816 :
node _T_817 = eq(_T_814, UInt<1>(0h0))
when _T_817 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_814, UInt<1>(0h1), "") : assert_78
node _T_818 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_819 = or(UInt<1>(0h0), _T_818)
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_819, UInt<1>(0h1), "") : assert_79
node _T_823 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_823 :
node _T_824 = asUInt(reset)
node _T_825 = eq(_T_824, UInt<1>(0h0))
when _T_825 :
node _T_826 = eq(source_ok_1, UInt<1>(0h0))
when _T_826 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_827 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_828 = asUInt(reset)
node _T_829 = eq(_T_828, UInt<1>(0h0))
when _T_829 :
node _T_830 = eq(_T_827, UInt<1>(0h0))
when _T_830 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_827, UInt<1>(0h1), "") : assert_81
node _T_831 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_T_831, UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_831, UInt<1>(0h1), "") : assert_82
node _T_835 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_836 = or(UInt<1>(0h0), _T_835)
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_836, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_840 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_841 = asUInt(reset)
node _T_842 = eq(_T_841, UInt<1>(0h0))
when _T_842 :
node _T_843 = eq(_T_840, UInt<1>(0h0))
when _T_843 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_840, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_844 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_845 = asUInt(reset)
node _T_846 = eq(_T_845, UInt<1>(0h0))
when _T_846 :
node _T_847 = eq(_T_844, UInt<1>(0h0))
when _T_847 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_844, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_848 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_849 = asUInt(reset)
node _T_850 = eq(_T_849, UInt<1>(0h0))
when _T_850 :
node _T_851 = eq(_T_848, UInt<1>(0h0))
when _T_851 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_848, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_852 = eq(a_first, UInt<1>(0h0))
node _T_853 = and(io.in.a.valid, _T_852)
when _T_853 :
node _T_854 = eq(io.in.a.bits.opcode, opcode)
node _T_855 = asUInt(reset)
node _T_856 = eq(_T_855, UInt<1>(0h0))
when _T_856 :
node _T_857 = eq(_T_854, UInt<1>(0h0))
when _T_857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_854, UInt<1>(0h1), "") : assert_87
node _T_858 = eq(io.in.a.bits.param, param)
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_T_858, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_858, UInt<1>(0h1), "") : assert_88
node _T_862 = eq(io.in.a.bits.size, size)
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(_T_862, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_862, UInt<1>(0h1), "") : assert_89
node _T_866 = eq(io.in.a.bits.source, source)
node _T_867 = asUInt(reset)
node _T_868 = eq(_T_867, UInt<1>(0h0))
when _T_868 :
node _T_869 = eq(_T_866, UInt<1>(0h0))
when _T_869 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_866, UInt<1>(0h1), "") : assert_90
node _T_870 = eq(io.in.a.bits.address, address)
node _T_871 = asUInt(reset)
node _T_872 = eq(_T_871, UInt<1>(0h0))
when _T_872 :
node _T_873 = eq(_T_870, UInt<1>(0h0))
when _T_873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_870, UInt<1>(0h1), "") : assert_91
node _T_874 = and(io.in.a.ready, io.in.a.valid)
node _T_875 = and(_T_874, a_first)
when _T_875 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_876 = eq(d_first, UInt<1>(0h0))
node _T_877 = and(io.in.d.valid, _T_876)
when _T_877 :
node _T_878 = eq(io.in.d.bits.opcode, opcode_1)
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_878, UInt<1>(0h1), "") : assert_92
node _T_882 = eq(io.in.d.bits.param, param_1)
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_882, UInt<1>(0h1), "") : assert_93
node _T_886 = eq(io.in.d.bits.size, size_1)
node _T_887 = asUInt(reset)
node _T_888 = eq(_T_887, UInt<1>(0h0))
when _T_888 :
node _T_889 = eq(_T_886, UInt<1>(0h0))
when _T_889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_886, UInt<1>(0h1), "") : assert_94
node _T_890 = eq(io.in.d.bits.source, source_1)
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_890, UInt<1>(0h1), "") : assert_95
node _T_894 = eq(io.in.d.bits.sink, sink)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_894, UInt<1>(0h1), "") : assert_96
node _T_898 = eq(io.in.d.bits.denied, denied)
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_898, UInt<1>(0h1), "") : assert_97
node _T_902 = and(io.in.d.ready, io.in.d.valid)
node _T_903 = and(_T_902, d_first)
when _T_903 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_904 = and(io.in.a.valid, a_first_1)
node _T_905 = and(_T_904, UInt<1>(0h1))
when _T_905 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_906 = and(io.in.a.ready, io.in.a.valid)
node _T_907 = and(_T_906, a_first_1)
node _T_908 = and(_T_907, UInt<1>(0h1))
when _T_908 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_909 = dshr(inflight, io.in.a.bits.source)
node _T_910 = bits(_T_909, 0, 0)
node _T_911 = eq(_T_910, UInt<1>(0h0))
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(_T_911, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_911, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_915 = and(io.in.d.valid, d_first_1)
node _T_916 = and(_T_915, UInt<1>(0h1))
node _T_917 = eq(d_release_ack, UInt<1>(0h0))
node _T_918 = and(_T_916, _T_917)
when _T_918 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_919 = and(io.in.d.ready, io.in.d.valid)
node _T_920 = and(_T_919, d_first_1)
node _T_921 = and(_T_920, UInt<1>(0h1))
node _T_922 = eq(d_release_ack, UInt<1>(0h0))
node _T_923 = and(_T_921, _T_922)
when _T_923 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_924 = and(io.in.d.valid, d_first_1)
node _T_925 = and(_T_924, UInt<1>(0h1))
node _T_926 = eq(d_release_ack, UInt<1>(0h0))
node _T_927 = and(_T_925, _T_926)
when _T_927 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_928 = dshr(inflight, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_930, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_934 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_935 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_936 = or(_T_934, _T_935)
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(_T_936, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_936, UInt<1>(0h1), "") : assert_100
node _T_940 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_940, UInt<1>(0h1), "") : assert_101
else :
node _T_944 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_945 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_946 = or(_T_944, _T_945)
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_946, UInt<1>(0h1), "") : assert_102
node _T_950 = eq(io.in.d.bits.size, a_size_lookup)
node _T_951 = asUInt(reset)
node _T_952 = eq(_T_951, UInt<1>(0h0))
when _T_952 :
node _T_953 = eq(_T_950, UInt<1>(0h0))
when _T_953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_950, UInt<1>(0h1), "") : assert_103
node _T_954 = and(io.in.d.valid, d_first_1)
node _T_955 = and(_T_954, a_first_1)
node _T_956 = and(_T_955, io.in.a.valid)
node _T_957 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_958 = and(_T_956, _T_957)
node _T_959 = eq(d_release_ack, UInt<1>(0h0))
node _T_960 = and(_T_958, _T_959)
when _T_960 :
node _T_961 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_962 = or(_T_961, io.in.a.ready)
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(_T_962, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_962, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_98
node _T_966 = orr(inflight)
node _T_967 = eq(_T_966, UInt<1>(0h0))
node _T_968 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_969 = or(_T_967, _T_968)
node _T_970 = lt(watchdog, plusarg_reader.out)
node _T_971 = or(_T_969, _T_970)
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(_T_971, UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_971, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_975 = and(io.in.a.ready, io.in.a.valid)
node _T_976 = and(io.in.d.ready, io.in.d.valid)
node _T_977 = or(_T_975, _T_976)
when _T_977 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_978 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_979 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_980 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_981 = and(_T_979, _T_980)
node _T_982 = and(_T_978, _T_981)
when _T_982 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_983 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_984 = and(_T_983, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_985 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_986 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_987 = and(_T_985, _T_986)
node _T_988 = and(_T_984, _T_987)
when _T_988 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_989 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_990 = bits(_T_989, 0, 0)
node _T_991 = eq(_T_990, UInt<1>(0h0))
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_991, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_995 = and(io.in.d.valid, d_first_2)
node _T_996 = and(_T_995, UInt<1>(0h1))
node _T_997 = and(_T_996, d_release_ack_1)
when _T_997 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_998 = and(io.in.d.ready, io.in.d.valid)
node _T_999 = and(_T_998, d_first_2)
node _T_1000 = and(_T_999, UInt<1>(0h1))
node _T_1001 = and(_T_1000, d_release_ack_1)
when _T_1001 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1002 = and(io.in.d.valid, d_first_2)
node _T_1003 = and(_T_1002, UInt<1>(0h1))
node _T_1004 = and(_T_1003, d_release_ack_1)
when _T_1004 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1005 = dshr(inflight_1, io.in.d.bits.source)
node _T_1006 = bits(_T_1005, 0, 0)
node _T_1007 = or(_T_1006, same_cycle_resp_1)
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1011 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(_T_1011, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1011, UInt<1>(0h1), "") : assert_108
else :
node _T_1015 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_109
node _T_1019 = and(io.in.d.valid, d_first_2)
node _T_1020 = and(_T_1019, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1021 = and(_T_1020, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1022 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = and(_T_1023, d_release_ack_1)
node _T_1025 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1026 = and(_T_1024, _T_1025)
when _T_1026 :
node _T_1027 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1028 = or(_T_1027, _WIRE_23.ready)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_99
node _T_1032 = orr(inflight_1)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
node _T_1034 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1035 = or(_T_1033, _T_1034)
node _T_1036 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1037 = or(_T_1035, _T_1036)
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1041 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1042 = and(io.in.d.ready, io.in.d.valid)
node _T_1043 = or(_T_1041, _T_1042)
when _T_1043 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_48( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _T_975 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_975; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_975; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1043 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1043; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1043; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1043; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_908 = _T_975 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_923 = _T_1043 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1019 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1019 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1001 = _T_1043 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1001 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1001 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1001 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
output io : { flip bypass : UInt<1>, pending : UInt<1>}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_49
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect nodeIn, auto.in
regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1)
connect in_reset, UInt<1>(0h0)
reg bypass_reg : UInt<1>, clock
node bypass = mux(in_reset, io.bypass, bypass_reg)
regreset flight : UInt<2>, clock, reset, UInt<2>(0h0)
node _T = and(nodeIn.a.ready, nodeIn.a.valid)
node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 2)
node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0))
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node a_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node a_last = or(_r_last_T, _r_last_T_1)
node r_3 = and(a_last, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(a_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid)
node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size)
node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0)
node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4)
node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2)
node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2)
node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0))
node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0))
regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1))
node r_counter1_1 = tail(_r_counter1_T_1, 1)
node b_first = eq(r_counter_1, UInt<1>(0h0))
node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1))
node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0))
node b_last = or(_r_last_T_2, _r_last_T_3)
node r_3_1 = and(b_last, _T_1)
node _r_count_T_1 = not(r_counter1_1)
node r_4_1 = and(r_beats1_1, _r_count_T_1)
when _T_1 :
node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1)
connect r_counter_1, _r_counter_T_1
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid)
node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size)
node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0)
node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7)
node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2)
node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0)
node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0))
regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1))
node r_counter1_2 = tail(_r_counter1_T_2, 1)
node c_first = eq(r_counter_2, UInt<1>(0h0))
node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1))
node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0))
node c_last = or(_r_last_T_4, _r_last_T_5)
node r_3_2 = and(c_last, _T_2)
node _r_count_T_2 = not(r_counter1_2)
node r_4_2 = and(r_beats1_2, _r_count_T_2)
when _T_2 :
node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2)
connect r_counter_2, _r_counter_T_2
node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid)
node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size)
node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0)
node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10)
node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2)
node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0)
node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0))
regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1))
node r_counter1_3 = tail(_r_counter1_T_3, 1)
node d_first = eq(r_counter_3, UInt<1>(0h0))
node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1))
node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0))
node d_last = or(_r_last_T_6, _r_last_T_7)
node r_3_3 = and(d_last, _T_3)
node _r_count_T_3 = not(r_counter1_3)
node r_4_3 = and(r_beats1_3, _r_count_T_3)
when _T_3 :
node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3)
connect r_counter_3, _r_counter_T_3
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid)
regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1))
node r_counter1_4 = tail(_r_counter1_T_4, 1)
node e_first = eq(r_counter_4, UInt<1>(0h0))
node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1))
node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0))
node e_last = or(_r_last_T_8, _r_last_T_9)
node r_3_4 = and(e_last, _T_4)
node _r_count_T_4 = not(r_counter1_4)
node r_4_4 = and(UInt<1>(0h0), _r_count_T_4)
when _T_4 :
node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4)
connect r_counter_4, _r_counter_T_4
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.mask, UInt<4>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.mask, UInt<4>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<2>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2)
node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1)
node c_request = and(_T_5, _T_6)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_8 = eq(_T_7, UInt<1>(0h0))
node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node c_response = or(_T_8, _T_10)
node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2)
node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node d_request = and(_T_11, _T_13)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_14.bits.sink, UInt<1>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_inc_T_1 = and(_a_inc_T, a_first)
node a_inc = and(_a_inc_T_1, UInt<1>(0h1))
wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_inc_WIRE.bits.data, UInt<32>(0h0)
connect _b_inc_WIRE.bits.mask, UInt<4>(0h0)
connect _b_inc_WIRE.bits.address, UInt<9>(0h0)
connect _b_inc_WIRE.bits.source, UInt<1>(0h0)
connect _b_inc_WIRE.bits.size, UInt<2>(0h0)
connect _b_inc_WIRE.bits.param, UInt<2>(0h0)
connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_inc_WIRE.valid, UInt<1>(0h0)
connect _b_inc_WIRE.ready, UInt<1>(0h0)
wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits
connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid
connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready
node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid)
node _b_inc_T_1 = and(_b_inc_T, b_first)
node b_inc = and(_b_inc_T_1, UInt<1>(0h1))
wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_inc_WIRE.bits.data, UInt<32>(0h0)
connect _c_inc_WIRE.bits.address, UInt<9>(0h0)
connect _c_inc_WIRE.bits.source, UInt<1>(0h0)
connect _c_inc_WIRE.bits.size, UInt<2>(0h0)
connect _c_inc_WIRE.bits.param, UInt<3>(0h0)
connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_inc_WIRE.valid, UInt<1>(0h0)
connect _c_inc_WIRE.ready, UInt<1>(0h0)
wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits
connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid
connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready
node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid)
node _c_inc_T_1 = and(_c_inc_T, c_first)
node c_inc = and(_c_inc_T_1, c_request)
node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _d_inc_T_1 = and(_d_inc_T, d_first)
node d_inc = and(_d_inc_T_1, d_request)
wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_inc_WIRE.bits.sink, UInt<1>(0h0)
connect _e_inc_WIRE.valid, UInt<1>(0h0)
connect _e_inc_WIRE.ready, UInt<1>(0h0)
wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits
connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid
connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready
node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid)
node _e_inc_T_1 = and(_e_inc_T, e_first)
node e_inc = and(_e_inc_T_1, UInt<1>(0h0))
node inc = cat(a_inc, d_inc)
node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_dec_T_1 = and(_a_dec_T, a_last)
node a_dec = and(_a_dec_T_1, UInt<1>(0h0))
wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_dec_WIRE.bits.data, UInt<32>(0h0)
connect _b_dec_WIRE.bits.mask, UInt<4>(0h0)
connect _b_dec_WIRE.bits.address, UInt<9>(0h0)
connect _b_dec_WIRE.bits.source, UInt<1>(0h0)
connect _b_dec_WIRE.bits.size, UInt<2>(0h0)
connect _b_dec_WIRE.bits.param, UInt<2>(0h0)
connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_dec_WIRE.valid, UInt<1>(0h0)
connect _b_dec_WIRE.ready, UInt<1>(0h0)
wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits
connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid
connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready
node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid)
node _b_dec_T_1 = and(_b_dec_T, b_last)
node b_dec = and(_b_dec_T_1, UInt<1>(0h0))
wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_dec_WIRE.bits.data, UInt<32>(0h0)
connect _c_dec_WIRE.bits.address, UInt<9>(0h0)
connect _c_dec_WIRE.bits.source, UInt<1>(0h0)
connect _c_dec_WIRE.bits.size, UInt<2>(0h0)
connect _c_dec_WIRE.bits.param, UInt<3>(0h0)
connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_dec_WIRE.valid, UInt<1>(0h0)
connect _c_dec_WIRE.ready, UInt<1>(0h0)
wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits
connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid
connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready
node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid)
node _c_dec_T_1 = and(_c_dec_T, c_last)
node c_dec = and(_c_dec_T_1, c_response)
node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _d_dec_T_1 = and(_d_dec_T, d_last)
node d_dec = and(_d_dec_T_1, UInt<1>(0h1))
wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_dec_WIRE.bits.sink, UInt<1>(0h0)
connect _e_dec_WIRE.valid, UInt<1>(0h0)
connect _e_dec_WIRE.ready, UInt<1>(0h0)
wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits
connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid
connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready
node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid)
node _e_dec_T_1 = and(_e_dec_T, e_last)
node e_dec = and(_e_dec_T_1, UInt<1>(0h1))
node dec = cat(a_dec, d_dec)
node _next_flight_T = bits(inc, 0, 0)
node _next_flight_T_1 = bits(inc, 1, 1)
node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1)
node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0)
node _next_flight_T_4 = add(flight, _next_flight_T_3)
node _next_flight_T_5 = tail(_next_flight_T_4, 1)
node _next_flight_T_6 = bits(dec, 0, 0)
node _next_flight_T_7 = bits(dec, 1, 1)
node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7)
node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0)
node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9)
node next_flight = tail(_next_flight_T_10, 1)
connect flight, next_flight
node _io_pending_T = gt(flight, UInt<1>(0h0))
connect io.pending, _io_pending_T
node _T_14 = eq(next_flight, UInt<1>(0h0))
node _T_15 = or(in_reset, _T_14)
when _T_15 :
connect bypass_reg, io.bypass
node _stall_T = neq(bypass, io.bypass)
node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid)
node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0)
node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1)
node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2)
node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0))
node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0))
regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1))
node stall_counter1 = tail(_stall_counter1_T, 1)
node stall_first = eq(stall_counter, UInt<1>(0h0))
node _stall_last_T = eq(stall_counter, UInt<1>(0h1))
node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0))
node stall_last = or(_stall_last_T, _stall_last_T_1)
node stall_done = and(stall_last, _stall_T_1)
node _stall_count_T = not(stall_counter1)
node stall_count = and(stall_beats1, _stall_count_T)
when _stall_T_1 :
node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1)
connect stall_counter, _stall_counter_T
node stall = and(_stall_T, stall_first)
node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0))
node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid)
node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass)
connect nodeOut.a.valid, _nodeOut_a_valid_T_2
node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0))
node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid)
node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0))
node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5)
connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6
node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0))
node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready)
node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1)
connect nodeIn.a.ready, _nodeIn_a_ready_T_2
connect nodeOut.a.bits, nodeIn.a.bits
connect x1_nodeOut.a.bits, nodeIn.a.bits
node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass)
connect nodeOut.d.ready, _nodeOut_d_ready_T
node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0))
node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1)
connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2
node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid)
connect nodeIn.d.valid, _nodeIn_d_valid_T
wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
connect nodeIn_d_bits_out, nodeIn.d.bits
connect nodeIn_d_bits_out, nodeOut.d.bits
wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
connect nodeIn_d_bits_out_1, nodeIn.d.bits
connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits
node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1)
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt
connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data
connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied
connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink
connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source
connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size
connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param
connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.mask, UInt<4>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<2>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.valid, UInt<1>(0h0)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.ready, UInt<1>(0h1)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.mask, UInt<4>(0h0)
connect _WIRE_24.bits.address, UInt<128>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
connect _WIRE_25.ready, UInt<1>(0h1)
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<32>(0h0)
connect _WIRE_26.bits.address, UInt<128>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<2>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
connect _WIRE_27.valid, UInt<1>(0h0)
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_28.bits.sink, UInt<1>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<32>(0h0)
connect _WIRE_30.bits.mask, UInt<4>(0h0)
connect _WIRE_30.bits.address, UInt<9>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<2>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<32>(0h0)
connect _WIRE_32.bits.address, UInt<9>(0h0)
connect _WIRE_32.bits.source, UInt<1>(0h0)
connect _WIRE_32.bits.size, UInt<2>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
connect _WIRE_33.valid, UInt<1>(0h0)
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_34.bits.sink, UInt<1>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
connect _WIRE_35.valid, UInt<1>(0h0)
extmodule plusarg_reader_100 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_101 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBusBypassBar( // @[BusBypass.scala:66:9]
input clock, // @[BusBypass.scala:66:9]
input reset, // @[BusBypass.scala:66:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_bypass // @[BusBypass.scala:67:16]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9]
wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9]
wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71]
wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71]
wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46]
wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9]
wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53]
wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_last = 1'h1; // @[Edges.scala:232:33]
wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28]
wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28]
wire b_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire b_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire c_last = 1'h1; // @[Edges.scala:232:33]
wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43]
wire d_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28]
wire e_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43]
wire e_last = 1'h1; // @[Edges.scala:232:33]
wire c_response = 1'h1; // @[Edges.scala:82:41]
wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire stall_last = 1'h1; // @[Edges.scala:232:33]
wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire r_beats1 = 1'h0; // @[Edges.scala:221:14]
wire r_4 = 1'h0; // @[Edges.scala:234:25]
wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37]
wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire r_3_1 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27]
wire r_4_1 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36]
wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25]
wire r_3_2 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27]
wire r_4_2 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14]
wire r_4_3 = 1'h0; // @[Edges.scala:234:25]
wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25]
wire r_3_4 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27]
wire r_4_4 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21]
wire c_request = 1'h0; // @[Edges.scala:68:40]
wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26]
wire b_inc = 1'h0; // @[Edges.scala:311:37]
wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26]
wire c_inc = 1'h0; // @[Edges.scala:312:37]
wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26]
wire e_inc = 1'h0; // @[Edges.scala:314:37]
wire a_dec = 1'h0; // @[Edges.scala:317:36]
wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26]
wire b_dec = 1'h0; // @[Edges.scala:318:36]
wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26]
wire c_dec = 1'h0; // @[Edges.scala:319:36]
wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26]
wire e_dec = 1'h0; // @[Edges.scala:321:36]
wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire stall_beats1 = 1'h0; // @[Edges.scala:221:14]
wire stall_count = 1'h0; // @[Edges.scala:234:25]
wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire _io_pending_T; // @[BusBypass.scala:84:27]
wire auto_in_a_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire auto_in_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
wire io_pending; // @[BusBypass.scala:66:9]
wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
reg in_reset; // @[BusBypass.scala:79:27]
reg bypass_reg; // @[BusBypass.scala:80:25]
wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21]
reg [1:0] flight; // @[Edges.scala:295:25]
wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35]
wire r_3; // @[Edges.scala:233:22]
assign r_3 = _T; // @[Decoupled.scala:51:35]
wire _a_inc_T; // @[Decoupled.scala:51:35]
assign _a_inc_T = _T; // @[Decoupled.scala:51:35]
wire _a_dec_T; // @[Decoupled.scala:51:35]
assign _a_dec_T = _T; // @[Decoupled.scala:51:35]
wire _stall_T_1; // @[Decoupled.scala:51:35]
assign _stall_T_1 = _T; // @[Decoupled.scala:51:35]
wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg r_counter; // @[Edges.scala:229:27]
wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25]
wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire r_3_3; // @[Edges.scala:233:22]
assign r_3_3 = _T_3; // @[Decoupled.scala:51:35]
wire _d_inc_T; // @[Decoupled.scala:51:35]
assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35]
wire _d_dec_T; // @[Decoupled.scala:51:35]
assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35]
wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36]
reg r_counter_3; // @[Edges.scala:229:27]
wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28]
wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25]
wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}]
wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35]
wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}]
wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35]
wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}]
wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18]
wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35]
wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35]
wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}]
wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18]
wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40]
wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40]
wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40]
wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40]
wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}]
wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30]
wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56]
wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56]
wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56]
wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56]
wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}]
wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46]
assign _io_pending_T = |flight; // @[Edges.scala:295:25]
assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27]
wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25]
wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35]
wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg stall_counter; // @[Edges.scala:229:27]
wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28]
wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25]
wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27]
wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire stall = _stall_T & stall_first; // @[Edges.scala:231:25]
wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21]
wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}]
assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}]
assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21]
wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}]
wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45]
assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}]
assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21]
wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34]
assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}]
assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18]
assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32]
assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35]
assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}]
assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24]
assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
always @(posedge clock) begin // @[BusBypass.scala:66:9]
if (reset) begin // @[BusBypass.scala:66:9]
in_reset <= 1'h1; // @[BusBypass.scala:79:27]
flight <= 2'h0; // @[Edges.scala:295:25]
r_counter <= 1'h0; // @[Edges.scala:229:27]
r_counter_3 <= 1'h0; // @[Edges.scala:229:27]
stall_counter <= 1'h0; // @[Edges.scala:229:27]
end
else begin // @[BusBypass.scala:66:9]
in_reset <= 1'h0; // @[BusBypass.scala:79:27]
flight <= next_flight; // @[Edges.scala:295:25, :324:46]
if (_T) // @[Decoupled.scala:51:35]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
if (_T_3) // @[Decoupled.scala:51:35]
r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21]
if (_stall_T_1) // @[Decoupled.scala:51:35]
stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21]
end
if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46]
bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25]
always @(posedge)
TLMonitor_49 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_3 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_3( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module GenericDeserializer_TLBeatw88_f32 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}}, busy : UInt<1>}
reg data : UInt<32>[2], clock
regreset beat : UInt<2>, clock, reset, UInt<2>(0h0)
node _io_in_ready_T = neq(beat, UInt<2>(0h2))
node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T)
connect io.in.ready, _io_in_ready_T_1
node _io_out_valid_T = eq(beat, UInt<2>(0h2))
node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T)
connect io.out.valid, _io_out_valid_T_1
node _io_out_bits_T = cat(data[1], data[0])
node _io_out_bits_T_1 = cat(io.in.bits.flit, _io_out_bits_T)
wire _io_out_bits_WIRE : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}
wire _io_out_bits_WIRE_1 : UInt<88>
connect _io_out_bits_WIRE_1, _io_out_bits_T_1
node _io_out_bits_T_2 = bits(_io_out_bits_WIRE_1, 0, 0)
connect _io_out_bits_WIRE.tail, _io_out_bits_T_2
node _io_out_bits_T_3 = bits(_io_out_bits_WIRE_1, 1, 1)
connect _io_out_bits_WIRE.head, _io_out_bits_T_3
node _io_out_bits_T_4 = bits(_io_out_bits_WIRE_1, 87, 2)
connect _io_out_bits_WIRE.payload, _io_out_bits_T_4
connect io.out.bits, _io_out_bits_WIRE
node _T = and(io.in.ready, io.in.valid)
when _T :
node _beat_T = eq(beat, UInt<2>(0h2))
node _beat_T_1 = add(beat, UInt<1>(0h1))
node _beat_T_2 = tail(_beat_T_1, 1)
node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2)
connect beat, _beat_T_3
node _T_1 = neq(beat, UInt<2>(0h2))
when _T_1 :
node _T_2 = bits(beat, 0, 0)
connect data[_T_2], io.in.bits.flit
node _io_busy_T = neq(beat, UInt<1>(0h0))
connect io.busy, _io_busy_T | module GenericDeserializer_TLBeatw88_f32( // @[Serdes.scala:37:7]
input clock, // @[Serdes.scala:37:7]
input reset, // @[Serdes.scala:37:7]
output io_in_ready, // @[Serdes.scala:39:14]
input io_in_valid, // @[Serdes.scala:39:14]
input [31:0] io_in_bits_flit, // @[Serdes.scala:39:14]
input io_out_ready, // @[Serdes.scala:39:14]
output io_out_valid, // @[Serdes.scala:39:14]
output [85:0] io_out_bits_payload, // @[Serdes.scala:39:14]
output io_out_bits_head, // @[Serdes.scala:39:14]
output io_out_bits_tail // @[Serdes.scala:39:14]
);
reg [31:0] data_0; // @[Serdes.scala:48:17]
reg [31:0] data_1; // @[Serdes.scala:48:17]
reg [1:0] beat; // @[Serdes.scala:49:21]
wire io_in_ready_0 = io_out_ready | beat != 2'h2; // @[Serdes.scala:37:7, :49:21, :51:{31,39}]
wire _beat_T = beat == 2'h2; // @[Serdes.scala:37:7, :49:21, :52:39]
wire _GEN = io_in_ready_0 & io_in_valid; // @[Decoupled.scala:51:35]
wire _GEN_0 = beat == 2'h2; // @[Serdes.scala:37:7, :48:17, :49:21, :51:39, :62:39, :63:47]
always @(posedge clock) begin // @[Serdes.scala:37:7]
if (~_GEN | _GEN_0 | beat[0]) begin // @[Decoupled.scala:51:35]
end
else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47]
data_0 <= io_in_bits_flit; // @[Serdes.scala:48:17]
if (~_GEN | _GEN_0 | ~(beat[0])) begin // @[Decoupled.scala:51:35]
end
else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47]
data_1 <= io_in_bits_flit; // @[Serdes.scala:48:17]
if (reset) // @[Serdes.scala:37:7]
beat <= 2'h0; // @[Serdes.scala:37:7, :49:21]
else if (_GEN) // @[Decoupled.scala:51:35]
beat <= _beat_T ? 2'h0 : beat + 2'h1; // @[Serdes.scala:37:7, :49:21, :52:39, :60:{16,53}]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_71 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_71( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLROM :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_39
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
connect nodeIn, auto.in
wire rom : UInt<64>[512]
connect rom[0], UInt<64>(0h405051300000517)
connect rom[1], UInt<64>(0h301022f330551073)
connect rom[2], UInt<64>(0h12f2934122d293)
connect rom[3], UInt<64>(0h3030107300028863)
connect rom[4], UInt<64>(0h3445307322200513)
connect rom[5], UInt<64>(0h3045107300800513)
connect rom[6], UInt<64>(0h1050007330052073)
connect rom[7], UInt<64>(0hffdff06f)
connect rom[8], UInt<64>(0hf1402573020005b7)
connect rom[9], UInt<64>(0h380006f00050463)
connect rom[10], UInt<64>(0h10069300458613)
connect rom[11], UInt<64>(0h46061300d62023)
connect rom[12], UInt<64>(0hfe069ae3ffc62683)
connect rom[13], UInt<64>(0h2c0006f)
connect rom[14], UInt<64>(0h0)
connect rom[15], UInt<64>(0h0)
connect rom[16], UInt<64>(0h5a283f81ff06f)
connect rom[17], UInt<64>(0h251513fe029ee3)
connect rom[18], UInt<64>(0h5a02300b505b3)
connect rom[19], UInt<64>(0h5250300001537)
connect rom[20], UInt<64>(0hf140257334151073)
connect rom[21], UInt<64>(0h185859300000597)
connect rom[22], UInt<64>(0h3006307308000613)
connect rom[23], UInt<64>(0h1330200073)
connect rom[24], UInt<64>(0h690a0000edfe0dd0)
connect rom[25], UInt<64>(0hf808000038000000)
connect rom[26], UInt<64>(0h1100000028000000)
connect rom[27], UInt<64>(0h10000000)
connect rom[28], UInt<64>(0hc008000071010000)
connect rom[29], UInt<64>(0h0)
connect rom[30], UInt<64>(0h0)
connect rom[31], UInt<64>(0h1000000)
connect rom[32], UInt<64>(0h400000003000000)
connect rom[33], UInt<64>(0h100000000000000)
connect rom[34], UInt<64>(0h400000003000000)
connect rom[35], UInt<64>(0h10000000f000000)
connect rom[36], UInt<64>(0h1500000003000000)
connect rom[37], UInt<64>(0h2d6263751b000000)
connect rom[38], UInt<64>(0h706968632c726162)
connect rom[39], UInt<64>(0h7665642d64726179)
connect rom[40], UInt<64>(0h300000000000000)
connect rom[41], UInt<64>(0h2600000011000000)
connect rom[42], UInt<64>(0h2c7261622d626375)
connect rom[43], UInt<64>(0h6472617970696863)
connect rom[44], UInt<64>(0h100000000000000)
connect rom[45], UInt<64>(0h73657361696c61)
connect rom[46], UInt<64>(0h1500000003000000)
connect rom[47], UInt<64>(0h636f732f2c000000)
connect rom[48], UInt<64>(0h406c61697265732f)
connect rom[49], UInt<64>(0h3030303032303031)
connect rom[50], UInt<64>(0h200000000000000)
connect rom[51], UInt<64>(0h736f686301000000)
connect rom[52], UInt<64>(0h300000000006e65)
connect rom[53], UInt<64>(0h3400000015000000)
connect rom[54], UInt<64>(0h7265732f636f732f)
connect rom[55], UInt<64>(0h32303031406c6169)
connect rom[56], UInt<64>(0h30303030)
connect rom[57], UInt<64>(0h100000002000000)
connect rom[58], UInt<64>(0h73757063)
connect rom[59], UInt<64>(0h400000003000000)
connect rom[60], UInt<64>(0h100000000000000)
connect rom[61], UInt<64>(0h400000003000000)
connect rom[62], UInt<64>(0hf000000)
connect rom[63], UInt<64>(0h400000003000000)
connect rom[64], UInt<64>(0h20a1070040000000)
connect rom[65], UInt<64>(0h4075706301000000)
connect rom[66], UInt<64>(0h300000000000030)
connect rom[67], UInt<64>(0h5300000004000000)
connect rom[68], UInt<64>(0h300000000f15365)
connect rom[69], UInt<64>(0h1b00000014000000)
connect rom[70], UInt<64>(0h2c7261622d626375)
connect rom[71], UInt<64>(0h697200726f646f73)
connect rom[72], UInt<64>(0h300000000766373)
connect rom[73], UInt<64>(0h6300000004000000)
connect rom[74], UInt<64>(0h300000000757063)
connect rom[75], UInt<64>(0h6f00000004000000)
connect rom[76], UInt<64>(0h300000000000000)
connect rom[77], UInt<64>(0h8e00000004000000)
connect rom[78], UInt<64>(0h300000000000000)
connect rom[79], UInt<64>(0h920000001a000000)
connect rom[80], UInt<64>(0h63697a6932337672)
connect rom[81], UInt<64>(0h6e6566697a5f7273)
connect rom[82], UInt<64>(0h7068697a5f696563)
connect rom[83], UInt<64>(0h30000000000006d)
connect rom[84], UInt<64>(0h9c00000005000000)
connect rom[85], UInt<64>(0h79616b6f)
connect rom[86], UInt<64>(0h400000003000000)
connect rom[87], UInt<64>(0h20a1070040000000)
connect rom[88], UInt<64>(0h400000003000000)
connect rom[89], UInt<64>(0h1000000a3000000)
connect rom[90], UInt<64>(0h65746e6901000000)
connect rom[91], UInt<64>(0h6f632d7470757272)
connect rom[92], UInt<64>(0h72656c6c6f72746e)
connect rom[93], UInt<64>(0h300000000000000)
connect rom[94], UInt<64>(0hb000000004000000)
connect rom[95], UInt<64>(0h300000001000000)
connect rom[96], UInt<64>(0h1b0000000f000000)
connect rom[97], UInt<64>(0h70632c7663736972)
connect rom[98], UInt<64>(0h63746e692d75)
connect rom[99], UInt<64>(0h3000000)
connect rom[100], UInt<64>(0h3000000c1000000)
connect rom[101], UInt<64>(0hd600000004000000)
connect rom[102], UInt<64>(0h200000002000000)
connect rom[103], UInt<64>(0h200000002000000)
connect rom[104], UInt<64>(0h6669746801000000)
connect rom[105], UInt<64>(0h300000000000000)
connect rom[106], UInt<64>(0h1b0000000a000000)
connect rom[107], UInt<64>(0h666974682c626375)
connect rom[108], UInt<64>(0h200000000000030)
connect rom[109], UInt<64>(0h636f7301000000)
connect rom[110], UInt<64>(0h400000003000000)
connect rom[111], UInt<64>(0h100000000000000)
connect rom[112], UInt<64>(0h400000003000000)
connect rom[113], UInt<64>(0h10000000f000000)
connect rom[114], UInt<64>(0h2000000003000000)
connect rom[115], UInt<64>(0h2d6263751b000000)
connect rom[116], UInt<64>(0h706968632c726162)
connect rom[117], UInt<64>(0h636f732d64726179)
connect rom[118], UInt<64>(0h2d656c706d697300)
connect rom[119], UInt<64>(0h300000000737562)
connect rom[120], UInt<64>(0hde00000000000000)
connect rom[121], UInt<64>(0h746f6f6201000000)
connect rom[122], UInt<64>(0h737365726464612d)
connect rom[123], UInt<64>(0h303031406765722d)
connect rom[124], UInt<64>(0h300000000000030)
connect rom[125], UInt<64>(0h8e00000008000000)
connect rom[126], UInt<64>(0h10000000100000)
connect rom[127], UInt<64>(0h800000003000000)
connect rom[128], UInt<64>(0h746e6f63e5000000)
connect rom[129], UInt<64>(0h2000000006c6f72)
connect rom[130], UInt<64>(0h7375626301000000)
connect rom[131], UInt<64>(0h6b636f6c635f)
connect rom[132], UInt<64>(0h400000003000000)
connect rom[133], UInt<64>(0hef000000)
connect rom[134], UInt<64>(0h400000003000000)
connect rom[135], UInt<64>(0h65cd1d53000000)
connect rom[136], UInt<64>(0hb00000003000000)
connect rom[137], UInt<64>(0h73756263fc000000)
connect rom[138], UInt<64>(0h6b636f6c635f)
connect rom[139], UInt<64>(0hc00000003000000)
connect rom[140], UInt<64>(0h657869661b000000)
connect rom[141], UInt<64>(0h6b636f6c632d64)
connect rom[142], UInt<64>(0h100000002000000)
connect rom[143], UInt<64>(0h303240746e696c63)
connect rom[144], UInt<64>(0h3030303030)
connect rom[145], UInt<64>(0hd00000003000000)
connect rom[146], UInt<64>(0h637369721b000000)
connect rom[147], UInt<64>(0h30746e696c632c76)
connect rom[148], UInt<64>(0h300000000000000)
connect rom[149], UInt<64>(0hf01000010000000)
connect rom[150], UInt<64>(0h300000002000000)
connect rom[151], UInt<64>(0h700000002000000)
connect rom[152], UInt<64>(0h800000003000000)
connect rom[153], UInt<64>(0h28e000000)
connect rom[154], UInt<64>(0h300000000000100)
connect rom[155], UInt<64>(0he500000008000000)
connect rom[156], UInt<64>(0h6c6f72746e6f63)
connect rom[157], UInt<64>(0h100000002000000)
connect rom[158], UInt<64>(0h61672d6b636f6c63)
connect rom[159], UInt<64>(0h3030303140726574)
connect rom[160], UInt<64>(0h300000000003030)
connect rom[161], UInt<64>(0h8e00000008000000)
connect rom[162], UInt<64>(0h10000000001000)
connect rom[163], UInt<64>(0h800000003000000)
connect rom[164], UInt<64>(0h746e6f63e5000000)
connect rom[165], UInt<64>(0h2000000006c6f72)
connect rom[166], UInt<64>(0h7562656401000000)
connect rom[167], UInt<64>(0h6f72746e6f632d67)
connect rom[168], UInt<64>(0h304072656c6c)
connect rom[169], UInt<64>(0h2100000003000000)
connect rom[170], UInt<64>(0h696669731b000000)
connect rom[171], UInt<64>(0h67756265642c6576)
connect rom[172], UInt<64>(0h736972003331302d)
connect rom[173], UInt<64>(0h67756265642c7663)
connect rom[174], UInt<64>(0h3331302d)
connect rom[175], UInt<64>(0h500000003000000)
connect rom[176], UInt<64>(0h6761746a23010000)
connect rom[177], UInt<64>(0h300000000000000)
connect rom[178], UInt<64>(0hf01000008000000)
connect rom[179], UInt<64>(0hffff000002000000)
connect rom[180], UInt<64>(0h800000003000000)
connect rom[181], UInt<64>(0h8e000000)
connect rom[182], UInt<64>(0h300000000100000)
connect rom[183], UInt<64>(0he500000008000000)
connect rom[184], UInt<64>(0h6c6f72746e6f63)
connect rom[185], UInt<64>(0h100000002000000)
connect rom[186], UInt<64>(0h303038406d697464)
connect rom[187], UInt<64>(0h3030303030)
connect rom[188], UInt<64>(0hd00000003000000)
connect rom[189], UInt<64>(0h696669731b000000)
connect rom[190], UInt<64>(0h306d6974642c6576)
connect rom[191], UInt<64>(0h300000000000000)
connect rom[192], UInt<64>(0h8e00000008000000)
connect rom[193], UInt<64>(0h40000000080)
connect rom[194], UInt<64>(0h400000003000000)
connect rom[195], UInt<64>(0h6d656de5000000)
connect rom[196], UInt<64>(0h400000003000000)
connect rom[197], UInt<64>(0h1000000d6000000)
connect rom[198], UInt<64>(0h100000002000000)
connect rom[199], UInt<64>(0h65642d726f727265)
connect rom[200], UInt<64>(0h3030334065636976)
connect rom[201], UInt<64>(0h300000000000030)
connect rom[202], UInt<64>(0h1b0000000e000000)
connect rom[203], UInt<64>(0h652c657669666973)
connect rom[204], UInt<64>(0h30726f7272)
connect rom[205], UInt<64>(0h800000003000000)
connect rom[206], UInt<64>(0h3000008e000000)
connect rom[207], UInt<64>(0h200000000100000)
connect rom[208], UInt<64>(0h7375626601000000)
connect rom[209], UInt<64>(0h6b636f6c635f)
connect rom[210], UInt<64>(0h400000003000000)
connect rom[211], UInt<64>(0hef000000)
connect rom[212], UInt<64>(0h400000003000000)
connect rom[213], UInt<64>(0h65cd1d53000000)
connect rom[214], UInt<64>(0hb00000003000000)
connect rom[215], UInt<64>(0h73756266fc000000)
connect rom[216], UInt<64>(0h6b636f6c635f)
connect rom[217], UInt<64>(0hc00000003000000)
connect rom[218], UInt<64>(0h657869661b000000)
connect rom[219], UInt<64>(0h6b636f6c632d64)
connect rom[220], UInt<64>(0h100000002000000)
connect rom[221], UInt<64>(0h7075727265746e69)
connect rom[222], UInt<64>(0h6f72746e6f632d74)
connect rom[223], UInt<64>(0h3030634072656c6c)
connect rom[224], UInt<64>(0h30303030)
connect rom[225], UInt<64>(0h400000003000000)
connect rom[226], UInt<64>(0h1000000b0000000)
connect rom[227], UInt<64>(0hc00000003000000)
connect rom[228], UInt<64>(0h637369721b000000)
connect rom[229], UInt<64>(0h3063696c702c76)
connect rom[230], UInt<64>(0h3000000)
connect rom[231], UInt<64>(0h3000000c1000000)
connect rom[232], UInt<64>(0hf01000008000000)
connect rom[233], UInt<64>(0hb00000002000000)
connect rom[234], UInt<64>(0h800000003000000)
connect rom[235], UInt<64>(0hc8e000000)
connect rom[236], UInt<64>(0h300000000000004)
connect rom[237], UInt<64>(0he500000008000000)
connect rom[238], UInt<64>(0h6c6f72746e6f63)
connect rom[239], UInt<64>(0h400000003000000)
connect rom[240], UInt<64>(0h100000030010000)
connect rom[241], UInt<64>(0h400000003000000)
connect rom[242], UInt<64>(0h100000043010000)
connect rom[243], UInt<64>(0h400000003000000)
connect rom[244], UInt<64>(0h4000000d6000000)
connect rom[245], UInt<64>(0h100000002000000)
connect rom[246], UInt<64>(0h6f6c635f73756270)
connect rom[247], UInt<64>(0h300000000006b63)
connect rom[248], UInt<64>(0hef00000004000000)
connect rom[249], UInt<64>(0h300000000000000)
connect rom[250], UInt<64>(0h5300000004000000)
connect rom[251], UInt<64>(0h30000000065cd1d)
connect rom[252], UInt<64>(0hfc0000000b000000)
connect rom[253], UInt<64>(0h6f6c635f73756270)
connect rom[254], UInt<64>(0h300000000006b63)
connect rom[255], UInt<64>(0h1b0000000c000000)
connect rom[256], UInt<64>(0h6c632d6465786966)
connect rom[257], UInt<64>(0h3000000006b636f)
connect rom[258], UInt<64>(0hd600000004000000)
connect rom[259], UInt<64>(0h200000003000000)
connect rom[260], UInt<64>(0h406d6f7201000000)
connect rom[261], UInt<64>(0h3030303031)
connect rom[262], UInt<64>(0hc00000003000000)
connect rom[263], UInt<64>(0h696669731b000000)
connect rom[264], UInt<64>(0h306d6f722c6576)
connect rom[265], UInt<64>(0h800000003000000)
connect rom[266], UInt<64>(0h1008e000000)
connect rom[267], UInt<64>(0h300000000000100)
connect rom[268], UInt<64>(0he500000004000000)
connect rom[269], UInt<64>(0h2000000006d656d)
connect rom[270], UInt<64>(0h7375627301000000)
connect rom[271], UInt<64>(0h6b636f6c635f)
connect rom[272], UInt<64>(0h400000003000000)
connect rom[273], UInt<64>(0hef000000)
connect rom[274], UInt<64>(0h400000003000000)
connect rom[275], UInt<64>(0h65cd1d53000000)
connect rom[276], UInt<64>(0hb00000003000000)
connect rom[277], UInt<64>(0h73756273fc000000)
connect rom[278], UInt<64>(0h6b636f6c635f)
connect rom[279], UInt<64>(0hc00000003000000)
connect rom[280], UInt<64>(0h657869661b000000)
connect rom[281], UInt<64>(0h6b636f6c632d64)
connect rom[282], UInt<64>(0h100000002000000)
connect rom[283], UInt<64>(0h31406c6169726573)
connect rom[284], UInt<64>(0h30303030323030)
connect rom[285], UInt<64>(0h400000003000000)
connect rom[286], UInt<64>(0h30000004e010000)
connect rom[287], UInt<64>(0hd00000003000000)
connect rom[288], UInt<64>(0h696669731b000000)
connect rom[289], UInt<64>(0h30747261752c6576)
connect rom[290], UInt<64>(0h300000000000000)
connect rom[291], UInt<64>(0h5501000004000000)
connect rom[292], UInt<64>(0h300000004000000)
connect rom[293], UInt<64>(0h6601000004000000)
connect rom[294], UInt<64>(0h300000001000000)
connect rom[295], UInt<64>(0h8e00000008000000)
connect rom[296], UInt<64>(0h10000000000210)
connect rom[297], UInt<64>(0h800000003000000)
connect rom[298], UInt<64>(0h746e6f63e5000000)
connect rom[299], UInt<64>(0h2000000006c6f72)
connect rom[300], UInt<64>(0h656c697401000000)
connect rom[301], UInt<64>(0h732d74657365722d)
connect rom[302], UInt<64>(0h3131407265747465)
connect rom[303], UInt<64>(0h30303030)
connect rom[304], UInt<64>(0h800000003000000)
connect rom[305], UInt<64>(0h11008e000000)
connect rom[306], UInt<64>(0h300000000100000)
connect rom[307], UInt<64>(0he500000008000000)
connect rom[308], UInt<64>(0h6c6f72746e6f63)
connect rom[309], UInt<64>(0h200000002000000)
connect rom[310], UInt<64>(0h900000002000000)
connect rom[311], UInt<64>(0h7373657264646123)
connect rom[312], UInt<64>(0h2300736c6c65632d)
connect rom[313], UInt<64>(0h6c65632d657a6973)
connect rom[314], UInt<64>(0h61706d6f6300736c)
connect rom[315], UInt<64>(0h6f6d00656c626974)
connect rom[316], UInt<64>(0h69726573006c6564)
connect rom[317], UInt<64>(0h6f64747300306c61)
connect rom[318], UInt<64>(0h687461702d7475)
connect rom[319], UInt<64>(0h65736162656d6974)
connect rom[320], UInt<64>(0h6e6575716572662d)
connect rom[321], UInt<64>(0h6b636f6c63007963)
connect rom[322], UInt<64>(0h6e6575716572662d)
connect rom[323], UInt<64>(0h6369766564007963)
connect rom[324], UInt<64>(0h6800657079745f65)
connect rom[325], UInt<64>(0h2d65726177647261)
connect rom[326], UInt<64>(0h6572622d63657865)
connect rom[327], UInt<64>(0h2d746e696f706b61)
connect rom[328], UInt<64>(0h657200746e756f63)
connect rom[329], UInt<64>(0h2c76637369720067)
connect rom[330], UInt<64>(0h7461747300617369)
connect rom[331], UInt<64>(0h622d626375007375)
connect rom[332], UInt<64>(0h6d6974642c7261)
connect rom[333], UInt<64>(0h75727265746e6923)
connect rom[334], UInt<64>(0h736c6c65632d7470)
connect rom[335], UInt<64>(0h75727265746e6900)
connect rom[336], UInt<64>(0h72746e6f632d7470)
connect rom[337], UInt<64>(0h68700072656c6c6f)
connect rom[338], UInt<64>(0h617200656c646e61)
connect rom[339], UInt<64>(0h676572007365676e)
connect rom[340], UInt<64>(0h230073656d616e2d)
connect rom[341], UInt<64>(0h65632d6b636f6c63)
connect rom[342], UInt<64>(0h636f6c6300736c6c)
connect rom[343], UInt<64>(0h74757074756f2d6b)
connect rom[344], UInt<64>(0h690073656d616e2d)
connect rom[345], UInt<64>(0h747075727265746e)
connect rom[346], UInt<64>(0h646e657478652d73)
connect rom[347], UInt<64>(0h6775626564006465)
connect rom[348], UInt<64>(0h6863617474612d)
connect rom[349], UInt<64>(0h616d2c7663736972)
connect rom[350], UInt<64>(0h69726f6972702d78)
connect rom[351], UInt<64>(0h7663736972007974)
connect rom[352], UInt<64>(0h6c63007665646e2c)
connect rom[353], UInt<64>(0h746e6900736b636f)
connect rom[354], UInt<64>(0h702d747075727265)
connect rom[355], UInt<64>(0h6e6900746e657261)
connect rom[356], UInt<64>(0h7374707572726574)
connect rom[357], UInt<64>(0h0)
connect rom[358], UInt<64>(0h0)
connect rom[359], UInt<64>(0h0)
connect rom[360], UInt<64>(0h0)
connect rom[361], UInt<64>(0h0)
connect rom[362], UInt<64>(0h0)
connect rom[363], UInt<64>(0h0)
connect rom[364], UInt<64>(0h0)
connect rom[365], UInt<64>(0h0)
connect rom[366], UInt<64>(0h0)
connect rom[367], UInt<64>(0h0)
connect rom[368], UInt<64>(0h0)
connect rom[369], UInt<64>(0h0)
connect rom[370], UInt<64>(0h0)
connect rom[371], UInt<64>(0h0)
connect rom[372], UInt<64>(0h0)
connect rom[373], UInt<64>(0h0)
connect rom[374], UInt<64>(0h0)
connect rom[375], UInt<64>(0h0)
connect rom[376], UInt<64>(0h0)
connect rom[377], UInt<64>(0h0)
connect rom[378], UInt<64>(0h0)
connect rom[379], UInt<64>(0h0)
connect rom[380], UInt<64>(0h0)
connect rom[381], UInt<64>(0h0)
connect rom[382], UInt<64>(0h0)
connect rom[383], UInt<64>(0h0)
connect rom[384], UInt<64>(0h0)
connect rom[385], UInt<64>(0h0)
connect rom[386], UInt<64>(0h0)
connect rom[387], UInt<64>(0h0)
connect rom[388], UInt<64>(0h0)
connect rom[389], UInt<64>(0h0)
connect rom[390], UInt<64>(0h0)
connect rom[391], UInt<64>(0h0)
connect rom[392], UInt<64>(0h0)
connect rom[393], UInt<64>(0h0)
connect rom[394], UInt<64>(0h0)
connect rom[395], UInt<64>(0h0)
connect rom[396], UInt<64>(0h0)
connect rom[397], UInt<64>(0h0)
connect rom[398], UInt<64>(0h0)
connect rom[399], UInt<64>(0h0)
connect rom[400], UInt<64>(0h0)
connect rom[401], UInt<64>(0h0)
connect rom[402], UInt<64>(0h0)
connect rom[403], UInt<64>(0h0)
connect rom[404], UInt<64>(0h0)
connect rom[405], UInt<64>(0h0)
connect rom[406], UInt<64>(0h0)
connect rom[407], UInt<64>(0h0)
connect rom[408], UInt<64>(0h0)
connect rom[409], UInt<64>(0h0)
connect rom[410], UInt<64>(0h0)
connect rom[411], UInt<64>(0h0)
connect rom[412], UInt<64>(0h0)
connect rom[413], UInt<64>(0h0)
connect rom[414], UInt<64>(0h0)
connect rom[415], UInt<64>(0h0)
connect rom[416], UInt<64>(0h0)
connect rom[417], UInt<64>(0h0)
connect rom[418], UInt<64>(0h0)
connect rom[419], UInt<64>(0h0)
connect rom[420], UInt<64>(0h0)
connect rom[421], UInt<64>(0h0)
connect rom[422], UInt<64>(0h0)
connect rom[423], UInt<64>(0h0)
connect rom[424], UInt<64>(0h0)
connect rom[425], UInt<64>(0h0)
connect rom[426], UInt<64>(0h0)
connect rom[427], UInt<64>(0h0)
connect rom[428], UInt<64>(0h0)
connect rom[429], UInt<64>(0h0)
connect rom[430], UInt<64>(0h0)
connect rom[431], UInt<64>(0h0)
connect rom[432], UInt<64>(0h0)
connect rom[433], UInt<64>(0h0)
connect rom[434], UInt<64>(0h0)
connect rom[435], UInt<64>(0h0)
connect rom[436], UInt<64>(0h0)
connect rom[437], UInt<64>(0h0)
connect rom[438], UInt<64>(0h0)
connect rom[439], UInt<64>(0h0)
connect rom[440], UInt<64>(0h0)
connect rom[441], UInt<64>(0h0)
connect rom[442], UInt<64>(0h0)
connect rom[443], UInt<64>(0h0)
connect rom[444], UInt<64>(0h0)
connect rom[445], UInt<64>(0h0)
connect rom[446], UInt<64>(0h0)
connect rom[447], UInt<64>(0h0)
connect rom[448], UInt<64>(0h0)
connect rom[449], UInt<64>(0h0)
connect rom[450], UInt<64>(0h0)
connect rom[451], UInt<64>(0h0)
connect rom[452], UInt<64>(0h0)
connect rom[453], UInt<64>(0h0)
connect rom[454], UInt<64>(0h0)
connect rom[455], UInt<64>(0h0)
connect rom[456], UInt<64>(0h0)
connect rom[457], UInt<64>(0h0)
connect rom[458], UInt<64>(0h0)
connect rom[459], UInt<64>(0h0)
connect rom[460], UInt<64>(0h0)
connect rom[461], UInt<64>(0h0)
connect rom[462], UInt<64>(0h0)
connect rom[463], UInt<64>(0h0)
connect rom[464], UInt<64>(0h0)
connect rom[465], UInt<64>(0h0)
connect rom[466], UInt<64>(0h0)
connect rom[467], UInt<64>(0h0)
connect rom[468], UInt<64>(0h0)
connect rom[469], UInt<64>(0h0)
connect rom[470], UInt<64>(0h0)
connect rom[471], UInt<64>(0h0)
connect rom[472], UInt<64>(0h0)
connect rom[473], UInt<64>(0h0)
connect rom[474], UInt<64>(0h0)
connect rom[475], UInt<64>(0h0)
connect rom[476], UInt<64>(0h0)
connect rom[477], UInt<64>(0h0)
connect rom[478], UInt<64>(0h0)
connect rom[479], UInt<64>(0h0)
connect rom[480], UInt<64>(0h0)
connect rom[481], UInt<64>(0h0)
connect rom[482], UInt<64>(0h0)
connect rom[483], UInt<64>(0h0)
connect rom[484], UInt<64>(0h0)
connect rom[485], UInt<64>(0h0)
connect rom[486], UInt<64>(0h0)
connect rom[487], UInt<64>(0h0)
connect rom[488], UInt<64>(0h0)
connect rom[489], UInt<64>(0h0)
connect rom[490], UInt<64>(0h0)
connect rom[491], UInt<64>(0h0)
connect rom[492], UInt<64>(0h0)
connect rom[493], UInt<64>(0h0)
connect rom[494], UInt<64>(0h0)
connect rom[495], UInt<64>(0h0)
connect rom[496], UInt<64>(0h0)
connect rom[497], UInt<64>(0h0)
connect rom[498], UInt<64>(0h0)
connect rom[499], UInt<64>(0h0)
connect rom[500], UInt<64>(0h0)
connect rom[501], UInt<64>(0h0)
connect rom[502], UInt<64>(0h0)
connect rom[503], UInt<64>(0h0)
connect rom[504], UInt<64>(0h0)
connect rom[505], UInt<64>(0h0)
connect rom[506], UInt<64>(0h0)
connect rom[507], UInt<64>(0h0)
connect rom[508], UInt<64>(0h0)
connect rom[509], UInt<64>(0h0)
connect rom[510], UInt<64>(0h0)
connect rom[511], UInt<64>(0h0)
connect nodeIn.d.valid, nodeIn.a.valid
connect nodeIn.a.ready, nodeIn.d.ready
node index = bits(nodeIn.a.bits.address, 11, 3)
node high = bits(nodeIn.a.bits.address, 15, 12)
node _nodeIn_d_bits_T = orr(high)
node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index])
wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeIn_d_bits_d.opcode, UInt<1>(0h1)
connect nodeIn_d_bits_d.param, UInt<1>(0h0)
connect nodeIn_d_bits_d.size, nodeIn.a.bits.size
connect nodeIn_d_bits_d.source, nodeIn.a.bits.source
connect nodeIn_d_bits_d.sink, UInt<1>(0h0)
connect nodeIn_d_bits_d.denied, UInt<1>(0h0)
connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1
connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt
connect nodeIn.d.bits.data, nodeIn_d_bits_d.data
connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied
connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink
connect nodeIn.d.bits.source, nodeIn_d_bits_d.source
connect nodeIn.d.bits.size, nodeIn_d_bits_d.size
connect nodeIn.d.bits.param, nodeIn_d_bits_d.param
connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLROM( // @[BootROM.scala:41:9]
input clock, // @[BootROM.scala:41:9]
input reset, // @[BootROM.scala:41:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9]
wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9]
wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9]
wire [511:0][63:0] _GEN =
'{64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h7374707572726574,
64'h6E6900746E657261,
64'h702D747075727265,
64'h746E6900736B636F,
64'h6C63007665646E2C,
64'h7663736972007974,
64'h69726F6972702D78,
64'h616D2C7663736972,
64'h6863617474612D,
64'h6775626564006465,
64'h646E657478652D73,
64'h747075727265746E,
64'h690073656D616E2D,
64'h74757074756F2D6B,
64'h636F6C6300736C6C,
64'h65632D6B636F6C63,
64'h230073656D616E2D,
64'h676572007365676E,
64'h617200656C646E61,
64'h68700072656C6C6F,
64'h72746E6F632D7470,
64'h75727265746E6900,
64'h736C6C65632D7470,
64'h75727265746E6923,
64'h6D6974642C7261,
64'h622D626375007375,
64'h7461747300617369,
64'h2C76637369720067,
64'h657200746E756F63,
64'h2D746E696F706B61,
64'h6572622D63657865,
64'h2D65726177647261,
64'h6800657079745F65,
64'h6369766564007963,
64'h6E6575716572662D,
64'h6B636F6C63007963,
64'h6E6575716572662D,
64'h65736162656D6974,
64'h687461702D7475,
64'h6F64747300306C61,
64'h69726573006C6564,
64'h6F6D00656C626974,
64'h61706D6F6300736C,
64'h6C65632D657A6973,
64'h2300736C6C65632D,
64'h7373657264646123,
64'h900000002000000,
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64'h800000003000000,
64'h30303030,
64'h3131407265747465,
64'h732D74657365722D,
64'h656C697401000000,
64'h2000000006C6F72,
64'h746E6F63E5000000,
64'h800000003000000,
64'h10000000000210,
64'h8E00000008000000,
64'h300000001000000,
64'h6601000004000000,
64'h300000004000000,
64'h5501000004000000,
64'h300000000000000,
64'h30747261752C6576,
64'h696669731B000000,
64'hD00000003000000,
64'h30000004E010000,
64'h400000003000000,
64'h30303030323030,
64'h31406C6169726573,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h73756273FC000000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hEF000000,
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64'h6B636F6C635F,
64'h7375627301000000,
64'h2000000006D656D,
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64'h306D6F722C6576,
64'h696669731B000000,
64'hC00000003000000,
64'h3030303031,
64'h406D6F7201000000,
64'h200000003000000,
64'hD600000004000000,
64'h3000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'hFC0000000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hEF00000004000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'h100000002000000,
64'h4000000D6000000,
64'h400000003000000,
64'h100000043010000,
64'h400000003000000,
64'h100000030010000,
64'h400000003000000,
64'h6C6F72746E6F63,
64'hE500000008000000,
64'h300000000000004,
64'hC8E000000,
64'h800000003000000,
64'hB00000002000000,
64'hF01000008000000,
64'h3000000C1000000,
64'h3000000,
64'h3063696C702C76,
64'h637369721B000000,
64'hC00000003000000,
64'h1000000B0000000,
64'h400000003000000,
64'h30303030,
64'h3030634072656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
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64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h73756266FC000000,
64'hB00000003000000,
64'h65CD1D53000000,
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64'hEF000000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375626601000000,
64'h200000000100000,
64'h3000008E000000,
64'h800000003000000,
64'h30726F7272,
64'h652C657669666973,
64'h1B0000000E000000,
64'h300000000000030,
64'h3030334065636976,
64'h65642D726F727265,
64'h100000002000000,
64'h1000000D6000000,
64'h400000003000000,
64'h6D656DE5000000,
64'h400000003000000,
64'h40000000080,
64'h8E00000008000000,
64'h300000000000000,
64'h306D6974642C6576,
64'h696669731B000000,
64'hD00000003000000,
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64'h6C6F72746E6F63,
64'hE500000008000000,
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64'h8E000000,
64'h800000003000000,
64'hFFFF000002000000,
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64'h300000000000000,
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64'h3331302D,
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64'h736972003331302D,
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64'h696669731B000000,
64'h2100000003000000,
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64'h7562656401000000,
64'h2000000006C6F72,
64'h746E6F63E5000000,
64'h800000003000000,
64'h10000000001000,
64'h8E00000008000000,
64'h300000000003030,
64'h3030303140726574,
64'h61672D6B636F6C63,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hE500000008000000,
64'h300000000000100,
64'h28E000000,
64'h800000003000000,
64'h700000002000000,
64'h300000002000000,
64'hF01000010000000,
64'h300000000000000,
64'h30746E696C632C76,
64'h637369721B000000,
64'hD00000003000000,
64'h3030303030,
64'h303240746E696C63,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h73756263FC000000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hEF000000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375626301000000,
64'h2000000006C6F72,
64'h746E6F63E5000000,
64'h800000003000000,
64'h10000000100000,
64'h8E00000008000000,
64'h300000000000030,
64'h303031406765722D,
64'h737365726464612D,
64'h746F6F6201000000,
64'hDE00000000000000,
64'h300000000737562,
64'h2D656C706D697300,
64'h636F732D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h2000000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h636F7301000000,
64'h200000000000030,
64'h666974682C626375,
64'h1B0000000A000000,
64'h300000000000000,
64'h6669746801000000,
64'h200000002000000,
64'h200000002000000,
64'hD600000004000000,
64'h3000000C1000000,
64'h3000000,
64'h63746E692D75,
64'h70632C7663736972,
64'h1B0000000F000000,
64'h300000001000000,
64'hB000000004000000,
64'h300000000000000,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6901000000,
64'h1000000A3000000,
64'h400000003000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h9C00000005000000,
64'h30000000000006D,
64'h7068697A5F696563,
64'h6E6566697A5F7273,
64'h63697A6932337672,
64'h920000001A000000,
64'h300000000000000,
64'h8E00000004000000,
64'h300000000000000,
64'h6F00000004000000,
64'h300000000757063,
64'h6300000004000000,
64'h300000000766373,
64'h697200726F646F73,
64'h2C7261622D626375,
64'h1B00000014000000,
64'h300000000F15365,
64'h5300000004000000,
64'h300000000000030,
64'h4075706301000000,
64'h20A1070040000000,
64'h400000003000000,
64'hF000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h73757063,
64'h100000002000000,
64'h30303030,
64'h32303031406C6169,
64'h7265732F636F732F,
64'h3400000015000000,
64'h300000000006E65,
64'h736F686301000000,
64'h200000000000000,
64'h3030303032303031,
64'h406C61697265732F,
64'h636F732F2C000000,
64'h1500000003000000,
64'h73657361696C61,
64'h100000000000000,
64'h6472617970696863,
64'h2C7261622D626375,
64'h2600000011000000,
64'h300000000000000,
64'h7665642D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h1500000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h1000000,
64'h0,
64'h0,
64'hC008000071010000,
64'h10000000,
64'h1100000028000000,
64'hF808000038000000,
64'h690A0000EDFE0DD0,
64'h1330200073,
64'h3006307308000613,
64'h185859300000597,
64'hF140257334151073,
64'h5250300001537,
64'h5A02300B505B3,
64'h251513FE029EE3,
64'h5A283F81FF06F,
64'h0,
64'h0,
64'h2C0006F,
64'hFE069AE3FFC62683,
64'h46061300D62023,
64'h10069300458613,
64'h380006F00050463,
64'hF1402573020005B7,
64'hFFDFF06F,
64'h1050007330052073,
64'h3045107300800513,
64'h3445307322200513,
64'h3030107300028863,
64'h12F2934122D293,
64'h301022F330551073,
64'h405051300000517};
wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22]
wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22]
wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22]
wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22]
wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22]
wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22]
wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22]
wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22]
wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22]
wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22]
wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22]
wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22]
wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22]
wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22]
wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22]
wire [63:0] rom_19 = 64'h5250300001537; // @[BootROM.scala:50:22]
wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22]
wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22]
wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22]
wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22]
wire [63:0] rom_24 = 64'h690A0000EDFE0DD0; // @[BootROM.scala:50:22]
wire [63:0] rom_25 = 64'hF808000038000000; // @[BootROM.scala:50:22]
wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22]
wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22]
wire [63:0] rom_28 = 64'hC008000071010000; // @[BootROM.scala:50:22]
wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22]
wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22]
wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22]
wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22]
wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22]
wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22]
wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22]
wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22]
wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22]
wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_68 = 64'h300000000F15365; // @[BootROM.scala:50:22]
wire [63:0] rom_69 = 64'h1B00000014000000; // @[BootROM.scala:50:22]
wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_70 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_71 = 64'h697200726F646F73; // @[BootROM.scala:50:22]
wire [63:0] rom_72 = 64'h300000000766373; // @[BootROM.scala:50:22]
wire [63:0] rom_73 = 64'h6300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_74 = 64'h300000000757063; // @[BootROM.scala:50:22]
wire [63:0] rom_75 = 64'h6F00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_77 = 64'h8E00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_79 = 64'h920000001A000000; // @[BootROM.scala:50:22]
wire [63:0] rom_80 = 64'h63697A6932337672; // @[BootROM.scala:50:22]
wire [63:0] rom_81 = 64'h6E6566697A5F7273; // @[BootROM.scala:50:22]
wire [63:0] rom_82 = 64'h7068697A5F696563; // @[BootROM.scala:50:22]
wire [63:0] rom_83 = 64'h30000000000006D; // @[BootROM.scala:50:22]
wire [63:0] rom_84 = 64'h9C00000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_85 = 64'h79616B6F; // @[BootROM.scala:50:22]
wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_87 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_89 = 64'h1000000A3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_90 = 64'h65746E6901000000; // @[BootROM.scala:50:22]
wire [63:0] rom_91 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_92 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_94 = 64'hB000000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_96 = 64'h1B0000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_97 = 64'h70632C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_98 = 64'h63746E692D75; // @[BootROM.scala:50:22]
wire [63:0] rom_104 = 64'h6669746801000000; // @[BootROM.scala:50:22]
wire [63:0] rom_106 = 64'h1B0000000A000000; // @[BootROM.scala:50:22]
wire [63:0] rom_107 = 64'h666974682C626375; // @[BootROM.scala:50:22]
wire [63:0] rom_108 = 64'h200000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_109 = 64'h636F7301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_111 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_113 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_114 = 64'h2000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_115 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_116 = 64'h706968632C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_117 = 64'h636F732D64726179; // @[BootROM.scala:50:22]
wire [63:0] rom_118 = 64'h2D656C706D697300; // @[BootROM.scala:50:22]
wire [63:0] rom_119 = 64'h300000000737562; // @[BootROM.scala:50:22]
wire [63:0] rom_120 = 64'hDE00000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_121 = 64'h746F6F6201000000; // @[BootROM.scala:50:22]
wire [63:0] rom_122 = 64'h737365726464612D; // @[BootROM.scala:50:22]
wire [63:0] rom_123 = 64'h303031406765722D; // @[BootROM.scala:50:22]
wire [63:0] rom_126 = 64'h10000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_130 = 64'h7375626301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_137 = 64'h73756263FC000000; // @[BootROM.scala:50:22]
wire [63:0] rom_143 = 64'h303240746E696C63; // @[BootROM.scala:50:22]
wire [63:0] rom_147 = 64'h30746E696C632C76; // @[BootROM.scala:50:22]
wire [63:0] rom_149 = 64'hF01000010000000; // @[BootROM.scala:50:22]
wire [63:0] rom_150 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_151 = 64'h700000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_153 = 64'h28E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_158 = 64'h61672D6B636F6C63; // @[BootROM.scala:50:22]
wire [63:0] rom_159 = 64'h3030303140726574; // @[BootROM.scala:50:22]
wire [63:0] rom_160 = 64'h300000000003030; // @[BootROM.scala:50:22]
wire [63:0] rom_162 = 64'h10000000001000; // @[BootROM.scala:50:22]
wire [63:0] rom_166 = 64'h7562656401000000; // @[BootROM.scala:50:22]
wire [63:0] rom_167 = 64'h6F72746E6F632D67; // @[BootROM.scala:50:22]
wire [63:0] rom_168 = 64'h304072656C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_169 = 64'h2100000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_171 = 64'h67756265642C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_172 = 64'h736972003331302D; // @[BootROM.scala:50:22]
wire [63:0] rom_173 = 64'h67756265642C7663; // @[BootROM.scala:50:22]
wire [63:0] rom_174 = 64'h3331302D; // @[BootROM.scala:50:22]
wire [63:0] rom_175 = 64'h500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_176 = 64'h6761746A23010000; // @[BootROM.scala:50:22]
wire [63:0] rom_179 = 64'hFFFF000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_181 = 64'h8E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_186 = 64'h303038406D697464; // @[BootROM.scala:50:22]
wire [63:0] rom_144 = 64'h3030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_187 = 64'h3030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_190 = 64'h306D6974642C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_193 = 64'h40000000080; // @[BootROM.scala:50:22]
wire [63:0] rom_195 = 64'h6D656DE5000000; // @[BootROM.scala:50:22]
wire [63:0] rom_197 = 64'h1000000D6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_199 = 64'h65642D726F727265; // @[BootROM.scala:50:22]
wire [63:0] rom_200 = 64'h3030334065636976; // @[BootROM.scala:50:22]
wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_124 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_201 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_202 = 64'h1B0000000E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_203 = 64'h652C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_204 = 64'h30726F7272; // @[BootROM.scala:50:22]
wire [63:0] rom_206 = 64'h3000008E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_207 = 64'h200000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_208 = 64'h7375626601000000; // @[BootROM.scala:50:22]
wire [63:0] rom_215 = 64'h73756266FC000000; // @[BootROM.scala:50:22]
wire [63:0] rom_221 = 64'h7075727265746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_222 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22]
wire [63:0] rom_223 = 64'h3030634072656C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_226 = 64'h1000000B0000000; // @[BootROM.scala:50:22]
wire [63:0] rom_146 = 64'h637369721B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_228 = 64'h637369721B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_229 = 64'h3063696C702C76; // @[BootROM.scala:50:22]
wire [63:0] rom_99 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_230 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_100 = 64'h3000000C1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_231 = 64'h3000000C1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_178 = 64'hF01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_232 = 64'hF01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_233 = 64'hB00000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_235 = 64'hC8E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_236 = 64'h300000000000004; // @[BootROM.scala:50:22]
wire [63:0] rom_240 = 64'h100000030010000; // @[BootROM.scala:50:22]
wire [63:0] rom_242 = 64'h100000043010000; // @[BootROM.scala:50:22]
wire [63:0] rom_244 = 64'h4000000D6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_248 = 64'hEF00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_250 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_251 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_252 = 64'hFC0000000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_246 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_253 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_247 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_254 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_255 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_256 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_257 = 64'h3000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_101 = 64'hD600000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_258 = 64'hD600000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_259 = 64'h200000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_260 = 64'h406D6F7201000000; // @[BootROM.scala:50:22]
wire [63:0] rom_261 = 64'h3030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_264 = 64'h306D6F722C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_266 = 64'h1008E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_154 = 64'h300000000000100; // @[BootROM.scala:50:22]
wire [63:0] rom_267 = 64'h300000000000100; // @[BootROM.scala:50:22]
wire [63:0] rom_268 = 64'hE500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_269 = 64'h2000000006D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_270 = 64'h7375627301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_133 = 64'hEF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_211 = 64'hEF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_273 = 64'hEF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_135 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_213 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_275 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_136 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_214 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_276 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_277 = 64'h73756273FC000000; // @[BootROM.scala:50:22]
wire [63:0] rom_131 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_138 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_209 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_216 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_271 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_278 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_139 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_217 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_227 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_262 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_279 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_140 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_218 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_280 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_141 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_219 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_281 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_142 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_157 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_185 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_198 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_220 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_245 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_282 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_283 = 64'h31406C6169726573; // @[BootROM.scala:50:22]
wire [63:0] rom_284 = 64'h30303030323030; // @[BootROM.scala:50:22]
wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_86 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_88 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_110 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_112 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_132 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_134 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_194 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_196 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_210 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_212 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_225 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_239 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_241 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_243 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_272 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_274 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_285 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_286 = 64'h30000004E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_145 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_188 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_287 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_170 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_189 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_263 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_288 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_289 = 64'h30747261752C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_76 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_78 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_93 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_105 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_148 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_177 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_191 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_249 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_290 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_291 = 64'h5501000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_292 = 64'h300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_293 = 64'h6601000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_95 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_294 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_125 = 64'h8E00000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_161 = 64'h8E00000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_192 = 64'h8E00000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_295 = 64'h8E00000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_296 = 64'h10000000000210; // @[BootROM.scala:50:22]
wire [63:0] rom_128 = 64'h746E6F63E5000000; // @[BootROM.scala:50:22]
wire [63:0] rom_164 = 64'h746E6F63E5000000; // @[BootROM.scala:50:22]
wire [63:0] rom_298 = 64'h746E6F63E5000000; // @[BootROM.scala:50:22]
wire [63:0] rom_129 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_165 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_299 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_300 = 64'h656C697401000000; // @[BootROM.scala:50:22]
wire [63:0] rom_301 = 64'h732D74657365722D; // @[BootROM.scala:50:22]
wire [63:0] rom_302 = 64'h3131407265747465; // @[BootROM.scala:50:22]
wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_224 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_303 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_127 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_152 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_163 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_180 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_205 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_234 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_265 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_297 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_304 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_305 = 64'h11008E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_182 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_306 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_155 = 64'hE500000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_183 = 64'hE500000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_237 = 64'hE500000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_307 = 64'hE500000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_156 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_184 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_238 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_308 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_102 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_103 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_309 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_310 = 64'h900000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_311 = 64'h7373657264646123; // @[BootROM.scala:50:22]
wire [63:0] rom_312 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22]
wire [63:0] rom_313 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22]
wire [63:0] rom_314 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_315 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22]
wire [63:0] rom_316 = 64'h69726573006C6564; // @[BootROM.scala:50:22]
wire [63:0] rom_317 = 64'h6F64747300306C61; // @[BootROM.scala:50:22]
wire [63:0] rom_318 = 64'h687461702D7475; // @[BootROM.scala:50:22]
wire [63:0] rom_319 = 64'h65736162656D6974; // @[BootROM.scala:50:22]
wire [63:0] rom_321 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22]
wire [63:0] rom_320 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_322 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_323 = 64'h6369766564007963; // @[BootROM.scala:50:22]
wire [63:0] rom_324 = 64'h6800657079745F65; // @[BootROM.scala:50:22]
wire [63:0] rom_325 = 64'h2D65726177647261; // @[BootROM.scala:50:22]
wire [63:0] rom_326 = 64'h6572622D63657865; // @[BootROM.scala:50:22]
wire [63:0] rom_327 = 64'h2D746E696F706B61; // @[BootROM.scala:50:22]
wire [63:0] rom_328 = 64'h657200746E756F63; // @[BootROM.scala:50:22]
wire [63:0] rom_329 = 64'h2C76637369720067; // @[BootROM.scala:50:22]
wire [63:0] rom_330 = 64'h7461747300617369; // @[BootROM.scala:50:22]
wire [63:0] rom_331 = 64'h622D626375007375; // @[BootROM.scala:50:22]
wire [63:0] rom_332 = 64'h6D6974642C7261; // @[BootROM.scala:50:22]
wire [63:0] rom_333 = 64'h75727265746E6923; // @[BootROM.scala:50:22]
wire [63:0] rom_334 = 64'h736C6C65632D7470; // @[BootROM.scala:50:22]
wire [63:0] rom_335 = 64'h75727265746E6900; // @[BootROM.scala:50:22]
wire [63:0] rom_336 = 64'h72746E6F632D7470; // @[BootROM.scala:50:22]
wire [63:0] rom_337 = 64'h68700072656C6C6F; // @[BootROM.scala:50:22]
wire [63:0] rom_338 = 64'h617200656C646E61; // @[BootROM.scala:50:22]
wire [63:0] rom_339 = 64'h676572007365676E; // @[BootROM.scala:50:22]
wire [63:0] rom_340 = 64'h230073656D616E2D; // @[BootROM.scala:50:22]
wire [63:0] rom_341 = 64'h65632D6B636F6C63; // @[BootROM.scala:50:22]
wire [63:0] rom_342 = 64'h636F6C6300736C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_343 = 64'h74757074756F2D6B; // @[BootROM.scala:50:22]
wire [63:0] rom_344 = 64'h690073656D616E2D; // @[BootROM.scala:50:22]
wire [63:0] rom_345 = 64'h747075727265746E; // @[BootROM.scala:50:22]
wire [63:0] rom_346 = 64'h646E657478652D73; // @[BootROM.scala:50:22]
wire [63:0] rom_347 = 64'h6775626564006465; // @[BootROM.scala:50:22]
wire [63:0] rom_348 = 64'h6863617474612D; // @[BootROM.scala:50:22]
wire [63:0] rom_349 = 64'h616D2C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_350 = 64'h69726F6972702D78; // @[BootROM.scala:50:22]
wire [63:0] rom_351 = 64'h7663736972007974; // @[BootROM.scala:50:22]
wire [63:0] rom_352 = 64'h6C63007665646E2C; // @[BootROM.scala:50:22]
wire [63:0] rom_353 = 64'h746E6900736B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_354 = 64'h702D747075727265; // @[BootROM.scala:50:22]
wire [63:0] rom_355 = 64'h6E6900746E657261; // @[BootROM.scala:50:22]
wire [63:0] rom_356 = 64'h7374707572726574; // @[BootROM.scala:50:22]
wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_357 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_358 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_359 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_360 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_361 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_362 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_363 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_364 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_365 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_366 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_367 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_368 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_369 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_370 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_371 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_372 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_373 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_374 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_375 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_376 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_377 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_378 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_379 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_380 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_381 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_382 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_383 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_384 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_385 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_386 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_387 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_388 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_389 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_390 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_391 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_392 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_393 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_394 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_395 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_396 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_397 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_398 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_399 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_400 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_401 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_402 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_403 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_404 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_405 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_406 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_407 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_408 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_409 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_410 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_411 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_412 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_413 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_414 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_415 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_416 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_417 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_418 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_419 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_420 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_421 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_422 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_423 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_424 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_425 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_426 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_427 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_428 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_429 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_430 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_431 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_432 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_433 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_434 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_435 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_436 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_437 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_438 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_439 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_440 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_441 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_442 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_443 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_444 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_445 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_446 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_447 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_448 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_449 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_450 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_451 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_452 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_453 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_454 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_455 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_456 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_457 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_458 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_459 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_460 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_461 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_462 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_463 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_464 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_465 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_466 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_467 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_468 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_469 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_470 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_471 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_472 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_473 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22]
wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17]
wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9]
wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_in_a_ready_0; // @[BootROM.scala:41:9]
wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
wire auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9]
assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17]
wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17]
assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9]
wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34]
wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64]
wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53]
wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}]
assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17]
assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
TLMonitor_39 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_17 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_17( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
output io_q // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_q_0; // @[AsyncResetReg.scala:56:7]
reg reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_38 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_38( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_3 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0_3
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1_3( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_3 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SourceD_5 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<128>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, flip bs_rdat : { data : UInt<128>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, bs_wdat : { data : UInt<128>}, flip evict_req : { set : UInt<11>, way : UInt<4>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<11>, way : UInt<4>}, grant_safe : UInt<1>}
wire s1_valid : UInt<1>
wire s2_valid : UInt<1>
wire s3_valid : UInt<1>
wire s2_ready : UInt<1>
wire s3_ready : UInt<1>
wire s4_ready : UInt<1>
regreset busy : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s1_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _s1_req_reg_T = eq(busy, UInt<1>(0h0))
node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid)
reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock
when _s1_req_reg_T_1 :
connect s1_req_reg, io.req.bits
node _s1_req_T = eq(busy, UInt<1>(0h0))
node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg)
wire s1_x_bypass : UInt<2>
node _s1_latch_bypass_T = or(busy, io.req.valid)
node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0))
node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready)
reg s1_latch_bypass : UInt<1>, clock
connect s1_latch_bypass, _s1_latch_bypass_T_2
reg s1_bypass_r : UInt<2>, clock
when s1_latch_bypass :
connect s1_bypass_r, s1_x_bypass
node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r)
node _s1_mask_sizeOH_T = or(s1_req.size, UInt<4>(0h0))
node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0)
node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount)
node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 3, 0)
node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf))
node s1_mask_sub_0_1 = geq(s1_req.size, UInt<3>(0h4))
node s1_mask_size = bits(s1_mask_sizeOH, 3, 3)
node s1_mask_bit = bits(s1_req.offset, 3, 3)
node s1_mask_nbit = eq(s1_mask_bit, UInt<1>(0h0))
node s1_mask_eq = and(UInt<1>(0h1), s1_mask_nbit)
node _s1_mask_acc_T = and(s1_mask_size, s1_mask_eq)
node s1_mask_acc = or(s1_mask_sub_0_1, _s1_mask_acc_T)
node s1_mask_eq_1 = and(UInt<1>(0h1), s1_mask_bit)
node _s1_mask_acc_T_1 = and(s1_mask_size, s1_mask_eq_1)
node s1_mask_acc_1 = or(s1_mask_sub_0_1, _s1_mask_acc_T_1)
node _s1_mask_T = cat(s1_mask_acc_1, s1_mask_acc)
node _s1_mask_T_1 = not(s1_bypass)
node s1_mask = and(_s1_mask_T, _s1_mask_T_1)
node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6))
node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2))
node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1)
node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7))
node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3)
node _s1_need_r_T = orr(s1_mask)
node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0])
node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5))
node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2)
node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0))
node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4)
node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0))
node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3))
node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7)
node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8)
node _s1_valid_r_T = or(busy, io.req.valid)
node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r)
node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0))
node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2)
node _s1_need_pb_T = bits(s1_req.opcode, 2, 2)
node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0))
node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0)
node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2)
node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5))
node _s1_single_T_1 = or(_s1_single_T, s1_grant)
node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6))
node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2)
node s1_retires = eq(s1_single, UInt<1>(0h0))
node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size)
node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0)
node _s1_beats1_T_2 = not(_s1_beats1_T_1)
node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 4)
node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3)
node _s1_beat_T = shr(s1_req.offset, 4)
node s1_beat = or(_s1_beat_T, s1_counter)
node s1_last = eq(s1_counter, s1_beats1)
node s1_first = eq(s1_counter, UInt<1>(0h0))
node _T = eq(s1_latch_bypass, UInt<1>(0h0))
node _T_1 = or(busy, io.req.valid)
node _T_2 = eq(s1_need_r, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
connect io.bs_radr.valid, s1_valid_r
connect io.bs_radr.bits.noop, UInt<1>(0h0)
connect io.bs_radr.bits.way, s1_req.way
connect io.bs_radr.bits.set, s1_req.set
connect io.bs_radr.bits.beat, s1_beat
connect io.bs_radr.bits.mask, s1_mask
node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0))
node _T_5 = and(io.bs_radr.valid, _T_4)
inst queue of Queue3_BankedStoreInnerDecoded_5
connect queue.clock, clock
connect queue.reset, reset
node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid)
reg queue_io_enq_valid_REG : UInt<1>, clock
connect queue_io_enq_valid_REG, _queue_io_enq_valid_T
reg queue_io_enq_valid_REG_1 : UInt<1>, clock
connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG
connect queue.io.enq.valid, queue_io_enq_valid_REG_1
connect queue.io.enq.bits.data, io.bs_rdat.data
node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0))
node _T_7 = or(_T_6, queue.io.enq.ready)
node _T_8 = asUInt(reset)
node _T_9 = eq(_T_8, UInt<1>(0h0))
when _T_9 :
node _T_10 = eq(_T_7, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid || queue.io.enq.ready)\n") : printf
assert(clock, _T_7, UInt<1>(0h1), "") : assert
node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0))
node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid)
when _T_12 :
connect s1_block_r, UInt<1>(0h1)
when io.req.valid :
connect busy, UInt<1>(0h1)
node _T_13 = and(s1_valid, s2_ready)
when _T_13 :
node _s1_counter_T = add(s1_counter, UInt<1>(0h1))
node _s1_counter_T_1 = tail(_s1_counter_T, 1)
connect s1_counter, _s1_counter_T_1
connect s1_block_r, UInt<1>(0h0)
when s1_last :
connect s1_counter, UInt<1>(0h0)
connect busy, UInt<1>(0h0)
node _T_14 = eq(s2_ready, UInt<1>(0h0))
node _T_15 = and(s1_valid, _T_14)
node _io_req_ready_T = eq(busy, UInt<1>(0h0))
connect io.req.ready, _io_req_ready_T
node _s1_valid_T = or(busy, io.req.valid)
node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0))
node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready)
node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2)
connect s1_valid, _s1_valid_T_3
node s2_latch = and(s1_valid, s2_ready)
regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0)
reg s2_beat : UInt<2>, clock
when s2_latch :
connect s2_beat, s1_beat
reg s2_bypass : UInt<2>, clock
when s2_latch :
connect s2_bypass, s1_bypass
reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock
when s2_latch :
connect s2_req, s1_req
reg s2_last : UInt<1>, clock
when s2_latch :
connect s2_last, s1_last
reg s2_need_r : UInt<1>, clock
when s2_latch :
connect s2_need_r, s1_need_r
reg s2_need_pb : UInt<1>, clock
when s2_latch :
connect s2_need_pb, s1_need_pb
reg s2_retires : UInt<1>, clock
when s2_latch :
connect s2_retires, s1_retires
node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0))
node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first)
reg s2_need_d : UInt<1>, clock
when s2_latch :
connect s2_need_d, _s2_need_d_T_1
wire s2_pdata_raw : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}
reg s2_pdata_r : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock
when s2_valid_pb :
connect s2_pdata_r, s2_pdata_raw
node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r)
node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data)
connect s2_pdata_raw.data, _s2_pdata_raw_data_T
node _s2_pdata_raw_mask_T = not(UInt<16>(0h0))
node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T)
connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1
node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt)
connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T
node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0])
connect io.pb_pop.valid, _io_pb_pop_valid_T
connect io.pb_pop.bits.index, s2_req.put
connect io.pb_pop.bits.last, s2_last
node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0))
node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T)
connect io.rel_pop.valid, _io_rel_pop_valid_T_1
connect io.rel_pop.bits.index, s2_req.put
connect io.rel_pop.bits.last, s2_last
node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0))
node _T_17 = and(io.pb_pop.valid, _T_16)
node _T_18 = eq(io.rel_pop.ready, UInt<1>(0h0))
node _T_19 = and(io.rel_pop.valid, _T_18)
node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready)
when pb_ready :
connect s2_valid_pb, UInt<1>(0h0)
node _T_20 = and(s2_valid, s3_ready)
when _T_20 :
connect s2_full, UInt<1>(0h0)
when s2_latch :
connect s2_valid_pb, s1_need_pb
when s2_latch :
connect s2_full, UInt<1>(0h1)
node _T_21 = eq(s3_ready, UInt<1>(0h0))
node _T_22 = and(s2_valid, _T_21)
node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0))
node _s2_valid_T_1 = or(_s2_valid_T, pb_ready)
node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1)
connect s2_valid, _s2_valid_T_2
node _s2_ready_T = eq(s2_full, UInt<1>(0h0))
node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0))
node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready)
node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2)
node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3)
connect s2_ready, _s2_ready_T_4
node s3_latch = and(s2_valid, s3_ready)
regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0)
reg s3_beat : UInt<2>, clock
when s3_latch :
connect s3_beat, s2_beat
reg s3_bypass : UInt<2>, clock
when s3_latch :
connect s3_bypass, s2_bypass
reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock
when s3_latch :
connect s3_req, s2_req
node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode)
reg s3_last : UInt<1>, clock
when s3_latch :
connect s3_last, s2_last
reg s3_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock
when s3_latch :
connect s3_pdata, s2_pdata
reg s3_need_pb : UInt<1>, clock
when s3_latch :
connect s3_need_pb, s2_need_pb
reg s3_retires : UInt<1>, clock
when s3_latch :
connect s3_retires, s2_retires
reg s3_need_r : UInt<1>, clock
when s3_latch :
connect s3_need_r, s2_need_r
node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6))
node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7))
node s3_acq = or(_s3_acq_T, _s3_acq_T_1)
wire s3_bypass_data : UInt
node _s3_rdata_T = bits(s3_bypass, 0, 0)
node _s3_rdata_T_1 = bits(s3_bypass, 1, 1)
node _s3_rdata_T_2 = bits(s3_bypass_data, 63, 0)
node _s3_rdata_T_3 = bits(s3_bypass_data, 127, 64)
node _s3_rdata_T_4 = bits(queue.io.deq.bits.data, 63, 0)
node _s3_rdata_T_5 = bits(queue.io.deq.bits.data, 127, 64)
node _s3_rdata_T_6 = mux(_s3_rdata_T, _s3_rdata_T_2, _s3_rdata_T_4)
node _s3_rdata_T_7 = mux(_s3_rdata_T_1, _s3_rdata_T_3, _s3_rdata_T_5)
node s3_rdata = cat(_s3_rdata_T_7, _s3_rdata_T_6)
node _grant_T = eq(s3_req.param, UInt<2>(0h2))
node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5))
wire resp_opcode : UInt<3>[8]
connect resp_opcode[0], UInt<1>(0h0)
connect resp_opcode[1], UInt<1>(0h0)
connect resp_opcode[2], UInt<1>(0h1)
connect resp_opcode[3], UInt<1>(0h1)
connect resp_opcode[4], UInt<1>(0h1)
connect resp_opcode[5], UInt<2>(0h2)
connect resp_opcode[6], grant
connect resp_opcode[7], UInt<3>(0h4)
wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect io.d, d
connect d.valid, s3_valid_d
node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6))
connect d.bits.opcode, _d_bits_opcode_T
node _d_bits_param_T = and(s3_req.prio[0], s3_acq)
node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0))
node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1))
node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0))
connect d.bits.param, _d_bits_param_T_3
connect d.bits.size, s3_req.size
connect d.bits.source, s3_req.source
connect d.bits.sink, s3_req.sink
connect d.bits.denied, s3_req.bad
connect d.bits.data, s3_rdata
node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0)
node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T)
connect d.bits.corrupt, _d_bits_corrupt_T_1
node _queue_io_deq_ready_T = and(s3_valid, s4_ready)
node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r)
connect queue.io.deq.ready, _queue_io_deq_ready_T_1
node _T_23 = eq(s3_full, UInt<1>(0h0))
node _T_24 = eq(s3_need_r, UInt<1>(0h0))
node _T_25 = or(_T_23, _T_24)
node _T_26 = or(_T_25, queue.io.deq.valid)
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full || !s3_need_r || queue.io.deq.valid)\n") : printf_1
assert(clock, _T_26, UInt<1>(0h1), "") : assert_1
when d.ready :
connect s3_valid_d, UInt<1>(0h0)
node _T_30 = and(s3_valid, s4_ready)
when _T_30 :
connect s3_full, UInt<1>(0h0)
when s3_latch :
connect s3_valid_d, s2_need_d
when s3_latch :
connect s3_full, UInt<1>(0h1)
node _T_31 = eq(s4_ready, UInt<1>(0h0))
node _T_32 = and(s3_valid, _T_31)
node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0))
node _s3_valid_T_1 = or(_s3_valid_T, d.ready)
node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1)
connect s3_valid, _s3_valid_T_2
node _s3_ready_T = eq(s3_full, UInt<1>(0h0))
node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0))
node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready)
node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2)
node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3)
connect s3_ready, _s3_ready_T_4
node _s4_latch_T = and(s3_valid, s3_retires)
node s4_latch = and(_s4_latch_T, s4_ready)
regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0)
reg s4_beat : UInt<2>, clock
when s4_latch :
connect s4_beat, s3_beat
reg s4_need_r : UInt<1>, clock
when s4_latch :
connect s4_need_r, s3_need_r
reg s4_need_bs : UInt<1>, clock
when s4_latch :
connect s4_need_bs, s3_need_pb
reg s4_need_pb : UInt<1>, clock
when s4_latch :
connect s4_need_pb, s3_need_pb
reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock
when s4_latch :
connect s4_req, s3_req
reg s4_adjusted_opcode : UInt<3>, clock
when s4_latch :
connect s4_adjusted_opcode, s3_adjusted_opcode
reg s4_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock
when s4_latch :
connect s4_pdata, s3_pdata
reg s4_rdata : UInt<128>, clock
when s4_latch :
connect s4_rdata, s3_rdata
inst atomics of Atomics_5
connect atomics.clock, clock
connect atomics.reset, reset
connect atomics.io.write, s4_req.prio[2]
connect atomics.io.a.opcode, s4_adjusted_opcode
connect atomics.io.a.param, s4_req.param
connect atomics.io.a.size, UInt<1>(0h0)
connect atomics.io.a.source, UInt<1>(0h0)
connect atomics.io.a.address, UInt<1>(0h0)
connect atomics.io.a.mask, s4_pdata.mask
connect atomics.io.a.data, s4_pdata.data
invalidate atomics.io.a.corrupt
connect atomics.io.data_in, s4_rdata
node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs)
connect io.bs_wadr.valid, _io_bs_wadr_valid_T
connect io.bs_wadr.bits.noop, UInt<1>(0h0)
connect io.bs_wadr.bits.way, s4_req.way
connect io.bs_wadr.bits.set, s4_req.set
connect io.bs_wadr.bits.beat, s4_beat
node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0)
node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1)
node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2)
node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3)
node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4)
node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5)
node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6)
node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7)
node _io_bs_wadr_bits_mask_T_8 = bits(s4_pdata.mask, 8, 8)
node _io_bs_wadr_bits_mask_T_9 = bits(s4_pdata.mask, 9, 9)
node _io_bs_wadr_bits_mask_T_10 = bits(s4_pdata.mask, 10, 10)
node _io_bs_wadr_bits_mask_T_11 = bits(s4_pdata.mask, 11, 11)
node _io_bs_wadr_bits_mask_T_12 = bits(s4_pdata.mask, 12, 12)
node _io_bs_wadr_bits_mask_T_13 = bits(s4_pdata.mask, 13, 13)
node _io_bs_wadr_bits_mask_T_14 = bits(s4_pdata.mask, 14, 14)
node _io_bs_wadr_bits_mask_T_15 = bits(s4_pdata.mask, 15, 15)
node _io_bs_wadr_bits_mask_T_16 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1)
node _io_bs_wadr_bits_mask_T_17 = or(_io_bs_wadr_bits_mask_T_16, _io_bs_wadr_bits_mask_T_2)
node _io_bs_wadr_bits_mask_T_18 = or(_io_bs_wadr_bits_mask_T_17, _io_bs_wadr_bits_mask_T_3)
node _io_bs_wadr_bits_mask_T_19 = or(_io_bs_wadr_bits_mask_T_18, _io_bs_wadr_bits_mask_T_4)
node _io_bs_wadr_bits_mask_T_20 = or(_io_bs_wadr_bits_mask_T_19, _io_bs_wadr_bits_mask_T_5)
node _io_bs_wadr_bits_mask_T_21 = or(_io_bs_wadr_bits_mask_T_20, _io_bs_wadr_bits_mask_T_6)
node _io_bs_wadr_bits_mask_T_22 = or(_io_bs_wadr_bits_mask_T_21, _io_bs_wadr_bits_mask_T_7)
node _io_bs_wadr_bits_mask_T_23 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_9)
node _io_bs_wadr_bits_mask_T_24 = or(_io_bs_wadr_bits_mask_T_23, _io_bs_wadr_bits_mask_T_10)
node _io_bs_wadr_bits_mask_T_25 = or(_io_bs_wadr_bits_mask_T_24, _io_bs_wadr_bits_mask_T_11)
node _io_bs_wadr_bits_mask_T_26 = or(_io_bs_wadr_bits_mask_T_25, _io_bs_wadr_bits_mask_T_12)
node _io_bs_wadr_bits_mask_T_27 = or(_io_bs_wadr_bits_mask_T_26, _io_bs_wadr_bits_mask_T_13)
node _io_bs_wadr_bits_mask_T_28 = or(_io_bs_wadr_bits_mask_T_27, _io_bs_wadr_bits_mask_T_14)
node _io_bs_wadr_bits_mask_T_29 = or(_io_bs_wadr_bits_mask_T_28, _io_bs_wadr_bits_mask_T_15)
node _io_bs_wadr_bits_mask_T_30 = cat(_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22)
connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_30
connect io.bs_wdat.data, atomics.io.data_out
node _T_33 = and(s4_full, s4_need_pb)
node _T_34 = and(_T_33, s4_pdata.corrupt)
node _T_35 = eq(_T_34, UInt<1>(0h0))
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
node _T_38 = eq(_T_35, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2
assert(clock, _T_35, UInt<1>(0h1), "") : assert_2
node _T_39 = eq(io.bs_wadr.ready, UInt<1>(0h0))
node _T_40 = and(io.bs_wadr.valid, _T_39)
node _T_41 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_42 = and(s4_req.prio[0], _T_41)
node _T_43 = eq(s4_req.param, UInt<3>(0h0))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_46 = and(s4_req.prio[0], _T_45)
node _T_47 = eq(s4_req.param, UInt<3>(0h1))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_50 = and(s4_req.prio[0], _T_49)
node _T_51 = eq(s4_req.param, UInt<3>(0h2))
node _T_52 = and(_T_50, _T_51)
node _T_53 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_54 = and(s4_req.prio[0], _T_53)
node _T_55 = eq(s4_req.param, UInt<3>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(s4_req.opcode, UInt<2>(0h2))
node _T_58 = and(s4_req.prio[0], _T_57)
node _T_59 = eq(s4_req.param, UInt<3>(0h4))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(s4_req.opcode, UInt<2>(0h3))
node _T_62 = and(s4_req.prio[0], _T_61)
node _T_63 = eq(s4_req.param, UInt<3>(0h0))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(s4_req.opcode, UInt<2>(0h3))
node _T_66 = and(s4_req.prio[0], _T_65)
node _T_67 = eq(s4_req.param, UInt<3>(0h1))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(s4_req.opcode, UInt<2>(0h3))
node _T_70 = and(s4_req.prio[0], _T_69)
node _T_71 = eq(s4_req.param, UInt<3>(0h2))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(s4_req.opcode, UInt<2>(0h3))
node _T_74 = and(s4_req.prio[0], _T_73)
node _T_75 = eq(s4_req.param, UInt<3>(0h3))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(s4_need_bs, UInt<1>(0h0))
node _T_78 = or(io.bs_wadr.ready, _T_77)
when _T_78 :
connect s4_full, UInt<1>(0h0)
when s4_latch :
connect s4_full, UInt<1>(0h1)
node _s4_ready_T = eq(s3_retires, UInt<1>(0h0))
node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0))
node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1)
node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready)
node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0))
node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4)
connect s4_ready, _s4_ready_T_5
node _retire_T = eq(s4_need_bs, UInt<1>(0h0))
node _retire_T_1 = or(io.bs_wadr.ready, _retire_T)
node retire = and(s4_full, _retire_T_1)
reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock
when retire :
connect s5_req, s4_req
reg s5_beat : UInt<2>, clock
when retire :
connect s5_beat, s4_beat
reg s5_dat : UInt<128>, clock
when retire :
connect s5_dat, atomics.io.data_out
reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock
when retire :
connect s6_req, s5_req
reg s6_beat : UInt<2>, clock
when retire :
connect s6_beat, s5_beat
reg s6_dat : UInt<128>, clock
when retire :
connect s6_dat, s5_dat
reg s7_dat : UInt<128>, clock
when retire :
connect s7_dat, s6_dat
node pre_s3_req = mux(s3_latch, s2_req, s3_req)
node pre_s4_req = mux(s4_latch, s3_req, s4_req)
node pre_s5_req = mux(retire, s4_req, s5_req)
node pre_s6_req = mux(retire, s5_req, s6_req)
node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat)
node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat)
node pre_s5_beat = mux(retire, s4_beat, s5_beat)
node pre_s6_beat = mux(retire, s5_beat, s6_beat)
node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat)
node pre_s6_dat = mux(retire, s5_dat, s6_dat)
node pre_s7_dat = mux(retire, s6_dat, s7_dat)
node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0))
node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T)
node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0))
node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full)
node pre_s4_full = or(s4_latch, _pre_s4_full_T_3)
node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set)
node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way)
node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1)
node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat)
node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3)
node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full)
node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set)
node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way)
node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1)
node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat)
node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3)
node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set)
node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way)
node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1)
node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat)
node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3)
node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<4>(0h0))
node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0)
node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount)
node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 3, 0)
node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf))
node pre_s3_4_bypass_sub_0_1 = geq(pre_s4_req.size, UInt<3>(0h4))
node pre_s3_4_bypass_size = bits(pre_s3_4_bypass_sizeOH, 3, 3)
node pre_s3_4_bypass_bit = bits(pre_s4_req.offset, 3, 3)
node pre_s3_4_bypass_nbit = eq(pre_s3_4_bypass_bit, UInt<1>(0h0))
node pre_s3_4_bypass_eq = and(UInt<1>(0h1), pre_s3_4_bypass_nbit)
node _pre_s3_4_bypass_acc_T = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq)
node pre_s3_4_bypass_acc = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T)
node pre_s3_4_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_4_bypass_bit)
node _pre_s3_4_bypass_acc_T_1 = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq_1)
node pre_s3_4_bypass_acc_1 = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T_1)
node _pre_s3_4_bypass_T = cat(pre_s3_4_bypass_acc_1, pre_s3_4_bypass_acc)
node pre_s3_4_bypass = mux(pre_s3_4_match, _pre_s3_4_bypass_T, UInt<1>(0h0))
node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<4>(0h0))
node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0)
node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount)
node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 3, 0)
node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf))
node pre_s3_5_bypass_sub_0_1 = geq(pre_s5_req.size, UInt<3>(0h4))
node pre_s3_5_bypass_size = bits(pre_s3_5_bypass_sizeOH, 3, 3)
node pre_s3_5_bypass_bit = bits(pre_s5_req.offset, 3, 3)
node pre_s3_5_bypass_nbit = eq(pre_s3_5_bypass_bit, UInt<1>(0h0))
node pre_s3_5_bypass_eq = and(UInt<1>(0h1), pre_s3_5_bypass_nbit)
node _pre_s3_5_bypass_acc_T = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq)
node pre_s3_5_bypass_acc = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T)
node pre_s3_5_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_5_bypass_bit)
node _pre_s3_5_bypass_acc_T_1 = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq_1)
node pre_s3_5_bypass_acc_1 = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T_1)
node _pre_s3_5_bypass_T = cat(pre_s3_5_bypass_acc_1, pre_s3_5_bypass_acc)
node pre_s3_5_bypass = mux(pre_s3_5_match, _pre_s3_5_bypass_T, UInt<1>(0h0))
node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<4>(0h0))
node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0)
node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount)
node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 3, 0)
node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf))
node pre_s3_6_bypass_sub_0_1 = geq(pre_s6_req.size, UInt<3>(0h4))
node pre_s3_6_bypass_size = bits(pre_s3_6_bypass_sizeOH, 3, 3)
node pre_s3_6_bypass_bit = bits(pre_s6_req.offset, 3, 3)
node pre_s3_6_bypass_nbit = eq(pre_s3_6_bypass_bit, UInt<1>(0h0))
node pre_s3_6_bypass_eq = and(UInt<1>(0h1), pre_s3_6_bypass_nbit)
node _pre_s3_6_bypass_acc_T = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq)
node pre_s3_6_bypass_acc = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T)
node pre_s3_6_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_6_bypass_bit)
node _pre_s3_6_bypass_acc_T_1 = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq_1)
node pre_s3_6_bypass_acc_1 = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T_1)
node _pre_s3_6_bypass_T = cat(pre_s3_6_bypass_acc_1, pre_s3_6_bypass_acc)
node pre_s3_6_bypass = mux(pre_s3_6_match, _pre_s3_6_bypass_T, UInt<1>(0h0))
reg s3_bypass_data_REG : UInt, clock
connect s3_bypass_data_REG, pre_s3_4_bypass
node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0)
node _s3_bypass_data_T_1 = bits(pre_s3_6_bypass, 1, 1)
node _s3_bypass_data_T_2 = bits(pre_s6_dat, 63, 0)
node _s3_bypass_data_T_3 = bits(pre_s6_dat, 127, 64)
node _s3_bypass_data_T_4 = bits(pre_s7_dat, 63, 0)
node _s3_bypass_data_T_5 = bits(pre_s7_dat, 127, 64)
node _s3_bypass_data_T_6 = mux(_s3_bypass_data_T, _s3_bypass_data_T_2, _s3_bypass_data_T_4)
node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_1, _s3_bypass_data_T_3, _s3_bypass_data_T_5)
node _s3_bypass_data_T_8 = cat(_s3_bypass_data_T_7, _s3_bypass_data_T_6)
node _s3_bypass_data_T_9 = bits(pre_s3_5_bypass, 0, 0)
node _s3_bypass_data_T_10 = bits(pre_s3_5_bypass, 1, 1)
node _s3_bypass_data_T_11 = bits(pre_s5_dat, 63, 0)
node _s3_bypass_data_T_12 = bits(pre_s5_dat, 127, 64)
node _s3_bypass_data_T_13 = bits(_s3_bypass_data_T_8, 63, 0)
node _s3_bypass_data_T_14 = bits(_s3_bypass_data_T_8, 127, 64)
node _s3_bypass_data_T_15 = mux(_s3_bypass_data_T_9, _s3_bypass_data_T_11, _s3_bypass_data_T_13)
node _s3_bypass_data_T_16 = mux(_s3_bypass_data_T_10, _s3_bypass_data_T_12, _s3_bypass_data_T_14)
node _s3_bypass_data_T_17 = cat(_s3_bypass_data_T_16, _s3_bypass_data_T_15)
reg s3_bypass_data_REG_1 : UInt, clock
connect s3_bypass_data_REG_1, _s3_bypass_data_T_17
node _s3_bypass_data_T_18 = bits(s3_bypass_data_REG, 0, 0)
node _s3_bypass_data_T_19 = bits(s3_bypass_data_REG, 1, 1)
node _s3_bypass_data_T_20 = bits(atomics.io.data_out, 63, 0)
node _s3_bypass_data_T_21 = bits(atomics.io.data_out, 127, 64)
node _s3_bypass_data_T_22 = bits(s3_bypass_data_REG_1, 63, 0)
node _s3_bypass_data_T_23 = bits(s3_bypass_data_REG_1, 127, 64)
node _s3_bypass_data_T_24 = mux(_s3_bypass_data_T_18, _s3_bypass_data_T_20, _s3_bypass_data_T_22)
node _s3_bypass_data_T_25 = mux(_s3_bypass_data_T_19, _s3_bypass_data_T_21, _s3_bypass_data_T_23)
node _s3_bypass_data_T_26 = cat(_s3_bypass_data_T_25, _s3_bypass_data_T_24)
connect s3_bypass_data, _s3_bypass_data_T_26
node _s1_2_match_T = eq(s2_req.set, s1_req.set)
node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way)
node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1)
node _s1_2_match_T_3 = eq(s2_beat, s1_beat)
node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3)
node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full)
node s1_2_match = and(_s1_2_match_T_5, s2_retires)
node _s1_3_match_T = eq(s3_req.set, s1_req.set)
node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way)
node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1)
node _s1_3_match_T_3 = eq(s3_beat, s1_beat)
node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3)
node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full)
node s1_3_match = and(_s1_3_match_T_5, s3_retires)
node _s1_4_match_T = eq(s4_req.set, s1_req.set)
node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way)
node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1)
node _s1_4_match_T_3 = eq(s4_beat, s1_beat)
node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3)
node s1_4_match = and(_s1_4_match_T_4, s4_full)
node s2 = eq(s1_2_match, UInt<1>(0h1))
node s3 = eq(s1_3_match, UInt<1>(0h0))
node s4 = eq(s1_4_match, UInt<1>(0h0))
node _T_79 = and(io.req.valid, s2)
node _T_80 = and(_T_79, s3)
node _T_81 = and(_T_80, s4)
node s2_1 = eq(s1_2_match, UInt<1>(0h1))
node s3_1 = eq(s1_3_match, UInt<1>(0h0))
node s4_1 = eq(s1_4_match, UInt<1>(0h0))
node _T_82 = and(io.req.valid, s2_1)
node _T_83 = and(_T_82, s3_1)
node _T_84 = and(_T_83, s4_1)
node s2_2 = eq(s1_2_match, UInt<1>(0h1))
node s3_2 = eq(s1_3_match, UInt<1>(0h0))
node s4_2 = eq(s1_4_match, UInt<1>(0h0))
node _T_85 = and(io.req.valid, s2_2)
node _T_86 = and(_T_85, s3_2)
node _T_87 = and(_T_86, s4_2)
node s2_3 = eq(s1_2_match, UInt<1>(0h1))
node s3_3 = eq(s1_3_match, UInt<1>(0h0))
node s4_3 = eq(s1_4_match, UInt<1>(0h0))
node _T_88 = and(io.req.valid, s2_3)
node _T_89 = and(_T_88, s3_3)
node _T_90 = and(_T_89, s4_3)
node s2_4 = eq(s1_2_match, UInt<1>(0h1))
node s3_4 = eq(s1_3_match, UInt<1>(0h0))
node s4_4 = eq(s1_4_match, UInt<1>(0h0))
node _T_91 = and(io.req.valid, s2_4)
node _T_92 = and(_T_91, s3_4)
node _T_93 = and(_T_92, s4_4)
node s2_5 = eq(s1_2_match, UInt<1>(0h1))
node s3_5 = eq(s1_3_match, UInt<1>(0h0))
node s4_5 = eq(s1_4_match, UInt<1>(0h0))
node _T_94 = and(io.req.valid, s2_5)
node _T_95 = and(_T_94, s3_5)
node _T_96 = and(_T_95, s4_5)
node s2_6 = eq(s1_2_match, UInt<1>(0h1))
node s3_6 = eq(s1_3_match, UInt<1>(0h0))
node s4_6 = eq(s1_4_match, UInt<1>(0h0))
node _T_97 = and(io.req.valid, s2_6)
node _T_98 = and(_T_97, s3_6)
node _T_99 = and(_T_98, s4_6)
node s2_7 = eq(s1_2_match, UInt<1>(0h1))
node s3_7 = eq(s1_3_match, UInt<1>(0h0))
node s4_7 = eq(s1_4_match, UInt<1>(0h0))
node _T_100 = and(io.req.valid, s2_7)
node _T_101 = and(_T_100, s3_7)
node _T_102 = and(_T_101, s4_7)
node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<4>(0h0))
node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0)
node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount)
node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 3, 0)
node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf))
node s1_2_bypass_sub_0_1 = geq(s2_req.size, UInt<3>(0h4))
node s1_2_bypass_size = bits(s1_2_bypass_sizeOH, 3, 3)
node s1_2_bypass_bit = bits(s2_req.offset, 3, 3)
node s1_2_bypass_nbit = eq(s1_2_bypass_bit, UInt<1>(0h0))
node s1_2_bypass_eq = and(UInt<1>(0h1), s1_2_bypass_nbit)
node _s1_2_bypass_acc_T = and(s1_2_bypass_size, s1_2_bypass_eq)
node s1_2_bypass_acc = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T)
node s1_2_bypass_eq_1 = and(UInt<1>(0h1), s1_2_bypass_bit)
node _s1_2_bypass_acc_T_1 = and(s1_2_bypass_size, s1_2_bypass_eq_1)
node s1_2_bypass_acc_1 = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T_1)
node _s1_2_bypass_T = cat(s1_2_bypass_acc_1, s1_2_bypass_acc)
node s1_2_bypass = mux(s1_2_match, _s1_2_bypass_T, UInt<1>(0h0))
node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<4>(0h0))
node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0)
node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount)
node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 3, 0)
node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf))
node s1_3_bypass_sub_0_1 = geq(s3_req.size, UInt<3>(0h4))
node s1_3_bypass_size = bits(s1_3_bypass_sizeOH, 3, 3)
node s1_3_bypass_bit = bits(s3_req.offset, 3, 3)
node s1_3_bypass_nbit = eq(s1_3_bypass_bit, UInt<1>(0h0))
node s1_3_bypass_eq = and(UInt<1>(0h1), s1_3_bypass_nbit)
node _s1_3_bypass_acc_T = and(s1_3_bypass_size, s1_3_bypass_eq)
node s1_3_bypass_acc = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T)
node s1_3_bypass_eq_1 = and(UInt<1>(0h1), s1_3_bypass_bit)
node _s1_3_bypass_acc_T_1 = and(s1_3_bypass_size, s1_3_bypass_eq_1)
node s1_3_bypass_acc_1 = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T_1)
node _s1_3_bypass_T = cat(s1_3_bypass_acc_1, s1_3_bypass_acc)
node s1_3_bypass = mux(s1_3_match, _s1_3_bypass_T, UInt<1>(0h0))
node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<4>(0h0))
node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0)
node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount)
node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 3, 0)
node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf))
node s1_4_bypass_sub_0_1 = geq(s4_req.size, UInt<3>(0h4))
node s1_4_bypass_size = bits(s1_4_bypass_sizeOH, 3, 3)
node s1_4_bypass_bit = bits(s4_req.offset, 3, 3)
node s1_4_bypass_nbit = eq(s1_4_bypass_bit, UInt<1>(0h0))
node s1_4_bypass_eq = and(UInt<1>(0h1), s1_4_bypass_nbit)
node _s1_4_bypass_acc_T = and(s1_4_bypass_size, s1_4_bypass_eq)
node s1_4_bypass_acc = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T)
node s1_4_bypass_eq_1 = and(UInt<1>(0h1), s1_4_bypass_bit)
node _s1_4_bypass_acc_T_1 = and(s1_4_bypass_size, s1_4_bypass_eq_1)
node s1_4_bypass_acc_1 = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T_1)
node _s1_4_bypass_T = cat(s1_4_bypass_acc_1, s1_4_bypass_acc)
node s1_4_bypass = mux(s1_4_match, _s1_4_bypass_T, UInt<1>(0h0))
node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass)
node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass)
connect s1_x_bypass, _s1_x_bypass_T_1
node _io_evict_safe_T = eq(busy, UInt<1>(0h0))
node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way)
node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1)
node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set)
node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3)
node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0))
node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way)
node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6)
node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set)
node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8)
node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9)
node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0))
node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way)
node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12)
node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set)
node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14)
node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15)
node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0))
node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way)
node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18)
node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set)
node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20)
node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21)
connect io.evict_safe, _io_evict_safe_T_22
node _io_grant_safe_T = eq(busy, UInt<1>(0h0))
node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way)
node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1)
node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set)
node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3)
node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0))
node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way)
node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6)
node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set)
node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8)
node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9)
node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0))
node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way)
node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12)
node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set)
node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14)
node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15)
node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0))
node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way)
node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18)
node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set)
node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20)
node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21)
connect io.grant_safe, _io_grant_safe_T_22 | module SourceD_5( // @[SourceD.scala:48:7]
input clock, // @[SourceD.scala:48:7]
input reset, // @[SourceD.scala:48:7]
output io_req_ready, // @[SourceD.scala:50:14]
input io_req_valid, // @[SourceD.scala:50:14]
input io_req_bits_prio_0, // @[SourceD.scala:50:14]
input io_req_bits_prio_1, // @[SourceD.scala:50:14]
input io_req_bits_prio_2, // @[SourceD.scala:50:14]
input io_req_bits_control, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_param, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_size, // @[SourceD.scala:50:14]
input [5:0] io_req_bits_source, // @[SourceD.scala:50:14]
input [8:0] io_req_bits_tag, // @[SourceD.scala:50:14]
input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14]
input [5:0] io_req_bits_put, // @[SourceD.scala:50:14]
input [10:0] io_req_bits_set, // @[SourceD.scala:50:14]
input [3:0] io_req_bits_sink, // @[SourceD.scala:50:14]
input [3:0] io_req_bits_way, // @[SourceD.scala:50:14]
input io_req_bits_bad, // @[SourceD.scala:50:14]
input io_d_ready, // @[SourceD.scala:50:14]
output io_d_valid, // @[SourceD.scala:50:14]
output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14]
output [1:0] io_d_bits_param, // @[SourceD.scala:50:14]
output [2:0] io_d_bits_size, // @[SourceD.scala:50:14]
output [5:0] io_d_bits_source, // @[SourceD.scala:50:14]
output [3:0] io_d_bits_sink, // @[SourceD.scala:50:14]
output io_d_bits_denied, // @[SourceD.scala:50:14]
output [127:0] io_d_bits_data, // @[SourceD.scala:50:14]
output io_d_bits_corrupt, // @[SourceD.scala:50:14]
input io_pb_pop_ready, // @[SourceD.scala:50:14]
output io_pb_pop_valid, // @[SourceD.scala:50:14]
output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14]
output io_pb_pop_bits_last, // @[SourceD.scala:50:14]
input [127:0] io_pb_beat_data, // @[SourceD.scala:50:14]
input [15:0] io_pb_beat_mask, // @[SourceD.scala:50:14]
input io_pb_beat_corrupt, // @[SourceD.scala:50:14]
input io_rel_pop_ready, // @[SourceD.scala:50:14]
output io_rel_pop_valid, // @[SourceD.scala:50:14]
output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14]
output io_rel_pop_bits_last, // @[SourceD.scala:50:14]
input [127:0] io_rel_beat_data, // @[SourceD.scala:50:14]
input io_rel_beat_corrupt, // @[SourceD.scala:50:14]
input io_bs_radr_ready, // @[SourceD.scala:50:14]
output io_bs_radr_valid, // @[SourceD.scala:50:14]
output [3:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14]
output [10:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14]
output [1:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14]
output [1:0] io_bs_radr_bits_mask, // @[SourceD.scala:50:14]
input [127:0] io_bs_rdat_data, // @[SourceD.scala:50:14]
input io_bs_wadr_ready, // @[SourceD.scala:50:14]
output io_bs_wadr_valid, // @[SourceD.scala:50:14]
output [3:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14]
output [10:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14]
output [1:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14]
output [1:0] io_bs_wadr_bits_mask, // @[SourceD.scala:50:14]
output [127:0] io_bs_wdat_data, // @[SourceD.scala:50:14]
input [10:0] io_evict_req_set, // @[SourceD.scala:50:14]
input [3:0] io_evict_req_way, // @[SourceD.scala:50:14]
output io_evict_safe, // @[SourceD.scala:50:14]
input [10:0] io_grant_req_set, // @[SourceD.scala:50:14]
input [3:0] io_grant_req_way, // @[SourceD.scala:50:14]
output io_grant_safe // @[SourceD.scala:50:14]
);
wire [127:0] _atomics_io_data_out; // @[SourceD.scala:258:23]
wire _queue_io_enq_ready; // @[SourceD.scala:120:21]
wire _queue_io_deq_valid; // @[SourceD.scala:120:21]
wire [127:0] _queue_io_deq_bits_data; // @[SourceD.scala:120:21]
wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7]
wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7]
wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7]
wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7]
wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7]
wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7]
wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7]
wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7]
wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7]
wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7]
wire [3:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7]
wire [3:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7]
wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7]
wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7]
wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7]
wire [127:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7]
wire [15:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7]
wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7]
wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7]
wire [127:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7]
wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7]
wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7]
wire [127:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7]
wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7]
wire [10:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7]
wire [3:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7]
wire [10:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7]
wire [3:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7]
wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7]
wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7]
wire s1_mask_size = 1'h1; // @[Misc.scala:209:26]
wire pre_s3_4_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire pre_s3_5_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire pre_s3_6_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire s1_2_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire s1_3_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire s1_4_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28]
wire [15:0] _s2_pdata_raw_mask_T = 16'hFFFF; // @[SourceD.scala:161:64]
wire _io_req_ready_T; // @[SourceD.scala:140:19]
wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15]
wire d_valid; // @[SourceD.scala:218:15]
wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15]
wire [1:0] d_bits_param; // @[SourceD.scala:218:15]
wire [2:0] d_bits_size; // @[SourceD.scala:218:15]
wire [5:0] d_bits_source; // @[SourceD.scala:218:15]
wire [3:0] d_bits_sink; // @[SourceD.scala:218:15]
wire d_bits_denied; // @[SourceD.scala:218:15]
wire [127:0] d_bits_data; // @[SourceD.scala:218:15]
wire d_bits_corrupt; // @[SourceD.scala:218:15]
wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34]
wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35]
wire s1_valid_r; // @[SourceD.scala:96:56]
wire [3:0] s1_req_way; // @[SourceD.scala:88:19]
wire [10:0] s1_req_set; // @[SourceD.scala:88:19]
wire [1:0] s1_beat; // @[SourceD.scala:102:56]
wire [1:0] s1_mask; // @[SourceD.scala:92:76]
wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31]
wire [1:0] _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:275:30]
wire _io_evict_safe_T_22; // @[SourceD.scala:378:90]
wire _io_grant_safe_T_22; // @[SourceD.scala:385:90]
wire io_req_ready_0; // @[SourceD.scala:48:7]
wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7]
wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7]
wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7]
wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7]
wire [3:0] io_d_bits_sink_0; // @[SourceD.scala:48:7]
wire io_d_bits_denied_0; // @[SourceD.scala:48:7]
wire [127:0] io_d_bits_data_0; // @[SourceD.scala:48:7]
wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7]
wire io_d_valid_0; // @[SourceD.scala:48:7]
wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7]
wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7]
wire io_pb_pop_valid_0; // @[SourceD.scala:48:7]
wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7]
wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7]
wire io_rel_pop_valid_0; // @[SourceD.scala:48:7]
wire [3:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7]
wire [10:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7]
wire [1:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7]
wire [1:0] io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7]
wire io_bs_radr_valid_0; // @[SourceD.scala:48:7]
wire [3:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7]
wire [10:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7]
wire [1:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7]
wire [1:0] io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7]
wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7]
wire [127:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7]
wire io_evict_safe_0; // @[SourceD.scala:48:7]
wire io_grant_safe_0; // @[SourceD.scala:48:7]
wire _s1_valid_T_3; // @[SourceD.scala:141:38]
wire s1_valid; // @[SourceD.scala:74:22]
wire _s2_valid_T_2; // @[SourceD.scala:183:23]
wire s2_valid; // @[SourceD.scala:75:22]
wire _s3_valid_T_2; // @[SourceD.scala:241:23]
wire s3_valid; // @[SourceD.scala:76:22]
wire _s2_ready_T_4; // @[SourceD.scala:184:24]
wire s2_ready; // @[SourceD.scala:77:22]
wire _s3_ready_T_4; // @[SourceD.scala:242:24]
wire s3_ready; // @[SourceD.scala:78:22]
wire _s4_ready_T_5; // @[SourceD.scala:293:59]
wire s4_ready; // @[SourceD.scala:79:22]
reg busy; // @[SourceD.scala:84:21]
reg s1_block_r; // @[SourceD.scala:85:27]
reg [1:0] s1_counter; // @[SourceD.scala:86:27]
wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43]
wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}]
reg s1_req_reg_prio_0; // @[SourceD.scala:87:29]
reg s1_req_reg_prio_1; // @[SourceD.scala:87:29]
reg s1_req_reg_prio_2; // @[SourceD.scala:87:29]
reg s1_req_reg_control; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29]
reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29]
reg [8:0] s1_req_reg_tag; // @[SourceD.scala:87:29]
reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29]
reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29]
reg [10:0] s1_req_reg_set; // @[SourceD.scala:87:29]
reg [3:0] s1_req_reg_sink; // @[SourceD.scala:87:29]
reg [3:0] s1_req_reg_way; // @[SourceD.scala:87:29]
reg s1_req_reg_bad; // @[SourceD.scala:87:29]
wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20]
wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [8:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [3:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19]
assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19]
wire [1:0] _s1_x_bypass_T_1; // @[SourceD.scala:360:44]
wire [1:0] s1_x_bypass; // @[SourceD.scala:89:25]
wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40]
wire _s1_latch_bypass_T; // @[SourceD.scala:90:40]
assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40]
wire _s1_valid_r_T; // @[SourceD.scala:96:26]
assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26]
wire _s1_valid_T; // @[SourceD.scala:141:21]
assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21]
wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}]
wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}]
reg s1_latch_bypass; // @[SourceD.scala:90:32]
reg [1:0] s1_bypass_r; // @[SourceD.scala:91:62]
wire [1:0] s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}]
wire [3:0] _s1_mask_sizeOH_T = {1'h0, s1_req_size}; // @[Misc.scala:202:34]
wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire s1_mask_sub_0_1 = s1_req_size[2]; // @[Misc.scala:206:21]
wire s1_mask_bit = s1_req_offset[3]; // @[Misc.scala:210:26]
wire s1_mask_eq_1 = s1_mask_bit; // @[Misc.scala:210:26, :214:27]
wire s1_mask_nbit = ~s1_mask_bit; // @[Misc.scala:210:26, :211:20]
wire s1_mask_eq = s1_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _s1_mask_acc_T = s1_mask_eq; // @[Misc.scala:214:27, :215:38]
wire s1_mask_acc = s1_mask_sub_0_1 | _s1_mask_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _s1_mask_acc_T_1 = s1_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire s1_mask_acc_1 = s1_mask_sub_0_1 | _s1_mask_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire [1:0] _s1_mask_T = {s1_mask_acc_1, s1_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] _s1_mask_T_1 = ~s1_bypass; // @[SourceD.scala:91:22, :92:78]
assign s1_mask = _s1_mask_T & _s1_mask_T_1; // @[Misc.scala:222:10]
assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76]
wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33]
wire _s1_grant_T; // @[SourceD.scala:93:33]
assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33]
wire _s1_single_T_2; // @[SourceD.scala:98:89]
assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89]
wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66]
wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}]
wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93]
wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}]
wire _s1_need_r_T = |s1_mask; // @[SourceD.scala:92:76, :94:27]
wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}]
wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66]
wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}]
wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78]
wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}]
wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34]
wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65]
wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}]
wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50]
wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}]
wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59]
assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}]
assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56]
wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54]
wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}]
wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72]
wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}]
wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53]
wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}]
wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}]
wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20]
wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71]
wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}]
wire [1:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:4]; // @[package.scala:243:46]
wire [1:0] s1_beats1 = s1_single ? 2'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}]
wire [1:0] _s1_beat_T = s1_req_offset[5:4]; // @[SourceD.scala:88:19, :102:32]
assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}]
assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56]
wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28]
wire s1_first = s1_counter == 2'h0; // @[SourceD.scala:86:27, :104:29]
wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35]
reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40]
reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32]
wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27]
wire [2:0] _s1_counter_T = {1'h0, s1_counter} + 3'h1; // @[SourceD.scala:86:27, :130:30]
wire [1:0] _s1_counter_T_1 = _s1_counter_T[1:0]; // @[SourceD.scala:130:30]
assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19]
assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19]
wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42]
wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}]
assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}]
assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38]
reg s2_full; // @[SourceD.scala:147:24]
reg s2_valid_pb; // @[SourceD.scala:148:28]
reg [1:0] s2_beat; // @[SourceD.scala:149:26]
reg [1:0] s2_bypass; // @[SourceD.scala:150:28]
reg s2_req_prio_0; // @[SourceD.scala:151:25]
reg s2_req_prio_1; // @[SourceD.scala:151:25]
reg s2_req_prio_2; // @[SourceD.scala:151:25]
reg s2_req_control; // @[SourceD.scala:151:25]
reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25]
reg [2:0] s2_req_param; // @[SourceD.scala:151:25]
reg [2:0] s2_req_size; // @[SourceD.scala:151:25]
reg [5:0] s2_req_source; // @[SourceD.scala:151:25]
reg [8:0] s2_req_tag; // @[SourceD.scala:151:25]
reg [5:0] s2_req_offset; // @[SourceD.scala:151:25]
reg [5:0] s2_req_put; // @[SourceD.scala:151:25]
assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25]
assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25]
reg [10:0] s2_req_set; // @[SourceD.scala:151:25]
reg [3:0] s2_req_sink; // @[SourceD.scala:151:25]
reg [3:0] s2_req_way; // @[SourceD.scala:151:25]
reg s2_req_bad; // @[SourceD.scala:151:25]
reg s2_last; // @[SourceD.scala:152:26]
assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26]
assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26]
reg s2_need_r; // @[SourceD.scala:153:28]
reg s2_need_pb; // @[SourceD.scala:154:29]
reg s2_retires; // @[SourceD.scala:155:29]
wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29]
wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}]
reg s2_need_d; // @[SourceD.scala:156:28]
wire [127:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30]
wire [15:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30]
wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30]
wire [127:0] s2_pdata_raw_data; // @[SourceD.scala:157:26]
wire [15:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26]
wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26]
reg [127:0] s2_pdata_r_data; // @[package.scala:88:63]
reg [15:0] s2_pdata_r_mask; // @[package.scala:88:63]
reg s2_pdata_r_corrupt; // @[package.scala:88:63]
wire [127:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}]
wire [15:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}]
wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}]
assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30]
assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30]
assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 16'hFFFF; // @[SourceD.scala:48:7, :151:25, :161:30]
assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30]
assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30]
assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30]
assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34]
assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34]
wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38]
assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}]
assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35]
wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21]
wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27]
wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27]
wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}]
assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}]
assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23]
wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15]
wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41]
wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}]
wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}]
assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}]
assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24]
reg s3_full; // @[SourceD.scala:190:24]
reg s3_valid_d; // @[SourceD.scala:191:27]
assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15]
reg [1:0] s3_beat; // @[SourceD.scala:192:26]
wire [1:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24]
reg [1:0] s3_bypass; // @[SourceD.scala:193:28]
reg s3_req_prio_0; // @[SourceD.scala:194:25]
reg s3_req_prio_1; // @[SourceD.scala:194:25]
reg s3_req_prio_2; // @[SourceD.scala:194:25]
reg s3_req_control; // @[SourceD.scala:194:25]
reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25]
reg [2:0] s3_req_param; // @[SourceD.scala:194:25]
reg [2:0] s3_req_size; // @[SourceD.scala:194:25]
assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15]
reg [5:0] s3_req_source; // @[SourceD.scala:194:25]
assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15]
reg [8:0] s3_req_tag; // @[SourceD.scala:194:25]
reg [5:0] s3_req_offset; // @[SourceD.scala:194:25]
reg [5:0] s3_req_put; // @[SourceD.scala:194:25]
reg [10:0] s3_req_set; // @[SourceD.scala:194:25]
reg [3:0] s3_req_sink; // @[SourceD.scala:194:25]
assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15]
reg [3:0] s3_req_way; // @[SourceD.scala:194:25]
reg s3_req_bad; // @[SourceD.scala:194:25]
assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15]
wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [8:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [10:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [3:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [3:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31]
reg s3_last; // @[SourceD.scala:196:26]
reg [127:0] s3_pdata_data; // @[SourceD.scala:197:27]
reg [15:0] s3_pdata_mask; // @[SourceD.scala:197:27]
reg s3_pdata_corrupt; // @[SourceD.scala:197:27]
reg s3_need_pb; // @[SourceD.scala:198:29]
reg s3_retires; // @[SourceD.scala:199:29]
reg s3_need_r; // @[SourceD.scala:200:28]
wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30]
wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64]
wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}]
wire [127:0] _s3_bypass_data_T_26; // @[package.scala:45:27]
wire [127:0] s3_bypass_data; // @[SourceD.scala:206:28]
wire _s3_rdata_T = s3_bypass[0]; // @[SourceD.scala:193:28, :208:78]
wire _s3_rdata_T_1 = s3_bypass[1]; // @[SourceD.scala:193:28, :208:78]
wire [63:0] _s3_rdata_T_2 = s3_bypass_data[63:0]; // @[SourceD.scala:206:28, :207:78]
wire [63:0] _s3_rdata_T_3 = s3_bypass_data[127:64]; // @[SourceD.scala:206:28, :207:78]
wire [63:0] _s3_rdata_T_4 = _queue_io_deq_bits_data[63:0]; // @[SourceD.scala:120:21, :207:78]
wire [63:0] _s3_rdata_T_5 = _queue_io_deq_bits_data[127:64]; // @[SourceD.scala:120:21, :207:78]
wire [63:0] _s3_rdata_T_6 = _s3_rdata_T ? _s3_rdata_T_2 : _s3_rdata_T_4; // @[SourceD.scala:207:78, :208:78, :210:75]
wire [63:0] _s3_rdata_T_7 = _s3_rdata_T_1 ? _s3_rdata_T_3 : _s3_rdata_T_5; // @[SourceD.scala:207:78, :208:78, :210:75]
wire [127:0] s3_rdata = {_s3_rdata_T_7, _s3_rdata_T_6}; // @[package.scala:45:27]
assign d_bits_data = s3_rdata; // @[package.scala:45:27]
wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32]
wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}]
wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28]
assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15]
wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24]
assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15]
wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24]
assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15]
wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32]
assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15]
wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24]
assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24]
assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24]
wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40]
wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68]
wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}]
assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}]
assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24]
wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48]
assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}]
assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32]
wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34]
wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}]
wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27]
wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}]
assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}]
assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23]
wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15]
wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41]
wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}]
wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}]
assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}]
assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24]
wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27]
wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}]
reg s4_full; // @[SourceD.scala:248:24]
reg [1:0] s4_beat; // @[SourceD.scala:249:26]
assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26]
wire [1:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24]
reg s4_need_r; // @[SourceD.scala:250:28]
reg s4_need_bs; // @[SourceD.scala:251:29]
reg s4_need_pb; // @[SourceD.scala:252:29]
reg s4_req_prio_0; // @[SourceD.scala:253:25]
reg s4_req_prio_1; // @[SourceD.scala:253:25]
reg s4_req_prio_2; // @[SourceD.scala:253:25]
reg s4_req_control; // @[SourceD.scala:253:25]
reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25]
reg [2:0] s4_req_param; // @[SourceD.scala:253:25]
reg [2:0] s4_req_size; // @[SourceD.scala:253:25]
reg [5:0] s4_req_source; // @[SourceD.scala:253:25]
reg [8:0] s4_req_tag; // @[SourceD.scala:253:25]
reg [5:0] s4_req_offset; // @[SourceD.scala:253:25]
reg [5:0] s4_req_put; // @[SourceD.scala:253:25]
reg [10:0] s4_req_set; // @[SourceD.scala:253:25]
assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25]
reg [3:0] s4_req_sink; // @[SourceD.scala:253:25]
reg [3:0] s4_req_way; // @[SourceD.scala:253:25]
assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25]
reg s4_req_bad; // @[SourceD.scala:253:25]
wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [8:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [10:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [3:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [3:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37]
reg [127:0] s4_pdata_data; // @[SourceD.scala:255:27]
reg [15:0] s4_pdata_mask; // @[SourceD.scala:255:27]
reg s4_pdata_corrupt; // @[SourceD.scala:255:27]
reg [127:0] s4_rdata; // @[SourceD.scala:256:27]
assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31]
assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31]
wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_8 = s4_pdata_mask[8]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_9 = s4_pdata_mask[9]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_10 = s4_pdata_mask[10]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_11 = s4_pdata_mask[11]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_12 = s4_pdata_mask[12]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_13 = s4_pdata_mask[13]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_14 = s4_pdata_mask[14]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_15 = s4_pdata_mask[15]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_16 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_17 = _io_bs_wadr_bits_mask_T_16 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_18 = _io_bs_wadr_bits_mask_T_17 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_19 = _io_bs_wadr_bits_mask_T_18 | _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_20 = _io_bs_wadr_bits_mask_T_19 | _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_21 = _io_bs_wadr_bits_mask_T_20 | _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_22 = _io_bs_wadr_bits_mask_T_21 | _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_23 = _io_bs_wadr_bits_mask_T_8 | _io_bs_wadr_bits_mask_T_9; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_24 = _io_bs_wadr_bits_mask_T_23 | _io_bs_wadr_bits_mask_T_10; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_25 = _io_bs_wadr_bits_mask_T_24 | _io_bs_wadr_bits_mask_T_11; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_26 = _io_bs_wadr_bits_mask_T_25 | _io_bs_wadr_bits_mask_T_12; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_27 = _io_bs_wadr_bits_mask_T_26 | _io_bs_wadr_bits_mask_T_13; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_28 = _io_bs_wadr_bits_mask_T_27 | _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_29 = _io_bs_wadr_bits_mask_T_28 | _io_bs_wadr_bits_mask_T_15; // @[SourceD.scala:275:{45,87}]
assign _io_bs_wadr_bits_mask_T_30 = {_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22}; // @[SourceD.scala:275:{30,87}]
assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:48:7, :275:30] |
Generate the Verilog code corresponding to this FIRRTL code module Tile_148 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_404
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_148( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_404 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_23 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 6)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 6)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<6>(0h20))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<6>(0h21))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<6>(0h22))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<6>(0h23))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_64 = shr(io.in.a.bits.source, 6)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_77 = shr(io.in.a.bits.source, 6)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<6>(0h20))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<6>(0h21))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<6>(0h22))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<6>(0h23))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_164 = shr(io.in.a.bits.source, 6)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_170 = shr(io.in.a.bits.source, 6)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_177 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_178 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_179 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = and(_T_192, _T_197)
node _T_199 = or(UInt<1>(0h0), _T_198)
node _T_200 = and(_T_191, _T_199)
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(_T_200, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_200, UInt<1>(0h1), "") : assert_2
node _T_204 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<6>(0h20))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<6>(0h21))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<6>(0h22))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<6>(0h23))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_229 = shr(io.in.a.bits.source, 6)
node _T_230 = eq(_T_229, UInt<1>(0h1))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_234 = and(_T_232, _T_233)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_235 = shr(io.in.a.bits.source, 6)
node _T_236 = eq(_T_235, UInt<1>(0h0))
node _T_237 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_238 = and(_T_236, _T_237)
node _T_239 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_242 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_243 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_244 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_204
connect _WIRE[1], _T_210
connect _WIRE[2], _T_216
connect _WIRE[3], _T_222
connect _WIRE[4], _T_228
connect _WIRE[5], _T_234
connect _WIRE[6], _T_240
connect _WIRE[7], _T_241
connect _WIRE[8], _T_242
connect _WIRE[9], _T_243
connect _WIRE[10], _T_244
node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[7], _T_245, UInt<1>(0h0))
node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = or(_T_246, _T_247)
node _T_258 = or(_T_257, _T_248)
node _T_259 = or(_T_258, _T_249)
node _T_260 = or(_T_259, _T_250)
node _T_261 = or(_T_260, _T_251)
node _T_262 = or(_T_261, _T_252)
node _T_263 = or(_T_262, _T_253)
node _T_264 = or(_T_263, _T_254)
node _T_265 = or(_T_264, _T_255)
node _T_266 = or(_T_265, _T_256)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_266
node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_269 = and(_T_267, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_WIRE_1, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_278, UInt<1>(0h1), "") : assert_3
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(source_ok, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_285, UInt<1>(0h1), "") : assert_5
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(is_aligned, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_292, UInt<1>(0h1), "") : assert_7
node _T_296 = not(io.in.a.bits.mask)
node _T_297 = eq(_T_296, UInt<1>(0h0))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_297, UInt<1>(0h1), "") : assert_8
node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_301, UInt<1>(0h1), "") : assert_9
node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_305 :
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_310 = shr(io.in.a.bits.source, 2)
node _T_311 = eq(_T_310, UInt<6>(0h20))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_315 = and(_T_313, _T_314)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_316 = shr(io.in.a.bits.source, 2)
node _T_317 = eq(_T_316, UInt<6>(0h21))
node _T_318 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_319 = and(_T_317, _T_318)
node _T_320 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_321 = and(_T_319, _T_320)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<6>(0h22))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<6>(0h23))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0)
node _T_334 = shr(io.in.a.bits.source, 6)
node _T_335 = eq(_T_334, UInt<1>(0h1))
node _T_336 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_337 = and(_T_335, _T_336)
node _T_338 = leq(uncommonBits_22, UInt<6>(0h3f))
node _T_339 = and(_T_337, _T_338)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0)
node _T_340 = shr(io.in.a.bits.source, 6)
node _T_341 = eq(_T_340, UInt<1>(0h0))
node _T_342 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_343 = and(_T_341, _T_342)
node _T_344 = leq(uncommonBits_23, UInt<6>(0h3f))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_347 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_348 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_349 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_350 = or(_T_309, _T_315)
node _T_351 = or(_T_350, _T_321)
node _T_352 = or(_T_351, _T_327)
node _T_353 = or(_T_352, _T_333)
node _T_354 = or(_T_353, _T_339)
node _T_355 = or(_T_354, _T_345)
node _T_356 = or(_T_355, _T_346)
node _T_357 = or(_T_356, _T_347)
node _T_358 = or(_T_357, _T_348)
node _T_359 = or(_T_358, _T_349)
node _T_360 = and(_T_308, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<13>(0h1000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = and(_T_362, _T_367)
node _T_369 = or(UInt<1>(0h0), _T_368)
node _T_370 = and(_T_361, _T_369)
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_370, UInt<1>(0h1), "") : assert_10
node _T_374 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<6>(0h20))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<6>(0h21))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<6>(0h22))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<6>(0h23))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0)
node _T_399 = shr(io.in.a.bits.source, 6)
node _T_400 = eq(_T_399, UInt<1>(0h1))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_28, UInt<6>(0h3f))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0)
node _T_405 = shr(io.in.a.bits.source, 6)
node _T_406 = eq(_T_405, UInt<1>(0h0))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_29, UInt<6>(0h3f))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_412 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_413 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_414 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_374
connect _WIRE_2[1], _T_380
connect _WIRE_2[2], _T_386
connect _WIRE_2[3], _T_392
connect _WIRE_2[4], _T_398
connect _WIRE_2[5], _T_404
connect _WIRE_2[6], _T_410
connect _WIRE_2[7], _T_411
connect _WIRE_2[8], _T_412
connect _WIRE_2[9], _T_413
connect _WIRE_2[10], _T_414
node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE_2[7], _T_415, UInt<1>(0h0))
node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = or(_T_416, _T_417)
node _T_428 = or(_T_427, _T_418)
node _T_429 = or(_T_428, _T_419)
node _T_430 = or(_T_429, _T_420)
node _T_431 = or(_T_430, _T_421)
node _T_432 = or(_T_431, _T_422)
node _T_433 = or(_T_432, _T_423)
node _T_434 = or(_T_433, _T_424)
node _T_435 = or(_T_434, _T_425)
node _T_436 = or(_T_435, _T_426)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_436
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = and(_WIRE_3, _T_447)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_448, UInt<1>(0h1), "") : assert_11
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(source_ok, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_T_455, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_455, UInt<1>(0h1), "") : assert_13
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(is_aligned, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_462, UInt<1>(0h1), "") : assert_15
node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_466, UInt<1>(0h1), "") : assert_16
node _T_470 = not(io.in.a.bits.mask)
node _T_471 = eq(_T_470, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_471, UInt<1>(0h1), "") : assert_17
node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_475, UInt<1>(0h1), "") : assert_18
node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_479 :
node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<6>(0h20))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<6>(0h21))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<6>(0h22))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<6>(0h23))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0)
node _T_508 = shr(io.in.a.bits.source, 6)
node _T_509 = eq(_T_508, UInt<1>(0h1))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_34, UInt<6>(0h3f))
node _T_513 = and(_T_511, _T_512)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0)
node _T_514 = shr(io.in.a.bits.source, 6)
node _T_515 = eq(_T_514, UInt<1>(0h0))
node _T_516 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_517 = and(_T_515, _T_516)
node _T_518 = leq(uncommonBits_35, UInt<6>(0h3f))
node _T_519 = and(_T_517, _T_518)
node _T_520 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_521 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_522 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_523 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_524 = or(_T_483, _T_489)
node _T_525 = or(_T_524, _T_495)
node _T_526 = or(_T_525, _T_501)
node _T_527 = or(_T_526, _T_507)
node _T_528 = or(_T_527, _T_513)
node _T_529 = or(_T_528, _T_519)
node _T_530 = or(_T_529, _T_520)
node _T_531 = or(_T_530, _T_521)
node _T_532 = or(_T_531, _T_522)
node _T_533 = or(_T_532, _T_523)
node _T_534 = and(_T_482, _T_533)
node _T_535 = or(UInt<1>(0h0), _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_535, UInt<1>(0h1), "") : assert_19
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<13>(0h1000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = and(_T_542, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_549, UInt<1>(0h1), "") : assert_20
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(source_ok, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(is_aligned, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_559, UInt<1>(0h1), "") : assert_23
node _T_563 = eq(io.in.a.bits.mask, mask)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_563, UInt<1>(0h1), "") : assert_24
node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_567, UInt<1>(0h1), "") : assert_25
node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_571 :
node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_574 = and(_T_572, _T_573)
node _T_575 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_576 = shr(io.in.a.bits.source, 2)
node _T_577 = eq(_T_576, UInt<6>(0h20))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<6>(0h21))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_588 = shr(io.in.a.bits.source, 2)
node _T_589 = eq(_T_588, UInt<6>(0h22))
node _T_590 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_591 = and(_T_589, _T_590)
node _T_592 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_593 = and(_T_591, _T_592)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_594 = shr(io.in.a.bits.source, 2)
node _T_595 = eq(_T_594, UInt<6>(0h23))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_599 = and(_T_597, _T_598)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0)
node _T_600 = shr(io.in.a.bits.source, 6)
node _T_601 = eq(_T_600, UInt<1>(0h1))
node _T_602 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_603 = and(_T_601, _T_602)
node _T_604 = leq(uncommonBits_40, UInt<6>(0h3f))
node _T_605 = and(_T_603, _T_604)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0)
node _T_606 = shr(io.in.a.bits.source, 6)
node _T_607 = eq(_T_606, UInt<1>(0h0))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_41, UInt<6>(0h3f))
node _T_611 = and(_T_609, _T_610)
node _T_612 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_613 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_614 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_615 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_616 = or(_T_575, _T_581)
node _T_617 = or(_T_616, _T_587)
node _T_618 = or(_T_617, _T_593)
node _T_619 = or(_T_618, _T_599)
node _T_620 = or(_T_619, _T_605)
node _T_621 = or(_T_620, _T_611)
node _T_622 = or(_T_621, _T_612)
node _T_623 = or(_T_622, _T_613)
node _T_624 = or(_T_623, _T_614)
node _T_625 = or(_T_624, _T_615)
node _T_626 = and(_T_574, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_629 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_630 = and(_T_628, _T_629)
node _T_631 = or(UInt<1>(0h0), _T_630)
node _T_632 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_633 = cvt(_T_632)
node _T_634 = and(_T_633, asSInt(UInt<13>(0h1000)))
node _T_635 = asSInt(_T_634)
node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0)))
node _T_637 = and(_T_631, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = and(_T_627, _T_638)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_639, UInt<1>(0h1), "") : assert_26
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(source_ok, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(is_aligned, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_649, UInt<1>(0h1), "") : assert_29
node _T_653 = eq(io.in.a.bits.mask, mask)
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_653, UInt<1>(0h1), "") : assert_30
node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_657 :
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_662 = shr(io.in.a.bits.source, 2)
node _T_663 = eq(_T_662, UInt<6>(0h20))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_668 = shr(io.in.a.bits.source, 2)
node _T_669 = eq(_T_668, UInt<6>(0h21))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_673 = and(_T_671, _T_672)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_674 = shr(io.in.a.bits.source, 2)
node _T_675 = eq(_T_674, UInt<6>(0h22))
node _T_676 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_677 = and(_T_675, _T_676)
node _T_678 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_679 = and(_T_677, _T_678)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_680 = shr(io.in.a.bits.source, 2)
node _T_681 = eq(_T_680, UInt<6>(0h23))
node _T_682 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_683 = and(_T_681, _T_682)
node _T_684 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0)
node _T_686 = shr(io.in.a.bits.source, 6)
node _T_687 = eq(_T_686, UInt<1>(0h1))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_46, UInt<6>(0h3f))
node _T_691 = and(_T_689, _T_690)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0)
node _T_692 = shr(io.in.a.bits.source, 6)
node _T_693 = eq(_T_692, UInt<1>(0h0))
node _T_694 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_695 = and(_T_693, _T_694)
node _T_696 = leq(uncommonBits_47, UInt<6>(0h3f))
node _T_697 = and(_T_695, _T_696)
node _T_698 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_699 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_700 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_701 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_702 = or(_T_661, _T_667)
node _T_703 = or(_T_702, _T_673)
node _T_704 = or(_T_703, _T_679)
node _T_705 = or(_T_704, _T_685)
node _T_706 = or(_T_705, _T_691)
node _T_707 = or(_T_706, _T_697)
node _T_708 = or(_T_707, _T_698)
node _T_709 = or(_T_708, _T_699)
node _T_710 = or(_T_709, _T_700)
node _T_711 = or(_T_710, _T_701)
node _T_712 = and(_T_660, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_712)
node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_715 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_716 = and(_T_714, _T_715)
node _T_717 = or(UInt<1>(0h0), _T_716)
node _T_718 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = and(_T_713, _T_724)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_725, UInt<1>(0h1), "") : assert_31
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(source_ok, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(is_aligned, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_735, UInt<1>(0h1), "") : assert_34
node _T_739 = not(mask)
node _T_740 = and(io.in.a.bits.mask, _T_739)
node _T_741 = eq(_T_740, UInt<1>(0h0))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_741, UInt<1>(0h1), "") : assert_35
node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_745 :
node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_748 = and(_T_746, _T_747)
node _T_749 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_750 = shr(io.in.a.bits.source, 2)
node _T_751 = eq(_T_750, UInt<6>(0h20))
node _T_752 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_753 = and(_T_751, _T_752)
node _T_754 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_755 = and(_T_753, _T_754)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_756 = shr(io.in.a.bits.source, 2)
node _T_757 = eq(_T_756, UInt<6>(0h21))
node _T_758 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_759 = and(_T_757, _T_758)
node _T_760 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_761 = and(_T_759, _T_760)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<6>(0h22))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_768 = shr(io.in.a.bits.source, 2)
node _T_769 = eq(_T_768, UInt<6>(0h23))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_773 = and(_T_771, _T_772)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0)
node _T_774 = shr(io.in.a.bits.source, 6)
node _T_775 = eq(_T_774, UInt<1>(0h1))
node _T_776 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_777 = and(_T_775, _T_776)
node _T_778 = leq(uncommonBits_52, UInt<6>(0h3f))
node _T_779 = and(_T_777, _T_778)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0)
node _T_780 = shr(io.in.a.bits.source, 6)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_783 = and(_T_781, _T_782)
node _T_784 = leq(uncommonBits_53, UInt<6>(0h3f))
node _T_785 = and(_T_783, _T_784)
node _T_786 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_787 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_788 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_789 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_790 = or(_T_749, _T_755)
node _T_791 = or(_T_790, _T_761)
node _T_792 = or(_T_791, _T_767)
node _T_793 = or(_T_792, _T_773)
node _T_794 = or(_T_793, _T_779)
node _T_795 = or(_T_794, _T_785)
node _T_796 = or(_T_795, _T_786)
node _T_797 = or(_T_796, _T_787)
node _T_798 = or(_T_797, _T_788)
node _T_799 = or(_T_798, _T_789)
node _T_800 = and(_T_748, _T_799)
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_803 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_804 = and(_T_802, _T_803)
node _T_805 = or(UInt<1>(0h0), _T_804)
node _T_806 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_807 = cvt(_T_806)
node _T_808 = and(_T_807, asSInt(UInt<13>(0h1000)))
node _T_809 = asSInt(_T_808)
node _T_810 = eq(_T_809, asSInt(UInt<1>(0h0)))
node _T_811 = and(_T_805, _T_810)
node _T_812 = or(UInt<1>(0h0), _T_811)
node _T_813 = and(_T_801, _T_812)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_813, UInt<1>(0h1), "") : assert_36
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(source_ok, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(is_aligned, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_823 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_824 = asUInt(reset)
node _T_825 = eq(_T_824, UInt<1>(0h0))
when _T_825 :
node _T_826 = eq(_T_823, UInt<1>(0h0))
when _T_826 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_823, UInt<1>(0h1), "") : assert_39
node _T_827 = eq(io.in.a.bits.mask, mask)
node _T_828 = asUInt(reset)
node _T_829 = eq(_T_828, UInt<1>(0h0))
when _T_829 :
node _T_830 = eq(_T_827, UInt<1>(0h0))
when _T_830 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_827, UInt<1>(0h1), "") : assert_40
node _T_831 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_831 :
node _T_832 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_833 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_834 = and(_T_832, _T_833)
node _T_835 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_836 = shr(io.in.a.bits.source, 2)
node _T_837 = eq(_T_836, UInt<6>(0h20))
node _T_838 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_839 = and(_T_837, _T_838)
node _T_840 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_841 = and(_T_839, _T_840)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_842 = shr(io.in.a.bits.source, 2)
node _T_843 = eq(_T_842, UInt<6>(0h21))
node _T_844 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_845 = and(_T_843, _T_844)
node _T_846 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_847 = and(_T_845, _T_846)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_848 = shr(io.in.a.bits.source, 2)
node _T_849 = eq(_T_848, UInt<6>(0h22))
node _T_850 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_851 = and(_T_849, _T_850)
node _T_852 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_853 = and(_T_851, _T_852)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_854 = shr(io.in.a.bits.source, 2)
node _T_855 = eq(_T_854, UInt<6>(0h23))
node _T_856 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_857 = and(_T_855, _T_856)
node _T_858 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_859 = and(_T_857, _T_858)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0)
node _T_860 = shr(io.in.a.bits.source, 6)
node _T_861 = eq(_T_860, UInt<1>(0h1))
node _T_862 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_863 = and(_T_861, _T_862)
node _T_864 = leq(uncommonBits_58, UInt<6>(0h3f))
node _T_865 = and(_T_863, _T_864)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0)
node _T_866 = shr(io.in.a.bits.source, 6)
node _T_867 = eq(_T_866, UInt<1>(0h0))
node _T_868 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_869 = and(_T_867, _T_868)
node _T_870 = leq(uncommonBits_59, UInt<6>(0h3f))
node _T_871 = and(_T_869, _T_870)
node _T_872 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_873 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_874 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_875 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_876 = or(_T_835, _T_841)
node _T_877 = or(_T_876, _T_847)
node _T_878 = or(_T_877, _T_853)
node _T_879 = or(_T_878, _T_859)
node _T_880 = or(_T_879, _T_865)
node _T_881 = or(_T_880, _T_871)
node _T_882 = or(_T_881, _T_872)
node _T_883 = or(_T_882, _T_873)
node _T_884 = or(_T_883, _T_874)
node _T_885 = or(_T_884, _T_875)
node _T_886 = and(_T_834, _T_885)
node _T_887 = or(UInt<1>(0h0), _T_886)
node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_889 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_890 = and(_T_888, _T_889)
node _T_891 = or(UInt<1>(0h0), _T_890)
node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = and(_T_891, _T_896)
node _T_898 = or(UInt<1>(0h0), _T_897)
node _T_899 = and(_T_887, _T_898)
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(_T_899, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_899, UInt<1>(0h1), "") : assert_41
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(source_ok, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(is_aligned, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_909 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(_T_909, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_909, UInt<1>(0h1), "") : assert_44
node _T_913 = eq(io.in.a.bits.mask, mask)
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_913, UInt<1>(0h1), "") : assert_45
node _T_917 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_917 :
node _T_918 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_919 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_920 = and(_T_918, _T_919)
node _T_921 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_922 = shr(io.in.a.bits.source, 2)
node _T_923 = eq(_T_922, UInt<6>(0h20))
node _T_924 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_925 = and(_T_923, _T_924)
node _T_926 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_927 = and(_T_925, _T_926)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_928 = shr(io.in.a.bits.source, 2)
node _T_929 = eq(_T_928, UInt<6>(0h21))
node _T_930 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_931 = and(_T_929, _T_930)
node _T_932 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_933 = and(_T_931, _T_932)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_934 = shr(io.in.a.bits.source, 2)
node _T_935 = eq(_T_934, UInt<6>(0h22))
node _T_936 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_937 = and(_T_935, _T_936)
node _T_938 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_939 = and(_T_937, _T_938)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_940 = shr(io.in.a.bits.source, 2)
node _T_941 = eq(_T_940, UInt<6>(0h23))
node _T_942 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_943 = and(_T_941, _T_942)
node _T_944 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_945 = and(_T_943, _T_944)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0)
node _T_946 = shr(io.in.a.bits.source, 6)
node _T_947 = eq(_T_946, UInt<1>(0h1))
node _T_948 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_949 = and(_T_947, _T_948)
node _T_950 = leq(uncommonBits_64, UInt<6>(0h3f))
node _T_951 = and(_T_949, _T_950)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0)
node _T_952 = shr(io.in.a.bits.source, 6)
node _T_953 = eq(_T_952, UInt<1>(0h0))
node _T_954 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_955 = and(_T_953, _T_954)
node _T_956 = leq(uncommonBits_65, UInt<6>(0h3f))
node _T_957 = and(_T_955, _T_956)
node _T_958 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_959 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_960 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_961 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_962 = or(_T_921, _T_927)
node _T_963 = or(_T_962, _T_933)
node _T_964 = or(_T_963, _T_939)
node _T_965 = or(_T_964, _T_945)
node _T_966 = or(_T_965, _T_951)
node _T_967 = or(_T_966, _T_957)
node _T_968 = or(_T_967, _T_958)
node _T_969 = or(_T_968, _T_959)
node _T_970 = or(_T_969, _T_960)
node _T_971 = or(_T_970, _T_961)
node _T_972 = and(_T_920, _T_971)
node _T_973 = or(UInt<1>(0h0), _T_972)
node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_976 = and(_T_974, _T_975)
node _T_977 = or(UInt<1>(0h0), _T_976)
node _T_978 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_979 = cvt(_T_978)
node _T_980 = and(_T_979, asSInt(UInt<13>(0h1000)))
node _T_981 = asSInt(_T_980)
node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0)))
node _T_983 = and(_T_977, _T_982)
node _T_984 = or(UInt<1>(0h0), _T_983)
node _T_985 = and(_T_973, _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_985, UInt<1>(0h1), "") : assert_46
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(source_ok, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(is_aligned, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_995 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_995, UInt<1>(0h1), "") : assert_49
node _T_999 = eq(io.in.a.bits.mask, mask)
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_999, UInt<1>(0h1), "") : assert_50
node _T_1003 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1007 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<6>(0h20))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<6>(0h21))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<6>(0h22))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<6>(0h23))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 6)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 6)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha0))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<8>(0ha1))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<8>(0ha2))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1011 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1011 :
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(source_ok_1, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1015 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_54
node _T_1019 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_55
node _T_1023 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_56
node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_57
node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1031 :
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(source_ok_1, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(sink_ok, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1038 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_60
node _T_1042 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1043 = asUInt(reset)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
when _T_1044 :
node _T_1045 = eq(_T_1042, UInt<1>(0h0))
when _T_1045 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1042, UInt<1>(0h1), "") : assert_61
node _T_1046 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_62
node _T_1050 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_63
node _T_1054 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1055 = or(UInt<1>(0h1), _T_1054)
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(_T_1055, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1055, UInt<1>(0h1), "") : assert_64
node _T_1059 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1059 :
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(source_ok_1, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(sink_ok, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1066 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_67
node _T_1070 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_68
node _T_1074 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_69
node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1079 = or(_T_1078, io.in.d.bits.corrupt)
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(_T_1079, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1079, UInt<1>(0h1), "") : assert_70
node _T_1083 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1084 = or(UInt<1>(0h1), _T_1083)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_71
node _T_1088 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(source_ok_1, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1092 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_73
node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_74
node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1101 = or(UInt<1>(0h1), _T_1100)
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_75
node _T_1105 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1105 :
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(source_ok_1, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1109 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_77
node _T_1113 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1114 = or(_T_1113, io.in.d.bits.corrupt)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_78
node _T_1118 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1119 = or(UInt<1>(0h1), _T_1118)
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_79
node _T_1123 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1123 :
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(source_ok_1, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1127 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_81
node _T_1131 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_82
node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1136 = or(UInt<1>(0h1), _T_1135)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<14>(0h0)
connect _WIRE_4.bits.source, UInt<9>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1140 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(_T_1140, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1140, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<9>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1144 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1148 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1152 = eq(a_first, UInt<1>(0h0))
node _T_1153 = and(io.in.a.valid, _T_1152)
when _T_1153 :
node _T_1154 = eq(io.in.a.bits.opcode, opcode)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_87
node _T_1158 = eq(io.in.a.bits.param, param)
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(_T_1158, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1158, UInt<1>(0h1), "") : assert_88
node _T_1162 = eq(io.in.a.bits.size, size)
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_89
node _T_1166 = eq(io.in.a.bits.source, source)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_90
node _T_1170 = eq(io.in.a.bits.address, address)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_91
node _T_1174 = and(io.in.a.ready, io.in.a.valid)
node _T_1175 = and(_T_1174, a_first)
when _T_1175 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1176 = eq(d_first, UInt<1>(0h0))
node _T_1177 = and(io.in.d.valid, _T_1176)
when _T_1177 :
node _T_1178 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_92
node _T_1182 = eq(io.in.d.bits.param, param_1)
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_93
node _T_1186 = eq(io.in.d.bits.size, size_1)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_94
node _T_1190 = eq(io.in.d.bits.source, source_1)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_95
node _T_1194 = eq(io.in.d.bits.sink, sink)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_96
node _T_1198 = eq(io.in.d.bits.denied, denied)
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_97
node _T_1202 = and(io.in.d.ready, io.in.d.valid)
node _T_1203 = and(_T_1202, d_first)
when _T_1203 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes : UInt<2056>, clock, reset, UInt<2056>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<257>
connect a_set, UInt<257>(0h0)
wire a_set_wo_ready : UInt<257>
connect a_set_wo_ready, UInt<257>(0h0)
wire a_opcodes_set : UInt<1028>
connect a_opcodes_set, UInt<1028>(0h0)
wire a_sizes_set : UInt<2056>
connect a_sizes_set, UInt<2056>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1204 = and(io.in.a.valid, a_first_1)
node _T_1205 = and(_T_1204, UInt<1>(0h1))
when _T_1205 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1206 = and(io.in.a.ready, io.in.a.valid)
node _T_1207 = and(_T_1206, a_first_1)
node _T_1208 = and(_T_1207, UInt<1>(0h1))
when _T_1208 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1209 = dshr(inflight, io.in.a.bits.source)
node _T_1210 = bits(_T_1209, 0, 0)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<257>
connect d_clr, UInt<257>(0h0)
wire d_clr_wo_ready : UInt<257>
connect d_clr_wo_ready, UInt<257>(0h0)
wire d_opcodes_clr : UInt<1028>
connect d_opcodes_clr, UInt<1028>(0h0)
wire d_sizes_clr : UInt<2056>
connect d_sizes_clr, UInt<2056>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1215 = and(io.in.d.valid, d_first_1)
node _T_1216 = and(_T_1215, UInt<1>(0h1))
node _T_1217 = eq(d_release_ack, UInt<1>(0h0))
node _T_1218 = and(_T_1216, _T_1217)
when _T_1218 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1219 = and(io.in.d.ready, io.in.d.valid)
node _T_1220 = and(_T_1219, d_first_1)
node _T_1221 = and(_T_1220, UInt<1>(0h1))
node _T_1222 = eq(d_release_ack, UInt<1>(0h0))
node _T_1223 = and(_T_1221, _T_1222)
when _T_1223 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1224 = and(io.in.d.valid, d_first_1)
node _T_1225 = and(_T_1224, UInt<1>(0h1))
node _T_1226 = eq(d_release_ack, UInt<1>(0h0))
node _T_1227 = and(_T_1225, _T_1226)
when _T_1227 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1228 = dshr(inflight, io.in.d.bits.source)
node _T_1229 = bits(_T_1228, 0, 0)
node _T_1230 = or(_T_1229, same_cycle_resp)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1234 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1235 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1236 = or(_T_1234, _T_1235)
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_100
node _T_1240 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_101
else :
node _T_1244 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1245 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1246 = or(_T_1244, _T_1245)
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_102
node _T_1250 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1251 = asUInt(reset)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
when _T_1252 :
node _T_1253 = eq(_T_1250, UInt<1>(0h0))
when _T_1253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1250, UInt<1>(0h1), "") : assert_103
node _T_1254 = and(io.in.d.valid, d_first_1)
node _T_1255 = and(_T_1254, a_first_1)
node _T_1256 = and(_T_1255, io.in.a.valid)
node _T_1257 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1258 = and(_T_1256, _T_1257)
node _T_1259 = eq(d_release_ack, UInt<1>(0h0))
node _T_1260 = and(_T_1258, _T_1259)
when _T_1260 :
node _T_1261 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1262 = or(_T_1261, io.in.a.ready)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_104
node _T_1266 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1267 = orr(a_set_wo_ready)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
node _T_1269 = or(_T_1266, _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_46
node _T_1273 = orr(inflight)
node _T_1274 = eq(_T_1273, UInt<1>(0h0))
node _T_1275 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1276 = or(_T_1274, _T_1275)
node _T_1277 = lt(watchdog, plusarg_reader.out)
node _T_1278 = or(_T_1276, _T_1277)
node _T_1279 = asUInt(reset)
node _T_1280 = eq(_T_1279, UInt<1>(0h0))
when _T_1280 :
node _T_1281 = eq(_T_1278, UInt<1>(0h0))
when _T_1281 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1278, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1282 = and(io.in.a.ready, io.in.a.valid)
node _T_1283 = and(io.in.d.ready, io.in.d.valid)
node _T_1284 = or(_T_1282, _T_1283)
when _T_1284 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes_1 : UInt<2056>, clock, reset, UInt<2056>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<14>(0h0)
connect _c_first_WIRE.bits.source, UInt<9>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<257>
connect c_set, UInt<257>(0h0)
wire c_set_wo_ready : UInt<257>
connect c_set_wo_ready, UInt<257>(0h0)
wire c_opcodes_set : UInt<1028>
connect c_opcodes_set, UInt<1028>(0h0)
wire c_sizes_set : UInt<2056>
connect c_sizes_set, UInt<2056>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<14>(0h0)
connect _WIRE_10.bits.source, UInt<9>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1285 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<14>(0h0)
connect _WIRE_12.bits.source, UInt<9>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1286 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1287 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1288 = and(_T_1286, _T_1287)
node _T_1289 = and(_T_1285, _T_1288)
when _T_1289 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<14>(0h0)
connect _WIRE_14.bits.source, UInt<9>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1290 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1291 = and(_T_1290, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<14>(0h0)
connect _WIRE_16.bits.source, UInt<9>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1292 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1293 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1294 = and(_T_1292, _T_1293)
node _T_1295 = and(_T_1291, _T_1294)
when _T_1295 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<14>(0h0)
connect _WIRE_18.bits.source, UInt<9>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1296 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1297 = bits(_T_1296, 0, 0)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<257>
connect d_clr_1, UInt<257>(0h0)
wire d_clr_wo_ready_1 : UInt<257>
connect d_clr_wo_ready_1, UInt<257>(0h0)
wire d_opcodes_clr_1 : UInt<1028>
connect d_opcodes_clr_1, UInt<1028>(0h0)
wire d_sizes_clr_1 : UInt<2056>
connect d_sizes_clr_1, UInt<2056>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1302 = and(io.in.d.valid, d_first_2)
node _T_1303 = and(_T_1302, UInt<1>(0h1))
node _T_1304 = and(_T_1303, d_release_ack_1)
when _T_1304 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1305 = and(io.in.d.ready, io.in.d.valid)
node _T_1306 = and(_T_1305, d_first_2)
node _T_1307 = and(_T_1306, UInt<1>(0h1))
node _T_1308 = and(_T_1307, d_release_ack_1)
when _T_1308 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1309 = and(io.in.d.valid, d_first_2)
node _T_1310 = and(_T_1309, UInt<1>(0h1))
node _T_1311 = and(_T_1310, d_release_ack_1)
when _T_1311 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1312 = dshr(inflight_1, io.in.d.bits.source)
node _T_1313 = bits(_T_1312, 0, 0)
node _T_1314 = or(_T_1313, same_cycle_resp_1)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<14>(0h0)
connect _WIRE_20.bits.source, UInt<9>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1318 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1319 = asUInt(reset)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
when _T_1320 :
node _T_1321 = eq(_T_1318, UInt<1>(0h0))
when _T_1321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1318, UInt<1>(0h1), "") : assert_109
else :
node _T_1322 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_110
node _T_1326 = and(io.in.d.valid, d_first_2)
node _T_1327 = and(_T_1326, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<14>(0h0)
connect _WIRE_22.bits.source, UInt<9>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1328 = and(_T_1327, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<14>(0h0)
connect _WIRE_24.bits.source, UInt<9>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1329 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1330 = and(_T_1328, _T_1329)
node _T_1331 = and(_T_1330, d_release_ack_1)
node _T_1332 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1333 = and(_T_1331, _T_1332)
when _T_1333 :
node _T_1334 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<14>(0h0)
connect _WIRE_26.bits.source, UInt<9>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1335 = or(_T_1334, _WIRE_27.ready)
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_111
node _T_1339 = orr(c_set_wo_ready)
when _T_1339 :
node _T_1340 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_47
node _T_1344 = orr(inflight_1)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
node _T_1346 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1347 = or(_T_1345, _T_1346)
node _T_1348 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1349 = or(_T_1347, _T_1348)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<14>(0h0)
connect _WIRE_28.bits.source, UInt<9>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1353 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1354 = and(io.in.d.ready, io.in.d.valid)
node _T_1355 = or(_T_1353, _T_1354)
when _T_1355 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_23( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4099:0] _c_sizes_set_T_1 = 4100'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [2055:0] c_sizes_set = 2056'h0; // @[Monitor.scala:741:34]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1282 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1282; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1282; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
wire _T_1355 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1355; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2055:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [2055:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [11:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [2055:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [2055:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_3 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1208 = _T_1282 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1208 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1208 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1208 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1208 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [11:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [4099:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1208 ? _a_sizes_set_T_1[2055:0] : 2056'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [2055:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1254 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1254 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1223 = _T_1355 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1223 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1223 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1223 ? _d_sizes_clr_T_5[2055:0] : 2056'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [2055:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [2055:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [2055:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [2055:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [2055:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [2055:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [2055:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1326 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1326 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1308 = _T_1355 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1308 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1308 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1308 ? _d_sizes_clr_T_11[2055:0] : 2056'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [2055:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
wire _source_ok_WIRE : UInt<1>[5]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2])
node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3])
node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = and(_T_11, _T_24)
node _T_65 = and(_T_64, _T_37)
node _T_66 = and(_T_65, _T_50)
node _T_67 = and(_T_66, _T_63)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_67, UInt<1>(0h1), "") : assert_1
node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_71 :
node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_76 = shr(io.in.a.bits.source, 2)
node _T_77 = eq(_T_76, UInt<1>(0h0))
node _T_78 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_79 = and(_T_77, _T_78)
node _T_80 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_81 = and(_T_79, _T_80)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_82 = shr(io.in.a.bits.source, 2)
node _T_83 = eq(_T_82, UInt<1>(0h1))
node _T_84 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_85 = and(_T_83, _T_84)
node _T_86 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_87 = and(_T_85, _T_86)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_88 = shr(io.in.a.bits.source, 2)
node _T_89 = eq(_T_88, UInt<2>(0h2))
node _T_90 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_91 = and(_T_89, _T_90)
node _T_92 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_93 = and(_T_91, _T_92)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_94 = shr(io.in.a.bits.source, 2)
node _T_95 = eq(_T_94, UInt<2>(0h3))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_99 = and(_T_97, _T_98)
node _T_100 = or(_T_75, _T_81)
node _T_101 = or(_T_100, _T_87)
node _T_102 = or(_T_101, _T_93)
node _T_103 = or(_T_102, _T_99)
node _T_104 = and(_T_74, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<27>(0h4000000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<15>(0h4000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = or(_T_111, _T_116)
node _T_148 = or(_T_147, _T_121)
node _T_149 = or(_T_148, _T_126)
node _T_150 = or(_T_149, _T_131)
node _T_151 = or(_T_150, _T_136)
node _T_152 = or(_T_151, _T_141)
node _T_153 = or(_T_152, _T_146)
node _T_154 = and(_T_106, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(_T_105, _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_156, UInt<1>(0h1), "") : assert_2
node _T_160 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_161 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_162 = and(_T_160, _T_161)
node _T_163 = or(UInt<1>(0h0), _T_162)
node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_170 = cvt(_T_169)
node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000)))
node _T_172 = asSInt(_T_171)
node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0)))
node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_175 = cvt(_T_174)
node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000)))
node _T_177 = asSInt(_T_176)
node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0)))
node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<27>(0h4000000)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<13>(0h1000)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<15>(0h4000)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = or(_T_168, _T_173)
node _T_205 = or(_T_204, _T_178)
node _T_206 = or(_T_205, _T_183)
node _T_207 = or(_T_206, _T_188)
node _T_208 = or(_T_207, _T_193)
node _T_209 = or(_T_208, _T_198)
node _T_210 = or(_T_209, _T_203)
node _T_211 = and(_T_163, _T_210)
node _T_212 = or(UInt<1>(0h0), _T_211)
node _T_213 = and(UInt<1>(0h0), _T_212)
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_213, UInt<1>(0h1), "") : assert_3
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(source_ok, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_220 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_221 = asUInt(reset)
node _T_222 = eq(_T_221, UInt<1>(0h0))
when _T_222 :
node _T_223 = eq(_T_220, UInt<1>(0h0))
when _T_223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_220, UInt<1>(0h1), "") : assert_5
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(is_aligned, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_227 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_228 = asUInt(reset)
node _T_229 = eq(_T_228, UInt<1>(0h0))
when _T_229 :
node _T_230 = eq(_T_227, UInt<1>(0h0))
when _T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_227, UInt<1>(0h1), "") : assert_7
node _T_231 = not(io.in.a.bits.mask)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_232, UInt<1>(0h1), "") : assert_8
node _T_236 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_237 = asUInt(reset)
node _T_238 = eq(_T_237, UInt<1>(0h0))
when _T_238 :
node _T_239 = eq(_T_236, UInt<1>(0h0))
when _T_239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_236, UInt<1>(0h1), "") : assert_9
node _T_240 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_240 :
node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_242 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_243 = and(_T_241, _T_242)
node _T_244 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_245 = shr(io.in.a.bits.source, 2)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_248 = and(_T_246, _T_247)
node _T_249 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_251 = shr(io.in.a.bits.source, 2)
node _T_252 = eq(_T_251, UInt<1>(0h1))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_256 = and(_T_254, _T_255)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_257 = shr(io.in.a.bits.source, 2)
node _T_258 = eq(_T_257, UInt<2>(0h2))
node _T_259 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_260 = and(_T_258, _T_259)
node _T_261 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_262 = and(_T_260, _T_261)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_263 = shr(io.in.a.bits.source, 2)
node _T_264 = eq(_T_263, UInt<2>(0h3))
node _T_265 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_266 = and(_T_264, _T_265)
node _T_267 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_268 = and(_T_266, _T_267)
node _T_269 = or(_T_244, _T_250)
node _T_270 = or(_T_269, _T_256)
node _T_271 = or(_T_270, _T_262)
node _T_272 = or(_T_271, _T_268)
node _T_273 = and(_T_243, _T_272)
node _T_274 = or(UInt<1>(0h0), _T_273)
node _T_275 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_276 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_277 = cvt(_T_276)
node _T_278 = and(_T_277, asSInt(UInt<14>(0h2000)))
node _T_279 = asSInt(_T_278)
node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0)))
node _T_281 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_292 = cvt(_T_291)
node _T_293 = and(_T_292, asSInt(UInt<18>(0h2f000)))
node _T_294 = asSInt(_T_293)
node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0)))
node _T_296 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<27>(0h4000000)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_307 = cvt(_T_306)
node _T_308 = and(_T_307, asSInt(UInt<13>(0h1000)))
node _T_309 = asSInt(_T_308)
node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<15>(0h4000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = or(_T_280, _T_285)
node _T_317 = or(_T_316, _T_290)
node _T_318 = or(_T_317, _T_295)
node _T_319 = or(_T_318, _T_300)
node _T_320 = or(_T_319, _T_305)
node _T_321 = or(_T_320, _T_310)
node _T_322 = or(_T_321, _T_315)
node _T_323 = and(_T_275, _T_322)
node _T_324 = or(UInt<1>(0h0), _T_323)
node _T_325 = and(_T_274, _T_324)
node _T_326 = asUInt(reset)
node _T_327 = eq(_T_326, UInt<1>(0h0))
when _T_327 :
node _T_328 = eq(_T_325, UInt<1>(0h0))
when _T_328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_325, UInt<1>(0h1), "") : assert_10
node _T_329 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_330 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_331 = and(_T_329, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<14>(0h2000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_339 = cvt(_T_338)
node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000)))
node _T_341 = asSInt(_T_340)
node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0)))
node _T_343 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_344 = cvt(_T_343)
node _T_345 = and(_T_344, asSInt(UInt<17>(0h10000)))
node _T_346 = asSInt(_T_345)
node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0)))
node _T_348 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_349 = cvt(_T_348)
node _T_350 = and(_T_349, asSInt(UInt<18>(0h2f000)))
node _T_351 = asSInt(_T_350)
node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0)))
node _T_353 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_359 = cvt(_T_358)
node _T_360 = and(_T_359, asSInt(UInt<27>(0h4000000)))
node _T_361 = asSInt(_T_360)
node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0)))
node _T_363 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<13>(0h1000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<15>(0h4000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = or(_T_337, _T_342)
node _T_374 = or(_T_373, _T_347)
node _T_375 = or(_T_374, _T_352)
node _T_376 = or(_T_375, _T_357)
node _T_377 = or(_T_376, _T_362)
node _T_378 = or(_T_377, _T_367)
node _T_379 = or(_T_378, _T_372)
node _T_380 = and(_T_332, _T_379)
node _T_381 = or(UInt<1>(0h0), _T_380)
node _T_382 = and(UInt<1>(0h0), _T_381)
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_382, UInt<1>(0h1), "") : assert_11
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(source_ok, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_389 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_389, UInt<1>(0h1), "") : assert_13
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(is_aligned, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_396 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_397 = asUInt(reset)
node _T_398 = eq(_T_397, UInt<1>(0h0))
when _T_398 :
node _T_399 = eq(_T_396, UInt<1>(0h0))
when _T_399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_396, UInt<1>(0h1), "") : assert_15
node _T_400 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_401 = asUInt(reset)
node _T_402 = eq(_T_401, UInt<1>(0h0))
when _T_402 :
node _T_403 = eq(_T_400, UInt<1>(0h0))
when _T_403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_400, UInt<1>(0h1), "") : assert_16
node _T_404 = not(io.in.a.bits.mask)
node _T_405 = eq(_T_404, UInt<1>(0h0))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_405, UInt<1>(0h1), "") : assert_17
node _T_409 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_409, UInt<1>(0h1), "") : assert_18
node _T_413 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_413 :
node _T_414 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_415 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_416 = and(_T_414, _T_415)
node _T_417 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_418 = shr(io.in.a.bits.source, 2)
node _T_419 = eq(_T_418, UInt<1>(0h0))
node _T_420 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_421 = and(_T_419, _T_420)
node _T_422 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_423 = and(_T_421, _T_422)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_424 = shr(io.in.a.bits.source, 2)
node _T_425 = eq(_T_424, UInt<1>(0h1))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_429 = and(_T_427, _T_428)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_430 = shr(io.in.a.bits.source, 2)
node _T_431 = eq(_T_430, UInt<2>(0h2))
node _T_432 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_433 = and(_T_431, _T_432)
node _T_434 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_435 = and(_T_433, _T_434)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_436 = shr(io.in.a.bits.source, 2)
node _T_437 = eq(_T_436, UInt<2>(0h3))
node _T_438 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_439 = and(_T_437, _T_438)
node _T_440 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_441 = and(_T_439, _T_440)
node _T_442 = or(_T_417, _T_423)
node _T_443 = or(_T_442, _T_429)
node _T_444 = or(_T_443, _T_435)
node _T_445 = or(_T_444, _T_441)
node _T_446 = and(_T_416, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = asUInt(reset)
node _T_449 = eq(_T_448, UInt<1>(0h0))
when _T_449 :
node _T_450 = eq(_T_447, UInt<1>(0h0))
when _T_450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_447, UInt<1>(0h1), "") : assert_19
node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_453 = and(_T_451, _T_452)
node _T_454 = or(UInt<1>(0h0), _T_453)
node _T_455 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_456 = cvt(_T_455)
node _T_457 = and(_T_456, asSInt(UInt<13>(0h1000)))
node _T_458 = asSInt(_T_457)
node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0)))
node _T_460 = and(_T_454, _T_459)
node _T_461 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_462 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_463 = and(_T_461, _T_462)
node _T_464 = or(UInt<1>(0h0), _T_463)
node _T_465 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_466 = cvt(_T_465)
node _T_467 = and(_T_466, asSInt(UInt<14>(0h2000)))
node _T_468 = asSInt(_T_467)
node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0)))
node _T_470 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_471 = cvt(_T_470)
node _T_472 = and(_T_471, asSInt(UInt<17>(0h10000)))
node _T_473 = asSInt(_T_472)
node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0)))
node _T_475 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_476 = cvt(_T_475)
node _T_477 = and(_T_476, asSInt(UInt<18>(0h2f000)))
node _T_478 = asSInt(_T_477)
node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0)))
node _T_480 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_481 = cvt(_T_480)
node _T_482 = and(_T_481, asSInt(UInt<17>(0h10000)))
node _T_483 = asSInt(_T_482)
node _T_484 = eq(_T_483, asSInt(UInt<1>(0h0)))
node _T_485 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_486 = cvt(_T_485)
node _T_487 = and(_T_486, asSInt(UInt<27>(0h4000000)))
node _T_488 = asSInt(_T_487)
node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0)))
node _T_490 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_491 = cvt(_T_490)
node _T_492 = and(_T_491, asSInt(UInt<13>(0h1000)))
node _T_493 = asSInt(_T_492)
node _T_494 = eq(_T_493, asSInt(UInt<1>(0h0)))
node _T_495 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_496 = cvt(_T_495)
node _T_497 = and(_T_496, asSInt(UInt<15>(0h4000)))
node _T_498 = asSInt(_T_497)
node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0)))
node _T_500 = or(_T_469, _T_474)
node _T_501 = or(_T_500, _T_479)
node _T_502 = or(_T_501, _T_484)
node _T_503 = or(_T_502, _T_489)
node _T_504 = or(_T_503, _T_494)
node _T_505 = or(_T_504, _T_499)
node _T_506 = and(_T_464, _T_505)
node _T_507 = or(UInt<1>(0h0), _T_460)
node _T_508 = or(_T_507, _T_506)
node _T_509 = asUInt(reset)
node _T_510 = eq(_T_509, UInt<1>(0h0))
when _T_510 :
node _T_511 = eq(_T_508, UInt<1>(0h0))
when _T_511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_508, UInt<1>(0h1), "") : assert_20
node _T_512 = asUInt(reset)
node _T_513 = eq(_T_512, UInt<1>(0h0))
when _T_513 :
node _T_514 = eq(source_ok, UInt<1>(0h0))
when _T_514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_515 = asUInt(reset)
node _T_516 = eq(_T_515, UInt<1>(0h0))
when _T_516 :
node _T_517 = eq(is_aligned, UInt<1>(0h0))
when _T_517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_518 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(_T_518, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_518, UInt<1>(0h1), "") : assert_23
node _T_522 = eq(io.in.a.bits.mask, mask)
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_522, UInt<1>(0h1), "") : assert_24
node _T_526 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_526, UInt<1>(0h1), "") : assert_25
node _T_530 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_530 :
node _T_531 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_532 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_535 = shr(io.in.a.bits.source, 2)
node _T_536 = eq(_T_535, UInt<1>(0h0))
node _T_537 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_538 = and(_T_536, _T_537)
node _T_539 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_540 = and(_T_538, _T_539)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_541 = shr(io.in.a.bits.source, 2)
node _T_542 = eq(_T_541, UInt<1>(0h1))
node _T_543 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_544 = and(_T_542, _T_543)
node _T_545 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_546 = and(_T_544, _T_545)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_547 = shr(io.in.a.bits.source, 2)
node _T_548 = eq(_T_547, UInt<2>(0h2))
node _T_549 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_550 = and(_T_548, _T_549)
node _T_551 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_552 = and(_T_550, _T_551)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_553 = shr(io.in.a.bits.source, 2)
node _T_554 = eq(_T_553, UInt<2>(0h3))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(_T_534, _T_540)
node _T_560 = or(_T_559, _T_546)
node _T_561 = or(_T_560, _T_552)
node _T_562 = or(_T_561, _T_558)
node _T_563 = and(_T_533, _T_562)
node _T_564 = or(UInt<1>(0h0), _T_563)
node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_567 = and(_T_565, _T_566)
node _T_568 = or(UInt<1>(0h0), _T_567)
node _T_569 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<13>(0h1000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = and(_T_568, _T_573)
node _T_575 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_576 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_577 = and(_T_575, _T_576)
node _T_578 = or(UInt<1>(0h0), _T_577)
node _T_579 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<14>(0h2000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<18>(0h2f000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<17>(0h10000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<27>(0h4000000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<13>(0h1000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<15>(0h4000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = or(_T_583, _T_588)
node _T_610 = or(_T_609, _T_593)
node _T_611 = or(_T_610, _T_598)
node _T_612 = or(_T_611, _T_603)
node _T_613 = or(_T_612, _T_608)
node _T_614 = and(_T_578, _T_613)
node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_617 = cvt(_T_616)
node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000)))
node _T_619 = asSInt(_T_618)
node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0)))
node _T_621 = and(_T_615, _T_620)
node _T_622 = or(UInt<1>(0h0), _T_574)
node _T_623 = or(_T_622, _T_614)
node _T_624 = or(_T_623, _T_621)
node _T_625 = and(_T_564, _T_624)
node _T_626 = asUInt(reset)
node _T_627 = eq(_T_626, UInt<1>(0h0))
when _T_627 :
node _T_628 = eq(_T_625, UInt<1>(0h0))
when _T_628 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_625, UInt<1>(0h1), "") : assert_26
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(source_ok, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(is_aligned, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_635 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_T_635, UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_635, UInt<1>(0h1), "") : assert_29
node _T_639 = eq(io.in.a.bits.mask, mask)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_639, UInt<1>(0h1), "") : assert_30
node _T_643 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_643 :
node _T_644 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_645 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_646 = and(_T_644, _T_645)
node _T_647 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_648 = shr(io.in.a.bits.source, 2)
node _T_649 = eq(_T_648, UInt<1>(0h0))
node _T_650 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_651 = and(_T_649, _T_650)
node _T_652 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_653 = and(_T_651, _T_652)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_654 = shr(io.in.a.bits.source, 2)
node _T_655 = eq(_T_654, UInt<1>(0h1))
node _T_656 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_657 = and(_T_655, _T_656)
node _T_658 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_659 = and(_T_657, _T_658)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<2>(0h2))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<2>(0h3))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _T_672 = or(_T_647, _T_653)
node _T_673 = or(_T_672, _T_659)
node _T_674 = or(_T_673, _T_665)
node _T_675 = or(_T_674, _T_671)
node _T_676 = and(_T_646, _T_675)
node _T_677 = or(UInt<1>(0h0), _T_676)
node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_680 = and(_T_678, _T_679)
node _T_681 = or(UInt<1>(0h0), _T_680)
node _T_682 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_683 = cvt(_T_682)
node _T_684 = and(_T_683, asSInt(UInt<13>(0h1000)))
node _T_685 = asSInt(_T_684)
node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0)))
node _T_687 = and(_T_681, _T_686)
node _T_688 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_689 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_690 = and(_T_688, _T_689)
node _T_691 = or(UInt<1>(0h0), _T_690)
node _T_692 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_693 = cvt(_T_692)
node _T_694 = and(_T_693, asSInt(UInt<14>(0h2000)))
node _T_695 = asSInt(_T_694)
node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0)))
node _T_697 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_698 = cvt(_T_697)
node _T_699 = and(_T_698, asSInt(UInt<18>(0h2f000)))
node _T_700 = asSInt(_T_699)
node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0)))
node _T_702 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_703 = cvt(_T_702)
node _T_704 = and(_T_703, asSInt(UInt<17>(0h10000)))
node _T_705 = asSInt(_T_704)
node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0)))
node _T_707 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_708 = cvt(_T_707)
node _T_709 = and(_T_708, asSInt(UInt<27>(0h4000000)))
node _T_710 = asSInt(_T_709)
node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0)))
node _T_712 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_713 = cvt(_T_712)
node _T_714 = and(_T_713, asSInt(UInt<13>(0h1000)))
node _T_715 = asSInt(_T_714)
node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0)))
node _T_717 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_718 = cvt(_T_717)
node _T_719 = and(_T_718, asSInt(UInt<15>(0h4000)))
node _T_720 = asSInt(_T_719)
node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0)))
node _T_722 = or(_T_696, _T_701)
node _T_723 = or(_T_722, _T_706)
node _T_724 = or(_T_723, _T_711)
node _T_725 = or(_T_724, _T_716)
node _T_726 = or(_T_725, _T_721)
node _T_727 = and(_T_691, _T_726)
node _T_728 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_729 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_730 = cvt(_T_729)
node _T_731 = and(_T_730, asSInt(UInt<17>(0h10000)))
node _T_732 = asSInt(_T_731)
node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0)))
node _T_734 = and(_T_728, _T_733)
node _T_735 = or(UInt<1>(0h0), _T_687)
node _T_736 = or(_T_735, _T_727)
node _T_737 = or(_T_736, _T_734)
node _T_738 = and(_T_677, _T_737)
node _T_739 = asUInt(reset)
node _T_740 = eq(_T_739, UInt<1>(0h0))
when _T_740 :
node _T_741 = eq(_T_738, UInt<1>(0h0))
when _T_741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_738, UInt<1>(0h1), "") : assert_31
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(source_ok, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_745 = asUInt(reset)
node _T_746 = eq(_T_745, UInt<1>(0h0))
when _T_746 :
node _T_747 = eq(is_aligned, UInt<1>(0h0))
when _T_747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_748 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_748, UInt<1>(0h1), "") : assert_34
node _T_752 = not(mask)
node _T_753 = and(io.in.a.bits.mask, _T_752)
node _T_754 = eq(_T_753, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_754, UInt<1>(0h1), "") : assert_35
node _T_758 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_758 :
node _T_759 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_760 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_761 = and(_T_759, _T_760)
node _T_762 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_763 = shr(io.in.a.bits.source, 2)
node _T_764 = eq(_T_763, UInt<1>(0h0))
node _T_765 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_766 = and(_T_764, _T_765)
node _T_767 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_768 = and(_T_766, _T_767)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_769 = shr(io.in.a.bits.source, 2)
node _T_770 = eq(_T_769, UInt<1>(0h1))
node _T_771 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_772 = and(_T_770, _T_771)
node _T_773 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_774 = and(_T_772, _T_773)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_775 = shr(io.in.a.bits.source, 2)
node _T_776 = eq(_T_775, UInt<2>(0h2))
node _T_777 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_778 = and(_T_776, _T_777)
node _T_779 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_780 = and(_T_778, _T_779)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_781 = shr(io.in.a.bits.source, 2)
node _T_782 = eq(_T_781, UInt<2>(0h3))
node _T_783 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_784 = and(_T_782, _T_783)
node _T_785 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_786 = and(_T_784, _T_785)
node _T_787 = or(_T_762, _T_768)
node _T_788 = or(_T_787, _T_774)
node _T_789 = or(_T_788, _T_780)
node _T_790 = or(_T_789, _T_786)
node _T_791 = and(_T_761, _T_790)
node _T_792 = or(UInt<1>(0h0), _T_791)
node _T_793 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_794 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_795 = and(_T_793, _T_794)
node _T_796 = or(UInt<1>(0h0), _T_795)
node _T_797 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_798 = cvt(_T_797)
node _T_799 = and(_T_798, asSInt(UInt<14>(0h2000)))
node _T_800 = asSInt(_T_799)
node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0)))
node _T_802 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_803 = cvt(_T_802)
node _T_804 = and(_T_803, asSInt(UInt<13>(0h1000)))
node _T_805 = asSInt(_T_804)
node _T_806 = eq(_T_805, asSInt(UInt<1>(0h0)))
node _T_807 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_808 = cvt(_T_807)
node _T_809 = and(_T_808, asSInt(UInt<18>(0h2f000)))
node _T_810 = asSInt(_T_809)
node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0)))
node _T_812 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_813 = cvt(_T_812)
node _T_814 = and(_T_813, asSInt(UInt<17>(0h10000)))
node _T_815 = asSInt(_T_814)
node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0)))
node _T_817 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_818 = cvt(_T_817)
node _T_819 = and(_T_818, asSInt(UInt<27>(0h4000000)))
node _T_820 = asSInt(_T_819)
node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0)))
node _T_822 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_823 = cvt(_T_822)
node _T_824 = and(_T_823, asSInt(UInt<13>(0h1000)))
node _T_825 = asSInt(_T_824)
node _T_826 = eq(_T_825, asSInt(UInt<1>(0h0)))
node _T_827 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_828 = cvt(_T_827)
node _T_829 = and(_T_828, asSInt(UInt<15>(0h4000)))
node _T_830 = asSInt(_T_829)
node _T_831 = eq(_T_830, asSInt(UInt<1>(0h0)))
node _T_832 = or(_T_801, _T_806)
node _T_833 = or(_T_832, _T_811)
node _T_834 = or(_T_833, _T_816)
node _T_835 = or(_T_834, _T_821)
node _T_836 = or(_T_835, _T_826)
node _T_837 = or(_T_836, _T_831)
node _T_838 = and(_T_796, _T_837)
node _T_839 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_840 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_841 = cvt(_T_840)
node _T_842 = and(_T_841, asSInt(UInt<17>(0h10000)))
node _T_843 = asSInt(_T_842)
node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0)))
node _T_845 = and(_T_839, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_838)
node _T_847 = or(_T_846, _T_845)
node _T_848 = and(_T_792, _T_847)
node _T_849 = asUInt(reset)
node _T_850 = eq(_T_849, UInt<1>(0h0))
when _T_850 :
node _T_851 = eq(_T_848, UInt<1>(0h0))
when _T_851 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_848, UInt<1>(0h1), "") : assert_36
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(source_ok, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_855 = asUInt(reset)
node _T_856 = eq(_T_855, UInt<1>(0h0))
when _T_856 :
node _T_857 = eq(is_aligned, UInt<1>(0h0))
when _T_857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_858 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_T_858, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_858, UInt<1>(0h1), "") : assert_39
node _T_862 = eq(io.in.a.bits.mask, mask)
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(_T_862, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_862, UInt<1>(0h1), "") : assert_40
node _T_866 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_866 :
node _T_867 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_868 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_869 = and(_T_867, _T_868)
node _T_870 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_871 = shr(io.in.a.bits.source, 2)
node _T_872 = eq(_T_871, UInt<1>(0h0))
node _T_873 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_874 = and(_T_872, _T_873)
node _T_875 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_876 = and(_T_874, _T_875)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_877 = shr(io.in.a.bits.source, 2)
node _T_878 = eq(_T_877, UInt<1>(0h1))
node _T_879 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_880 = and(_T_878, _T_879)
node _T_881 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_882 = and(_T_880, _T_881)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_883 = shr(io.in.a.bits.source, 2)
node _T_884 = eq(_T_883, UInt<2>(0h2))
node _T_885 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_886 = and(_T_884, _T_885)
node _T_887 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_888 = and(_T_886, _T_887)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_889 = shr(io.in.a.bits.source, 2)
node _T_890 = eq(_T_889, UInt<2>(0h3))
node _T_891 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_892 = and(_T_890, _T_891)
node _T_893 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_894 = and(_T_892, _T_893)
node _T_895 = or(_T_870, _T_876)
node _T_896 = or(_T_895, _T_882)
node _T_897 = or(_T_896, _T_888)
node _T_898 = or(_T_897, _T_894)
node _T_899 = and(_T_869, _T_898)
node _T_900 = or(UInt<1>(0h0), _T_899)
node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_902 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_903 = and(_T_901, _T_902)
node _T_904 = or(UInt<1>(0h0), _T_903)
node _T_905 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_906 = cvt(_T_905)
node _T_907 = and(_T_906, asSInt(UInt<14>(0h2000)))
node _T_908 = asSInt(_T_907)
node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0)))
node _T_910 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_911 = cvt(_T_910)
node _T_912 = and(_T_911, asSInt(UInt<13>(0h1000)))
node _T_913 = asSInt(_T_912)
node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0)))
node _T_915 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<18>(0h2f000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_921 = cvt(_T_920)
node _T_922 = and(_T_921, asSInt(UInt<17>(0h10000)))
node _T_923 = asSInt(_T_922)
node _T_924 = eq(_T_923, asSInt(UInt<1>(0h0)))
node _T_925 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_926 = cvt(_T_925)
node _T_927 = and(_T_926, asSInt(UInt<27>(0h4000000)))
node _T_928 = asSInt(_T_927)
node _T_929 = eq(_T_928, asSInt(UInt<1>(0h0)))
node _T_930 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_931 = cvt(_T_930)
node _T_932 = and(_T_931, asSInt(UInt<13>(0h1000)))
node _T_933 = asSInt(_T_932)
node _T_934 = eq(_T_933, asSInt(UInt<1>(0h0)))
node _T_935 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_936 = cvt(_T_935)
node _T_937 = and(_T_936, asSInt(UInt<15>(0h4000)))
node _T_938 = asSInt(_T_937)
node _T_939 = eq(_T_938, asSInt(UInt<1>(0h0)))
node _T_940 = or(_T_909, _T_914)
node _T_941 = or(_T_940, _T_919)
node _T_942 = or(_T_941, _T_924)
node _T_943 = or(_T_942, _T_929)
node _T_944 = or(_T_943, _T_934)
node _T_945 = or(_T_944, _T_939)
node _T_946 = and(_T_904, _T_945)
node _T_947 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_948 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_949 = cvt(_T_948)
node _T_950 = and(_T_949, asSInt(UInt<17>(0h10000)))
node _T_951 = asSInt(_T_950)
node _T_952 = eq(_T_951, asSInt(UInt<1>(0h0)))
node _T_953 = and(_T_947, _T_952)
node _T_954 = or(UInt<1>(0h0), _T_946)
node _T_955 = or(_T_954, _T_953)
node _T_956 = and(_T_900, _T_955)
node _T_957 = asUInt(reset)
node _T_958 = eq(_T_957, UInt<1>(0h0))
when _T_958 :
node _T_959 = eq(_T_956, UInt<1>(0h0))
when _T_959 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_956, UInt<1>(0h1), "") : assert_41
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(source_ok, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(is_aligned, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_966 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_966, UInt<1>(0h1), "") : assert_44
node _T_970 = eq(io.in.a.bits.mask, mask)
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_970, UInt<1>(0h1), "") : assert_45
node _T_974 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_974 :
node _T_975 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_976 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_977 = and(_T_975, _T_976)
node _T_978 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_979 = shr(io.in.a.bits.source, 2)
node _T_980 = eq(_T_979, UInt<1>(0h0))
node _T_981 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_982 = and(_T_980, _T_981)
node _T_983 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_984 = and(_T_982, _T_983)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_985 = shr(io.in.a.bits.source, 2)
node _T_986 = eq(_T_985, UInt<1>(0h1))
node _T_987 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_988 = and(_T_986, _T_987)
node _T_989 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_990 = and(_T_988, _T_989)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_991 = shr(io.in.a.bits.source, 2)
node _T_992 = eq(_T_991, UInt<2>(0h2))
node _T_993 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_994 = and(_T_992, _T_993)
node _T_995 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_996 = and(_T_994, _T_995)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_997 = shr(io.in.a.bits.source, 2)
node _T_998 = eq(_T_997, UInt<2>(0h3))
node _T_999 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1000 = and(_T_998, _T_999)
node _T_1001 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1002 = and(_T_1000, _T_1001)
node _T_1003 = or(_T_978, _T_984)
node _T_1004 = or(_T_1003, _T_990)
node _T_1005 = or(_T_1004, _T_996)
node _T_1006 = or(_T_1005, _T_1002)
node _T_1007 = and(_T_977, _T_1006)
node _T_1008 = or(UInt<1>(0h0), _T_1007)
node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1010 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = or(UInt<1>(0h0), _T_1011)
node _T_1013 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1014 = cvt(_T_1013)
node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000)))
node _T_1016 = asSInt(_T_1015)
node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0)))
node _T_1018 = and(_T_1012, _T_1017)
node _T_1019 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1020 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1021 = cvt(_T_1020)
node _T_1022 = and(_T_1021, asSInt(UInt<14>(0h2000)))
node _T_1023 = asSInt(_T_1022)
node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0)))
node _T_1025 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1026 = cvt(_T_1025)
node _T_1027 = and(_T_1026, asSInt(UInt<17>(0h10000)))
node _T_1028 = asSInt(_T_1027)
node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0)))
node _T_1030 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1031 = cvt(_T_1030)
node _T_1032 = and(_T_1031, asSInt(UInt<18>(0h2f000)))
node _T_1033 = asSInt(_T_1032)
node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0)))
node _T_1035 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1036 = cvt(_T_1035)
node _T_1037 = and(_T_1036, asSInt(UInt<17>(0h10000)))
node _T_1038 = asSInt(_T_1037)
node _T_1039 = eq(_T_1038, asSInt(UInt<1>(0h0)))
node _T_1040 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1041 = cvt(_T_1040)
node _T_1042 = and(_T_1041, asSInt(UInt<27>(0h4000000)))
node _T_1043 = asSInt(_T_1042)
node _T_1044 = eq(_T_1043, asSInt(UInt<1>(0h0)))
node _T_1045 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1046 = cvt(_T_1045)
node _T_1047 = and(_T_1046, asSInt(UInt<13>(0h1000)))
node _T_1048 = asSInt(_T_1047)
node _T_1049 = eq(_T_1048, asSInt(UInt<1>(0h0)))
node _T_1050 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1051 = cvt(_T_1050)
node _T_1052 = and(_T_1051, asSInt(UInt<15>(0h4000)))
node _T_1053 = asSInt(_T_1052)
node _T_1054 = eq(_T_1053, asSInt(UInt<1>(0h0)))
node _T_1055 = or(_T_1024, _T_1029)
node _T_1056 = or(_T_1055, _T_1034)
node _T_1057 = or(_T_1056, _T_1039)
node _T_1058 = or(_T_1057, _T_1044)
node _T_1059 = or(_T_1058, _T_1049)
node _T_1060 = or(_T_1059, _T_1054)
node _T_1061 = and(_T_1019, _T_1060)
node _T_1062 = or(UInt<1>(0h0), _T_1018)
node _T_1063 = or(_T_1062, _T_1061)
node _T_1064 = and(_T_1008, _T_1063)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_46
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(source_ok, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(is_aligned, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1074 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_49
node _T_1078 = eq(io.in.a.bits.mask, mask)
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_50
node _T_1082 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1086 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_52
node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_29 = shr(io.in.d.bits.source, 2)
node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0))
node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31)
node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_35 = shr(io.in.d.bits.source, 2)
node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1))
node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_41 = shr(io.in.d.bits.source, 2)
node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2))
node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_47 = shr(io.in.d.bits.source, 2)
node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3))
node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
wire _source_ok_WIRE_1 : UInt<1>[5]
connect _source_ok_WIRE_1[0], _source_ok_T_28
connect _source_ok_WIRE_1[1], _source_ok_T_34
connect _source_ok_WIRE_1[2], _source_ok_T_40
connect _source_ok_WIRE_1[3], _source_ok_T_46
connect _source_ok_WIRE_1[4], _source_ok_T_52
node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3])
node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1090 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1090 :
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(source_ok_1, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1094 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_54
node _T_1098 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_55
node _T_1102 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_56
node _T_1106 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_57
node _T_1110 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1110 :
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(source_ok_1, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1114 = asUInt(reset)
node _T_1115 = eq(_T_1114, UInt<1>(0h0))
when _T_1115 :
node _T_1116 = eq(sink_ok, UInt<1>(0h0))
when _T_1116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_60
node _T_1121 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_61
node _T_1125 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_62
node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_63
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(UInt<1>(0h1), _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_64
node _T_1138 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1138 :
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(source_ok_1, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(sink_ok, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1145 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_67
node _T_1149 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_68
node _T_1153 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_69
node _T_1157 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1158 = or(_T_1157, io.in.d.bits.corrupt)
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(_T_1158, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1158, UInt<1>(0h1), "") : assert_70
node _T_1162 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1163 = or(UInt<1>(0h1), _T_1162)
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(_T_1163, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1163, UInt<1>(0h1), "") : assert_71
node _T_1167 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(source_ok_1, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1171 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_73
node _T_1175 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_74
node _T_1179 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1180 = or(UInt<1>(0h1), _T_1179)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_75
node _T_1184 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1184 :
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(source_ok_1, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1188 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_77
node _T_1192 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1193 = or(_T_1192, io.in.d.bits.corrupt)
node _T_1194 = asUInt(reset)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
when _T_1195 :
node _T_1196 = eq(_T_1193, UInt<1>(0h0))
when _T_1196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1193, UInt<1>(0h1), "") : assert_78
node _T_1197 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1198 = or(UInt<1>(0h1), _T_1197)
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_79
node _T_1202 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1202 :
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(source_ok_1, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1206 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(_T_1206, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1206, UInt<1>(0h1), "") : assert_81
node _T_1210 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1211 = asUInt(reset)
node _T_1212 = eq(_T_1211, UInt<1>(0h0))
when _T_1212 :
node _T_1213 = eq(_T_1210, UInt<1>(0h0))
when _T_1213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1210, UInt<1>(0h1), "") : assert_82
node _T_1214 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1215 = or(UInt<1>(0h1), _T_1214)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1219 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(_T_1219, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1219, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1223 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1227 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1231 = eq(a_first, UInt<1>(0h0))
node _T_1232 = and(io.in.a.valid, _T_1231)
when _T_1232 :
node _T_1233 = eq(io.in.a.bits.opcode, opcode)
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_87
node _T_1237 = eq(io.in.a.bits.param, param)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_88
node _T_1241 = eq(io.in.a.bits.size, size)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_89
node _T_1245 = eq(io.in.a.bits.source, source)
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_90
node _T_1249 = eq(io.in.a.bits.address, address)
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(_T_1249, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1249, UInt<1>(0h1), "") : assert_91
node _T_1253 = and(io.in.a.ready, io.in.a.valid)
node _T_1254 = and(_T_1253, a_first)
when _T_1254 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1255 = eq(d_first, UInt<1>(0h0))
node _T_1256 = and(io.in.d.valid, _T_1255)
when _T_1256 :
node _T_1257 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1258 = asUInt(reset)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
when _T_1259 :
node _T_1260 = eq(_T_1257, UInt<1>(0h0))
when _T_1260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1257, UInt<1>(0h1), "") : assert_92
node _T_1261 = eq(io.in.d.bits.param, param_1)
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_93
node _T_1265 = eq(io.in.d.bits.size, size_1)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_94
node _T_1269 = eq(io.in.d.bits.source, source_1)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_95
node _T_1273 = eq(io.in.d.bits.sink, sink)
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_96
node _T_1277 = eq(io.in.d.bits.denied, denied)
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(_T_1277, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1277, UInt<1>(0h1), "") : assert_97
node _T_1281 = and(io.in.d.ready, io.in.d.valid)
node _T_1282 = and(_T_1281, d_first)
when _T_1282 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0)
regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0)
regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<17>
connect a_set, UInt<17>(0h0)
wire a_set_wo_ready : UInt<17>
connect a_set_wo_ready, UInt<17>(0h0)
wire a_opcodes_set : UInt<68>
connect a_opcodes_set, UInt<68>(0h0)
wire a_sizes_set : UInt<136>
connect a_sizes_set, UInt<136>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1283 = and(io.in.a.valid, a_first_1)
node _T_1284 = and(_T_1283, UInt<1>(0h1))
when _T_1284 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1285 = and(io.in.a.ready, io.in.a.valid)
node _T_1286 = and(_T_1285, a_first_1)
node _T_1287 = and(_T_1286, UInt<1>(0h1))
when _T_1287 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1288 = dshr(inflight, io.in.a.bits.source)
node _T_1289 = bits(_T_1288, 0, 0)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(_T_1290, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1290, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<17>
connect d_clr, UInt<17>(0h0)
wire d_clr_wo_ready : UInt<17>
connect d_clr_wo_ready, UInt<17>(0h0)
wire d_opcodes_clr : UInt<68>
connect d_opcodes_clr, UInt<68>(0h0)
wire d_sizes_clr : UInt<136>
connect d_sizes_clr, UInt<136>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1294 = and(io.in.d.valid, d_first_1)
node _T_1295 = and(_T_1294, UInt<1>(0h1))
node _T_1296 = eq(d_release_ack, UInt<1>(0h0))
node _T_1297 = and(_T_1295, _T_1296)
when _T_1297 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1298 = and(io.in.d.ready, io.in.d.valid)
node _T_1299 = and(_T_1298, d_first_1)
node _T_1300 = and(_T_1299, UInt<1>(0h1))
node _T_1301 = eq(d_release_ack, UInt<1>(0h0))
node _T_1302 = and(_T_1300, _T_1301)
when _T_1302 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1303 = and(io.in.d.valid, d_first_1)
node _T_1304 = and(_T_1303, UInt<1>(0h1))
node _T_1305 = eq(d_release_ack, UInt<1>(0h0))
node _T_1306 = and(_T_1304, _T_1305)
when _T_1306 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1307 = dshr(inflight, io.in.d.bits.source)
node _T_1308 = bits(_T_1307, 0, 0)
node _T_1309 = or(_T_1308, same_cycle_resp)
node _T_1310 = asUInt(reset)
node _T_1311 = eq(_T_1310, UInt<1>(0h0))
when _T_1311 :
node _T_1312 = eq(_T_1309, UInt<1>(0h0))
when _T_1312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1309, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1313 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1314 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1315 = or(_T_1313, _T_1314)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_100
node _T_1319 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_101
else :
node _T_1323 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1324 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1325 = or(_T_1323, _T_1324)
node _T_1326 = asUInt(reset)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
when _T_1327 :
node _T_1328 = eq(_T_1325, UInt<1>(0h0))
when _T_1328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1325, UInt<1>(0h1), "") : assert_102
node _T_1329 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1330 = asUInt(reset)
node _T_1331 = eq(_T_1330, UInt<1>(0h0))
when _T_1331 :
node _T_1332 = eq(_T_1329, UInt<1>(0h0))
when _T_1332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1329, UInt<1>(0h1), "") : assert_103
node _T_1333 = and(io.in.d.valid, d_first_1)
node _T_1334 = and(_T_1333, a_first_1)
node _T_1335 = and(_T_1334, io.in.a.valid)
node _T_1336 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1337 = and(_T_1335, _T_1336)
node _T_1338 = eq(d_release_ack, UInt<1>(0h0))
node _T_1339 = and(_T_1337, _T_1338)
when _T_1339 :
node _T_1340 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1341 = or(_T_1340, io.in.a.ready)
node _T_1342 = asUInt(reset)
node _T_1343 = eq(_T_1342, UInt<1>(0h0))
when _T_1343 :
node _T_1344 = eq(_T_1341, UInt<1>(0h0))
when _T_1344 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1341, UInt<1>(0h1), "") : assert_104
node _T_1345 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1346 = orr(a_set_wo_ready)
node _T_1347 = eq(_T_1346, UInt<1>(0h0))
node _T_1348 = or(_T_1345, _T_1347)
node _T_1349 = asUInt(reset)
node _T_1350 = eq(_T_1349, UInt<1>(0h0))
when _T_1350 :
node _T_1351 = eq(_T_1348, UInt<1>(0h0))
when _T_1351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1348, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader
node _T_1352 = orr(inflight)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
node _T_1354 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1355 = or(_T_1353, _T_1354)
node _T_1356 = lt(watchdog, plusarg_reader.out)
node _T_1357 = or(_T_1355, _T_1356)
node _T_1358 = asUInt(reset)
node _T_1359 = eq(_T_1358, UInt<1>(0h0))
when _T_1359 :
node _T_1360 = eq(_T_1357, UInt<1>(0h0))
when _T_1360 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1357, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1361 = and(io.in.a.ready, io.in.a.valid)
node _T_1362 = and(io.in.d.ready, io.in.d.valid)
node _T_1363 = or(_T_1361, _T_1362)
when _T_1363 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0)
regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0)
regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<17>
connect c_set, UInt<17>(0h0)
wire c_set_wo_ready : UInt<17>
connect c_set_wo_ready, UInt<17>(0h0)
wire c_opcodes_set : UInt<68>
connect c_opcodes_set, UInt<68>(0h0)
wire c_sizes_set : UInt<136>
connect c_sizes_set, UInt<136>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1364 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1365 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1366 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1367 = and(_T_1365, _T_1366)
node _T_1368 = and(_T_1364, _T_1367)
when _T_1368 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1369 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1370 = and(_T_1369, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1371 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1372 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1373 = and(_T_1371, _T_1372)
node _T_1374 = and(_T_1370, _T_1373)
when _T_1374 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1375 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1376 = bits(_T_1375, 0, 0)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<17>
connect d_clr_1, UInt<17>(0h0)
wire d_clr_wo_ready_1 : UInt<17>
connect d_clr_wo_ready_1, UInt<17>(0h0)
wire d_opcodes_clr_1 : UInt<68>
connect d_opcodes_clr_1, UInt<68>(0h0)
wire d_sizes_clr_1 : UInt<136>
connect d_sizes_clr_1, UInt<136>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1381 = and(io.in.d.valid, d_first_2)
node _T_1382 = and(_T_1381, UInt<1>(0h1))
node _T_1383 = and(_T_1382, d_release_ack_1)
when _T_1383 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1384 = and(io.in.d.ready, io.in.d.valid)
node _T_1385 = and(_T_1384, d_first_2)
node _T_1386 = and(_T_1385, UInt<1>(0h1))
node _T_1387 = and(_T_1386, d_release_ack_1)
when _T_1387 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1388 = and(io.in.d.valid, d_first_2)
node _T_1389 = and(_T_1388, UInt<1>(0h1))
node _T_1390 = and(_T_1389, d_release_ack_1)
when _T_1390 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1391 = dshr(inflight_1, io.in.d.bits.source)
node _T_1392 = bits(_T_1391, 0, 0)
node _T_1393 = or(_T_1392, same_cycle_resp_1)
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(_T_1393, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1393, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1397 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1398 = asUInt(reset)
node _T_1399 = eq(_T_1398, UInt<1>(0h0))
when _T_1399 :
node _T_1400 = eq(_T_1397, UInt<1>(0h0))
when _T_1400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1397, UInt<1>(0h1), "") : assert_109
else :
node _T_1401 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1402 = asUInt(reset)
node _T_1403 = eq(_T_1402, UInt<1>(0h0))
when _T_1403 :
node _T_1404 = eq(_T_1401, UInt<1>(0h0))
when _T_1404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1401, UInt<1>(0h1), "") : assert_110
node _T_1405 = and(io.in.d.valid, d_first_2)
node _T_1406 = and(_T_1405, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1407 = and(_T_1406, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1408 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1409 = and(_T_1407, _T_1408)
node _T_1410 = and(_T_1409, d_release_ack_1)
node _T_1411 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1412 = and(_T_1410, _T_1411)
when _T_1412 :
node _T_1413 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1414 = or(_T_1413, _WIRE_23.ready)
node _T_1415 = asUInt(reset)
node _T_1416 = eq(_T_1415, UInt<1>(0h0))
when _T_1416 :
node _T_1417 = eq(_T_1414, UInt<1>(0h0))
when _T_1417 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1414, UInt<1>(0h1), "") : assert_111
node _T_1418 = orr(c_set_wo_ready)
when _T_1418 :
node _T_1419 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1420 = asUInt(reset)
node _T_1421 = eq(_T_1420, UInt<1>(0h0))
when _T_1421 :
node _T_1422 = eq(_T_1419, UInt<1>(0h0))
when _T_1422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1419, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_1
node _T_1423 = orr(inflight_1)
node _T_1424 = eq(_T_1423, UInt<1>(0h0))
node _T_1425 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1426 = or(_T_1424, _T_1425)
node _T_1427 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1428 = or(_T_1426, _T_1427)
node _T_1429 = asUInt(reset)
node _T_1430 = eq(_T_1429, UInt<1>(0h0))
when _T_1430 :
node _T_1431 = eq(_T_1428, UInt<1>(0h0))
when _T_1431 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1428, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1432 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1433 = and(io.in.d.ready, io.in.d.valid)
node _T_1434 = or(_T_1432, _T_1433)
when _T_1434 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_2 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_3 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34]
wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34]
wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34]
wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1361 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1361; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1361; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1434 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1434; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1434; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1434; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [16:0] a_set; // @[Monitor.scala:626:34]
wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [135:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1287 = _T_1361 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1287 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1287 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1287 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1287 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1287 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [16:0] d_clr; // @[Monitor.scala:664:34]
wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1333 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1333 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1302 = _T_1434 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1302 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1302 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1302 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16:0] d_clr_1; // @[Monitor.scala:774:34]
wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1405 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1405 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1387 = _T_1434 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1387 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1387 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1387 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_119 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}}
wire _in_flight_WIRE : UInt<1>[10]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
connect _in_flight_WIRE[8], UInt<1>(0h0)
connect _in_flight_WIRE[9], UInt<1>(0h0)
regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = or(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_16 = or(_T_15, UInt<1>(0h0))
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_21 = or(_T_20, UInt<1>(0h0))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_21, UInt<1>(0h1), "") : assert_4
node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_26 = or(_T_25, UInt<1>(0h0))
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_26, UInt<1>(0h1), "") : assert_5
node _T_30 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_31 = or(_T_30, UInt<1>(0h0))
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
node _T_34 = eq(_T_31, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_31, UInt<1>(0h1), "") : assert_6
node _T_35 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_36 = or(_T_35, UInt<1>(0h0))
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_36, UInt<1>(0h1), "") : assert_7
node _T_40 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_41 = or(_T_40, UInt<1>(0h0))
node _T_42 = asUInt(reset)
node _T_43 = eq(_T_42, UInt<1>(0h0))
when _T_43 :
node _T_44 = eq(_T_41, UInt<1>(0h0))
when _T_44 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_41, UInt<1>(0h1), "") : assert_8
node _T_45 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_46 = or(_T_45, UInt<1>(0h0))
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9
assert(clock, _T_46, UInt<1>(0h1), "") : assert_9
node _T_50 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9))
node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_52 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_53 = and(_T_51, _T_52)
node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_55 = and(_T_53, _T_54)
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_57 = and(_T_55, _T_56)
node _T_58 = or(_T_50, _T_57)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10
assert(clock, _T_58, UInt<1>(0h1), "") : assert_10 | module NoCMonitor_119( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 4'h3; // @[Monitor.scala:21:46]
wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 4'h4; // @[Monitor.scala:21:46]
wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 4'h5; // @[Monitor.scala:21:46]
wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46]
wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 4'h7; // @[Monitor.scala:21:46]
wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 4'h8; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x2_10 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[2], out : { sync : UInt<1>[2]}}
wire nodeIn : UInt<1>[2]
invalidate nodeIn[0]
invalidate nodeIn[1]
wire nodeOut : { sync : UInt<1>[2]}
invalidate nodeOut.sync[0]
invalidate nodeOut.sync[1]
connect auto.out, nodeOut
connect nodeIn, auto.in
node _T = cat(nodeIn[1], nodeIn[0])
inst reg of AsyncResetRegVec_w2_i0_10
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, _T
connect reg.io.en, UInt<1>(0h1)
node _T_1 = bits(reg.io.q, 0, 0)
node _T_2 = bits(reg.io.q, 1, 1)
connect nodeOut.sync[0], _T_1
connect nodeOut.sync[1], _T_2 | module IntSyncCrossingSource_n1x2_10( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
input auto_in_1, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_1 // @[LazyModuleImp.scala:107:25]
);
wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21]
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire nodeOut_sync_1; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
wire auto_out_sync_1_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9]
assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21]
AsyncResetRegVec_w2_i0_10 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d ({nodeIn_1, nodeIn_0}), // @[Crossing.scala:45:36]
.io_q (_reg_io_q)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_24 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_280
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_24( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_280 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_31 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_31(); // @[MulAddRecFN.scala:169:7]
wire [25:0] _sigSum_T_2 = 26'h0; // @[MulAddRecFN.scala:192:16, :193:47]
wire [25:0] _sigSum_T_3 = 26'h0; // @[MulAddRecFN.scala:192:16, :193:47]
wire [47:0] _sigSum_T_4 = 48'h3FFFFFFFFFFF; // @[MulAddRecFN.scala:196:28]
wire [73:0] sigSum_hi = 74'h3FFFFFFFFFFF; // @[MulAddRecFN.scala:192:12]
wire [74:0] sigSum = 75'h7FFFFFFFFFFF; // @[MulAddRecFN.scala:192:12]
wire [10:0] _CDom_sExp_T_1 = 11'h102; // @[MulAddRecFN.scala:203:43]
wire [9:0] _CDom_sExp_T_2 = 10'h102; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = 10'h102; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = 50'h3FFFFF; // @[MulAddRecFN.scala:206:20]
wire [2:0] _CDom_absSigSum_T_3 = 3'h3; // @[MulAddRecFN.scala:207:22]
wire [46:0] _CDom_absSigSum_T_4 = 47'h1FFFFF; // @[MulAddRecFN.scala:210:23]
wire [49:0] _CDom_absSigSum_T_5 = 50'h18000001FFFFF; // @[MulAddRecFN.scala:209:71]
wire [49:0] _CDom_absSigSum_T_1 = 50'h3FFFFFFC00000; // @[MulAddRecFN.scala:205:12, :206:13]
wire [49:0] CDom_absSigSum = 50'h3FFFFFFC00000; // @[MulAddRecFN.scala:205:12, :206:13]
wire [23:0] _CDom_absSigSumExtra_T = 24'hFFFFFF; // @[MulAddRecFN.scala:215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = 24'h0; // @[MulAddRecFN.scala:215:14]
wire [24:0] _CDom_absSigSumExtra_T_3 = 25'h1FFFFFF; // @[MulAddRecFN.scala:216:19]
wire [80:0] _CDom_mainSig_T = 81'hFFFFFFF00000000; // @[MulAddRecFN.scala:219:24]
wire [28:0] CDom_mainSig = 29'h1FFFF800; // @[MulAddRecFN.scala:219:56]
wire [23:0] _CDom_reduced4SigExtra_T = 24'hC00000; // @[MulAddRecFN.scala:222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = 27'h6000000; // @[MulAddRecFN.scala:222:53]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = 3'h6; // @[primitives.scala:123:15]
wire [3:0] CDom_reduced4SigExtra_hi = 4'h8; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = 7'h40; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = 3'h2; // @[MulAddRecFN.scala:223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = 3'h5; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = 9'h1F8; // @[primitives.scala:76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = 6'h3C; // @[primitives.scala:78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = 4'hC; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = 4'h3; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = 6'hF; // @[primitives.scala:77:20]
wire [25:0] _CDom_sig_T = 26'h3FFFF00; // @[MulAddRecFN.scala:225:25]
wire [26:0] CDom_sig = 27'h7FFFE00; // @[MulAddRecFN.scala:225:12]
wire [50:0] _notCDom_absSigSum_T_1 = 51'h7800000000000; // @[MulAddRecFN.scala:235:13]
wire [50:0] _notCDom_absSigSum_T = 51'h7FFFFFFFFFFF; // @[MulAddRecFN.scala:235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_2 = 51'h7FFFFFFFFFFF; // @[MulAddRecFN.scala:235:20, :236:19]
wire [51:0] _notCDom_absSigSum_T_3 = 52'h800000000000; // @[MulAddRecFN.scala:236:41]
wire [50:0] _notCDom_absSigSum_T_4 = 51'h800000000000; // @[MulAddRecFN.scala:234:12, :236:41]
wire [50:0] notCDom_absSigSum = 51'h800000000000; // @[MulAddRecFN.scala:234:12, :236:41]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = 6'h0; // @[primitives.scala:107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = 6'h0; // @[primitives.scala:107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = 4'h2; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = 7'h10; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = 13'h400; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = 26'h800000; // @[primitives.scala:107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = 5'h19; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = 5'h2; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = 5'h2; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = 5'h2; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = 6'h4; // @[MulAddRecFN.scala:240:56]
wire [6:0] _notCDom_sExp_T = 7'h4; // @[MulAddRecFN.scala:241:76]
wire [10:0] _notCDom_sExp_T_1 = 11'hFF; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = 114'h8000000000000; // @[MulAddRecFN.scala:243:27]
wire [28:0] notCDom_mainSig = 29'h10000000; // @[MulAddRecFN.scala:243:50]
wire [12:0] notCDom_reduced2AbsSigSum_lo = 13'h0; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T = 13'h0; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = 13'h0; // @[primitives.scala:107:20]
wire [1:0] CDom_reduced4SigExtra_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _CDom_reduced4SigExtra_T_7 = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = 2'h0; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:107:20, :120:33]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:107:20, :120:33]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:107:20, :120:33]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:107:20, :120:33]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:107:20, :120:33]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:107:20, :120:33]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = 4'h0; // @[primitives.scala:107:20, :120:33]
wire [3:0] notCDom_reduced4SigExtra_hi = 4'h0; // @[primitives.scala:107:20, :120:33]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = 4'h1; // @[MulAddRecFN.scala:248:46]
wire [16:0] notCDom_reduced4SigExtra_shift = 17'h1FFFC; // @[primitives.scala:76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = 6'h3E; // @[primitives.scala:78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = 4'hE; // @[primitives.scala:52:21, :77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = 4'hE; // @[primitives.scala:52:21, :77:20]
wire [1:0] _CDom_sExp_T = 2'h1; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = 2'h1; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = 4'h7; // @[primitives.scala:77:20]
wire [1:0] _CDom_absSigSum_T_2 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = 2'h3; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = 6'h1F; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = 7'h0; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = 7'h0; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = 7'h0; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = 7'h0; // @[primitives.scala:107:20]
wire [25:0] _notCDom_sig_T = 26'h2000000; // @[MulAddRecFN.scala:251:28]
wire [1:0] CDom_reduced4SigExtra_hi_hi = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [1:0] _notCDom_completeCancellation_T = 2'h2; // @[primitives.scala:77:20, :103:33, :107:20, :124:20]
wire [26:0] io_rawOut_sig = 27'h4000000; // @[MulAddRecFN.scala:169:7, :172:16, :193:47, :251:12, :294:25]
wire [26:0] _sigSum_T_1 = 27'h4000000; // @[MulAddRecFN.scala:169:7, :172:16, :193:47, :251:12, :294:25]
wire [26:0] notCDom_sig = 27'h4000000; // @[MulAddRecFN.scala:169:7, :172:16, :193:47, :251:12, :294:25]
wire [26:0] _io_rawOut_sig_T = 27'h4000000; // @[MulAddRecFN.scala:169:7, :172:16, :193:47, :251:12, :294:25]
wire [9:0] io_rawOut_sExp = 10'hFF; // @[MulAddRecFN.scala:169:7, :172:16, :241:46, :293:26]
wire [9:0] _notCDom_sExp_T_2 = 10'hFF; // @[MulAddRecFN.scala:169:7, :172:16, :241:46, :293:26]
wire [9:0] notCDom_sExp = 10'hFF; // @[MulAddRecFN.scala:169:7, :172:16, :241:46, :293:26]
wire [9:0] _io_rawOut_sExp_T = 10'hFF; // @[MulAddRecFN.scala:169:7, :172:16, :241:46, :293:26]
wire [2:0] io_roundingMode = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] _CDom_sig_T_1 = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] notCDom_reduced4SigExtra_lo = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [2:0] _notCDom_sig_T_1 = 3'h0; // @[primitives.scala:107:20, :124:20]
wire [48:0] io_mulAddResult = 49'h13FFFFFFFFFFF; // @[MulAddRecFN.scala:169:7, :172:16]
wire [25:0] io_fromPreMul_highAlignedSigC = 26'h3FFFFFF; // @[MulAddRecFN.scala:169:7, :172:16]
wire [4:0] io_fromPreMul_CDom_CAlignDist = 5'hA; // @[MulAddRecFN.scala:169:7, :172:16]
wire [9:0] io_fromPreMul_sExpSum = 10'h103; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_signProd = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire io_fromPreMul_isZeroC = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire io_fromPreMul_doSubMags = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire io_fromPreMul_bit0AlignedSigC = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire io_rawOut_sign = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _sigSum_T = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _CDom_absSigSumExtra_T_4 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire CDom_reduced4SigExtra_reducedVec_6 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _CDom_reduced4SigExtra_T_12 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _CDom_reduced4SigExtra_T_13 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _CDom_reduced4SigExtra_T_17 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _CDom_reduced4SigExtra_T_18 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire notCDom_reduced2AbsSigSum_reducedVec_23 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _notCDom_normDistReduced2_T_23 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _notCDom_reduced4SigExtra_T_9 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _notCDom_reduced4SigExtra_T_12 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _notCDom_reduced4SigExtra_T_13 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _notCDom_reduced4SigExtra_T_17 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _notCDom_reduced4SigExtra_T_18 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _notCDom_sign_T = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire notCDom_sign = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_invalidExc_T_4 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_isZero_T = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_sign_T_3 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_sign_T_9 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_sign_T_12 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_sign_T_13 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_sign_T_14 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_sign_T_15 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_sign_T_16 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire _io_rawOut_sign_T_17 = 1'h1; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :118:30, :123:57]
wire io_fromPreMul_isSigNaNAny = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_fromPreMul_isNaNAOrB = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_fromPreMul_isInfA = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_fromPreMul_isZeroA = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_fromPreMul_isInfB = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_fromPreMul_isZeroB = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_fromPreMul_isNaNC = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_fromPreMul_isInfC = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_fromPreMul_CIsDominant = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_invalidExc = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_rawOut_isNaN = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_rawOut_isInf = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire io_rawOut_isZero = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire roundingMode_min = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire opSignC = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_absSigSumExtra_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire CDom_absSigSumExtra = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire CDom_reduced4SigExtra_reducedVec_0 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire CDom_reduced4SigExtra_reducedVec_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire CDom_reduced4SigExtra_reducedVec_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire CDom_reduced4SigExtra_reducedVec_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire CDom_reduced4SigExtra_reducedVec_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire CDom_reduced4SigExtra_reducedVec_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_reduced4SigExtra_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_reduced4SigExtra_T_9 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire CDom_reduced4SigExtra = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_sig_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_sig_T_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _CDom_sig_T_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_signSigSum = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_0 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_7 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_9 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_10 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_11 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_12 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_13 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_14 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_15 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_16 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_17 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_18 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_19 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_20 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_21 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_22 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_24 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced2AbsSigSum_reducedVec_25 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_7 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_9 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_10 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_11 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_12 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_13 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_14 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_15 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_16 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_17 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_18 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_19 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_20 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_21 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_22 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_24 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_normDistReduced2_T_25 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced4SigExtra_reducedVec_0 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced4SigExtra_reducedVec_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced4SigExtra_reducedVec_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced4SigExtra_reducedVec_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced4SigExtra_reducedVec_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced4SigExtra_reducedVec_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced4SigExtra_reducedVec_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_reduced4SigExtra_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_reduced4SigExtra = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_sig_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notCDom_sig_T_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notCDom_completeCancellation = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notNaN_isInfProd = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notNaN_isInfOut = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _notNaN_addZeros_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire notNaN_addZeros = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T_3 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T_7 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_invalidExc_T_9 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_isNaN_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_isZero_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_isZero_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_1 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_2 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_4 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_5 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_6 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_7 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_8 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_10 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
wire _io_rawOut_sign_T_11 = 1'h0; // @[primitives.scala:77:20, :91:52, :101:30, :103:54, :106:{15,57}, :118:30, :120:54]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_132 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_132( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_27 :
output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : { sync : UInt<1>[1]}
invalidate nodeIn.sync[0]
wire nodeOut : UInt<1>[1]
invalidate nodeOut[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn.sync | module IntSyncSyncCrossingSink_n1x1_27( // @[Crossing.scala:96:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:96:9]
assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ScalePipe_2 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}}, out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}}}
wire out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}}
connect out.bits.index, io.in.bits.index
connect out.bits.id, io.in.bits.id
connect out.bits.scale.bits, io.in.bits.scale.bits
connect out.bits.data, io.in.bits.data
connect out.valid, io.in.valid
wire _out_bits_data_WIRE : { bits : UInt<32>}
wire _out_bits_data_WIRE_1 : UInt<32>
connect _out_bits_data_WIRE_1, io.in.bits.scale.bits
node _out_bits_data_T = bits(_out_bits_data_WIRE_1, 31, 0)
connect _out_bits_data_WIRE.bits, _out_bits_data_T
node out_bits_data_f_rec_rawIn_sign = bits(_out_bits_data_WIRE.bits, 31, 31)
node out_bits_data_f_rec_rawIn_expIn = bits(_out_bits_data_WIRE.bits, 30, 23)
node out_bits_data_f_rec_rawIn_fractIn = bits(_out_bits_data_WIRE.bits, 22, 0)
node out_bits_data_f_rec_rawIn_isZeroExpIn = eq(out_bits_data_f_rec_rawIn_expIn, UInt<1>(0h0))
node out_bits_data_f_rec_rawIn_isZeroFractIn = eq(out_bits_data_f_rec_rawIn_fractIn, UInt<1>(0h0))
node _out_bits_data_f_rec_rawIn_normDist_T = bits(out_bits_data_f_rec_rawIn_fractIn, 0, 0)
node _out_bits_data_f_rec_rawIn_normDist_T_1 = bits(out_bits_data_f_rec_rawIn_fractIn, 1, 1)
node _out_bits_data_f_rec_rawIn_normDist_T_2 = bits(out_bits_data_f_rec_rawIn_fractIn, 2, 2)
node _out_bits_data_f_rec_rawIn_normDist_T_3 = bits(out_bits_data_f_rec_rawIn_fractIn, 3, 3)
node _out_bits_data_f_rec_rawIn_normDist_T_4 = bits(out_bits_data_f_rec_rawIn_fractIn, 4, 4)
node _out_bits_data_f_rec_rawIn_normDist_T_5 = bits(out_bits_data_f_rec_rawIn_fractIn, 5, 5)
node _out_bits_data_f_rec_rawIn_normDist_T_6 = bits(out_bits_data_f_rec_rawIn_fractIn, 6, 6)
node _out_bits_data_f_rec_rawIn_normDist_T_7 = bits(out_bits_data_f_rec_rawIn_fractIn, 7, 7)
node _out_bits_data_f_rec_rawIn_normDist_T_8 = bits(out_bits_data_f_rec_rawIn_fractIn, 8, 8)
node _out_bits_data_f_rec_rawIn_normDist_T_9 = bits(out_bits_data_f_rec_rawIn_fractIn, 9, 9)
node _out_bits_data_f_rec_rawIn_normDist_T_10 = bits(out_bits_data_f_rec_rawIn_fractIn, 10, 10)
node _out_bits_data_f_rec_rawIn_normDist_T_11 = bits(out_bits_data_f_rec_rawIn_fractIn, 11, 11)
node _out_bits_data_f_rec_rawIn_normDist_T_12 = bits(out_bits_data_f_rec_rawIn_fractIn, 12, 12)
node _out_bits_data_f_rec_rawIn_normDist_T_13 = bits(out_bits_data_f_rec_rawIn_fractIn, 13, 13)
node _out_bits_data_f_rec_rawIn_normDist_T_14 = bits(out_bits_data_f_rec_rawIn_fractIn, 14, 14)
node _out_bits_data_f_rec_rawIn_normDist_T_15 = bits(out_bits_data_f_rec_rawIn_fractIn, 15, 15)
node _out_bits_data_f_rec_rawIn_normDist_T_16 = bits(out_bits_data_f_rec_rawIn_fractIn, 16, 16)
node _out_bits_data_f_rec_rawIn_normDist_T_17 = bits(out_bits_data_f_rec_rawIn_fractIn, 17, 17)
node _out_bits_data_f_rec_rawIn_normDist_T_18 = bits(out_bits_data_f_rec_rawIn_fractIn, 18, 18)
node _out_bits_data_f_rec_rawIn_normDist_T_19 = bits(out_bits_data_f_rec_rawIn_fractIn, 19, 19)
node _out_bits_data_f_rec_rawIn_normDist_T_20 = bits(out_bits_data_f_rec_rawIn_fractIn, 20, 20)
node _out_bits_data_f_rec_rawIn_normDist_T_21 = bits(out_bits_data_f_rec_rawIn_fractIn, 21, 21)
node _out_bits_data_f_rec_rawIn_normDist_T_22 = bits(out_bits_data_f_rec_rawIn_fractIn, 22, 22)
node _out_bits_data_f_rec_rawIn_normDist_T_23 = mux(_out_bits_data_f_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _out_bits_data_f_rec_rawIn_normDist_T_24 = mux(_out_bits_data_f_rec_rawIn_normDist_T_2, UInt<5>(0h14), _out_bits_data_f_rec_rawIn_normDist_T_23)
node _out_bits_data_f_rec_rawIn_normDist_T_25 = mux(_out_bits_data_f_rec_rawIn_normDist_T_3, UInt<5>(0h13), _out_bits_data_f_rec_rawIn_normDist_T_24)
node _out_bits_data_f_rec_rawIn_normDist_T_26 = mux(_out_bits_data_f_rec_rawIn_normDist_T_4, UInt<5>(0h12), _out_bits_data_f_rec_rawIn_normDist_T_25)
node _out_bits_data_f_rec_rawIn_normDist_T_27 = mux(_out_bits_data_f_rec_rawIn_normDist_T_5, UInt<5>(0h11), _out_bits_data_f_rec_rawIn_normDist_T_26)
node _out_bits_data_f_rec_rawIn_normDist_T_28 = mux(_out_bits_data_f_rec_rawIn_normDist_T_6, UInt<5>(0h10), _out_bits_data_f_rec_rawIn_normDist_T_27)
node _out_bits_data_f_rec_rawIn_normDist_T_29 = mux(_out_bits_data_f_rec_rawIn_normDist_T_7, UInt<4>(0hf), _out_bits_data_f_rec_rawIn_normDist_T_28)
node _out_bits_data_f_rec_rawIn_normDist_T_30 = mux(_out_bits_data_f_rec_rawIn_normDist_T_8, UInt<4>(0he), _out_bits_data_f_rec_rawIn_normDist_T_29)
node _out_bits_data_f_rec_rawIn_normDist_T_31 = mux(_out_bits_data_f_rec_rawIn_normDist_T_9, UInt<4>(0hd), _out_bits_data_f_rec_rawIn_normDist_T_30)
node _out_bits_data_f_rec_rawIn_normDist_T_32 = mux(_out_bits_data_f_rec_rawIn_normDist_T_10, UInt<4>(0hc), _out_bits_data_f_rec_rawIn_normDist_T_31)
node _out_bits_data_f_rec_rawIn_normDist_T_33 = mux(_out_bits_data_f_rec_rawIn_normDist_T_11, UInt<4>(0hb), _out_bits_data_f_rec_rawIn_normDist_T_32)
node _out_bits_data_f_rec_rawIn_normDist_T_34 = mux(_out_bits_data_f_rec_rawIn_normDist_T_12, UInt<4>(0ha), _out_bits_data_f_rec_rawIn_normDist_T_33)
node _out_bits_data_f_rec_rawIn_normDist_T_35 = mux(_out_bits_data_f_rec_rawIn_normDist_T_13, UInt<4>(0h9), _out_bits_data_f_rec_rawIn_normDist_T_34)
node _out_bits_data_f_rec_rawIn_normDist_T_36 = mux(_out_bits_data_f_rec_rawIn_normDist_T_14, UInt<4>(0h8), _out_bits_data_f_rec_rawIn_normDist_T_35)
node _out_bits_data_f_rec_rawIn_normDist_T_37 = mux(_out_bits_data_f_rec_rawIn_normDist_T_15, UInt<3>(0h7), _out_bits_data_f_rec_rawIn_normDist_T_36)
node _out_bits_data_f_rec_rawIn_normDist_T_38 = mux(_out_bits_data_f_rec_rawIn_normDist_T_16, UInt<3>(0h6), _out_bits_data_f_rec_rawIn_normDist_T_37)
node _out_bits_data_f_rec_rawIn_normDist_T_39 = mux(_out_bits_data_f_rec_rawIn_normDist_T_17, UInt<3>(0h5), _out_bits_data_f_rec_rawIn_normDist_T_38)
node _out_bits_data_f_rec_rawIn_normDist_T_40 = mux(_out_bits_data_f_rec_rawIn_normDist_T_18, UInt<3>(0h4), _out_bits_data_f_rec_rawIn_normDist_T_39)
node _out_bits_data_f_rec_rawIn_normDist_T_41 = mux(_out_bits_data_f_rec_rawIn_normDist_T_19, UInt<2>(0h3), _out_bits_data_f_rec_rawIn_normDist_T_40)
node _out_bits_data_f_rec_rawIn_normDist_T_42 = mux(_out_bits_data_f_rec_rawIn_normDist_T_20, UInt<2>(0h2), _out_bits_data_f_rec_rawIn_normDist_T_41)
node _out_bits_data_f_rec_rawIn_normDist_T_43 = mux(_out_bits_data_f_rec_rawIn_normDist_T_21, UInt<1>(0h1), _out_bits_data_f_rec_rawIn_normDist_T_42)
node out_bits_data_f_rec_rawIn_normDist = mux(_out_bits_data_f_rec_rawIn_normDist_T_22, UInt<1>(0h0), _out_bits_data_f_rec_rawIn_normDist_T_43)
node _out_bits_data_f_rec_rawIn_subnormFract_T = dshl(out_bits_data_f_rec_rawIn_fractIn, out_bits_data_f_rec_rawIn_normDist)
node _out_bits_data_f_rec_rawIn_subnormFract_T_1 = bits(_out_bits_data_f_rec_rawIn_subnormFract_T, 21, 0)
node out_bits_data_f_rec_rawIn_subnormFract = shl(_out_bits_data_f_rec_rawIn_subnormFract_T_1, 1)
node _out_bits_data_f_rec_rawIn_adjustedExp_T = xor(out_bits_data_f_rec_rawIn_normDist, UInt<9>(0h1ff))
node _out_bits_data_f_rec_rawIn_adjustedExp_T_1 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, _out_bits_data_f_rec_rawIn_adjustedExp_T, out_bits_data_f_rec_rawIn_expIn)
node _out_bits_data_f_rec_rawIn_adjustedExp_T_2 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _out_bits_data_f_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _out_bits_data_f_rec_rawIn_adjustedExp_T_2)
node _out_bits_data_f_rec_rawIn_adjustedExp_T_4 = add(_out_bits_data_f_rec_rawIn_adjustedExp_T_1, _out_bits_data_f_rec_rawIn_adjustedExp_T_3)
node out_bits_data_f_rec_rawIn_adjustedExp = tail(_out_bits_data_f_rec_rawIn_adjustedExp_T_4, 1)
node out_bits_data_f_rec_rawIn_isZero = and(out_bits_data_f_rec_rawIn_isZeroExpIn, out_bits_data_f_rec_rawIn_isZeroFractIn)
node _out_bits_data_f_rec_rawIn_isSpecial_T = bits(out_bits_data_f_rec_rawIn_adjustedExp, 8, 7)
node out_bits_data_f_rec_rawIn_isSpecial = eq(_out_bits_data_f_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire out_bits_data_f_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _out_bits_data_f_rec_rawIn_out_isNaN_T = eq(out_bits_data_f_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _out_bits_data_f_rec_rawIn_out_isNaN_T_1 = and(out_bits_data_f_rec_rawIn_isSpecial, _out_bits_data_f_rec_rawIn_out_isNaN_T)
connect out_bits_data_f_rec_rawIn.isNaN, _out_bits_data_f_rec_rawIn_out_isNaN_T_1
node _out_bits_data_f_rec_rawIn_out_isInf_T = and(out_bits_data_f_rec_rawIn_isSpecial, out_bits_data_f_rec_rawIn_isZeroFractIn)
connect out_bits_data_f_rec_rawIn.isInf, _out_bits_data_f_rec_rawIn_out_isInf_T
connect out_bits_data_f_rec_rawIn.isZero, out_bits_data_f_rec_rawIn_isZero
connect out_bits_data_f_rec_rawIn.sign, out_bits_data_f_rec_rawIn_sign
node _out_bits_data_f_rec_rawIn_out_sExp_T = bits(out_bits_data_f_rec_rawIn_adjustedExp, 8, 0)
node _out_bits_data_f_rec_rawIn_out_sExp_T_1 = cvt(_out_bits_data_f_rec_rawIn_out_sExp_T)
connect out_bits_data_f_rec_rawIn.sExp, _out_bits_data_f_rec_rawIn_out_sExp_T_1
node _out_bits_data_f_rec_rawIn_out_sig_T = eq(out_bits_data_f_rec_rawIn_isZero, UInt<1>(0h0))
node _out_bits_data_f_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _out_bits_data_f_rec_rawIn_out_sig_T)
node _out_bits_data_f_rec_rawIn_out_sig_T_2 = mux(out_bits_data_f_rec_rawIn_isZeroExpIn, out_bits_data_f_rec_rawIn_subnormFract, out_bits_data_f_rec_rawIn_fractIn)
node _out_bits_data_f_rec_rawIn_out_sig_T_3 = cat(_out_bits_data_f_rec_rawIn_out_sig_T_1, _out_bits_data_f_rec_rawIn_out_sig_T_2)
connect out_bits_data_f_rec_rawIn.sig, _out_bits_data_f_rec_rawIn_out_sig_T_3
node _out_bits_data_f_rec_T = bits(out_bits_data_f_rec_rawIn.sExp, 8, 6)
node _out_bits_data_f_rec_T_1 = mux(out_bits_data_f_rec_rawIn.isZero, UInt<3>(0h0), _out_bits_data_f_rec_T)
node _out_bits_data_f_rec_T_2 = mux(out_bits_data_f_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _out_bits_data_f_rec_T_3 = or(_out_bits_data_f_rec_T_1, _out_bits_data_f_rec_T_2)
node _out_bits_data_f_rec_T_4 = cat(out_bits_data_f_rec_rawIn.sign, _out_bits_data_f_rec_T_3)
node _out_bits_data_f_rec_T_5 = bits(out_bits_data_f_rec_rawIn.sExp, 5, 0)
node _out_bits_data_f_rec_T_6 = cat(_out_bits_data_f_rec_T_4, _out_bits_data_f_rec_T_5)
node _out_bits_data_f_rec_T_7 = bits(out_bits_data_f_rec_rawIn.sig, 22, 0)
node out_bits_data_f_rec = cat(_out_bits_data_f_rec_T_6, _out_bits_data_f_rec_T_7)
inst out_bits_data_in_to_rec_fn of INToRecFN_i8_e8_s24_2
connect out_bits_data_in_to_rec_fn.io.signedIn, UInt<1>(0h1)
wire _out_bits_data_in_to_rec_fn_io_in_WIRE : UInt<8>
node _out_bits_data_in_to_rec_fn_io_in_T = asUInt(io.in.bits.data)
connect _out_bits_data_in_to_rec_fn_io_in_WIRE, _out_bits_data_in_to_rec_fn_io_in_T
connect out_bits_data_in_to_rec_fn.io.in, _out_bits_data_in_to_rec_fn_io_in_WIRE
connect out_bits_data_in_to_rec_fn.io.roundingMode, UInt<3>(0h0)
connect out_bits_data_in_to_rec_fn.io.detectTininess, UInt<1>(0h1)
inst out_bits_data_muladder of MulAddRecFN_e8_s24_2
connect out_bits_data_muladder.io.op, UInt<1>(0h0)
connect out_bits_data_muladder.io.roundingMode, UInt<3>(0h0)
connect out_bits_data_muladder.io.detectTininess, UInt<1>(0h1)
connect out_bits_data_muladder.io.a, out_bits_data_in_to_rec_fn.io.out
connect out_bits_data_muladder.io.b, out_bits_data_f_rec
connect out_bits_data_muladder.io.c, UInt<1>(0h0)
inst out_bits_data_rec_fn_to_in of RecFNToIN_e8_s24_i8_2
connect out_bits_data_rec_fn_to_in.clock, clock
connect out_bits_data_rec_fn_to_in.reset, reset
connect out_bits_data_rec_fn_to_in.io.in, out_bits_data_muladder.io.out
connect out_bits_data_rec_fn_to_in.io.roundingMode, UInt<3>(0h0)
connect out_bits_data_rec_fn_to_in.io.signedOut, UInt<1>(0h1)
node out_bits_data_overflow = bits(out_bits_data_rec_fn_to_in.io.intExceptionFlags, 1, 1)
node out_bits_data_sign_exp = bits(out_bits_data_rec_fn_to_in.io.in, 31, 23)
node _out_bits_data_sign_isZero_T = bits(out_bits_data_sign_exp, 8, 6)
node out_bits_data_sign_isZero = eq(_out_bits_data_sign_isZero_T, UInt<1>(0h0))
node _out_bits_data_sign_isSpecial_T = bits(out_bits_data_sign_exp, 8, 7)
node out_bits_data_sign_isSpecial = eq(_out_bits_data_sign_isSpecial_T, UInt<2>(0h3))
wire out_bits_data_sign_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _out_bits_data_sign_out_isNaN_T = bits(out_bits_data_sign_exp, 6, 6)
node _out_bits_data_sign_out_isNaN_T_1 = and(out_bits_data_sign_isSpecial, _out_bits_data_sign_out_isNaN_T)
connect out_bits_data_sign_out.isNaN, _out_bits_data_sign_out_isNaN_T_1
node _out_bits_data_sign_out_isInf_T = bits(out_bits_data_sign_exp, 6, 6)
node _out_bits_data_sign_out_isInf_T_1 = eq(_out_bits_data_sign_out_isInf_T, UInt<1>(0h0))
node _out_bits_data_sign_out_isInf_T_2 = and(out_bits_data_sign_isSpecial, _out_bits_data_sign_out_isInf_T_1)
connect out_bits_data_sign_out.isInf, _out_bits_data_sign_out_isInf_T_2
connect out_bits_data_sign_out.isZero, out_bits_data_sign_isZero
node _out_bits_data_sign_out_sign_T = bits(out_bits_data_rec_fn_to_in.io.in, 32, 32)
connect out_bits_data_sign_out.sign, _out_bits_data_sign_out_sign_T
node _out_bits_data_sign_out_sExp_T = cvt(out_bits_data_sign_exp)
connect out_bits_data_sign_out.sExp, _out_bits_data_sign_out_sExp_T
node _out_bits_data_sign_out_sig_T = eq(out_bits_data_sign_isZero, UInt<1>(0h0))
node _out_bits_data_sign_out_sig_T_1 = cat(UInt<1>(0h0), _out_bits_data_sign_out_sig_T)
node _out_bits_data_sign_out_sig_T_2 = bits(out_bits_data_rec_fn_to_in.io.in, 22, 0)
node _out_bits_data_sign_out_sig_T_3 = cat(_out_bits_data_sign_out_sig_T_1, _out_bits_data_sign_out_sig_T_2)
connect out_bits_data_sign_out.sig, _out_bits_data_sign_out_sig_T_3
node out_bits_data_sat = mux(out_bits_data_sign_out.sign, asSInt(UInt<8>(0h80)), asSInt(UInt<8>(0h7f)))
wire _out_bits_data_WIRE_2 : SInt<8>
node _out_bits_data_T_1 = asSInt(out_bits_data_rec_fn_to_in.io.out)
connect _out_bits_data_WIRE_2, _out_bits_data_T_1
node _out_bits_data_T_2 = mux(out_bits_data_overflow, out_bits_data_sat, _out_bits_data_WIRE_2)
connect out.bits.data, _out_bits_data_T_2
regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_out_pipe_v, out.valid
reg io_out_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock
when out.valid :
connect io_out_pipe_b, out.bits
regreset io_out_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_out_pipe_pipe_v, io_out_pipe_v
reg io_out_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock
when io_out_pipe_v :
connect io_out_pipe_pipe_b, io_out_pipe_b
regreset io_out_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_out_pipe_pipe_pipe_v, io_out_pipe_pipe_v
reg io_out_pipe_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock
when io_out_pipe_pipe_v :
connect io_out_pipe_pipe_pipe_b, io_out_pipe_pipe_b
regreset io_out_pipe_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_out_pipe_pipe_pipe_pipe_v, io_out_pipe_pipe_pipe_v
reg io_out_pipe_pipe_pipe_pipe_b : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}, clock
when io_out_pipe_pipe_pipe_v :
connect io_out_pipe_pipe_pipe_pipe_b, io_out_pipe_pipe_pipe_b
wire io_out_pipe_pipe_pipe_pipe_out : { valid : UInt<1>, bits : { data : SInt<8>, scale : { bits : UInt<32>}, id : UInt<2>, index : UInt}}
connect io_out_pipe_pipe_pipe_pipe_out.valid, io_out_pipe_pipe_pipe_pipe_v
connect io_out_pipe_pipe_pipe_pipe_out.bits, io_out_pipe_pipe_pipe_pipe_b
connect io.out, io_out_pipe_pipe_pipe_pipe_out | module ScalePipe_2( // @[VectorScalarMultiplier.scala:33:7]
input clock, // @[VectorScalarMultiplier.scala:33:7]
input reset, // @[VectorScalarMultiplier.scala:33:7]
input io_in_valid, // @[VectorScalarMultiplier.scala:35:14]
input [7:0] io_in_bits_data, // @[VectorScalarMultiplier.scala:35:14]
input [31:0] io_in_bits_scale_bits, // @[VectorScalarMultiplier.scala:35:14]
input [1:0] io_in_bits_id, // @[VectorScalarMultiplier.scala:35:14]
input [3:0] io_in_bits_index, // @[VectorScalarMultiplier.scala:35:14]
output io_out_valid, // @[VectorScalarMultiplier.scala:35:14]
output [7:0] io_out_bits_data, // @[VectorScalarMultiplier.scala:35:14]
output [1:0] io_out_bits_id, // @[VectorScalarMultiplier.scala:35:14]
output [3:0] io_out_bits_index // @[VectorScalarMultiplier.scala:35:14]
);
wire out_bits_data_f_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [2:0] _out_bits_data_rec_fn_to_in_io_intExceptionFlags; // @[Configs.scala:93:34]
wire [32:0] _out_bits_data_muladder_io_out; // @[Configs.scala:84:30]
wire [32:0] _out_bits_data_in_to_rec_fn_io_out; // @[Configs.scala:76:34]
wire io_in_valid_0 = io_in_valid; // @[VectorScalarMultiplier.scala:33:7]
wire [7:0] io_in_bits_data_0 = io_in_bits_data; // @[VectorScalarMultiplier.scala:33:7]
wire [31:0] io_in_bits_scale_bits_0 = io_in_bits_scale_bits; // @[VectorScalarMultiplier.scala:33:7]
wire [1:0] io_in_bits_id_0 = io_in_bits_id; // @[VectorScalarMultiplier.scala:33:7]
wire [3:0] io_in_bits_index_0 = io_in_bits_index; // @[VectorScalarMultiplier.scala:33:7]
wire out_valid = io_in_valid_0; // @[VectorScalarMultiplier.scala:33:7, :40:21]
wire [7:0] _out_bits_data_in_to_rec_fn_io_in_T = io_in_bits_data_0; // @[VectorScalarMultiplier.scala:33:7]
wire [31:0] out_bits_scale_bits = io_in_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:33:7, :40:21]
wire [31:0] _out_bits_data_WIRE_1 = io_in_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:33:7, :41:89]
wire [1:0] out_bits_id = io_in_bits_id_0; // @[VectorScalarMultiplier.scala:33:7, :40:21]
wire [3:0] out_bits_index = io_in_bits_index_0; // @[VectorScalarMultiplier.scala:33:7, :40:21]
wire io_out_pipe_pipe_pipe_pipe_out_valid; // @[Valid.scala:135:21]
wire [7:0] io_out_pipe_pipe_pipe_pipe_out_bits_data; // @[Valid.scala:135:21]
wire [31:0] io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits; // @[Valid.scala:135:21]
wire [1:0] io_out_pipe_pipe_pipe_pipe_out_bits_id; // @[Valid.scala:135:21]
wire [3:0] io_out_pipe_pipe_pipe_pipe_out_bits_index; // @[Valid.scala:135:21]
wire [31:0] io_out_bits_scale_bits; // @[VectorScalarMultiplier.scala:33:7]
wire [7:0] io_out_bits_data_0; // @[VectorScalarMultiplier.scala:33:7]
wire [1:0] io_out_bits_id_0; // @[VectorScalarMultiplier.scala:33:7]
wire [3:0] io_out_bits_index_0; // @[VectorScalarMultiplier.scala:33:7]
wire io_out_valid_0; // @[VectorScalarMultiplier.scala:33:7]
wire [7:0] _out_bits_data_T_2; // @[Configs.scala:104:12]
wire [7:0] out_bits_data; // @[VectorScalarMultiplier.scala:40:21]
wire [31:0] _out_bits_data_T; // @[VectorScalarMultiplier.scala:41:89]
assign _out_bits_data_T = _out_bits_data_WIRE_1; // @[VectorScalarMultiplier.scala:41:89]
wire [31:0] _out_bits_data_WIRE_bits = _out_bits_data_T; // @[VectorScalarMultiplier.scala:41:89]
wire out_bits_data_f_rec_rawIn_sign = _out_bits_data_WIRE_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire out_bits_data_f_rec_rawIn_sign_0 = out_bits_data_f_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] out_bits_data_f_rec_rawIn_expIn = _out_bits_data_WIRE_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] out_bits_data_f_rec_rawIn_fractIn = _out_bits_data_WIRE_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire out_bits_data_f_rec_rawIn_isZeroExpIn = out_bits_data_f_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire out_bits_data_f_rec_rawIn_isZeroFractIn = out_bits_data_f_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _out_bits_data_f_rec_rawIn_normDist_T = out_bits_data_f_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_1 = out_bits_data_f_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_2 = out_bits_data_f_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_3 = out_bits_data_f_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_4 = out_bits_data_f_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_5 = out_bits_data_f_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_6 = out_bits_data_f_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_7 = out_bits_data_f_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_8 = out_bits_data_f_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_9 = out_bits_data_f_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_10 = out_bits_data_f_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_11 = out_bits_data_f_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_12 = out_bits_data_f_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_13 = out_bits_data_f_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_14 = out_bits_data_f_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_15 = out_bits_data_f_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_16 = out_bits_data_f_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_17 = out_bits_data_f_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_18 = out_bits_data_f_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_19 = out_bits_data_f_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_20 = out_bits_data_f_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_21 = out_bits_data_f_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _out_bits_data_f_rec_rawIn_normDist_T_22 = out_bits_data_f_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_23 = _out_bits_data_f_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_24 = _out_bits_data_f_rec_rawIn_normDist_T_2 ? 5'h14 : _out_bits_data_f_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_25 = _out_bits_data_f_rec_rawIn_normDist_T_3 ? 5'h13 : _out_bits_data_f_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_26 = _out_bits_data_f_rec_rawIn_normDist_T_4 ? 5'h12 : _out_bits_data_f_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_27 = _out_bits_data_f_rec_rawIn_normDist_T_5 ? 5'h11 : _out_bits_data_f_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_28 = _out_bits_data_f_rec_rawIn_normDist_T_6 ? 5'h10 : _out_bits_data_f_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_29 = _out_bits_data_f_rec_rawIn_normDist_T_7 ? 5'hF : _out_bits_data_f_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_30 = _out_bits_data_f_rec_rawIn_normDist_T_8 ? 5'hE : _out_bits_data_f_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_31 = _out_bits_data_f_rec_rawIn_normDist_T_9 ? 5'hD : _out_bits_data_f_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_32 = _out_bits_data_f_rec_rawIn_normDist_T_10 ? 5'hC : _out_bits_data_f_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_33 = _out_bits_data_f_rec_rawIn_normDist_T_11 ? 5'hB : _out_bits_data_f_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_34 = _out_bits_data_f_rec_rawIn_normDist_T_12 ? 5'hA : _out_bits_data_f_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_35 = _out_bits_data_f_rec_rawIn_normDist_T_13 ? 5'h9 : _out_bits_data_f_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_36 = _out_bits_data_f_rec_rawIn_normDist_T_14 ? 5'h8 : _out_bits_data_f_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_37 = _out_bits_data_f_rec_rawIn_normDist_T_15 ? 5'h7 : _out_bits_data_f_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_38 = _out_bits_data_f_rec_rawIn_normDist_T_16 ? 5'h6 : _out_bits_data_f_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_39 = _out_bits_data_f_rec_rawIn_normDist_T_17 ? 5'h5 : _out_bits_data_f_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_40 = _out_bits_data_f_rec_rawIn_normDist_T_18 ? 5'h4 : _out_bits_data_f_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_41 = _out_bits_data_f_rec_rawIn_normDist_T_19 ? 5'h3 : _out_bits_data_f_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_42 = _out_bits_data_f_rec_rawIn_normDist_T_20 ? 5'h2 : _out_bits_data_f_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _out_bits_data_f_rec_rawIn_normDist_T_43 = _out_bits_data_f_rec_rawIn_normDist_T_21 ? 5'h1 : _out_bits_data_f_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] out_bits_data_f_rec_rawIn_normDist = _out_bits_data_f_rec_rawIn_normDist_T_22 ? 5'h0 : _out_bits_data_f_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _out_bits_data_f_rec_rawIn_subnormFract_T = {31'h0, out_bits_data_f_rec_rawIn_fractIn} << out_bits_data_f_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _out_bits_data_f_rec_rawIn_subnormFract_T_1 = _out_bits_data_f_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] out_bits_data_f_rec_rawIn_subnormFract = {_out_bits_data_f_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _out_bits_data_f_rec_rawIn_adjustedExp_T = {4'hF, ~out_bits_data_f_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_1 = out_bits_data_f_rec_rawIn_isZeroExpIn ? _out_bits_data_f_rec_rawIn_adjustedExp_T : {1'h0, out_bits_data_f_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_2 = out_bits_data_f_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_3 = {6'h20, _out_bits_data_f_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _out_bits_data_f_rec_rawIn_adjustedExp_T_4 = {1'h0, _out_bits_data_f_rec_rawIn_adjustedExp_T_1} + {2'h0, _out_bits_data_f_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] out_bits_data_f_rec_rawIn_adjustedExp = _out_bits_data_f_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _out_bits_data_f_rec_rawIn_out_sExp_T = out_bits_data_f_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire out_bits_data_f_rec_rawIn_isZero = out_bits_data_f_rec_rawIn_isZeroExpIn & out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire out_bits_data_f_rec_rawIn_isZero_0 = out_bits_data_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _out_bits_data_f_rec_rawIn_isSpecial_T = out_bits_data_f_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire out_bits_data_f_rec_rawIn_isSpecial = &_out_bits_data_f_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _out_bits_data_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _out_bits_data_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _out_bits_data_f_rec_T_2 = out_bits_data_f_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _out_bits_data_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _out_bits_data_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire out_bits_data_f_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] out_bits_data_f_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] out_bits_data_f_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _out_bits_data_f_rec_rawIn_out_isNaN_T = ~out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _out_bits_data_f_rec_rawIn_out_isNaN_T_1 = out_bits_data_f_rec_rawIn_isSpecial & _out_bits_data_f_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign out_bits_data_f_rec_rawIn_isNaN = _out_bits_data_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _out_bits_data_f_rec_rawIn_out_isInf_T = out_bits_data_f_rec_rawIn_isSpecial & out_bits_data_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign out_bits_data_f_rec_rawIn_isInf = _out_bits_data_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _out_bits_data_f_rec_rawIn_out_sExp_T_1 = {1'h0, _out_bits_data_f_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign out_bits_data_f_rec_rawIn_sExp = _out_bits_data_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _out_bits_data_f_rec_rawIn_out_sig_T = ~out_bits_data_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _out_bits_data_f_rec_rawIn_out_sig_T_1 = {1'h0, _out_bits_data_f_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _out_bits_data_f_rec_rawIn_out_sig_T_2 = out_bits_data_f_rec_rawIn_isZeroExpIn ? out_bits_data_f_rec_rawIn_subnormFract : out_bits_data_f_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _out_bits_data_f_rec_rawIn_out_sig_T_3 = {_out_bits_data_f_rec_rawIn_out_sig_T_1, _out_bits_data_f_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign out_bits_data_f_rec_rawIn_sig = _out_bits_data_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _out_bits_data_f_rec_T = out_bits_data_f_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _out_bits_data_f_rec_T_1 = out_bits_data_f_rec_rawIn_isZero_0 ? 3'h0 : _out_bits_data_f_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _out_bits_data_f_rec_T_3 = {_out_bits_data_f_rec_T_1[2:1], _out_bits_data_f_rec_T_1[0] | _out_bits_data_f_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _out_bits_data_f_rec_T_4 = {out_bits_data_f_rec_rawIn_sign_0, _out_bits_data_f_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _out_bits_data_f_rec_T_5 = out_bits_data_f_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _out_bits_data_f_rec_T_6 = {_out_bits_data_f_rec_T_4, _out_bits_data_f_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _out_bits_data_f_rec_T_7 = out_bits_data_f_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] out_bits_data_f_rec = {_out_bits_data_f_rec_T_6, _out_bits_data_f_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [7:0] _out_bits_data_in_to_rec_fn_io_in_WIRE = _out_bits_data_in_to_rec_fn_io_in_T; // @[Configs.scala:78:41]
wire out_bits_data_overflow = _out_bits_data_rec_fn_to_in_io_intExceptionFlags[1]; // @[Configs.scala:93:34, :98:57]
wire [8:0] out_bits_data_sign_exp = _out_bits_data_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _out_bits_data_sign_isZero_T = out_bits_data_sign_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire out_bits_data_sign_isZero = _out_bits_data_sign_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire out_bits_data_sign_out_isZero = out_bits_data_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _out_bits_data_sign_isSpecial_T = out_bits_data_sign_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire out_bits_data_sign_isSpecial = &_out_bits_data_sign_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _out_bits_data_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _out_bits_data_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _out_bits_data_sign_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _out_bits_data_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _out_bits_data_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire out_bits_data_sign_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_data_sign_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_data_sign_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] out_bits_data_sign_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] out_bits_data_sign_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _out_bits_data_sign_out_isNaN_T = out_bits_data_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _out_bits_data_sign_out_isInf_T = out_bits_data_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _out_bits_data_sign_out_isNaN_T_1 = out_bits_data_sign_isSpecial & _out_bits_data_sign_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign out_bits_data_sign_out_isNaN = _out_bits_data_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _out_bits_data_sign_out_isInf_T_1 = ~_out_bits_data_sign_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _out_bits_data_sign_out_isInf_T_2 = out_bits_data_sign_isSpecial & _out_bits_data_sign_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign out_bits_data_sign_out_isInf = _out_bits_data_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _out_bits_data_sign_out_sign_T = _out_bits_data_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign out_bits_data_sign_out_sign = _out_bits_data_sign_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _out_bits_data_sign_out_sExp_T = {1'h0, out_bits_data_sign_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign out_bits_data_sign_out_sExp = _out_bits_data_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _out_bits_data_sign_out_sig_T = ~out_bits_data_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _out_bits_data_sign_out_sig_T_1 = {1'h0, _out_bits_data_sign_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _out_bits_data_sign_out_sig_T_2 = _out_bits_data_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _out_bits_data_sign_out_sig_T_3 = {_out_bits_data_sign_out_sig_T_1, _out_bits_data_sign_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign out_bits_data_sign_out_sig = _out_bits_data_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [7:0] out_bits_data_sat = out_bits_data_sign_out_sign ? 8'h80 : 8'h7F; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _out_bits_data_T_1; // @[Configs.scala:104:56]
wire [7:0] _out_bits_data_WIRE_2 = _out_bits_data_T_1; // @[Configs.scala:104:56]
assign _out_bits_data_T_2 = out_bits_data_overflow ? out_bits_data_sat : _out_bits_data_WIRE_2; // @[Configs.scala:98:57, :102:22, :104:{12,56}]
assign out_bits_data = _out_bits_data_T_2; // @[VectorScalarMultiplier.scala:40:21]
reg io_out_pipe_v; // @[Valid.scala:141:24]
reg [7:0] io_out_pipe_b_data; // @[Valid.scala:142:26]
reg [31:0] io_out_pipe_b_scale_bits; // @[Valid.scala:142:26]
reg [1:0] io_out_pipe_b_id; // @[Valid.scala:142:26]
reg [3:0] io_out_pipe_b_index; // @[Valid.scala:142:26]
reg io_out_pipe_pipe_v; // @[Valid.scala:141:24]
reg [7:0] io_out_pipe_pipe_b_data; // @[Valid.scala:142:26]
reg [31:0] io_out_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26]
reg [1:0] io_out_pipe_pipe_b_id; // @[Valid.scala:142:26]
reg [3:0] io_out_pipe_pipe_b_index; // @[Valid.scala:142:26]
reg io_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24]
reg [7:0] io_out_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26]
reg [31:0] io_out_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26]
reg [1:0] io_out_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26]
reg [3:0] io_out_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26]
reg io_out_pipe_pipe_pipe_pipe_v; // @[Valid.scala:141:24]
assign io_out_pipe_pipe_pipe_pipe_out_valid = io_out_pipe_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [7:0] io_out_pipe_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26]
assign io_out_pipe_pipe_pipe_pipe_out_bits_data = io_out_pipe_pipe_pipe_pipe_b_data; // @[Valid.scala:135:21, :142:26]
reg [31:0] io_out_pipe_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26]
assign io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits = io_out_pipe_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:135:21, :142:26]
reg [1:0] io_out_pipe_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26]
assign io_out_pipe_pipe_pipe_pipe_out_bits_id = io_out_pipe_pipe_pipe_pipe_b_id; // @[Valid.scala:135:21, :142:26]
reg [3:0] io_out_pipe_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26]
assign io_out_pipe_pipe_pipe_pipe_out_bits_index = io_out_pipe_pipe_pipe_pipe_b_index; // @[Valid.scala:135:21, :142:26]
assign io_out_valid_0 = io_out_pipe_pipe_pipe_pipe_out_valid; // @[Valid.scala:135:21]
assign io_out_bits_data_0 = io_out_pipe_pipe_pipe_pipe_out_bits_data; // @[Valid.scala:135:21]
assign io_out_bits_scale_bits = io_out_pipe_pipe_pipe_pipe_out_bits_scale_bits; // @[Valid.scala:135:21]
assign io_out_bits_id_0 = io_out_pipe_pipe_pipe_pipe_out_bits_id; // @[Valid.scala:135:21]
assign io_out_bits_index_0 = io_out_pipe_pipe_pipe_pipe_out_bits_index; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[VectorScalarMultiplier.scala:33:7]
if (reset) begin // @[VectorScalarMultiplier.scala:33:7]
io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_out_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_out_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_out_pipe_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[VectorScalarMultiplier.scala:33:7]
io_out_pipe_v <= out_valid; // @[Valid.scala:141:24]
io_out_pipe_pipe_v <= io_out_pipe_v; // @[Valid.scala:141:24]
io_out_pipe_pipe_pipe_v <= io_out_pipe_pipe_v; // @[Valid.scala:141:24]
io_out_pipe_pipe_pipe_pipe_v <= io_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24]
end
if (out_valid) begin // @[VectorScalarMultiplier.scala:40:21]
io_out_pipe_b_data <= out_bits_data; // @[Valid.scala:142:26]
io_out_pipe_b_scale_bits <= out_bits_scale_bits; // @[Valid.scala:142:26]
io_out_pipe_b_id <= out_bits_id; // @[Valid.scala:142:26]
io_out_pipe_b_index <= out_bits_index; // @[Valid.scala:142:26]
end
if (io_out_pipe_v) begin // @[Valid.scala:141:24]
io_out_pipe_pipe_b_data <= io_out_pipe_b_data; // @[Valid.scala:142:26]
io_out_pipe_pipe_b_scale_bits <= io_out_pipe_b_scale_bits; // @[Valid.scala:142:26]
io_out_pipe_pipe_b_id <= io_out_pipe_b_id; // @[Valid.scala:142:26]
io_out_pipe_pipe_b_index <= io_out_pipe_b_index; // @[Valid.scala:142:26]
end
if (io_out_pipe_pipe_v) begin // @[Valid.scala:141:24]
io_out_pipe_pipe_pipe_b_data <= io_out_pipe_pipe_b_data; // @[Valid.scala:142:26]
io_out_pipe_pipe_pipe_b_scale_bits <= io_out_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26]
io_out_pipe_pipe_pipe_b_id <= io_out_pipe_pipe_b_id; // @[Valid.scala:142:26]
io_out_pipe_pipe_pipe_b_index <= io_out_pipe_pipe_b_index; // @[Valid.scala:142:26]
end
if (io_out_pipe_pipe_pipe_v) begin // @[Valid.scala:141:24]
io_out_pipe_pipe_pipe_pipe_b_data <= io_out_pipe_pipe_pipe_b_data; // @[Valid.scala:142:26]
io_out_pipe_pipe_pipe_pipe_b_scale_bits <= io_out_pipe_pipe_pipe_b_scale_bits; // @[Valid.scala:142:26]
io_out_pipe_pipe_pipe_pipe_b_id <= io_out_pipe_pipe_pipe_b_id; // @[Valid.scala:142:26]
io_out_pipe_pipe_pipe_pipe_b_index <= io_out_pipe_pipe_pipe_b_index; // @[Valid.scala:142:26]
end
always @(posedge)
INToRecFN_i8_e8_s24_2 out_bits_data_in_to_rec_fn ( // @[Configs.scala:76:34]
.io_in (_out_bits_data_in_to_rec_fn_io_in_WIRE), // @[Configs.scala:78:41]
.io_out (_out_bits_data_in_to_rec_fn_io_out)
); // @[Configs.scala:76:34]
MulAddRecFN_e8_s24_2 out_bits_data_muladder ( // @[Configs.scala:84:30]
.io_a (_out_bits_data_in_to_rec_fn_io_out), // @[Configs.scala:76:34]
.io_b (out_bits_data_f_rec), // @[recFNFromFN.scala:50:41]
.io_out (_out_bits_data_muladder_io_out)
); // @[Configs.scala:84:30]
RecFNToIN_e8_s24_i8_2 out_bits_data_rec_fn_to_in ( // @[Configs.scala:93:34]
.clock (clock),
.reset (reset),
.io_in (_out_bits_data_muladder_io_out), // @[Configs.scala:84:30]
.io_out (_out_bits_data_T_1),
.io_intExceptionFlags (_out_bits_data_rec_fn_to_in_io_intExceptionFlags)
); // @[Configs.scala:93:34]
assign io_out_valid = io_out_valid_0; // @[VectorScalarMultiplier.scala:33:7]
assign io_out_bits_data = io_out_bits_data_0; // @[VectorScalarMultiplier.scala:33:7]
assign io_out_bits_id = io_out_bits_id_0; // @[VectorScalarMultiplier.scala:33:7]
assign io_out_bits_index = io_out_bits_index_0; // @[VectorScalarMultiplier.scala:33:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_379 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_123
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_379( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_123 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_74 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_150
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_74( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_150 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RenameStage :
input clock : Clock
input reset : Reset
output io : { ren_stalls : UInt<1>[3], flip kill : UInt<1>, flip dec_fire : UInt<1>[3], flip dec_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], ren2_mask : UInt<1>[3], ren2_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip dis_fire : UInt<1>[3], flip dis_ready : UInt<1>, flip wakeups : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[7], flip com_valids : UInt<1>[3], flip com_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], flip rbk_valids : UInt<1>[3], flip rollback : UInt<1>, flip debug_rob_empty : UInt<1>, debug : { freelist : UInt<100>, isprlist : UInt<100>, busytable : UInt<100>}}
connect io.ren_stalls[0], UInt<1>(0h0)
connect io.ren_stalls[1], UInt<1>(0h0)
connect io.ren_stalls[2], UInt<1>(0h0)
invalidate io.debug.busytable
invalidate io.debug.isprlist
invalidate io.debug.freelist
wire ren1_fire : UInt<1>[3]
wire ren1_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3]
wire ren2_valids : UInt<1>[3]
wire ren2_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3]
wire ren2_alloc_reqs : UInt<1>[3]
connect ren1_fire[0], io.dec_fire[0]
connect ren1_uops[0], io.dec_uops[0]
connect ren1_fire[1], io.dec_fire[1]
connect ren1_uops[1], io.dec_uops[1]
connect ren1_fire[2], io.dec_fire[2]
connect ren1_uops[2], io.dec_uops[2]
regreset r_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
wire next_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect next_uop, r_uop
when io.kill :
connect r_valid, UInt<1>(0h0)
else :
when io.dis_ready :
connect r_valid, ren1_fire[0]
connect next_uop, ren1_uops[0]
else :
node _r_valid_T = eq(io.dis_fire[0], UInt<1>(0h0))
node _r_valid_T_1 = and(r_valid, _r_valid_T)
connect r_valid, _r_valid_T_1
connect next_uop, r_uop
wire r_uop_bypassed_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_bypassed_uop, next_uop
node _r_uop_bypass_hits_rs1_T = eq(ren2_uops[0].ldst, next_uop.lrs1)
node r_uop_bypass_hits_rs1_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs1_T)
node _r_uop_bypass_hits_rs1_T_1 = eq(ren2_uops[1].ldst, next_uop.lrs1)
node r_uop_bypass_hits_rs1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs1_T_1)
node _r_uop_bypass_hits_rs1_T_2 = eq(ren2_uops[2].ldst, next_uop.lrs1)
node r_uop_bypass_hits_rs1_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs1_T_2)
node _r_uop_bypass_hits_rs2_T = eq(ren2_uops[0].ldst, next_uop.lrs2)
node r_uop_bypass_hits_rs2_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs2_T)
node _r_uop_bypass_hits_rs2_T_1 = eq(ren2_uops[1].ldst, next_uop.lrs2)
node r_uop_bypass_hits_rs2_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs2_T_1)
node _r_uop_bypass_hits_rs2_T_2 = eq(ren2_uops[2].ldst, next_uop.lrs2)
node r_uop_bypass_hits_rs2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs2_T_2)
node _r_uop_bypass_hits_rs3_T = eq(ren2_uops[0].ldst, next_uop.lrs3)
node r_uop_bypass_hits_rs3_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs3_T)
node _r_uop_bypass_hits_rs3_T_1 = eq(ren2_uops[1].ldst, next_uop.lrs3)
node r_uop_bypass_hits_rs3_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs3_T_1)
node _r_uop_bypass_hits_rs3_T_2 = eq(ren2_uops[2].ldst, next_uop.lrs3)
node r_uop_bypass_hits_rs3_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs3_T_2)
node _r_uop_bypass_hits_dst_T = eq(ren2_uops[0].ldst, next_uop.ldst)
node r_uop_bypass_hits_dst_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_dst_T)
node _r_uop_bypass_hits_dst_T_1 = eq(ren2_uops[1].ldst, next_uop.ldst)
node r_uop_bypass_hits_dst_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_dst_T_1)
node _r_uop_bypass_hits_dst_T_2 = eq(ren2_uops[2].ldst, next_uop.ldst)
node r_uop_bypass_hits_dst_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_dst_T_2)
node _r_uop_bypass_sel_rs1_enc_T = mux(r_uop_bypass_hits_rs1_0, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs1_enc_T_1 = mux(r_uop_bypass_hits_rs1_1, UInt<3>(0h2), _r_uop_bypass_sel_rs1_enc_T)
node r_uop_bypass_sel_rs1_enc = mux(r_uop_bypass_hits_rs1_2, UInt<3>(0h1), _r_uop_bypass_sel_rs1_enc_T_1)
node r_uop_bypass_sel_rs1_2 = bits(r_uop_bypass_sel_rs1_enc, 0, 0)
node r_uop_bypass_sel_rs1_1 = bits(r_uop_bypass_sel_rs1_enc, 1, 1)
node r_uop_bypass_sel_rs1_0 = bits(r_uop_bypass_sel_rs1_enc, 2, 2)
node _r_uop_bypass_sel_rs2_enc_T = mux(r_uop_bypass_hits_rs2_0, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs2_enc_T_1 = mux(r_uop_bypass_hits_rs2_1, UInt<3>(0h2), _r_uop_bypass_sel_rs2_enc_T)
node r_uop_bypass_sel_rs2_enc = mux(r_uop_bypass_hits_rs2_2, UInt<3>(0h1), _r_uop_bypass_sel_rs2_enc_T_1)
node r_uop_bypass_sel_rs2_2 = bits(r_uop_bypass_sel_rs2_enc, 0, 0)
node r_uop_bypass_sel_rs2_1 = bits(r_uop_bypass_sel_rs2_enc, 1, 1)
node r_uop_bypass_sel_rs2_0 = bits(r_uop_bypass_sel_rs2_enc, 2, 2)
node _r_uop_bypass_sel_rs3_enc_T = mux(r_uop_bypass_hits_rs3_0, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs3_enc_T_1 = mux(r_uop_bypass_hits_rs3_1, UInt<3>(0h2), _r_uop_bypass_sel_rs3_enc_T)
node r_uop_bypass_sel_rs3_enc = mux(r_uop_bypass_hits_rs3_2, UInt<3>(0h1), _r_uop_bypass_sel_rs3_enc_T_1)
node r_uop_bypass_sel_rs3_2 = bits(r_uop_bypass_sel_rs3_enc, 0, 0)
node r_uop_bypass_sel_rs3_1 = bits(r_uop_bypass_sel_rs3_enc, 1, 1)
node r_uop_bypass_sel_rs3_0 = bits(r_uop_bypass_sel_rs3_enc, 2, 2)
node _r_uop_bypass_sel_dst_enc_T = mux(r_uop_bypass_hits_dst_0, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_dst_enc_T_1 = mux(r_uop_bypass_hits_dst_1, UInt<3>(0h2), _r_uop_bypass_sel_dst_enc_T)
node r_uop_bypass_sel_dst_enc = mux(r_uop_bypass_hits_dst_2, UInt<3>(0h1), _r_uop_bypass_sel_dst_enc_T_1)
node r_uop_bypass_sel_dst_2 = bits(r_uop_bypass_sel_dst_enc, 0, 0)
node r_uop_bypass_sel_dst_1 = bits(r_uop_bypass_sel_dst_enc, 1, 1)
node r_uop_bypass_sel_dst_0 = bits(r_uop_bypass_sel_dst_enc, 2, 2)
node _r_uop_do_bypass_rs1_T = or(r_uop_bypass_hits_rs1_0, r_uop_bypass_hits_rs1_1)
node r_uop_do_bypass_rs1 = or(_r_uop_do_bypass_rs1_T, r_uop_bypass_hits_rs1_2)
node _r_uop_do_bypass_rs2_T = or(r_uop_bypass_hits_rs2_0, r_uop_bypass_hits_rs2_1)
node r_uop_do_bypass_rs2 = or(_r_uop_do_bypass_rs2_T, r_uop_bypass_hits_rs2_2)
node _r_uop_do_bypass_rs3_T = or(r_uop_bypass_hits_rs3_0, r_uop_bypass_hits_rs3_1)
node r_uop_do_bypass_rs3 = or(_r_uop_do_bypass_rs3_T, r_uop_bypass_hits_rs3_2)
node _r_uop_do_bypass_dst_T = or(r_uop_bypass_hits_dst_0, r_uop_bypass_hits_dst_1)
node r_uop_do_bypass_dst = or(_r_uop_do_bypass_dst_T, r_uop_bypass_hits_dst_2)
when r_uop_do_bypass_rs1 :
node _r_uop_bypassed_uop_prs1_T = mux(r_uop_bypass_sel_rs1_0, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_1 = mux(r_uop_bypass_sel_rs1_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_2 = mux(r_uop_bypass_sel_rs1_2, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_3 = or(_r_uop_bypassed_uop_prs1_T, _r_uop_bypassed_uop_prs1_T_1)
node _r_uop_bypassed_uop_prs1_T_4 = or(_r_uop_bypassed_uop_prs1_T_3, _r_uop_bypassed_uop_prs1_T_2)
wire _r_uop_bypassed_uop_prs1_WIRE : UInt<7>
connect _r_uop_bypassed_uop_prs1_WIRE, _r_uop_bypassed_uop_prs1_T_4
connect r_uop_bypassed_uop.prs1, _r_uop_bypassed_uop_prs1_WIRE
when r_uop_do_bypass_rs2 :
node _r_uop_bypassed_uop_prs2_T = mux(r_uop_bypass_sel_rs2_0, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_1 = mux(r_uop_bypass_sel_rs2_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_2 = mux(r_uop_bypass_sel_rs2_2, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_3 = or(_r_uop_bypassed_uop_prs2_T, _r_uop_bypassed_uop_prs2_T_1)
node _r_uop_bypassed_uop_prs2_T_4 = or(_r_uop_bypassed_uop_prs2_T_3, _r_uop_bypassed_uop_prs2_T_2)
wire _r_uop_bypassed_uop_prs2_WIRE : UInt<7>
connect _r_uop_bypassed_uop_prs2_WIRE, _r_uop_bypassed_uop_prs2_T_4
connect r_uop_bypassed_uop.prs2, _r_uop_bypassed_uop_prs2_WIRE
when r_uop_do_bypass_rs3 :
node _r_uop_bypassed_uop_prs3_T = mux(r_uop_bypass_sel_rs3_0, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_1 = mux(r_uop_bypass_sel_rs3_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_2 = mux(r_uop_bypass_sel_rs3_2, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_3 = or(_r_uop_bypassed_uop_prs3_T, _r_uop_bypassed_uop_prs3_T_1)
node _r_uop_bypassed_uop_prs3_T_4 = or(_r_uop_bypassed_uop_prs3_T_3, _r_uop_bypassed_uop_prs3_T_2)
wire _r_uop_bypassed_uop_prs3_WIRE : UInt<7>
connect _r_uop_bypassed_uop_prs3_WIRE, _r_uop_bypassed_uop_prs3_T_4
connect r_uop_bypassed_uop.prs3, _r_uop_bypassed_uop_prs3_WIRE
when r_uop_do_bypass_dst :
node _r_uop_bypassed_uop_stale_pdst_T = mux(r_uop_bypass_sel_dst_0, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_1 = mux(r_uop_bypass_sel_dst_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_2 = mux(r_uop_bypass_sel_dst_2, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_3 = or(_r_uop_bypassed_uop_stale_pdst_T, _r_uop_bypassed_uop_stale_pdst_T_1)
node _r_uop_bypassed_uop_stale_pdst_T_4 = or(_r_uop_bypassed_uop_stale_pdst_T_3, _r_uop_bypassed_uop_stale_pdst_T_2)
wire _r_uop_bypassed_uop_stale_pdst_WIRE : UInt<7>
connect _r_uop_bypassed_uop_stale_pdst_WIRE, _r_uop_bypassed_uop_stale_pdst_T_4
connect r_uop_bypassed_uop.stale_pdst, _r_uop_bypassed_uop_stale_pdst_WIRE
node _r_uop_bypassed_uop_prs1_busy_T = or(next_uop.prs1_busy, r_uop_do_bypass_rs1)
connect r_uop_bypassed_uop.prs1_busy, _r_uop_bypassed_uop_prs1_busy_T
node _r_uop_bypassed_uop_prs2_busy_T = or(next_uop.prs2_busy, r_uop_do_bypass_rs2)
connect r_uop_bypassed_uop.prs2_busy, _r_uop_bypassed_uop_prs2_busy_T
node _r_uop_bypassed_uop_prs3_busy_T = or(next_uop.prs3_busy, r_uop_do_bypass_rs3)
connect r_uop_bypassed_uop.prs3_busy, _r_uop_bypassed_uop_prs3_busy_T
invalidate r_uop_bypassed_uop.prs3
connect r_uop_bypassed_uop.prs3_busy, UInt<1>(0h0)
wire r_uop_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_newuop, r_uop_bypassed_uop
node _r_uop_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_uop_newuop_br_mask_T_1 = and(r_uop_bypassed_uop.br_mask, _r_uop_newuop_br_mask_T)
connect r_uop_newuop.br_mask, _r_uop_newuop_br_mask_T_1
connect r_uop, r_uop_newuop
connect ren2_valids[0], r_valid
connect ren2_uops[0], r_uop
regreset r_valid_1 : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
wire next_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect next_uop_1, r_uop_1
when io.kill :
connect r_valid_1, UInt<1>(0h0)
else :
when io.dis_ready :
connect r_valid_1, ren1_fire[1]
connect next_uop_1, ren1_uops[1]
else :
node _r_valid_T_2 = eq(io.dis_fire[1], UInt<1>(0h0))
node _r_valid_T_3 = and(r_valid_1, _r_valid_T_2)
connect r_valid_1, _r_valid_T_3
connect next_uop_1, r_uop_1
wire r_uop_bypassed_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_bypassed_uop_1, next_uop_1
node _r_uop_bypass_hits_rs1_T_3 = eq(ren2_uops[0].ldst, next_uop_1.lrs1)
node r_uop_bypass_hits_rs1_0_1 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs1_T_3)
node _r_uop_bypass_hits_rs1_T_4 = eq(ren2_uops[1].ldst, next_uop_1.lrs1)
node r_uop_bypass_hits_rs1_1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs1_T_4)
node _r_uop_bypass_hits_rs1_T_5 = eq(ren2_uops[2].ldst, next_uop_1.lrs1)
node r_uop_bypass_hits_rs1_2_1 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs1_T_5)
node _r_uop_bypass_hits_rs2_T_3 = eq(ren2_uops[0].ldst, next_uop_1.lrs2)
node r_uop_bypass_hits_rs2_0_1 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs2_T_3)
node _r_uop_bypass_hits_rs2_T_4 = eq(ren2_uops[1].ldst, next_uop_1.lrs2)
node r_uop_bypass_hits_rs2_1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs2_T_4)
node _r_uop_bypass_hits_rs2_T_5 = eq(ren2_uops[2].ldst, next_uop_1.lrs2)
node r_uop_bypass_hits_rs2_2_1 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs2_T_5)
node _r_uop_bypass_hits_rs3_T_3 = eq(ren2_uops[0].ldst, next_uop_1.lrs3)
node r_uop_bypass_hits_rs3_0_1 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs3_T_3)
node _r_uop_bypass_hits_rs3_T_4 = eq(ren2_uops[1].ldst, next_uop_1.lrs3)
node r_uop_bypass_hits_rs3_1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs3_T_4)
node _r_uop_bypass_hits_rs3_T_5 = eq(ren2_uops[2].ldst, next_uop_1.lrs3)
node r_uop_bypass_hits_rs3_2_1 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs3_T_5)
node _r_uop_bypass_hits_dst_T_3 = eq(ren2_uops[0].ldst, next_uop_1.ldst)
node r_uop_bypass_hits_dst_0_1 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_dst_T_3)
node _r_uop_bypass_hits_dst_T_4 = eq(ren2_uops[1].ldst, next_uop_1.ldst)
node r_uop_bypass_hits_dst_1_1 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_dst_T_4)
node _r_uop_bypass_hits_dst_T_5 = eq(ren2_uops[2].ldst, next_uop_1.ldst)
node r_uop_bypass_hits_dst_2_1 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_dst_T_5)
node _r_uop_bypass_sel_rs1_enc_T_2 = mux(r_uop_bypass_hits_rs1_0_1, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs1_enc_T_3 = mux(r_uop_bypass_hits_rs1_1_1, UInt<3>(0h2), _r_uop_bypass_sel_rs1_enc_T_2)
node r_uop_bypass_sel_rs1_enc_1 = mux(r_uop_bypass_hits_rs1_2_1, UInt<3>(0h1), _r_uop_bypass_sel_rs1_enc_T_3)
node r_uop_bypass_sel_rs1_2_1 = bits(r_uop_bypass_sel_rs1_enc_1, 0, 0)
node r_uop_bypass_sel_rs1_1_1 = bits(r_uop_bypass_sel_rs1_enc_1, 1, 1)
node r_uop_bypass_sel_rs1_0_1 = bits(r_uop_bypass_sel_rs1_enc_1, 2, 2)
node _r_uop_bypass_sel_rs2_enc_T_2 = mux(r_uop_bypass_hits_rs2_0_1, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs2_enc_T_3 = mux(r_uop_bypass_hits_rs2_1_1, UInt<3>(0h2), _r_uop_bypass_sel_rs2_enc_T_2)
node r_uop_bypass_sel_rs2_enc_1 = mux(r_uop_bypass_hits_rs2_2_1, UInt<3>(0h1), _r_uop_bypass_sel_rs2_enc_T_3)
node r_uop_bypass_sel_rs2_2_1 = bits(r_uop_bypass_sel_rs2_enc_1, 0, 0)
node r_uop_bypass_sel_rs2_1_1 = bits(r_uop_bypass_sel_rs2_enc_1, 1, 1)
node r_uop_bypass_sel_rs2_0_1 = bits(r_uop_bypass_sel_rs2_enc_1, 2, 2)
node _r_uop_bypass_sel_rs3_enc_T_2 = mux(r_uop_bypass_hits_rs3_0_1, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs3_enc_T_3 = mux(r_uop_bypass_hits_rs3_1_1, UInt<3>(0h2), _r_uop_bypass_sel_rs3_enc_T_2)
node r_uop_bypass_sel_rs3_enc_1 = mux(r_uop_bypass_hits_rs3_2_1, UInt<3>(0h1), _r_uop_bypass_sel_rs3_enc_T_3)
node r_uop_bypass_sel_rs3_2_1 = bits(r_uop_bypass_sel_rs3_enc_1, 0, 0)
node r_uop_bypass_sel_rs3_1_1 = bits(r_uop_bypass_sel_rs3_enc_1, 1, 1)
node r_uop_bypass_sel_rs3_0_1 = bits(r_uop_bypass_sel_rs3_enc_1, 2, 2)
node _r_uop_bypass_sel_dst_enc_T_2 = mux(r_uop_bypass_hits_dst_0_1, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_dst_enc_T_3 = mux(r_uop_bypass_hits_dst_1_1, UInt<3>(0h2), _r_uop_bypass_sel_dst_enc_T_2)
node r_uop_bypass_sel_dst_enc_1 = mux(r_uop_bypass_hits_dst_2_1, UInt<3>(0h1), _r_uop_bypass_sel_dst_enc_T_3)
node r_uop_bypass_sel_dst_2_1 = bits(r_uop_bypass_sel_dst_enc_1, 0, 0)
node r_uop_bypass_sel_dst_1_1 = bits(r_uop_bypass_sel_dst_enc_1, 1, 1)
node r_uop_bypass_sel_dst_0_1 = bits(r_uop_bypass_sel_dst_enc_1, 2, 2)
node _r_uop_do_bypass_rs1_T_1 = or(r_uop_bypass_hits_rs1_0_1, r_uop_bypass_hits_rs1_1_1)
node r_uop_do_bypass_rs1_1 = or(_r_uop_do_bypass_rs1_T_1, r_uop_bypass_hits_rs1_2_1)
node _r_uop_do_bypass_rs2_T_1 = or(r_uop_bypass_hits_rs2_0_1, r_uop_bypass_hits_rs2_1_1)
node r_uop_do_bypass_rs2_1 = or(_r_uop_do_bypass_rs2_T_1, r_uop_bypass_hits_rs2_2_1)
node _r_uop_do_bypass_rs3_T_1 = or(r_uop_bypass_hits_rs3_0_1, r_uop_bypass_hits_rs3_1_1)
node r_uop_do_bypass_rs3_1 = or(_r_uop_do_bypass_rs3_T_1, r_uop_bypass_hits_rs3_2_1)
node _r_uop_do_bypass_dst_T_1 = or(r_uop_bypass_hits_dst_0_1, r_uop_bypass_hits_dst_1_1)
node r_uop_do_bypass_dst_1 = or(_r_uop_do_bypass_dst_T_1, r_uop_bypass_hits_dst_2_1)
when r_uop_do_bypass_rs1_1 :
node _r_uop_bypassed_uop_prs1_T_5 = mux(r_uop_bypass_sel_rs1_0_1, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_6 = mux(r_uop_bypass_sel_rs1_1_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_7 = mux(r_uop_bypass_sel_rs1_2_1, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_8 = or(_r_uop_bypassed_uop_prs1_T_5, _r_uop_bypassed_uop_prs1_T_6)
node _r_uop_bypassed_uop_prs1_T_9 = or(_r_uop_bypassed_uop_prs1_T_8, _r_uop_bypassed_uop_prs1_T_7)
wire _r_uop_bypassed_uop_prs1_WIRE_1 : UInt<7>
connect _r_uop_bypassed_uop_prs1_WIRE_1, _r_uop_bypassed_uop_prs1_T_9
connect r_uop_bypassed_uop_1.prs1, _r_uop_bypassed_uop_prs1_WIRE_1
when r_uop_do_bypass_rs2_1 :
node _r_uop_bypassed_uop_prs2_T_5 = mux(r_uop_bypass_sel_rs2_0_1, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_6 = mux(r_uop_bypass_sel_rs2_1_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_7 = mux(r_uop_bypass_sel_rs2_2_1, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_8 = or(_r_uop_bypassed_uop_prs2_T_5, _r_uop_bypassed_uop_prs2_T_6)
node _r_uop_bypassed_uop_prs2_T_9 = or(_r_uop_bypassed_uop_prs2_T_8, _r_uop_bypassed_uop_prs2_T_7)
wire _r_uop_bypassed_uop_prs2_WIRE_1 : UInt<7>
connect _r_uop_bypassed_uop_prs2_WIRE_1, _r_uop_bypassed_uop_prs2_T_9
connect r_uop_bypassed_uop_1.prs2, _r_uop_bypassed_uop_prs2_WIRE_1
when r_uop_do_bypass_rs3_1 :
node _r_uop_bypassed_uop_prs3_T_5 = mux(r_uop_bypass_sel_rs3_0_1, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_6 = mux(r_uop_bypass_sel_rs3_1_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_7 = mux(r_uop_bypass_sel_rs3_2_1, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_8 = or(_r_uop_bypassed_uop_prs3_T_5, _r_uop_bypassed_uop_prs3_T_6)
node _r_uop_bypassed_uop_prs3_T_9 = or(_r_uop_bypassed_uop_prs3_T_8, _r_uop_bypassed_uop_prs3_T_7)
wire _r_uop_bypassed_uop_prs3_WIRE_1 : UInt<7>
connect _r_uop_bypassed_uop_prs3_WIRE_1, _r_uop_bypassed_uop_prs3_T_9
connect r_uop_bypassed_uop_1.prs3, _r_uop_bypassed_uop_prs3_WIRE_1
when r_uop_do_bypass_dst_1 :
node _r_uop_bypassed_uop_stale_pdst_T_5 = mux(r_uop_bypass_sel_dst_0_1, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_6 = mux(r_uop_bypass_sel_dst_1_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_7 = mux(r_uop_bypass_sel_dst_2_1, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_8 = or(_r_uop_bypassed_uop_stale_pdst_T_5, _r_uop_bypassed_uop_stale_pdst_T_6)
node _r_uop_bypassed_uop_stale_pdst_T_9 = or(_r_uop_bypassed_uop_stale_pdst_T_8, _r_uop_bypassed_uop_stale_pdst_T_7)
wire _r_uop_bypassed_uop_stale_pdst_WIRE_1 : UInt<7>
connect _r_uop_bypassed_uop_stale_pdst_WIRE_1, _r_uop_bypassed_uop_stale_pdst_T_9
connect r_uop_bypassed_uop_1.stale_pdst, _r_uop_bypassed_uop_stale_pdst_WIRE_1
node _r_uop_bypassed_uop_prs1_busy_T_1 = or(next_uop_1.prs1_busy, r_uop_do_bypass_rs1_1)
connect r_uop_bypassed_uop_1.prs1_busy, _r_uop_bypassed_uop_prs1_busy_T_1
node _r_uop_bypassed_uop_prs2_busy_T_1 = or(next_uop_1.prs2_busy, r_uop_do_bypass_rs2_1)
connect r_uop_bypassed_uop_1.prs2_busy, _r_uop_bypassed_uop_prs2_busy_T_1
node _r_uop_bypassed_uop_prs3_busy_T_1 = or(next_uop_1.prs3_busy, r_uop_do_bypass_rs3_1)
connect r_uop_bypassed_uop_1.prs3_busy, _r_uop_bypassed_uop_prs3_busy_T_1
invalidate r_uop_bypassed_uop_1.prs3
connect r_uop_bypassed_uop_1.prs3_busy, UInt<1>(0h0)
wire r_uop_newuop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_newuop_1, r_uop_bypassed_uop_1
node _r_uop_newuop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _r_uop_newuop_br_mask_T_3 = and(r_uop_bypassed_uop_1.br_mask, _r_uop_newuop_br_mask_T_2)
connect r_uop_newuop_1.br_mask, _r_uop_newuop_br_mask_T_3
connect r_uop_1, r_uop_newuop_1
connect ren2_valids[1], r_valid_1
connect ren2_uops[1], r_uop_1
regreset r_valid_2 : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
wire next_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect next_uop_2, r_uop_2
when io.kill :
connect r_valid_2, UInt<1>(0h0)
else :
when io.dis_ready :
connect r_valid_2, ren1_fire[2]
connect next_uop_2, ren1_uops[2]
else :
node _r_valid_T_4 = eq(io.dis_fire[2], UInt<1>(0h0))
node _r_valid_T_5 = and(r_valid_2, _r_valid_T_4)
connect r_valid_2, _r_valid_T_5
connect next_uop_2, r_uop_2
wire r_uop_bypassed_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_bypassed_uop_2, next_uop_2
node _r_uop_bypass_hits_rs1_T_6 = eq(ren2_uops[0].ldst, next_uop_2.lrs1)
node r_uop_bypass_hits_rs1_0_2 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs1_T_6)
node _r_uop_bypass_hits_rs1_T_7 = eq(ren2_uops[1].ldst, next_uop_2.lrs1)
node r_uop_bypass_hits_rs1_1_2 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs1_T_7)
node _r_uop_bypass_hits_rs1_T_8 = eq(ren2_uops[2].ldst, next_uop_2.lrs1)
node r_uop_bypass_hits_rs1_2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs1_T_8)
node _r_uop_bypass_hits_rs2_T_6 = eq(ren2_uops[0].ldst, next_uop_2.lrs2)
node r_uop_bypass_hits_rs2_0_2 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs2_T_6)
node _r_uop_bypass_hits_rs2_T_7 = eq(ren2_uops[1].ldst, next_uop_2.lrs2)
node r_uop_bypass_hits_rs2_1_2 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs2_T_7)
node _r_uop_bypass_hits_rs2_T_8 = eq(ren2_uops[2].ldst, next_uop_2.lrs2)
node r_uop_bypass_hits_rs2_2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs2_T_8)
node _r_uop_bypass_hits_rs3_T_6 = eq(ren2_uops[0].ldst, next_uop_2.lrs3)
node r_uop_bypass_hits_rs3_0_2 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs3_T_6)
node _r_uop_bypass_hits_rs3_T_7 = eq(ren2_uops[1].ldst, next_uop_2.lrs3)
node r_uop_bypass_hits_rs3_1_2 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_rs3_T_7)
node _r_uop_bypass_hits_rs3_T_8 = eq(ren2_uops[2].ldst, next_uop_2.lrs3)
node r_uop_bypass_hits_rs3_2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_rs3_T_8)
node _r_uop_bypass_hits_dst_T_6 = eq(ren2_uops[0].ldst, next_uop_2.ldst)
node r_uop_bypass_hits_dst_0_2 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_dst_T_6)
node _r_uop_bypass_hits_dst_T_7 = eq(ren2_uops[1].ldst, next_uop_2.ldst)
node r_uop_bypass_hits_dst_1_2 = and(ren2_alloc_reqs[1], _r_uop_bypass_hits_dst_T_7)
node _r_uop_bypass_hits_dst_T_8 = eq(ren2_uops[2].ldst, next_uop_2.ldst)
node r_uop_bypass_hits_dst_2_2 = and(ren2_alloc_reqs[2], _r_uop_bypass_hits_dst_T_8)
node _r_uop_bypass_sel_rs1_enc_T_4 = mux(r_uop_bypass_hits_rs1_0_2, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs1_enc_T_5 = mux(r_uop_bypass_hits_rs1_1_2, UInt<3>(0h2), _r_uop_bypass_sel_rs1_enc_T_4)
node r_uop_bypass_sel_rs1_enc_2 = mux(r_uop_bypass_hits_rs1_2_2, UInt<3>(0h1), _r_uop_bypass_sel_rs1_enc_T_5)
node r_uop_bypass_sel_rs1_2_2 = bits(r_uop_bypass_sel_rs1_enc_2, 0, 0)
node r_uop_bypass_sel_rs1_1_2 = bits(r_uop_bypass_sel_rs1_enc_2, 1, 1)
node r_uop_bypass_sel_rs1_0_2 = bits(r_uop_bypass_sel_rs1_enc_2, 2, 2)
node _r_uop_bypass_sel_rs2_enc_T_4 = mux(r_uop_bypass_hits_rs2_0_2, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs2_enc_T_5 = mux(r_uop_bypass_hits_rs2_1_2, UInt<3>(0h2), _r_uop_bypass_sel_rs2_enc_T_4)
node r_uop_bypass_sel_rs2_enc_2 = mux(r_uop_bypass_hits_rs2_2_2, UInt<3>(0h1), _r_uop_bypass_sel_rs2_enc_T_5)
node r_uop_bypass_sel_rs2_2_2 = bits(r_uop_bypass_sel_rs2_enc_2, 0, 0)
node r_uop_bypass_sel_rs2_1_2 = bits(r_uop_bypass_sel_rs2_enc_2, 1, 1)
node r_uop_bypass_sel_rs2_0_2 = bits(r_uop_bypass_sel_rs2_enc_2, 2, 2)
node _r_uop_bypass_sel_rs3_enc_T_4 = mux(r_uop_bypass_hits_rs3_0_2, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_rs3_enc_T_5 = mux(r_uop_bypass_hits_rs3_1_2, UInt<3>(0h2), _r_uop_bypass_sel_rs3_enc_T_4)
node r_uop_bypass_sel_rs3_enc_2 = mux(r_uop_bypass_hits_rs3_2_2, UInt<3>(0h1), _r_uop_bypass_sel_rs3_enc_T_5)
node r_uop_bypass_sel_rs3_2_2 = bits(r_uop_bypass_sel_rs3_enc_2, 0, 0)
node r_uop_bypass_sel_rs3_1_2 = bits(r_uop_bypass_sel_rs3_enc_2, 1, 1)
node r_uop_bypass_sel_rs3_0_2 = bits(r_uop_bypass_sel_rs3_enc_2, 2, 2)
node _r_uop_bypass_sel_dst_enc_T_4 = mux(r_uop_bypass_hits_dst_0_2, UInt<3>(0h4), UInt<3>(0h0))
node _r_uop_bypass_sel_dst_enc_T_5 = mux(r_uop_bypass_hits_dst_1_2, UInt<3>(0h2), _r_uop_bypass_sel_dst_enc_T_4)
node r_uop_bypass_sel_dst_enc_2 = mux(r_uop_bypass_hits_dst_2_2, UInt<3>(0h1), _r_uop_bypass_sel_dst_enc_T_5)
node r_uop_bypass_sel_dst_2_2 = bits(r_uop_bypass_sel_dst_enc_2, 0, 0)
node r_uop_bypass_sel_dst_1_2 = bits(r_uop_bypass_sel_dst_enc_2, 1, 1)
node r_uop_bypass_sel_dst_0_2 = bits(r_uop_bypass_sel_dst_enc_2, 2, 2)
node _r_uop_do_bypass_rs1_T_2 = or(r_uop_bypass_hits_rs1_0_2, r_uop_bypass_hits_rs1_1_2)
node r_uop_do_bypass_rs1_2 = or(_r_uop_do_bypass_rs1_T_2, r_uop_bypass_hits_rs1_2_2)
node _r_uop_do_bypass_rs2_T_2 = or(r_uop_bypass_hits_rs2_0_2, r_uop_bypass_hits_rs2_1_2)
node r_uop_do_bypass_rs2_2 = or(_r_uop_do_bypass_rs2_T_2, r_uop_bypass_hits_rs2_2_2)
node _r_uop_do_bypass_rs3_T_2 = or(r_uop_bypass_hits_rs3_0_2, r_uop_bypass_hits_rs3_1_2)
node r_uop_do_bypass_rs3_2 = or(_r_uop_do_bypass_rs3_T_2, r_uop_bypass_hits_rs3_2_2)
node _r_uop_do_bypass_dst_T_2 = or(r_uop_bypass_hits_dst_0_2, r_uop_bypass_hits_dst_1_2)
node r_uop_do_bypass_dst_2 = or(_r_uop_do_bypass_dst_T_2, r_uop_bypass_hits_dst_2_2)
when r_uop_do_bypass_rs1_2 :
node _r_uop_bypassed_uop_prs1_T_10 = mux(r_uop_bypass_sel_rs1_0_2, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_11 = mux(r_uop_bypass_sel_rs1_1_2, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_12 = mux(r_uop_bypass_sel_rs1_2_2, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs1_T_13 = or(_r_uop_bypassed_uop_prs1_T_10, _r_uop_bypassed_uop_prs1_T_11)
node _r_uop_bypassed_uop_prs1_T_14 = or(_r_uop_bypassed_uop_prs1_T_13, _r_uop_bypassed_uop_prs1_T_12)
wire _r_uop_bypassed_uop_prs1_WIRE_2 : UInt<7>
connect _r_uop_bypassed_uop_prs1_WIRE_2, _r_uop_bypassed_uop_prs1_T_14
connect r_uop_bypassed_uop_2.prs1, _r_uop_bypassed_uop_prs1_WIRE_2
when r_uop_do_bypass_rs2_2 :
node _r_uop_bypassed_uop_prs2_T_10 = mux(r_uop_bypass_sel_rs2_0_2, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_11 = mux(r_uop_bypass_sel_rs2_1_2, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_12 = mux(r_uop_bypass_sel_rs2_2_2, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs2_T_13 = or(_r_uop_bypassed_uop_prs2_T_10, _r_uop_bypassed_uop_prs2_T_11)
node _r_uop_bypassed_uop_prs2_T_14 = or(_r_uop_bypassed_uop_prs2_T_13, _r_uop_bypassed_uop_prs2_T_12)
wire _r_uop_bypassed_uop_prs2_WIRE_2 : UInt<7>
connect _r_uop_bypassed_uop_prs2_WIRE_2, _r_uop_bypassed_uop_prs2_T_14
connect r_uop_bypassed_uop_2.prs2, _r_uop_bypassed_uop_prs2_WIRE_2
when r_uop_do_bypass_rs3_2 :
node _r_uop_bypassed_uop_prs3_T_10 = mux(r_uop_bypass_sel_rs3_0_2, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_11 = mux(r_uop_bypass_sel_rs3_1_2, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_12 = mux(r_uop_bypass_sel_rs3_2_2, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_prs3_T_13 = or(_r_uop_bypassed_uop_prs3_T_10, _r_uop_bypassed_uop_prs3_T_11)
node _r_uop_bypassed_uop_prs3_T_14 = or(_r_uop_bypassed_uop_prs3_T_13, _r_uop_bypassed_uop_prs3_T_12)
wire _r_uop_bypassed_uop_prs3_WIRE_2 : UInt<7>
connect _r_uop_bypassed_uop_prs3_WIRE_2, _r_uop_bypassed_uop_prs3_T_14
connect r_uop_bypassed_uop_2.prs3, _r_uop_bypassed_uop_prs3_WIRE_2
when r_uop_do_bypass_dst_2 :
node _r_uop_bypassed_uop_stale_pdst_T_10 = mux(r_uop_bypass_sel_dst_0_2, ren2_uops[0].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_11 = mux(r_uop_bypass_sel_dst_1_2, ren2_uops[1].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_12 = mux(r_uop_bypass_sel_dst_2_2, ren2_uops[2].pdst, UInt<1>(0h0))
node _r_uop_bypassed_uop_stale_pdst_T_13 = or(_r_uop_bypassed_uop_stale_pdst_T_10, _r_uop_bypassed_uop_stale_pdst_T_11)
node _r_uop_bypassed_uop_stale_pdst_T_14 = or(_r_uop_bypassed_uop_stale_pdst_T_13, _r_uop_bypassed_uop_stale_pdst_T_12)
wire _r_uop_bypassed_uop_stale_pdst_WIRE_2 : UInt<7>
connect _r_uop_bypassed_uop_stale_pdst_WIRE_2, _r_uop_bypassed_uop_stale_pdst_T_14
connect r_uop_bypassed_uop_2.stale_pdst, _r_uop_bypassed_uop_stale_pdst_WIRE_2
node _r_uop_bypassed_uop_prs1_busy_T_2 = or(next_uop_2.prs1_busy, r_uop_do_bypass_rs1_2)
connect r_uop_bypassed_uop_2.prs1_busy, _r_uop_bypassed_uop_prs1_busy_T_2
node _r_uop_bypassed_uop_prs2_busy_T_2 = or(next_uop_2.prs2_busy, r_uop_do_bypass_rs2_2)
connect r_uop_bypassed_uop_2.prs2_busy, _r_uop_bypassed_uop_prs2_busy_T_2
node _r_uop_bypassed_uop_prs3_busy_T_2 = or(next_uop_2.prs3_busy, r_uop_do_bypass_rs3_2)
connect r_uop_bypassed_uop_2.prs3_busy, _r_uop_bypassed_uop_prs3_busy_T_2
invalidate r_uop_bypassed_uop_2.prs3
connect r_uop_bypassed_uop_2.prs3_busy, UInt<1>(0h0)
wire r_uop_newuop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_newuop_2, r_uop_bypassed_uop_2
node _r_uop_newuop_br_mask_T_4 = not(io.brupdate.b1.resolve_mask)
node _r_uop_newuop_br_mask_T_5 = and(r_uop_bypassed_uop_2.br_mask, _r_uop_newuop_br_mask_T_4)
connect r_uop_newuop_2.br_mask, _r_uop_newuop_br_mask_T_5
connect r_uop_2, r_uop_newuop_2
connect ren2_valids[2], r_valid_2
connect ren2_uops[2], r_uop_2
connect io.ren2_mask, ren2_valids
inst maptable of RenameMapTable
connect maptable.clock, clock
connect maptable.reset, reset
inst freelist of RenameFreeList
connect freelist.clock, clock
connect freelist.reset, reset
inst busytable of RenameBusyTable
connect busytable.clock, clock
connect busytable.reset, reset
wire ren2_br_tags : { valid : UInt<1>, bits : UInt<4>}[3]
wire com_valids : UInt<1>[3]
wire rbk_valids : UInt<1>[3]
node _ren2_alloc_reqs_0_T = eq(ren2_uops[0].dst_rtype, UInt<2>(0h0))
node _ren2_alloc_reqs_0_T_1 = and(ren2_uops[0].ldst_val, _ren2_alloc_reqs_0_T)
node _ren2_alloc_reqs_0_T_2 = and(_ren2_alloc_reqs_0_T_1, io.dis_fire[0])
connect ren2_alloc_reqs[0], _ren2_alloc_reqs_0_T_2
node _ren2_br_tags_0_valid_T = eq(ren2_uops[0].is_sfb, UInt<1>(0h0))
node _ren2_br_tags_0_valid_T_1 = and(ren2_uops[0].is_br, _ren2_br_tags_0_valid_T)
node _ren2_br_tags_0_valid_T_2 = or(_ren2_br_tags_0_valid_T_1, ren2_uops[0].is_jalr)
node _ren2_br_tags_0_valid_T_3 = and(io.dis_fire[0], _ren2_br_tags_0_valid_T_2)
connect ren2_br_tags[0].valid, _ren2_br_tags_0_valid_T_3
node _com_valids_0_T = eq(io.com_uops[0].dst_rtype, UInt<2>(0h0))
node _com_valids_0_T_1 = and(io.com_uops[0].ldst_val, _com_valids_0_T)
node _com_valids_0_T_2 = and(_com_valids_0_T_1, io.com_valids[0])
connect com_valids[0], _com_valids_0_T_2
node _rbk_valids_0_T = eq(io.com_uops[0].dst_rtype, UInt<2>(0h0))
node _rbk_valids_0_T_1 = and(io.com_uops[0].ldst_val, _rbk_valids_0_T)
node _rbk_valids_0_T_2 = and(_rbk_valids_0_T_1, io.rbk_valids[0])
connect rbk_valids[0], _rbk_valids_0_T_2
connect ren2_br_tags[0].bits, ren2_uops[0].br_tag
node _ren2_alloc_reqs_1_T = eq(ren2_uops[1].dst_rtype, UInt<2>(0h0))
node _ren2_alloc_reqs_1_T_1 = and(ren2_uops[1].ldst_val, _ren2_alloc_reqs_1_T)
node _ren2_alloc_reqs_1_T_2 = and(_ren2_alloc_reqs_1_T_1, io.dis_fire[1])
connect ren2_alloc_reqs[1], _ren2_alloc_reqs_1_T_2
node _ren2_br_tags_1_valid_T = eq(ren2_uops[1].is_sfb, UInt<1>(0h0))
node _ren2_br_tags_1_valid_T_1 = and(ren2_uops[1].is_br, _ren2_br_tags_1_valid_T)
node _ren2_br_tags_1_valid_T_2 = or(_ren2_br_tags_1_valid_T_1, ren2_uops[1].is_jalr)
node _ren2_br_tags_1_valid_T_3 = and(io.dis_fire[1], _ren2_br_tags_1_valid_T_2)
connect ren2_br_tags[1].valid, _ren2_br_tags_1_valid_T_3
node _com_valids_1_T = eq(io.com_uops[1].dst_rtype, UInt<2>(0h0))
node _com_valids_1_T_1 = and(io.com_uops[1].ldst_val, _com_valids_1_T)
node _com_valids_1_T_2 = and(_com_valids_1_T_1, io.com_valids[1])
connect com_valids[1], _com_valids_1_T_2
node _rbk_valids_1_T = eq(io.com_uops[1].dst_rtype, UInt<2>(0h0))
node _rbk_valids_1_T_1 = and(io.com_uops[1].ldst_val, _rbk_valids_1_T)
node _rbk_valids_1_T_2 = and(_rbk_valids_1_T_1, io.rbk_valids[1])
connect rbk_valids[1], _rbk_valids_1_T_2
connect ren2_br_tags[1].bits, ren2_uops[1].br_tag
node _ren2_alloc_reqs_2_T = eq(ren2_uops[2].dst_rtype, UInt<2>(0h0))
node _ren2_alloc_reqs_2_T_1 = and(ren2_uops[2].ldst_val, _ren2_alloc_reqs_2_T)
node _ren2_alloc_reqs_2_T_2 = and(_ren2_alloc_reqs_2_T_1, io.dis_fire[2])
connect ren2_alloc_reqs[2], _ren2_alloc_reqs_2_T_2
node _ren2_br_tags_2_valid_T = eq(ren2_uops[2].is_sfb, UInt<1>(0h0))
node _ren2_br_tags_2_valid_T_1 = and(ren2_uops[2].is_br, _ren2_br_tags_2_valid_T)
node _ren2_br_tags_2_valid_T_2 = or(_ren2_br_tags_2_valid_T_1, ren2_uops[2].is_jalr)
node _ren2_br_tags_2_valid_T_3 = and(io.dis_fire[2], _ren2_br_tags_2_valid_T_2)
connect ren2_br_tags[2].valid, _ren2_br_tags_2_valid_T_3
node _com_valids_2_T = eq(io.com_uops[2].dst_rtype, UInt<2>(0h0))
node _com_valids_2_T_1 = and(io.com_uops[2].ldst_val, _com_valids_2_T)
node _com_valids_2_T_2 = and(_com_valids_2_T_1, io.com_valids[2])
connect com_valids[2], _com_valids_2_T_2
node _rbk_valids_2_T = eq(io.com_uops[2].dst_rtype, UInt<2>(0h0))
node _rbk_valids_2_T_1 = and(io.com_uops[2].ldst_val, _rbk_valids_2_T)
node _rbk_valids_2_T_2 = and(_rbk_valids_2_T_1, io.rbk_valids[2])
connect rbk_valids[2], _rbk_valids_2_T_2
connect ren2_br_tags[2].bits, ren2_uops[2].br_tag
wire map_reqs : { lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst : UInt<6>}[3]
wire remap_reqs : { ldst : UInt<6>, pdst : UInt<7>, valid : UInt<1>}[3]
connect map_reqs[0].lrs1, ren1_uops[0].lrs1
connect map_reqs[0].lrs2, ren1_uops[0].lrs2
connect map_reqs[0].lrs3, ren1_uops[0].lrs3
connect map_reqs[0].ldst, ren1_uops[0].ldst
node _remap_reqs_0_ldst_T = mux(io.rollback, io.com_uops[2].ldst, ren2_uops[0].ldst)
connect remap_reqs[0].ldst, _remap_reqs_0_ldst_T
node _remap_reqs_0_pdst_T = mux(io.rollback, io.com_uops[2].stale_pdst, ren2_uops[0].pdst)
connect remap_reqs[0].pdst, _remap_reqs_0_pdst_T
connect map_reqs[1].lrs1, ren1_uops[1].lrs1
connect map_reqs[1].lrs2, ren1_uops[1].lrs2
connect map_reqs[1].lrs3, ren1_uops[1].lrs3
connect map_reqs[1].ldst, ren1_uops[1].ldst
node _remap_reqs_1_ldst_T = mux(io.rollback, io.com_uops[1].ldst, ren2_uops[1].ldst)
connect remap_reqs[1].ldst, _remap_reqs_1_ldst_T
node _remap_reqs_1_pdst_T = mux(io.rollback, io.com_uops[1].stale_pdst, ren2_uops[1].pdst)
connect remap_reqs[1].pdst, _remap_reqs_1_pdst_T
connect map_reqs[2].lrs1, ren1_uops[2].lrs1
connect map_reqs[2].lrs2, ren1_uops[2].lrs2
connect map_reqs[2].lrs3, ren1_uops[2].lrs3
connect map_reqs[2].ldst, ren1_uops[2].ldst
node _remap_reqs_2_ldst_T = mux(io.rollback, io.com_uops[0].ldst, ren2_uops[2].ldst)
connect remap_reqs[2].ldst, _remap_reqs_2_ldst_T
node _remap_reqs_2_pdst_T = mux(io.rollback, io.com_uops[0].stale_pdst, ren2_uops[2].pdst)
connect remap_reqs[2].pdst, _remap_reqs_2_pdst_T
node _remap_reqs_0_valid_T = or(ren2_alloc_reqs[0], rbk_valids[2])
connect remap_reqs[0].valid, _remap_reqs_0_valid_T
node _remap_reqs_1_valid_T = or(ren2_alloc_reqs[1], rbk_valids[1])
connect remap_reqs[1].valid, _remap_reqs_1_valid_T
node _remap_reqs_2_valid_T = or(ren2_alloc_reqs[2], rbk_valids[0])
connect remap_reqs[2].valid, _remap_reqs_2_valid_T
connect maptable.io.map_reqs[0].ldst, map_reqs[0].ldst
connect maptable.io.map_reqs[0].lrs3, map_reqs[0].lrs3
connect maptable.io.map_reqs[0].lrs2, map_reqs[0].lrs2
connect maptable.io.map_reqs[0].lrs1, map_reqs[0].lrs1
connect maptable.io.map_reqs[1].ldst, map_reqs[1].ldst
connect maptable.io.map_reqs[1].lrs3, map_reqs[1].lrs3
connect maptable.io.map_reqs[1].lrs2, map_reqs[1].lrs2
connect maptable.io.map_reqs[1].lrs1, map_reqs[1].lrs1
connect maptable.io.map_reqs[2].ldst, map_reqs[2].ldst
connect maptable.io.map_reqs[2].lrs3, map_reqs[2].lrs3
connect maptable.io.map_reqs[2].lrs2, map_reqs[2].lrs2
connect maptable.io.map_reqs[2].lrs1, map_reqs[2].lrs1
connect maptable.io.remap_reqs[0].valid, remap_reqs[0].valid
connect maptable.io.remap_reqs[0].pdst, remap_reqs[0].pdst
connect maptable.io.remap_reqs[0].ldst, remap_reqs[0].ldst
connect maptable.io.remap_reqs[1].valid, remap_reqs[1].valid
connect maptable.io.remap_reqs[1].pdst, remap_reqs[1].pdst
connect maptable.io.remap_reqs[1].ldst, remap_reqs[1].ldst
connect maptable.io.remap_reqs[2].valid, remap_reqs[2].valid
connect maptable.io.remap_reqs[2].pdst, remap_reqs[2].pdst
connect maptable.io.remap_reqs[2].ldst, remap_reqs[2].ldst
connect maptable.io.ren_br_tags[0].bits, ren2_br_tags[0].bits
connect maptable.io.ren_br_tags[0].valid, ren2_br_tags[0].valid
connect maptable.io.ren_br_tags[1].bits, ren2_br_tags[1].bits
connect maptable.io.ren_br_tags[1].valid, ren2_br_tags[1].valid
connect maptable.io.ren_br_tags[2].bits, ren2_br_tags[2].bits
connect maptable.io.ren_br_tags[2].valid, ren2_br_tags[2].valid
connect maptable.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect maptable.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect maptable.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect maptable.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect maptable.io.brupdate.b2.taken, io.brupdate.b2.taken
connect maptable.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect maptable.io.brupdate.b2.valid, io.brupdate.b2.valid
connect maptable.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect maptable.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect maptable.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect maptable.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect maptable.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect maptable.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect maptable.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect maptable.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect maptable.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect maptable.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect maptable.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect maptable.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect maptable.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect maptable.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect maptable.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect maptable.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect maptable.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect maptable.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect maptable.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect maptable.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect maptable.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect maptable.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect maptable.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect maptable.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect maptable.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect maptable.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect maptable.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect maptable.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect maptable.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect maptable.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect maptable.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect maptable.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect maptable.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect maptable.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect maptable.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect maptable.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect maptable.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect maptable.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect maptable.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect maptable.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect maptable.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect maptable.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect maptable.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect maptable.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect maptable.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect maptable.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect maptable.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect maptable.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect maptable.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect maptable.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect maptable.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect maptable.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect maptable.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect maptable.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect maptable.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect maptable.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect maptable.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect maptable.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect maptable.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect maptable.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect maptable.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect maptable.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect maptable.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect maptable.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect maptable.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect maptable.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect maptable.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect maptable.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect maptable.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect maptable.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect maptable.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect maptable.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect maptable.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect maptable.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect maptable.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect maptable.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect maptable.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect maptable.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect maptable.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect maptable.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect maptable.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect maptable.io.rollback, io.rollback
connect ren1_uops[0].prs1, maptable.io.map_resps[0].prs1
connect ren1_uops[0].prs2, maptable.io.map_resps[0].prs2
connect ren1_uops[0].prs3, maptable.io.map_resps[0].prs3
connect ren1_uops[0].stale_pdst, maptable.io.map_resps[0].stale_pdst
connect ren1_uops[1].prs1, maptable.io.map_resps[1].prs1
connect ren1_uops[1].prs2, maptable.io.map_resps[1].prs2
connect ren1_uops[1].prs3, maptable.io.map_resps[1].prs3
connect ren1_uops[1].stale_pdst, maptable.io.map_resps[1].stale_pdst
connect ren1_uops[2].prs1, maptable.io.map_resps[2].prs1
connect ren1_uops[2].prs2, maptable.io.map_resps[2].prs2
connect ren1_uops[2].prs3, maptable.io.map_resps[2].prs3
connect ren1_uops[2].stale_pdst, maptable.io.map_resps[2].stale_pdst
connect freelist.io.reqs[0], ren2_alloc_reqs[0]
connect freelist.io.reqs[1], ren2_alloc_reqs[1]
connect freelist.io.reqs[2], ren2_alloc_reqs[2]
node _freelist_io_dealloc_pregs_0_valid_T = or(com_valids[0], rbk_valids[0])
connect freelist.io.dealloc_pregs[0].valid, _freelist_io_dealloc_pregs_0_valid_T
node _freelist_io_dealloc_pregs_1_valid_T = or(com_valids[1], rbk_valids[1])
connect freelist.io.dealloc_pregs[1].valid, _freelist_io_dealloc_pregs_1_valid_T
node _freelist_io_dealloc_pregs_2_valid_T = or(com_valids[2], rbk_valids[2])
connect freelist.io.dealloc_pregs[2].valid, _freelist_io_dealloc_pregs_2_valid_T
node _freelist_io_dealloc_pregs_0_bits_T = mux(io.rollback, io.com_uops[0].pdst, io.com_uops[0].stale_pdst)
connect freelist.io.dealloc_pregs[0].bits, _freelist_io_dealloc_pregs_0_bits_T
node _freelist_io_dealloc_pregs_1_bits_T = mux(io.rollback, io.com_uops[1].pdst, io.com_uops[1].stale_pdst)
connect freelist.io.dealloc_pregs[1].bits, _freelist_io_dealloc_pregs_1_bits_T
node _freelist_io_dealloc_pregs_2_bits_T = mux(io.rollback, io.com_uops[2].pdst, io.com_uops[2].stale_pdst)
connect freelist.io.dealloc_pregs[2].bits, _freelist_io_dealloc_pregs_2_bits_T
connect freelist.io.ren_br_tags[0].bits, ren2_br_tags[0].bits
connect freelist.io.ren_br_tags[0].valid, ren2_br_tags[0].valid
connect freelist.io.ren_br_tags[1].bits, ren2_br_tags[1].bits
connect freelist.io.ren_br_tags[1].valid, ren2_br_tags[1].valid
connect freelist.io.ren_br_tags[2].bits, ren2_br_tags[2].bits
connect freelist.io.ren_br_tags[2].valid, ren2_br_tags[2].valid
connect freelist.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect freelist.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect freelist.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect freelist.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect freelist.io.brupdate.b2.taken, io.brupdate.b2.taken
connect freelist.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect freelist.io.brupdate.b2.valid, io.brupdate.b2.valid
connect freelist.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect freelist.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect freelist.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect freelist.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect freelist.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect freelist.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect freelist.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect freelist.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect freelist.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect freelist.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect freelist.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect freelist.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect freelist.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect freelist.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect freelist.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect freelist.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect freelist.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect freelist.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect freelist.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect freelist.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect freelist.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect freelist.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect freelist.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect freelist.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect freelist.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect freelist.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect freelist.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect freelist.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect freelist.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect freelist.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect freelist.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect freelist.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect freelist.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect freelist.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect freelist.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect freelist.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect freelist.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect freelist.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect freelist.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect freelist.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect freelist.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect freelist.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect freelist.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect freelist.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect freelist.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect freelist.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect freelist.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect freelist.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect freelist.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect freelist.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect freelist.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect freelist.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect freelist.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect freelist.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect freelist.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect freelist.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect freelist.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect freelist.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect freelist.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect freelist.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect freelist.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect freelist.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect freelist.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect freelist.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect freelist.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect freelist.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect freelist.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect freelist.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect freelist.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect freelist.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect freelist.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect freelist.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect freelist.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect freelist.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect freelist.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect freelist.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect freelist.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect freelist.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect freelist.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect freelist.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect freelist.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect freelist.io.debug.pipeline_empty, io.debug_rob_empty
node _T = eq(ren2_alloc_reqs[0], UInt<1>(0h0))
node _T_1 = neq(freelist.io.alloc_pregs[0].bits, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(ren2_alloc_reqs[1], UInt<1>(0h0))
node _T_4 = neq(freelist.io.alloc_pregs[1].bits, UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(ren2_alloc_reqs[2], UInt<1>(0h0))
node _T_7 = neq(freelist.io.alloc_pregs[2].bits, UInt<1>(0h0))
node _T_8 = or(_T_6, _T_7)
node _T_9 = and(_T_2, _T_5)
node _T_10 = and(_T_9, _T_8)
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
node _T_13 = eq(_T_10, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename-stage] A uop is trying to allocate the zero physical register.\n at rename-stage.scala:300 assert (ren2_alloc_reqs zip freelist.io.alloc_pregs map {case (r,p) => !r || p.bits =/= 0.U} reduce (_&&_),\n") : printf
assert(clock, _T_10, UInt<1>(0h1), "") : assert
node _ren2_uops_0_pdst_T = neq(ren2_uops[0].ldst, UInt<1>(0h0))
node _ren2_uops_0_pdst_T_1 = or(_ren2_uops_0_pdst_T, UInt<1>(0h0))
node _ren2_uops_0_pdst_T_2 = mux(_ren2_uops_0_pdst_T_1, freelist.io.alloc_pregs[0].bits, UInt<1>(0h0))
connect ren2_uops[0].pdst, _ren2_uops_0_pdst_T_2
node _ren2_uops_1_pdst_T = neq(ren2_uops[1].ldst, UInt<1>(0h0))
node _ren2_uops_1_pdst_T_1 = or(_ren2_uops_1_pdst_T, UInt<1>(0h0))
node _ren2_uops_1_pdst_T_2 = mux(_ren2_uops_1_pdst_T_1, freelist.io.alloc_pregs[1].bits, UInt<1>(0h0))
connect ren2_uops[1].pdst, _ren2_uops_1_pdst_T_2
node _ren2_uops_2_pdst_T = neq(ren2_uops[2].ldst, UInt<1>(0h0))
node _ren2_uops_2_pdst_T_1 = or(_ren2_uops_2_pdst_T, UInt<1>(0h0))
node _ren2_uops_2_pdst_T_2 = mux(_ren2_uops_2_pdst_T_1, freelist.io.alloc_pregs[2].bits, UInt<1>(0h0))
connect ren2_uops[2].pdst, _ren2_uops_2_pdst_T_2
connect busytable.io.ren_uops[0].debug_tsrc, ren2_uops[0].debug_tsrc
connect busytable.io.ren_uops[0].debug_fsrc, ren2_uops[0].debug_fsrc
connect busytable.io.ren_uops[0].bp_xcpt_if, ren2_uops[0].bp_xcpt_if
connect busytable.io.ren_uops[0].bp_debug_if, ren2_uops[0].bp_debug_if
connect busytable.io.ren_uops[0].xcpt_ma_if, ren2_uops[0].xcpt_ma_if
connect busytable.io.ren_uops[0].xcpt_ae_if, ren2_uops[0].xcpt_ae_if
connect busytable.io.ren_uops[0].xcpt_pf_if, ren2_uops[0].xcpt_pf_if
connect busytable.io.ren_uops[0].fp_single, ren2_uops[0].fp_single
connect busytable.io.ren_uops[0].fp_val, ren2_uops[0].fp_val
connect busytable.io.ren_uops[0].frs3_en, ren2_uops[0].frs3_en
connect busytable.io.ren_uops[0].lrs2_rtype, ren2_uops[0].lrs2_rtype
connect busytable.io.ren_uops[0].lrs1_rtype, ren2_uops[0].lrs1_rtype
connect busytable.io.ren_uops[0].dst_rtype, ren2_uops[0].dst_rtype
connect busytable.io.ren_uops[0].ldst_val, ren2_uops[0].ldst_val
connect busytable.io.ren_uops[0].lrs3, ren2_uops[0].lrs3
connect busytable.io.ren_uops[0].lrs2, ren2_uops[0].lrs2
connect busytable.io.ren_uops[0].lrs1, ren2_uops[0].lrs1
connect busytable.io.ren_uops[0].ldst, ren2_uops[0].ldst
connect busytable.io.ren_uops[0].ldst_is_rs1, ren2_uops[0].ldst_is_rs1
connect busytable.io.ren_uops[0].flush_on_commit, ren2_uops[0].flush_on_commit
connect busytable.io.ren_uops[0].is_unique, ren2_uops[0].is_unique
connect busytable.io.ren_uops[0].is_sys_pc2epc, ren2_uops[0].is_sys_pc2epc
connect busytable.io.ren_uops[0].uses_stq, ren2_uops[0].uses_stq
connect busytable.io.ren_uops[0].uses_ldq, ren2_uops[0].uses_ldq
connect busytable.io.ren_uops[0].is_amo, ren2_uops[0].is_amo
connect busytable.io.ren_uops[0].is_fencei, ren2_uops[0].is_fencei
connect busytable.io.ren_uops[0].is_fence, ren2_uops[0].is_fence
connect busytable.io.ren_uops[0].mem_signed, ren2_uops[0].mem_signed
connect busytable.io.ren_uops[0].mem_size, ren2_uops[0].mem_size
connect busytable.io.ren_uops[0].mem_cmd, ren2_uops[0].mem_cmd
connect busytable.io.ren_uops[0].bypassable, ren2_uops[0].bypassable
connect busytable.io.ren_uops[0].exc_cause, ren2_uops[0].exc_cause
connect busytable.io.ren_uops[0].exception, ren2_uops[0].exception
connect busytable.io.ren_uops[0].stale_pdst, ren2_uops[0].stale_pdst
connect busytable.io.ren_uops[0].ppred_busy, ren2_uops[0].ppred_busy
connect busytable.io.ren_uops[0].prs3_busy, ren2_uops[0].prs3_busy
connect busytable.io.ren_uops[0].prs2_busy, ren2_uops[0].prs2_busy
connect busytable.io.ren_uops[0].prs1_busy, ren2_uops[0].prs1_busy
connect busytable.io.ren_uops[0].ppred, ren2_uops[0].ppred
connect busytable.io.ren_uops[0].prs3, ren2_uops[0].prs3
connect busytable.io.ren_uops[0].prs2, ren2_uops[0].prs2
connect busytable.io.ren_uops[0].prs1, ren2_uops[0].prs1
connect busytable.io.ren_uops[0].pdst, ren2_uops[0].pdst
connect busytable.io.ren_uops[0].rxq_idx, ren2_uops[0].rxq_idx
connect busytable.io.ren_uops[0].stq_idx, ren2_uops[0].stq_idx
connect busytable.io.ren_uops[0].ldq_idx, ren2_uops[0].ldq_idx
connect busytable.io.ren_uops[0].rob_idx, ren2_uops[0].rob_idx
connect busytable.io.ren_uops[0].csr_addr, ren2_uops[0].csr_addr
connect busytable.io.ren_uops[0].imm_packed, ren2_uops[0].imm_packed
connect busytable.io.ren_uops[0].taken, ren2_uops[0].taken
connect busytable.io.ren_uops[0].pc_lob, ren2_uops[0].pc_lob
connect busytable.io.ren_uops[0].edge_inst, ren2_uops[0].edge_inst
connect busytable.io.ren_uops[0].ftq_idx, ren2_uops[0].ftq_idx
connect busytable.io.ren_uops[0].br_tag, ren2_uops[0].br_tag
connect busytable.io.ren_uops[0].br_mask, ren2_uops[0].br_mask
connect busytable.io.ren_uops[0].is_sfb, ren2_uops[0].is_sfb
connect busytable.io.ren_uops[0].is_jal, ren2_uops[0].is_jal
connect busytable.io.ren_uops[0].is_jalr, ren2_uops[0].is_jalr
connect busytable.io.ren_uops[0].is_br, ren2_uops[0].is_br
connect busytable.io.ren_uops[0].iw_p2_poisoned, ren2_uops[0].iw_p2_poisoned
connect busytable.io.ren_uops[0].iw_p1_poisoned, ren2_uops[0].iw_p1_poisoned
connect busytable.io.ren_uops[0].iw_state, ren2_uops[0].iw_state
connect busytable.io.ren_uops[0].ctrl.is_std, ren2_uops[0].ctrl.is_std
connect busytable.io.ren_uops[0].ctrl.is_sta, ren2_uops[0].ctrl.is_sta
connect busytable.io.ren_uops[0].ctrl.is_load, ren2_uops[0].ctrl.is_load
connect busytable.io.ren_uops[0].ctrl.csr_cmd, ren2_uops[0].ctrl.csr_cmd
connect busytable.io.ren_uops[0].ctrl.fcn_dw, ren2_uops[0].ctrl.fcn_dw
connect busytable.io.ren_uops[0].ctrl.op_fcn, ren2_uops[0].ctrl.op_fcn
connect busytable.io.ren_uops[0].ctrl.imm_sel, ren2_uops[0].ctrl.imm_sel
connect busytable.io.ren_uops[0].ctrl.op2_sel, ren2_uops[0].ctrl.op2_sel
connect busytable.io.ren_uops[0].ctrl.op1_sel, ren2_uops[0].ctrl.op1_sel
connect busytable.io.ren_uops[0].ctrl.br_type, ren2_uops[0].ctrl.br_type
connect busytable.io.ren_uops[0].fu_code, ren2_uops[0].fu_code
connect busytable.io.ren_uops[0].iq_type, ren2_uops[0].iq_type
connect busytable.io.ren_uops[0].debug_pc, ren2_uops[0].debug_pc
connect busytable.io.ren_uops[0].is_rvc, ren2_uops[0].is_rvc
connect busytable.io.ren_uops[0].debug_inst, ren2_uops[0].debug_inst
connect busytable.io.ren_uops[0].inst, ren2_uops[0].inst
connect busytable.io.ren_uops[0].uopc, ren2_uops[0].uopc
connect busytable.io.ren_uops[1].debug_tsrc, ren2_uops[1].debug_tsrc
connect busytable.io.ren_uops[1].debug_fsrc, ren2_uops[1].debug_fsrc
connect busytable.io.ren_uops[1].bp_xcpt_if, ren2_uops[1].bp_xcpt_if
connect busytable.io.ren_uops[1].bp_debug_if, ren2_uops[1].bp_debug_if
connect busytable.io.ren_uops[1].xcpt_ma_if, ren2_uops[1].xcpt_ma_if
connect busytable.io.ren_uops[1].xcpt_ae_if, ren2_uops[1].xcpt_ae_if
connect busytable.io.ren_uops[1].xcpt_pf_if, ren2_uops[1].xcpt_pf_if
connect busytable.io.ren_uops[1].fp_single, ren2_uops[1].fp_single
connect busytable.io.ren_uops[1].fp_val, ren2_uops[1].fp_val
connect busytable.io.ren_uops[1].frs3_en, ren2_uops[1].frs3_en
connect busytable.io.ren_uops[1].lrs2_rtype, ren2_uops[1].lrs2_rtype
connect busytable.io.ren_uops[1].lrs1_rtype, ren2_uops[1].lrs1_rtype
connect busytable.io.ren_uops[1].dst_rtype, ren2_uops[1].dst_rtype
connect busytable.io.ren_uops[1].ldst_val, ren2_uops[1].ldst_val
connect busytable.io.ren_uops[1].lrs3, ren2_uops[1].lrs3
connect busytable.io.ren_uops[1].lrs2, ren2_uops[1].lrs2
connect busytable.io.ren_uops[1].lrs1, ren2_uops[1].lrs1
connect busytable.io.ren_uops[1].ldst, ren2_uops[1].ldst
connect busytable.io.ren_uops[1].ldst_is_rs1, ren2_uops[1].ldst_is_rs1
connect busytable.io.ren_uops[1].flush_on_commit, ren2_uops[1].flush_on_commit
connect busytable.io.ren_uops[1].is_unique, ren2_uops[1].is_unique
connect busytable.io.ren_uops[1].is_sys_pc2epc, ren2_uops[1].is_sys_pc2epc
connect busytable.io.ren_uops[1].uses_stq, ren2_uops[1].uses_stq
connect busytable.io.ren_uops[1].uses_ldq, ren2_uops[1].uses_ldq
connect busytable.io.ren_uops[1].is_amo, ren2_uops[1].is_amo
connect busytable.io.ren_uops[1].is_fencei, ren2_uops[1].is_fencei
connect busytable.io.ren_uops[1].is_fence, ren2_uops[1].is_fence
connect busytable.io.ren_uops[1].mem_signed, ren2_uops[1].mem_signed
connect busytable.io.ren_uops[1].mem_size, ren2_uops[1].mem_size
connect busytable.io.ren_uops[1].mem_cmd, ren2_uops[1].mem_cmd
connect busytable.io.ren_uops[1].bypassable, ren2_uops[1].bypassable
connect busytable.io.ren_uops[1].exc_cause, ren2_uops[1].exc_cause
connect busytable.io.ren_uops[1].exception, ren2_uops[1].exception
connect busytable.io.ren_uops[1].stale_pdst, ren2_uops[1].stale_pdst
connect busytable.io.ren_uops[1].ppred_busy, ren2_uops[1].ppred_busy
connect busytable.io.ren_uops[1].prs3_busy, ren2_uops[1].prs3_busy
connect busytable.io.ren_uops[1].prs2_busy, ren2_uops[1].prs2_busy
connect busytable.io.ren_uops[1].prs1_busy, ren2_uops[1].prs1_busy
connect busytable.io.ren_uops[1].ppred, ren2_uops[1].ppred
connect busytable.io.ren_uops[1].prs3, ren2_uops[1].prs3
connect busytable.io.ren_uops[1].prs2, ren2_uops[1].prs2
connect busytable.io.ren_uops[1].prs1, ren2_uops[1].prs1
connect busytable.io.ren_uops[1].pdst, ren2_uops[1].pdst
connect busytable.io.ren_uops[1].rxq_idx, ren2_uops[1].rxq_idx
connect busytable.io.ren_uops[1].stq_idx, ren2_uops[1].stq_idx
connect busytable.io.ren_uops[1].ldq_idx, ren2_uops[1].ldq_idx
connect busytable.io.ren_uops[1].rob_idx, ren2_uops[1].rob_idx
connect busytable.io.ren_uops[1].csr_addr, ren2_uops[1].csr_addr
connect busytable.io.ren_uops[1].imm_packed, ren2_uops[1].imm_packed
connect busytable.io.ren_uops[1].taken, ren2_uops[1].taken
connect busytable.io.ren_uops[1].pc_lob, ren2_uops[1].pc_lob
connect busytable.io.ren_uops[1].edge_inst, ren2_uops[1].edge_inst
connect busytable.io.ren_uops[1].ftq_idx, ren2_uops[1].ftq_idx
connect busytable.io.ren_uops[1].br_tag, ren2_uops[1].br_tag
connect busytable.io.ren_uops[1].br_mask, ren2_uops[1].br_mask
connect busytable.io.ren_uops[1].is_sfb, ren2_uops[1].is_sfb
connect busytable.io.ren_uops[1].is_jal, ren2_uops[1].is_jal
connect busytable.io.ren_uops[1].is_jalr, ren2_uops[1].is_jalr
connect busytable.io.ren_uops[1].is_br, ren2_uops[1].is_br
connect busytable.io.ren_uops[1].iw_p2_poisoned, ren2_uops[1].iw_p2_poisoned
connect busytable.io.ren_uops[1].iw_p1_poisoned, ren2_uops[1].iw_p1_poisoned
connect busytable.io.ren_uops[1].iw_state, ren2_uops[1].iw_state
connect busytable.io.ren_uops[1].ctrl.is_std, ren2_uops[1].ctrl.is_std
connect busytable.io.ren_uops[1].ctrl.is_sta, ren2_uops[1].ctrl.is_sta
connect busytable.io.ren_uops[1].ctrl.is_load, ren2_uops[1].ctrl.is_load
connect busytable.io.ren_uops[1].ctrl.csr_cmd, ren2_uops[1].ctrl.csr_cmd
connect busytable.io.ren_uops[1].ctrl.fcn_dw, ren2_uops[1].ctrl.fcn_dw
connect busytable.io.ren_uops[1].ctrl.op_fcn, ren2_uops[1].ctrl.op_fcn
connect busytable.io.ren_uops[1].ctrl.imm_sel, ren2_uops[1].ctrl.imm_sel
connect busytable.io.ren_uops[1].ctrl.op2_sel, ren2_uops[1].ctrl.op2_sel
connect busytable.io.ren_uops[1].ctrl.op1_sel, ren2_uops[1].ctrl.op1_sel
connect busytable.io.ren_uops[1].ctrl.br_type, ren2_uops[1].ctrl.br_type
connect busytable.io.ren_uops[1].fu_code, ren2_uops[1].fu_code
connect busytable.io.ren_uops[1].iq_type, ren2_uops[1].iq_type
connect busytable.io.ren_uops[1].debug_pc, ren2_uops[1].debug_pc
connect busytable.io.ren_uops[1].is_rvc, ren2_uops[1].is_rvc
connect busytable.io.ren_uops[1].debug_inst, ren2_uops[1].debug_inst
connect busytable.io.ren_uops[1].inst, ren2_uops[1].inst
connect busytable.io.ren_uops[1].uopc, ren2_uops[1].uopc
connect busytable.io.ren_uops[2].debug_tsrc, ren2_uops[2].debug_tsrc
connect busytable.io.ren_uops[2].debug_fsrc, ren2_uops[2].debug_fsrc
connect busytable.io.ren_uops[2].bp_xcpt_if, ren2_uops[2].bp_xcpt_if
connect busytable.io.ren_uops[2].bp_debug_if, ren2_uops[2].bp_debug_if
connect busytable.io.ren_uops[2].xcpt_ma_if, ren2_uops[2].xcpt_ma_if
connect busytable.io.ren_uops[2].xcpt_ae_if, ren2_uops[2].xcpt_ae_if
connect busytable.io.ren_uops[2].xcpt_pf_if, ren2_uops[2].xcpt_pf_if
connect busytable.io.ren_uops[2].fp_single, ren2_uops[2].fp_single
connect busytable.io.ren_uops[2].fp_val, ren2_uops[2].fp_val
connect busytable.io.ren_uops[2].frs3_en, ren2_uops[2].frs3_en
connect busytable.io.ren_uops[2].lrs2_rtype, ren2_uops[2].lrs2_rtype
connect busytable.io.ren_uops[2].lrs1_rtype, ren2_uops[2].lrs1_rtype
connect busytable.io.ren_uops[2].dst_rtype, ren2_uops[2].dst_rtype
connect busytable.io.ren_uops[2].ldst_val, ren2_uops[2].ldst_val
connect busytable.io.ren_uops[2].lrs3, ren2_uops[2].lrs3
connect busytable.io.ren_uops[2].lrs2, ren2_uops[2].lrs2
connect busytable.io.ren_uops[2].lrs1, ren2_uops[2].lrs1
connect busytable.io.ren_uops[2].ldst, ren2_uops[2].ldst
connect busytable.io.ren_uops[2].ldst_is_rs1, ren2_uops[2].ldst_is_rs1
connect busytable.io.ren_uops[2].flush_on_commit, ren2_uops[2].flush_on_commit
connect busytable.io.ren_uops[2].is_unique, ren2_uops[2].is_unique
connect busytable.io.ren_uops[2].is_sys_pc2epc, ren2_uops[2].is_sys_pc2epc
connect busytable.io.ren_uops[2].uses_stq, ren2_uops[2].uses_stq
connect busytable.io.ren_uops[2].uses_ldq, ren2_uops[2].uses_ldq
connect busytable.io.ren_uops[2].is_amo, ren2_uops[2].is_amo
connect busytable.io.ren_uops[2].is_fencei, ren2_uops[2].is_fencei
connect busytable.io.ren_uops[2].is_fence, ren2_uops[2].is_fence
connect busytable.io.ren_uops[2].mem_signed, ren2_uops[2].mem_signed
connect busytable.io.ren_uops[2].mem_size, ren2_uops[2].mem_size
connect busytable.io.ren_uops[2].mem_cmd, ren2_uops[2].mem_cmd
connect busytable.io.ren_uops[2].bypassable, ren2_uops[2].bypassable
connect busytable.io.ren_uops[2].exc_cause, ren2_uops[2].exc_cause
connect busytable.io.ren_uops[2].exception, ren2_uops[2].exception
connect busytable.io.ren_uops[2].stale_pdst, ren2_uops[2].stale_pdst
connect busytable.io.ren_uops[2].ppred_busy, ren2_uops[2].ppred_busy
connect busytable.io.ren_uops[2].prs3_busy, ren2_uops[2].prs3_busy
connect busytable.io.ren_uops[2].prs2_busy, ren2_uops[2].prs2_busy
connect busytable.io.ren_uops[2].prs1_busy, ren2_uops[2].prs1_busy
connect busytable.io.ren_uops[2].ppred, ren2_uops[2].ppred
connect busytable.io.ren_uops[2].prs3, ren2_uops[2].prs3
connect busytable.io.ren_uops[2].prs2, ren2_uops[2].prs2
connect busytable.io.ren_uops[2].prs1, ren2_uops[2].prs1
connect busytable.io.ren_uops[2].pdst, ren2_uops[2].pdst
connect busytable.io.ren_uops[2].rxq_idx, ren2_uops[2].rxq_idx
connect busytable.io.ren_uops[2].stq_idx, ren2_uops[2].stq_idx
connect busytable.io.ren_uops[2].ldq_idx, ren2_uops[2].ldq_idx
connect busytable.io.ren_uops[2].rob_idx, ren2_uops[2].rob_idx
connect busytable.io.ren_uops[2].csr_addr, ren2_uops[2].csr_addr
connect busytable.io.ren_uops[2].imm_packed, ren2_uops[2].imm_packed
connect busytable.io.ren_uops[2].taken, ren2_uops[2].taken
connect busytable.io.ren_uops[2].pc_lob, ren2_uops[2].pc_lob
connect busytable.io.ren_uops[2].edge_inst, ren2_uops[2].edge_inst
connect busytable.io.ren_uops[2].ftq_idx, ren2_uops[2].ftq_idx
connect busytable.io.ren_uops[2].br_tag, ren2_uops[2].br_tag
connect busytable.io.ren_uops[2].br_mask, ren2_uops[2].br_mask
connect busytable.io.ren_uops[2].is_sfb, ren2_uops[2].is_sfb
connect busytable.io.ren_uops[2].is_jal, ren2_uops[2].is_jal
connect busytable.io.ren_uops[2].is_jalr, ren2_uops[2].is_jalr
connect busytable.io.ren_uops[2].is_br, ren2_uops[2].is_br
connect busytable.io.ren_uops[2].iw_p2_poisoned, ren2_uops[2].iw_p2_poisoned
connect busytable.io.ren_uops[2].iw_p1_poisoned, ren2_uops[2].iw_p1_poisoned
connect busytable.io.ren_uops[2].iw_state, ren2_uops[2].iw_state
connect busytable.io.ren_uops[2].ctrl.is_std, ren2_uops[2].ctrl.is_std
connect busytable.io.ren_uops[2].ctrl.is_sta, ren2_uops[2].ctrl.is_sta
connect busytable.io.ren_uops[2].ctrl.is_load, ren2_uops[2].ctrl.is_load
connect busytable.io.ren_uops[2].ctrl.csr_cmd, ren2_uops[2].ctrl.csr_cmd
connect busytable.io.ren_uops[2].ctrl.fcn_dw, ren2_uops[2].ctrl.fcn_dw
connect busytable.io.ren_uops[2].ctrl.op_fcn, ren2_uops[2].ctrl.op_fcn
connect busytable.io.ren_uops[2].ctrl.imm_sel, ren2_uops[2].ctrl.imm_sel
connect busytable.io.ren_uops[2].ctrl.op2_sel, ren2_uops[2].ctrl.op2_sel
connect busytable.io.ren_uops[2].ctrl.op1_sel, ren2_uops[2].ctrl.op1_sel
connect busytable.io.ren_uops[2].ctrl.br_type, ren2_uops[2].ctrl.br_type
connect busytable.io.ren_uops[2].fu_code, ren2_uops[2].fu_code
connect busytable.io.ren_uops[2].iq_type, ren2_uops[2].iq_type
connect busytable.io.ren_uops[2].debug_pc, ren2_uops[2].debug_pc
connect busytable.io.ren_uops[2].is_rvc, ren2_uops[2].is_rvc
connect busytable.io.ren_uops[2].debug_inst, ren2_uops[2].debug_inst
connect busytable.io.ren_uops[2].inst, ren2_uops[2].inst
connect busytable.io.ren_uops[2].uopc, ren2_uops[2].uopc
connect busytable.io.rebusy_reqs[0], ren2_alloc_reqs[0]
connect busytable.io.rebusy_reqs[1], ren2_alloc_reqs[1]
connect busytable.io.rebusy_reqs[2], ren2_alloc_reqs[2]
connect busytable.io.wb_valids[0], io.wakeups[0].valid
connect busytable.io.wb_valids[1], io.wakeups[1].valid
connect busytable.io.wb_valids[2], io.wakeups[2].valid
connect busytable.io.wb_valids[3], io.wakeups[3].valid
connect busytable.io.wb_valids[4], io.wakeups[4].valid
connect busytable.io.wb_valids[5], io.wakeups[5].valid
connect busytable.io.wb_valids[6], io.wakeups[6].valid
connect busytable.io.wb_pdsts[0], io.wakeups[0].bits.uop.pdst
connect busytable.io.wb_pdsts[1], io.wakeups[1].bits.uop.pdst
connect busytable.io.wb_pdsts[2], io.wakeups[2].bits.uop.pdst
connect busytable.io.wb_pdsts[3], io.wakeups[3].bits.uop.pdst
connect busytable.io.wb_pdsts[4], io.wakeups[4].bits.uop.pdst
connect busytable.io.wb_pdsts[5], io.wakeups[5].bits.uop.pdst
connect busytable.io.wb_pdsts[6], io.wakeups[6].bits.uop.pdst
node _T_14 = neq(io.wakeups[0].bits.uop.dst_rtype, UInt<2>(0h0))
node _T_15 = and(io.wakeups[0].valid, _T_14)
node _T_16 = neq(io.wakeups[1].bits.uop.dst_rtype, UInt<2>(0h0))
node _T_17 = and(io.wakeups[1].valid, _T_16)
node _T_18 = neq(io.wakeups[2].bits.uop.dst_rtype, UInt<2>(0h0))
node _T_19 = and(io.wakeups[2].valid, _T_18)
node _T_20 = neq(io.wakeups[3].bits.uop.dst_rtype, UInt<2>(0h0))
node _T_21 = and(io.wakeups[3].valid, _T_20)
node _T_22 = neq(io.wakeups[4].bits.uop.dst_rtype, UInt<2>(0h0))
node _T_23 = and(io.wakeups[4].valid, _T_22)
node _T_24 = neq(io.wakeups[5].bits.uop.dst_rtype, UInt<2>(0h0))
node _T_25 = and(io.wakeups[5].valid, _T_24)
node _T_26 = neq(io.wakeups[6].bits.uop.dst_rtype, UInt<2>(0h0))
node _T_27 = and(io.wakeups[6].valid, _T_26)
node _T_28 = or(_T_15, _T_17)
node _T_29 = or(_T_28, _T_19)
node _T_30 = or(_T_29, _T_21)
node _T_31 = or(_T_30, _T_23)
node _T_32 = or(_T_31, _T_25)
node _T_33 = or(_T_32, _T_27)
node _T_34 = eq(_T_33, UInt<1>(0h0))
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
node _T_37 = eq(_T_34, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] Wakeup has wrong rtype.\n at rename-stage.scala:317 assert (!(io.wakeups.map(x => x.valid && x.bits.uop.dst_rtype =/= rtype).reduce(_||_)),\n") : printf_1
assert(clock, _T_34, UInt<1>(0h1), "") : assert_1
node _ren2_uops_0_prs1_busy_T = eq(ren2_uops[0].lrs1_rtype, UInt<2>(0h0))
node _ren2_uops_0_prs1_busy_T_1 = and(_ren2_uops_0_prs1_busy_T, busytable.io.busy_resps[0].prs1_busy)
connect ren2_uops[0].prs1_busy, _ren2_uops_0_prs1_busy_T_1
node _ren2_uops_0_prs2_busy_T = eq(ren2_uops[0].lrs2_rtype, UInt<2>(0h0))
node _ren2_uops_0_prs2_busy_T_1 = and(_ren2_uops_0_prs2_busy_T, busytable.io.busy_resps[0].prs2_busy)
connect ren2_uops[0].prs2_busy, _ren2_uops_0_prs2_busy_T_1
node _ren2_uops_0_prs3_busy_T = and(ren2_uops[0].frs3_en, busytable.io.busy_resps[0].prs3_busy)
connect ren2_uops[0].prs3_busy, _ren2_uops_0_prs3_busy_T
node _T_38 = and(ren2_valids[0], busytable.io.busy_resps[0].prs1_busy)
node _T_39 = eq(UInt<2>(0h0), UInt<2>(0h0))
node _T_40 = and(_T_38, _T_39)
node _T_41 = eq(ren2_uops[0].lrs1, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = eq(_T_42, UInt<1>(0h0))
node _T_44 = asUInt(reset)
node _T_45 = eq(_T_44, UInt<1>(0h0))
when _T_45 :
node _T_46 = eq(_T_43, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:328 assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n") : printf_2
assert(clock, _T_43, UInt<1>(0h1), "") : assert_2
node _T_47 = and(ren2_valids[0], busytable.io.busy_resps[0].prs2_busy)
node _T_48 = eq(UInt<2>(0h0), UInt<2>(0h0))
node _T_49 = and(_T_47, _T_48)
node _T_50 = eq(ren2_uops[0].lrs2, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
node _T_52 = eq(_T_51, UInt<1>(0h0))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:329 assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n") : printf_3
assert(clock, _T_52, UInt<1>(0h1), "") : assert_3
node _ren2_uops_1_prs1_busy_T = eq(ren2_uops[1].lrs1_rtype, UInt<2>(0h0))
node _ren2_uops_1_prs1_busy_T_1 = and(_ren2_uops_1_prs1_busy_T, busytable.io.busy_resps[1].prs1_busy)
connect ren2_uops[1].prs1_busy, _ren2_uops_1_prs1_busy_T_1
node _ren2_uops_1_prs2_busy_T = eq(ren2_uops[1].lrs2_rtype, UInt<2>(0h0))
node _ren2_uops_1_prs2_busy_T_1 = and(_ren2_uops_1_prs2_busy_T, busytable.io.busy_resps[1].prs2_busy)
connect ren2_uops[1].prs2_busy, _ren2_uops_1_prs2_busy_T_1
node _ren2_uops_1_prs3_busy_T = and(ren2_uops[1].frs3_en, busytable.io.busy_resps[1].prs3_busy)
connect ren2_uops[1].prs3_busy, _ren2_uops_1_prs3_busy_T
node _T_56 = and(ren2_valids[1], busytable.io.busy_resps[1].prs1_busy)
node _T_57 = eq(UInt<2>(0h0), UInt<2>(0h0))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(ren2_uops[1].lrs1, UInt<1>(0h0))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:328 assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n") : printf_4
assert(clock, _T_61, UInt<1>(0h1), "") : assert_4
node _T_65 = and(ren2_valids[1], busytable.io.busy_resps[1].prs2_busy)
node _T_66 = eq(UInt<2>(0h0), UInt<2>(0h0))
node _T_67 = and(_T_65, _T_66)
node _T_68 = eq(ren2_uops[1].lrs2, UInt<1>(0h0))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:329 assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n") : printf_5
assert(clock, _T_70, UInt<1>(0h1), "") : assert_5
node _ren2_uops_2_prs1_busy_T = eq(ren2_uops[2].lrs1_rtype, UInt<2>(0h0))
node _ren2_uops_2_prs1_busy_T_1 = and(_ren2_uops_2_prs1_busy_T, busytable.io.busy_resps[2].prs1_busy)
connect ren2_uops[2].prs1_busy, _ren2_uops_2_prs1_busy_T_1
node _ren2_uops_2_prs2_busy_T = eq(ren2_uops[2].lrs2_rtype, UInt<2>(0h0))
node _ren2_uops_2_prs2_busy_T_1 = and(_ren2_uops_2_prs2_busy_T, busytable.io.busy_resps[2].prs2_busy)
connect ren2_uops[2].prs2_busy, _ren2_uops_2_prs2_busy_T_1
node _ren2_uops_2_prs3_busy_T = and(ren2_uops[2].frs3_en, busytable.io.busy_resps[2].prs3_busy)
connect ren2_uops[2].prs3_busy, _ren2_uops_2_prs3_busy_T
node _T_74 = and(ren2_valids[2], busytable.io.busy_resps[2].prs1_busy)
node _T_75 = eq(UInt<2>(0h0), UInt<2>(0h0))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(ren2_uops[2].lrs1, UInt<1>(0h0))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(_T_78, UInt<1>(0h0))
node _T_80 = asUInt(reset)
node _T_81 = eq(_T_80, UInt<1>(0h0))
when _T_81 :
node _T_82 = eq(_T_79, UInt<1>(0h0))
when _T_82 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:328 assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n") : printf_6
assert(clock, _T_79, UInt<1>(0h1), "") : assert_6
node _T_83 = and(ren2_valids[2], busytable.io.busy_resps[2].prs2_busy)
node _T_84 = eq(UInt<2>(0h0), UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(ren2_uops[2].lrs2, UInt<1>(0h0))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(_T_87, UInt<1>(0h0))
node _T_89 = asUInt(reset)
node _T_90 = eq(_T_89, UInt<1>(0h0))
when _T_90 :
node _T_91 = eq(_T_88, UInt<1>(0h0))
when _T_91 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:329 assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n") : printf_7
assert(clock, _T_88, UInt<1>(0h1), "") : assert_7
node _io_ren_stalls_0_T = eq(ren2_uops[0].dst_rtype, UInt<2>(0h0))
node _io_ren_stalls_0_T_1 = eq(freelist.io.alloc_pregs[0].valid, UInt<1>(0h0))
node _io_ren_stalls_0_T_2 = and(_io_ren_stalls_0_T, _io_ren_stalls_0_T_1)
connect io.ren_stalls[0], _io_ren_stalls_0_T_2
wire bypassed_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect bypassed_uop, ren2_uops[0]
wire io_ren2_uops_0_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect io_ren2_uops_0_newuop, bypassed_uop
node _io_ren2_uops_0_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_ren2_uops_0_newuop_br_mask_T_1 = and(bypassed_uop.br_mask, _io_ren2_uops_0_newuop_br_mask_T)
connect io_ren2_uops_0_newuop.br_mask, _io_ren2_uops_0_newuop_br_mask_T_1
connect io.ren2_uops[0], io_ren2_uops_0_newuop
node _io_ren_stalls_1_T = eq(ren2_uops[1].dst_rtype, UInt<2>(0h0))
node _io_ren_stalls_1_T_1 = eq(freelist.io.alloc_pregs[1].valid, UInt<1>(0h0))
node _io_ren_stalls_1_T_2 = and(_io_ren_stalls_1_T, _io_ren_stalls_1_T_1)
connect io.ren_stalls[1], _io_ren_stalls_1_T_2
wire bypassed_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
wire bypassed_uop_bypassed_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect bypassed_uop_bypassed_uop, ren2_uops[1]
node _bypassed_uop_bypass_hits_rs1_T = eq(ren2_uops[0].ldst, ren2_uops[1].lrs1)
node bypassed_uop_bypass_hits_rs1_0 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs1_T)
node _bypassed_uop_bypass_hits_rs2_T = eq(ren2_uops[0].ldst, ren2_uops[1].lrs2)
node bypassed_uop_bypass_hits_rs2_0 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs2_T)
node _bypassed_uop_bypass_hits_rs3_T = eq(ren2_uops[0].ldst, ren2_uops[1].lrs3)
node bypassed_uop_bypass_hits_rs3_0 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs3_T)
node _bypassed_uop_bypass_hits_dst_T = eq(ren2_uops[0].ldst, ren2_uops[1].ldst)
node bypassed_uop_bypass_hits_dst_0 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_dst_T)
node bypassed_uop_bypass_sel_rs1_enc = mux(bypassed_uop_bypass_hits_rs1_0, UInt<1>(0h1), UInt<1>(0h0))
node bypassed_uop_bypass_sel_rs1_0 = bits(bypassed_uop_bypass_sel_rs1_enc, 0, 0)
node bypassed_uop_bypass_sel_rs2_enc = mux(bypassed_uop_bypass_hits_rs2_0, UInt<1>(0h1), UInt<1>(0h0))
node bypassed_uop_bypass_sel_rs2_0 = bits(bypassed_uop_bypass_sel_rs2_enc, 0, 0)
node bypassed_uop_bypass_sel_rs3_enc = mux(bypassed_uop_bypass_hits_rs3_0, UInt<1>(0h1), UInt<1>(0h0))
node bypassed_uop_bypass_sel_rs3_0 = bits(bypassed_uop_bypass_sel_rs3_enc, 0, 0)
node bypassed_uop_bypass_sel_dst_enc = mux(bypassed_uop_bypass_hits_dst_0, UInt<1>(0h1), UInt<1>(0h0))
node bypassed_uop_bypass_sel_dst_0 = bits(bypassed_uop_bypass_sel_dst_enc, 0, 0)
when bypassed_uop_bypass_hits_rs1_0 :
connect bypassed_uop_bypassed_uop.prs1, ren2_uops[0].pdst
when bypassed_uop_bypass_hits_rs2_0 :
connect bypassed_uop_bypassed_uop.prs2, ren2_uops[0].pdst
when bypassed_uop_bypass_hits_rs3_0 :
connect bypassed_uop_bypassed_uop.prs3, ren2_uops[0].pdst
when bypassed_uop_bypass_hits_dst_0 :
connect bypassed_uop_bypassed_uop.stale_pdst, ren2_uops[0].pdst
node _bypassed_uop_bypassed_uop_prs1_busy_T = or(ren2_uops[1].prs1_busy, bypassed_uop_bypass_hits_rs1_0)
connect bypassed_uop_bypassed_uop.prs1_busy, _bypassed_uop_bypassed_uop_prs1_busy_T
node _bypassed_uop_bypassed_uop_prs2_busy_T = or(ren2_uops[1].prs2_busy, bypassed_uop_bypass_hits_rs2_0)
connect bypassed_uop_bypassed_uop.prs2_busy, _bypassed_uop_bypassed_uop_prs2_busy_T
node _bypassed_uop_bypassed_uop_prs3_busy_T = or(ren2_uops[1].prs3_busy, bypassed_uop_bypass_hits_rs3_0)
connect bypassed_uop_bypassed_uop.prs3_busy, _bypassed_uop_bypassed_uop_prs3_busy_T
invalidate bypassed_uop_bypassed_uop.prs3
connect bypassed_uop_bypassed_uop.prs3_busy, UInt<1>(0h0)
connect bypassed_uop_1, bypassed_uop_bypassed_uop
wire io_ren2_uops_1_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect io_ren2_uops_1_newuop, bypassed_uop_1
node _io_ren2_uops_1_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_ren2_uops_1_newuop_br_mask_T_1 = and(bypassed_uop_1.br_mask, _io_ren2_uops_1_newuop_br_mask_T)
connect io_ren2_uops_1_newuop.br_mask, _io_ren2_uops_1_newuop_br_mask_T_1
connect io.ren2_uops[1], io_ren2_uops_1_newuop
node _io_ren_stalls_2_T = eq(ren2_uops[2].dst_rtype, UInt<2>(0h0))
node _io_ren_stalls_2_T_1 = eq(freelist.io.alloc_pregs[2].valid, UInt<1>(0h0))
node _io_ren_stalls_2_T_2 = and(_io_ren_stalls_2_T, _io_ren_stalls_2_T_1)
connect io.ren_stalls[2], _io_ren_stalls_2_T_2
wire bypassed_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
wire bypassed_uop_bypassed_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect bypassed_uop_bypassed_uop_1, ren2_uops[2]
node _bypassed_uop_bypass_hits_rs1_T_1 = eq(ren2_uops[0].ldst, ren2_uops[2].lrs1)
node bypassed_uop_bypass_hits_rs1_0_1 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs1_T_1)
node _bypassed_uop_bypass_hits_rs1_T_2 = eq(ren2_uops[1].ldst, ren2_uops[2].lrs1)
node bypassed_uop_bypass_hits_rs1_1 = and(ren2_alloc_reqs[1], _bypassed_uop_bypass_hits_rs1_T_2)
node _bypassed_uop_bypass_hits_rs2_T_1 = eq(ren2_uops[0].ldst, ren2_uops[2].lrs2)
node bypassed_uop_bypass_hits_rs2_0_1 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs2_T_1)
node _bypassed_uop_bypass_hits_rs2_T_2 = eq(ren2_uops[1].ldst, ren2_uops[2].lrs2)
node bypassed_uop_bypass_hits_rs2_1 = and(ren2_alloc_reqs[1], _bypassed_uop_bypass_hits_rs2_T_2)
node _bypassed_uop_bypass_hits_rs3_T_1 = eq(ren2_uops[0].ldst, ren2_uops[2].lrs3)
node bypassed_uop_bypass_hits_rs3_0_1 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_rs3_T_1)
node _bypassed_uop_bypass_hits_rs3_T_2 = eq(ren2_uops[1].ldst, ren2_uops[2].lrs3)
node bypassed_uop_bypass_hits_rs3_1 = and(ren2_alloc_reqs[1], _bypassed_uop_bypass_hits_rs3_T_2)
node _bypassed_uop_bypass_hits_dst_T_1 = eq(ren2_uops[0].ldst, ren2_uops[2].ldst)
node bypassed_uop_bypass_hits_dst_0_1 = and(ren2_alloc_reqs[0], _bypassed_uop_bypass_hits_dst_T_1)
node _bypassed_uop_bypass_hits_dst_T_2 = eq(ren2_uops[1].ldst, ren2_uops[2].ldst)
node bypassed_uop_bypass_hits_dst_1 = and(ren2_alloc_reqs[1], _bypassed_uop_bypass_hits_dst_T_2)
node _bypassed_uop_bypass_sel_rs1_enc_T = mux(bypassed_uop_bypass_hits_rs1_0_1, UInt<2>(0h2), UInt<2>(0h0))
node bypassed_uop_bypass_sel_rs1_enc_1 = mux(bypassed_uop_bypass_hits_rs1_1, UInt<2>(0h1), _bypassed_uop_bypass_sel_rs1_enc_T)
node bypassed_uop_bypass_sel_rs1_1 = bits(bypassed_uop_bypass_sel_rs1_enc_1, 0, 0)
node bypassed_uop_bypass_sel_rs1_0_1 = bits(bypassed_uop_bypass_sel_rs1_enc_1, 1, 1)
node _bypassed_uop_bypass_sel_rs2_enc_T = mux(bypassed_uop_bypass_hits_rs2_0_1, UInt<2>(0h2), UInt<2>(0h0))
node bypassed_uop_bypass_sel_rs2_enc_1 = mux(bypassed_uop_bypass_hits_rs2_1, UInt<2>(0h1), _bypassed_uop_bypass_sel_rs2_enc_T)
node bypassed_uop_bypass_sel_rs2_1 = bits(bypassed_uop_bypass_sel_rs2_enc_1, 0, 0)
node bypassed_uop_bypass_sel_rs2_0_1 = bits(bypassed_uop_bypass_sel_rs2_enc_1, 1, 1)
node _bypassed_uop_bypass_sel_rs3_enc_T = mux(bypassed_uop_bypass_hits_rs3_0_1, UInt<2>(0h2), UInt<2>(0h0))
node bypassed_uop_bypass_sel_rs3_enc_1 = mux(bypassed_uop_bypass_hits_rs3_1, UInt<2>(0h1), _bypassed_uop_bypass_sel_rs3_enc_T)
node bypassed_uop_bypass_sel_rs3_1 = bits(bypassed_uop_bypass_sel_rs3_enc_1, 0, 0)
node bypassed_uop_bypass_sel_rs3_0_1 = bits(bypassed_uop_bypass_sel_rs3_enc_1, 1, 1)
node _bypassed_uop_bypass_sel_dst_enc_T = mux(bypassed_uop_bypass_hits_dst_0_1, UInt<2>(0h2), UInt<2>(0h0))
node bypassed_uop_bypass_sel_dst_enc_1 = mux(bypassed_uop_bypass_hits_dst_1, UInt<2>(0h1), _bypassed_uop_bypass_sel_dst_enc_T)
node bypassed_uop_bypass_sel_dst_1 = bits(bypassed_uop_bypass_sel_dst_enc_1, 0, 0)
node bypassed_uop_bypass_sel_dst_0_1 = bits(bypassed_uop_bypass_sel_dst_enc_1, 1, 1)
node bypassed_uop_do_bypass_rs1 = or(bypassed_uop_bypass_hits_rs1_0_1, bypassed_uop_bypass_hits_rs1_1)
node bypassed_uop_do_bypass_rs2 = or(bypassed_uop_bypass_hits_rs2_0_1, bypassed_uop_bypass_hits_rs2_1)
node bypassed_uop_do_bypass_rs3 = or(bypassed_uop_bypass_hits_rs3_0_1, bypassed_uop_bypass_hits_rs3_1)
node bypassed_uop_do_bypass_dst = or(bypassed_uop_bypass_hits_dst_0_1, bypassed_uop_bypass_hits_dst_1)
when bypassed_uop_do_bypass_rs1 :
node _bypassed_uop_bypassed_uop_prs1_T = mux(bypassed_uop_bypass_sel_rs1_0_1, ren2_uops[0].pdst, UInt<1>(0h0))
node _bypassed_uop_bypassed_uop_prs1_T_1 = mux(bypassed_uop_bypass_sel_rs1_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _bypassed_uop_bypassed_uop_prs1_T_2 = or(_bypassed_uop_bypassed_uop_prs1_T, _bypassed_uop_bypassed_uop_prs1_T_1)
wire _bypassed_uop_bypassed_uop_prs1_WIRE : UInt<7>
connect _bypassed_uop_bypassed_uop_prs1_WIRE, _bypassed_uop_bypassed_uop_prs1_T_2
connect bypassed_uop_bypassed_uop_1.prs1, _bypassed_uop_bypassed_uop_prs1_WIRE
when bypassed_uop_do_bypass_rs2 :
node _bypassed_uop_bypassed_uop_prs2_T = mux(bypassed_uop_bypass_sel_rs2_0_1, ren2_uops[0].pdst, UInt<1>(0h0))
node _bypassed_uop_bypassed_uop_prs2_T_1 = mux(bypassed_uop_bypass_sel_rs2_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _bypassed_uop_bypassed_uop_prs2_T_2 = or(_bypassed_uop_bypassed_uop_prs2_T, _bypassed_uop_bypassed_uop_prs2_T_1)
wire _bypassed_uop_bypassed_uop_prs2_WIRE : UInt<7>
connect _bypassed_uop_bypassed_uop_prs2_WIRE, _bypassed_uop_bypassed_uop_prs2_T_2
connect bypassed_uop_bypassed_uop_1.prs2, _bypassed_uop_bypassed_uop_prs2_WIRE
when bypassed_uop_do_bypass_rs3 :
node _bypassed_uop_bypassed_uop_prs3_T = mux(bypassed_uop_bypass_sel_rs3_0_1, ren2_uops[0].pdst, UInt<1>(0h0))
node _bypassed_uop_bypassed_uop_prs3_T_1 = mux(bypassed_uop_bypass_sel_rs3_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _bypassed_uop_bypassed_uop_prs3_T_2 = or(_bypassed_uop_bypassed_uop_prs3_T, _bypassed_uop_bypassed_uop_prs3_T_1)
wire _bypassed_uop_bypassed_uop_prs3_WIRE : UInt<7>
connect _bypassed_uop_bypassed_uop_prs3_WIRE, _bypassed_uop_bypassed_uop_prs3_T_2
connect bypassed_uop_bypassed_uop_1.prs3, _bypassed_uop_bypassed_uop_prs3_WIRE
when bypassed_uop_do_bypass_dst :
node _bypassed_uop_bypassed_uop_stale_pdst_T = mux(bypassed_uop_bypass_sel_dst_0_1, ren2_uops[0].pdst, UInt<1>(0h0))
node _bypassed_uop_bypassed_uop_stale_pdst_T_1 = mux(bypassed_uop_bypass_sel_dst_1, ren2_uops[1].pdst, UInt<1>(0h0))
node _bypassed_uop_bypassed_uop_stale_pdst_T_2 = or(_bypassed_uop_bypassed_uop_stale_pdst_T, _bypassed_uop_bypassed_uop_stale_pdst_T_1)
wire _bypassed_uop_bypassed_uop_stale_pdst_WIRE : UInt<7>
connect _bypassed_uop_bypassed_uop_stale_pdst_WIRE, _bypassed_uop_bypassed_uop_stale_pdst_T_2
connect bypassed_uop_bypassed_uop_1.stale_pdst, _bypassed_uop_bypassed_uop_stale_pdst_WIRE
node _bypassed_uop_bypassed_uop_prs1_busy_T_1 = or(ren2_uops[2].prs1_busy, bypassed_uop_do_bypass_rs1)
connect bypassed_uop_bypassed_uop_1.prs1_busy, _bypassed_uop_bypassed_uop_prs1_busy_T_1
node _bypassed_uop_bypassed_uop_prs2_busy_T_1 = or(ren2_uops[2].prs2_busy, bypassed_uop_do_bypass_rs2)
connect bypassed_uop_bypassed_uop_1.prs2_busy, _bypassed_uop_bypassed_uop_prs2_busy_T_1
node _bypassed_uop_bypassed_uop_prs3_busy_T_1 = or(ren2_uops[2].prs3_busy, bypassed_uop_do_bypass_rs3)
connect bypassed_uop_bypassed_uop_1.prs3_busy, _bypassed_uop_bypassed_uop_prs3_busy_T_1
invalidate bypassed_uop_bypassed_uop_1.prs3
connect bypassed_uop_bypassed_uop_1.prs3_busy, UInt<1>(0h0)
connect bypassed_uop_2, bypassed_uop_bypassed_uop_1
wire io_ren2_uops_2_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect io_ren2_uops_2_newuop, bypassed_uop_2
node _io_ren2_uops_2_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_ren2_uops_2_newuop_br_mask_T_1 = and(bypassed_uop_2.br_mask, _io_ren2_uops_2_newuop_br_mask_T)
connect io_ren2_uops_2_newuop.br_mask, _io_ren2_uops_2_newuop_br_mask_T_1
connect io.ren2_uops[2], io_ren2_uops_2_newuop
connect io.debug.freelist, freelist.io.debug.freelist
connect io.debug.isprlist, freelist.io.debug.isprlist
connect io.debug.busytable, busytable.io.debug.busytable | module RenameStage( // @[rename-stage.scala:160:7]
input clock, // @[rename-stage.scala:160:7]
input reset, // @[rename-stage.scala:160:7]
output io_ren_stalls_0, // @[rename-stage.scala:60:14]
output io_ren_stalls_1, // @[rename-stage.scala:60:14]
output io_ren_stalls_2, // @[rename-stage.scala:60:14]
input io_kill, // @[rename-stage.scala:60:14]
input io_dec_fire_0, // @[rename-stage.scala:60:14]
input io_dec_fire_1, // @[rename-stage.scala:60:14]
input io_dec_fire_2, // @[rename-stage.scala:60:14]
input [6:0] io_dec_uops_0_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_0_inst, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_0_debug_inst, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_dec_uops_0_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_dec_uops_0_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_dec_uops_0_fu_code, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_br, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_jalr, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_jal, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_dec_uops_0_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_dec_uops_0_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_dec_uops_0_ftq_idx, // @[rename-stage.scala:60:14]
input io_dec_uops_0_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_pc_lob, // @[rename-stage.scala:60:14]
input io_dec_uops_0_taken, // @[rename-stage.scala:60:14]
input [19:0] io_dec_uops_0_imm_packed, // @[rename-stage.scala:60:14]
input io_dec_uops_0_exception, // @[rename-stage.scala:60:14]
input [63:0] io_dec_uops_0_exc_cause, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_dec_uops_0_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_mem_size, // @[rename-stage.scala:60:14]
input io_dec_uops_0_mem_signed, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_fence, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_fencei, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_amo, // @[rename-stage.scala:60:14]
input io_dec_uops_0_uses_ldq, // @[rename-stage.scala:60:14]
input io_dec_uops_0_uses_stq, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_unique, // @[rename-stage.scala:60:14]
input io_dec_uops_0_flush_on_commit, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs3, // @[rename-stage.scala:60:14]
input io_dec_uops_0_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_dec_uops_0_frs3_en, // @[rename-stage.scala:60:14]
input io_dec_uops_0_fp_val, // @[rename-stage.scala:60:14]
input io_dec_uops_0_fp_single, // @[rename-stage.scala:60:14]
input io_dec_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bp_debug_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_debug_fsrc, // @[rename-stage.scala:60:14]
input [6:0] io_dec_uops_1_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_1_inst, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_1_debug_inst, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_dec_uops_1_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_dec_uops_1_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_dec_uops_1_fu_code, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_br, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_jalr, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_jal, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_dec_uops_1_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_dec_uops_1_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_dec_uops_1_ftq_idx, // @[rename-stage.scala:60:14]
input io_dec_uops_1_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_1_pc_lob, // @[rename-stage.scala:60:14]
input io_dec_uops_1_taken, // @[rename-stage.scala:60:14]
input [19:0] io_dec_uops_1_imm_packed, // @[rename-stage.scala:60:14]
input io_dec_uops_1_exception, // @[rename-stage.scala:60:14]
input [63:0] io_dec_uops_1_exc_cause, // @[rename-stage.scala:60:14]
input io_dec_uops_1_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_dec_uops_1_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_1_mem_size, // @[rename-stage.scala:60:14]
input io_dec_uops_1_mem_signed, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_fence, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_fencei, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_amo, // @[rename-stage.scala:60:14]
input io_dec_uops_1_uses_ldq, // @[rename-stage.scala:60:14]
input io_dec_uops_1_uses_stq, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_dec_uops_1_is_unique, // @[rename-stage.scala:60:14]
input io_dec_uops_1_flush_on_commit, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_1_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_1_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_1_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_1_lrs3, // @[rename-stage.scala:60:14]
input io_dec_uops_1_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_1_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_1_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_1_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_dec_uops_1_frs3_en, // @[rename-stage.scala:60:14]
input io_dec_uops_1_fp_val, // @[rename-stage.scala:60:14]
input io_dec_uops_1_fp_single, // @[rename-stage.scala:60:14]
input io_dec_uops_1_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_dec_uops_1_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_dec_uops_1_bp_debug_if, // @[rename-stage.scala:60:14]
input io_dec_uops_1_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_1_debug_fsrc, // @[rename-stage.scala:60:14]
input [6:0] io_dec_uops_2_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_2_inst, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_2_debug_inst, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_dec_uops_2_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_dec_uops_2_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_dec_uops_2_fu_code, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_br, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_jalr, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_jal, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_dec_uops_2_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_dec_uops_2_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_dec_uops_2_ftq_idx, // @[rename-stage.scala:60:14]
input io_dec_uops_2_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_2_pc_lob, // @[rename-stage.scala:60:14]
input io_dec_uops_2_taken, // @[rename-stage.scala:60:14]
input [19:0] io_dec_uops_2_imm_packed, // @[rename-stage.scala:60:14]
input io_dec_uops_2_exception, // @[rename-stage.scala:60:14]
input [63:0] io_dec_uops_2_exc_cause, // @[rename-stage.scala:60:14]
input io_dec_uops_2_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_dec_uops_2_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_2_mem_size, // @[rename-stage.scala:60:14]
input io_dec_uops_2_mem_signed, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_fence, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_fencei, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_amo, // @[rename-stage.scala:60:14]
input io_dec_uops_2_uses_ldq, // @[rename-stage.scala:60:14]
input io_dec_uops_2_uses_stq, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_dec_uops_2_is_unique, // @[rename-stage.scala:60:14]
input io_dec_uops_2_flush_on_commit, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_2_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_2_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_2_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_2_lrs3, // @[rename-stage.scala:60:14]
input io_dec_uops_2_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_2_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_2_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_2_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_dec_uops_2_frs3_en, // @[rename-stage.scala:60:14]
input io_dec_uops_2_fp_val, // @[rename-stage.scala:60:14]
input io_dec_uops_2_fp_single, // @[rename-stage.scala:60:14]
input io_dec_uops_2_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_dec_uops_2_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_dec_uops_2_bp_debug_if, // @[rename-stage.scala:60:14]
input io_dec_uops_2_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_2_debug_fsrc, // @[rename-stage.scala:60:14]
output io_ren2_mask_0, // @[rename-stage.scala:60:14]
output io_ren2_mask_1, // @[rename-stage.scala:60:14]
output io_ren2_mask_2, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_0_uopc, // @[rename-stage.scala:60:14]
output [31:0] io_ren2_uops_0_inst, // @[rename-stage.scala:60:14]
output [31:0] io_ren2_uops_0_debug_inst, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_rvc, // @[rename-stage.scala:60:14]
output [39:0] io_ren2_uops_0_debug_pc, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_0_iq_type, // @[rename-stage.scala:60:14]
output [9:0] io_ren2_uops_0_fu_code, // @[rename-stage.scala:60:14]
output [3:0] io_ren2_uops_0_ctrl_br_type, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_ctrl_op1_sel, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_0_ctrl_op2_sel, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_0_ctrl_imm_sel, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_0_ctrl_op_fcn, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_0_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_ctrl_is_load, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_ctrl_is_sta, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_ctrl_is_std, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_iw_state, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_iw_p1_poisoned, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_iw_p2_poisoned, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_br, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_jalr, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_jal, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_sfb, // @[rename-stage.scala:60:14]
output [15:0] io_ren2_uops_0_br_mask, // @[rename-stage.scala:60:14]
output [3:0] io_ren2_uops_0_br_tag, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_0_ftq_idx, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_edge_inst, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_pc_lob, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_taken, // @[rename-stage.scala:60:14]
output [19:0] io_ren2_uops_0_imm_packed, // @[rename-stage.scala:60:14]
output [11:0] io_ren2_uops_0_csr_addr, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_rxq_idx, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_0_pdst, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_0_prs1, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_0_prs2, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_prs1_busy, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_prs2_busy, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_0_stale_pdst, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_exception, // @[rename-stage.scala:60:14]
output [63:0] io_ren2_uops_0_exc_cause, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_bypassable, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_0_mem_cmd, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_mem_size, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_mem_signed, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_fence, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_fencei, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_amo, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_uses_ldq, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_uses_stq, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_is_unique, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_flush_on_commit, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_ldst_is_rs1, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_ldst, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_lrs1, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_lrs2, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_lrs3, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_ldst_val, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_dst_rtype, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_frs3_en, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_fp_val, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_fp_single, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_xcpt_ma_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_bp_debug_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_debug_fsrc, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_0_debug_tsrc, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_1_uopc, // @[rename-stage.scala:60:14]
output [31:0] io_ren2_uops_1_inst, // @[rename-stage.scala:60:14]
output [31:0] io_ren2_uops_1_debug_inst, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_rvc, // @[rename-stage.scala:60:14]
output [39:0] io_ren2_uops_1_debug_pc, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_1_iq_type, // @[rename-stage.scala:60:14]
output [9:0] io_ren2_uops_1_fu_code, // @[rename-stage.scala:60:14]
output [3:0] io_ren2_uops_1_ctrl_br_type, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_ctrl_op1_sel, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_1_ctrl_op2_sel, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_1_ctrl_imm_sel, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_1_ctrl_op_fcn, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_1_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_ctrl_is_load, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_ctrl_is_sta, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_ctrl_is_std, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_iw_state, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_iw_p1_poisoned, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_iw_p2_poisoned, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_br, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_jalr, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_jal, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_sfb, // @[rename-stage.scala:60:14]
output [15:0] io_ren2_uops_1_br_mask, // @[rename-stage.scala:60:14]
output [3:0] io_ren2_uops_1_br_tag, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_1_ftq_idx, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_edge_inst, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_1_pc_lob, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_taken, // @[rename-stage.scala:60:14]
output [19:0] io_ren2_uops_1_imm_packed, // @[rename-stage.scala:60:14]
output [11:0] io_ren2_uops_1_csr_addr, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_rxq_idx, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_1_pdst, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_1_prs1, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_1_prs2, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_prs1_busy, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_prs2_busy, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_1_stale_pdst, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_exception, // @[rename-stage.scala:60:14]
output [63:0] io_ren2_uops_1_exc_cause, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_bypassable, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_1_mem_cmd, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_mem_size, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_mem_signed, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_fence, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_fencei, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_amo, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_uses_ldq, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_uses_stq, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_sys_pc2epc, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_is_unique, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_flush_on_commit, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_ldst_is_rs1, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_1_ldst, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_1_lrs1, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_1_lrs2, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_1_lrs3, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_ldst_val, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_dst_rtype, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_lrs1_rtype, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_lrs2_rtype, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_frs3_en, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_fp_val, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_fp_single, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_xcpt_pf_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_xcpt_ae_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_xcpt_ma_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_bp_debug_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_1_bp_xcpt_if, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_debug_fsrc, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_1_debug_tsrc, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_2_uopc, // @[rename-stage.scala:60:14]
output [31:0] io_ren2_uops_2_inst, // @[rename-stage.scala:60:14]
output [31:0] io_ren2_uops_2_debug_inst, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_rvc, // @[rename-stage.scala:60:14]
output [39:0] io_ren2_uops_2_debug_pc, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_2_iq_type, // @[rename-stage.scala:60:14]
output [9:0] io_ren2_uops_2_fu_code, // @[rename-stage.scala:60:14]
output [3:0] io_ren2_uops_2_ctrl_br_type, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_ctrl_op1_sel, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_2_ctrl_op2_sel, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_2_ctrl_imm_sel, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_2_ctrl_op_fcn, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
output [2:0] io_ren2_uops_2_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_ctrl_is_load, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_ctrl_is_sta, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_ctrl_is_std, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_iw_state, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_iw_p1_poisoned, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_iw_p2_poisoned, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_br, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_jalr, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_jal, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_sfb, // @[rename-stage.scala:60:14]
output [15:0] io_ren2_uops_2_br_mask, // @[rename-stage.scala:60:14]
output [3:0] io_ren2_uops_2_br_tag, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_2_ftq_idx, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_edge_inst, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_2_pc_lob, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_taken, // @[rename-stage.scala:60:14]
output [19:0] io_ren2_uops_2_imm_packed, // @[rename-stage.scala:60:14]
output [11:0] io_ren2_uops_2_csr_addr, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_rxq_idx, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_2_pdst, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_2_prs1, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_2_prs2, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_prs1_busy, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_prs2_busy, // @[rename-stage.scala:60:14]
output [6:0] io_ren2_uops_2_stale_pdst, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_exception, // @[rename-stage.scala:60:14]
output [63:0] io_ren2_uops_2_exc_cause, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_bypassable, // @[rename-stage.scala:60:14]
output [4:0] io_ren2_uops_2_mem_cmd, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_mem_size, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_mem_signed, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_fence, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_fencei, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_amo, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_uses_ldq, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_uses_stq, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_sys_pc2epc, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_is_unique, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_flush_on_commit, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_ldst_is_rs1, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_2_ldst, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_2_lrs1, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_2_lrs2, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_2_lrs3, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_ldst_val, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_dst_rtype, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_lrs1_rtype, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_lrs2_rtype, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_frs3_en, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_fp_val, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_fp_single, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_xcpt_pf_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_xcpt_ae_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_xcpt_ma_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_bp_debug_if, // @[rename-stage.scala:60:14]
output io_ren2_uops_2_bp_xcpt_if, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_debug_fsrc, // @[rename-stage.scala:60:14]
output [1:0] io_ren2_uops_2_debug_tsrc, // @[rename-stage.scala:60:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[rename-stage.scala:60:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_brupdate_b2_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_br, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_jal, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_fence, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_amo, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_unique, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_fp_val, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_fp_single, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_brupdate_b2_valid, // @[rename-stage.scala:60:14]
input io_brupdate_b2_mispredict, // @[rename-stage.scala:60:14]
input io_brupdate_b2_taken, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_cfi_type, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_pc_sel, // @[rename-stage.scala:60:14]
input [39:0] io_brupdate_b2_jalr_target, // @[rename-stage.scala:60:14]
input [20:0] io_brupdate_b2_target_offset, // @[rename-stage.scala:60:14]
input io_dis_fire_0, // @[rename-stage.scala:60:14]
input io_dis_fire_1, // @[rename-stage.scala:60:14]
input io_dis_fire_2, // @[rename-stage.scala:60:14]
input io_dis_ready, // @[rename-stage.scala:60:14]
input io_wakeups_0_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_0_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_0_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_0_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_0_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_wakeups_0_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_0_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_0_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_0_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_0_bits_data, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_predicated, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_fflags_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_0_bits_fflags_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_0_bits_fflags_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_0_bits_fflags_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_0_bits_fflags_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_wakeups_0_bits_fflags_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_fflags_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_0_bits_fflags_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_0_bits_fflags_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_fflags_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_fflags_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_fflags_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_fflags_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_fflags_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_fflags_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_0_bits_fflags_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_flags, // @[rename-stage.scala:60:14]
input io_wakeups_1_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_1_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_1_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_1_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_1_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_1_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_wakeups_1_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_1_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_1_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_1_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_1_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_wakeups_2_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_2_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_2_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_2_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_2_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_2_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_2_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_2_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_2_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_2_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_2_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_2_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_wakeups_2_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_2_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_2_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_2_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_2_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_2_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_2_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_2_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_2_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_2_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_2_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_2_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_2_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_2_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_2_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_2_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_2_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_2_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_2_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_2_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_2_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_2_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_2_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_wakeups_3_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_3_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_3_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_3_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_3_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_3_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_3_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_3_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_3_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_3_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_3_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_3_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_wakeups_3_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_3_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_3_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_3_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_3_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_3_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_3_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_3_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_3_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_3_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_3_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_3_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_3_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_3_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_3_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_3_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_3_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_3_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_3_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_3_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_3_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_3_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_3_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_wakeups_4_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_4_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_4_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_4_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_4_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_4_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_4_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_4_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_4_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_4_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_4_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_4_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_wakeups_4_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_4_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_4_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_4_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_4_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_4_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_4_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_4_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_4_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_4_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_4_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_4_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_4_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_4_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_4_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_4_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_4_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_4_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_4_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_4_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_4_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_4_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_4_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_wakeups_5_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_5_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_5_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_5_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_5_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_5_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_5_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_5_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_5_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_5_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_5_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_5_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_wakeups_5_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_5_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_5_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_5_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_5_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_5_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_5_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_5_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_5_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_5_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_5_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_5_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_5_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_5_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_5_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_5_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_5_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_5_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_5_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_5_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_5_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_5_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_5_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_wakeups_6_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_6_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_6_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_6_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_6_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_6_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_6_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_6_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_6_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_6_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_6_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_6_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_wakeups_6_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_6_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_6_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_6_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_6_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_6_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_6_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_6_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_6_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_6_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_6_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_6_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_6_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_6_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_6_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_6_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_6_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_6_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_6_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_6_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_6_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_6_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_6_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_com_valids_0, // @[rename-stage.scala:60:14]
input io_com_valids_1, // @[rename-stage.scala:60:14]
input io_com_valids_2, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_0_inst, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_0_debug_inst, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_com_uops_0_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_com_uops_0_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_0_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_iw_state, // @[rename-stage.scala:60:14]
input io_com_uops_0_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_0_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_br, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_jalr, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_jal, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_com_uops_0_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_0_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_ftq_idx, // @[rename-stage.scala:60:14]
input io_com_uops_0_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_pc_lob, // @[rename-stage.scala:60:14]
input io_com_uops_0_taken, // @[rename-stage.scala:60:14]
input [19:0] io_com_uops_0_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_com_uops_0_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_ppred, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs1_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs2_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs3_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_stale_pdst, // @[rename-stage.scala:60:14]
input io_com_uops_0_exception, // @[rename-stage.scala:60:14]
input [63:0] io_com_uops_0_exc_cause, // @[rename-stage.scala:60:14]
input io_com_uops_0_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_mem_size, // @[rename-stage.scala:60:14]
input io_com_uops_0_mem_signed, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_fence, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_fencei, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_amo, // @[rename-stage.scala:60:14]
input io_com_uops_0_uses_ldq, // @[rename-stage.scala:60:14]
input io_com_uops_0_uses_stq, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_unique, // @[rename-stage.scala:60:14]
input io_com_uops_0_flush_on_commit, // @[rename-stage.scala:60:14]
input io_com_uops_0_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs3, // @[rename-stage.scala:60:14]
input io_com_uops_0_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_com_uops_0_frs3_en, // @[rename-stage.scala:60:14]
input io_com_uops_0_fp_val, // @[rename-stage.scala:60:14]
input io_com_uops_0_fp_single, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_bp_debug_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_debug_tsrc, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_1_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_1_inst, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_1_debug_inst, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_com_uops_1_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_1_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_com_uops_1_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_1_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_1_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_1_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_1_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_com_uops_1_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_1_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_com_uops_1_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_com_uops_1_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_com_uops_1_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_iw_state, // @[rename-stage.scala:60:14]
input io_com_uops_1_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_1_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_br, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_jalr, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_jal, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_com_uops_1_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_1_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_1_ftq_idx, // @[rename-stage.scala:60:14]
input io_com_uops_1_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_1_pc_lob, // @[rename-stage.scala:60:14]
input io_com_uops_1_taken, // @[rename-stage.scala:60:14]
input [19:0] io_com_uops_1_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_com_uops_1_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_1_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_1_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_1_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_1_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_1_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_1_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_1_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_1_ppred, // @[rename-stage.scala:60:14]
input io_com_uops_1_prs1_busy, // @[rename-stage.scala:60:14]
input io_com_uops_1_prs2_busy, // @[rename-stage.scala:60:14]
input io_com_uops_1_prs3_busy, // @[rename-stage.scala:60:14]
input io_com_uops_1_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_1_stale_pdst, // @[rename-stage.scala:60:14]
input io_com_uops_1_exception, // @[rename-stage.scala:60:14]
input [63:0] io_com_uops_1_exc_cause, // @[rename-stage.scala:60:14]
input io_com_uops_1_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_1_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_mem_size, // @[rename-stage.scala:60:14]
input io_com_uops_1_mem_signed, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_fence, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_fencei, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_amo, // @[rename-stage.scala:60:14]
input io_com_uops_1_uses_ldq, // @[rename-stage.scala:60:14]
input io_com_uops_1_uses_stq, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_com_uops_1_is_unique, // @[rename-stage.scala:60:14]
input io_com_uops_1_flush_on_commit, // @[rename-stage.scala:60:14]
input io_com_uops_1_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_1_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_1_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_1_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_1_lrs3, // @[rename-stage.scala:60:14]
input io_com_uops_1_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_com_uops_1_frs3_en, // @[rename-stage.scala:60:14]
input io_com_uops_1_fp_val, // @[rename-stage.scala:60:14]
input io_com_uops_1_fp_single, // @[rename-stage.scala:60:14]
input io_com_uops_1_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_com_uops_1_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_com_uops_1_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_com_uops_1_bp_debug_if, // @[rename-stage.scala:60:14]
input io_com_uops_1_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_1_debug_tsrc, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_2_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_2_inst, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_2_debug_inst, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_com_uops_2_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_2_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_com_uops_2_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_2_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_2_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_2_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_2_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_com_uops_2_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_2_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_com_uops_2_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_com_uops_2_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_com_uops_2_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_iw_state, // @[rename-stage.scala:60:14]
input io_com_uops_2_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_2_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_br, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_jalr, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_jal, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_sfb, // @[rename-stage.scala:60:14]
input [15:0] io_com_uops_2_br_mask, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_2_br_tag, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_2_ftq_idx, // @[rename-stage.scala:60:14]
input io_com_uops_2_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_2_pc_lob, // @[rename-stage.scala:60:14]
input io_com_uops_2_taken, // @[rename-stage.scala:60:14]
input [19:0] io_com_uops_2_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_com_uops_2_csr_addr, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_2_rob_idx, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_2_ldq_idx, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_2_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_rxq_idx, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_2_pdst, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_2_prs1, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_2_prs2, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_2_prs3, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_2_ppred, // @[rename-stage.scala:60:14]
input io_com_uops_2_prs1_busy, // @[rename-stage.scala:60:14]
input io_com_uops_2_prs2_busy, // @[rename-stage.scala:60:14]
input io_com_uops_2_prs3_busy, // @[rename-stage.scala:60:14]
input io_com_uops_2_ppred_busy, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_2_stale_pdst, // @[rename-stage.scala:60:14]
input io_com_uops_2_exception, // @[rename-stage.scala:60:14]
input [63:0] io_com_uops_2_exc_cause, // @[rename-stage.scala:60:14]
input io_com_uops_2_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_2_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_mem_size, // @[rename-stage.scala:60:14]
input io_com_uops_2_mem_signed, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_fence, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_fencei, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_amo, // @[rename-stage.scala:60:14]
input io_com_uops_2_uses_ldq, // @[rename-stage.scala:60:14]
input io_com_uops_2_uses_stq, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_com_uops_2_is_unique, // @[rename-stage.scala:60:14]
input io_com_uops_2_flush_on_commit, // @[rename-stage.scala:60:14]
input io_com_uops_2_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_2_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_2_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_2_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_2_lrs3, // @[rename-stage.scala:60:14]
input io_com_uops_2_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_com_uops_2_frs3_en, // @[rename-stage.scala:60:14]
input io_com_uops_2_fp_val, // @[rename-stage.scala:60:14]
input io_com_uops_2_fp_single, // @[rename-stage.scala:60:14]
input io_com_uops_2_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_com_uops_2_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_com_uops_2_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_com_uops_2_bp_debug_if, // @[rename-stage.scala:60:14]
input io_com_uops_2_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_2_debug_tsrc, // @[rename-stage.scala:60:14]
input io_rbk_valids_0, // @[rename-stage.scala:60:14]
input io_rbk_valids_1, // @[rename-stage.scala:60:14]
input io_rbk_valids_2, // @[rename-stage.scala:60:14]
input io_rollback, // @[rename-stage.scala:60:14]
input io_debug_rob_empty // @[rename-stage.scala:60:14]
);
wire [1:0] bypassed_uop_2_debug_tsrc; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_2_debug_fsrc; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_bp_xcpt_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_bp_debug_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_xcpt_ma_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_xcpt_ae_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_xcpt_pf_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_fp_single; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_fp_val; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_frs3_en; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_2_lrs2_rtype; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_2_lrs1_rtype; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_2_dst_rtype; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_ldst_val; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_2_lrs3; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_2_lrs2; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_2_lrs1; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_2_ldst; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_ldst_is_rs1; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_flush_on_commit; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_unique; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_sys_pc2epc; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_uses_stq; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_uses_ldq; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_amo; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_fencei; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_fence; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_mem_signed; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_2_mem_size; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_2_mem_cmd; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_bypassable; // @[rename-stage.scala:341:28]
wire [63:0] bypassed_uop_2_exc_cause; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_exception; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_2_stale_pdst; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_ppred_busy; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_prs2_busy; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_prs1_busy; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_2_ppred; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_2_prs2; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_2_prs1; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_2_pdst; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_2_rxq_idx; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_2_stq_idx; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_2_ldq_idx; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_2_rob_idx; // @[rename-stage.scala:341:28]
wire [11:0] bypassed_uop_2_csr_addr; // @[rename-stage.scala:341:28]
wire [19:0] bypassed_uop_2_imm_packed; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_taken; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_2_pc_lob; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_edge_inst; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_2_ftq_idx; // @[rename-stage.scala:341:28]
wire [3:0] bypassed_uop_2_br_tag; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_sfb; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_jal; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_jalr; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_br; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_iw_p2_poisoned; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_iw_p1_poisoned; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_2_iw_state; // @[rename-stage.scala:341:28]
wire [9:0] bypassed_uop_2_fu_code; // @[rename-stage.scala:341:28]
wire [2:0] bypassed_uop_2_iq_type; // @[rename-stage.scala:341:28]
wire [39:0] bypassed_uop_2_debug_pc; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_is_rvc; // @[rename-stage.scala:341:28]
wire [31:0] bypassed_uop_2_debug_inst; // @[rename-stage.scala:341:28]
wire [31:0] bypassed_uop_2_inst; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_2_uopc; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_ctrl_is_std; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_ctrl_is_sta; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_ctrl_is_load; // @[rename-stage.scala:341:28]
wire [2:0] bypassed_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:341:28]
wire bypassed_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_2_ctrl_op_fcn; // @[rename-stage.scala:341:28]
wire [2:0] bypassed_uop_2_ctrl_imm_sel; // @[rename-stage.scala:341:28]
wire [2:0] bypassed_uop_2_ctrl_op2_sel; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_2_ctrl_op1_sel; // @[rename-stage.scala:341:28]
wire [3:0] bypassed_uop_2_ctrl_br_type; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_debug_tsrc; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_debug_fsrc; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_bp_xcpt_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_bp_debug_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_xcpt_ma_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_xcpt_ae_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_xcpt_pf_if; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_fp_single; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_fp_val; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_frs3_en; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_lrs2_rtype; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_lrs1_rtype; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_dst_rtype; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_ldst_val; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_1_lrs3; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_1_lrs2; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_1_lrs1; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_1_ldst; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_ldst_is_rs1; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_flush_on_commit; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_unique; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_sys_pc2epc; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_uses_stq; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_uses_ldq; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_amo; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_fencei; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_fence; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_mem_signed; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_mem_size; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_1_mem_cmd; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_bypassable; // @[rename-stage.scala:341:28]
wire [63:0] bypassed_uop_1_exc_cause; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_exception; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_1_stale_pdst; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_ppred_busy; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_prs2_busy; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_prs1_busy; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_1_ppred; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_1_prs2; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_1_prs1; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_1_pdst; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_rxq_idx; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_1_stq_idx; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_1_ldq_idx; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_1_rob_idx; // @[rename-stage.scala:341:28]
wire [11:0] bypassed_uop_1_csr_addr; // @[rename-stage.scala:341:28]
wire [19:0] bypassed_uop_1_imm_packed; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_taken; // @[rename-stage.scala:341:28]
wire [5:0] bypassed_uop_1_pc_lob; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_edge_inst; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_1_ftq_idx; // @[rename-stage.scala:341:28]
wire [3:0] bypassed_uop_1_br_tag; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_sfb; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_jal; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_jalr; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_br; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_iw_p2_poisoned; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_iw_p1_poisoned; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_iw_state; // @[rename-stage.scala:341:28]
wire [9:0] bypassed_uop_1_fu_code; // @[rename-stage.scala:341:28]
wire [2:0] bypassed_uop_1_iq_type; // @[rename-stage.scala:341:28]
wire [39:0] bypassed_uop_1_debug_pc; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_is_rvc; // @[rename-stage.scala:341:28]
wire [31:0] bypassed_uop_1_debug_inst; // @[rename-stage.scala:341:28]
wire [31:0] bypassed_uop_1_inst; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_1_uopc; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_ctrl_is_std; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_ctrl_is_sta; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_ctrl_is_load; // @[rename-stage.scala:341:28]
wire [2:0] bypassed_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:341:28]
wire bypassed_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:341:28]
wire [4:0] bypassed_uop_1_ctrl_op_fcn; // @[rename-stage.scala:341:28]
wire [2:0] bypassed_uop_1_ctrl_imm_sel; // @[rename-stage.scala:341:28]
wire [2:0] bypassed_uop_1_ctrl_op2_sel; // @[rename-stage.scala:341:28]
wire [1:0] bypassed_uop_1_ctrl_op1_sel; // @[rename-stage.scala:341:28]
wire [3:0] bypassed_uop_1_ctrl_br_type; // @[rename-stage.scala:341:28]
wire [6:0] r_uop_bypassed_uop_2_stale_pdst; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_2_prs2_busy; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_2_prs1_busy; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_bypassed_uop_2_prs2; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_bypassed_uop_2_prs1; // @[rename-stage.scala:174:28]
wire [1:0] next_uop_2_debug_tsrc; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_2_debug_fsrc; // @[rename-stage.scala:123:24]
wire next_uop_2_bp_xcpt_if; // @[rename-stage.scala:123:24]
wire next_uop_2_bp_debug_if; // @[rename-stage.scala:123:24]
wire next_uop_2_xcpt_ma_if; // @[rename-stage.scala:123:24]
wire next_uop_2_xcpt_ae_if; // @[rename-stage.scala:123:24]
wire next_uop_2_xcpt_pf_if; // @[rename-stage.scala:123:24]
wire next_uop_2_fp_single; // @[rename-stage.scala:123:24]
wire next_uop_2_fp_val; // @[rename-stage.scala:123:24]
wire next_uop_2_frs3_en; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_2_lrs2_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_2_lrs1_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_2_dst_rtype; // @[rename-stage.scala:123:24]
wire next_uop_2_ldst_val; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_2_lrs3; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_2_lrs2; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_2_lrs1; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_2_ldst; // @[rename-stage.scala:123:24]
wire next_uop_2_ldst_is_rs1; // @[rename-stage.scala:123:24]
wire next_uop_2_flush_on_commit; // @[rename-stage.scala:123:24]
wire next_uop_2_is_unique; // @[rename-stage.scala:123:24]
wire next_uop_2_is_sys_pc2epc; // @[rename-stage.scala:123:24]
wire next_uop_2_uses_stq; // @[rename-stage.scala:123:24]
wire next_uop_2_uses_ldq; // @[rename-stage.scala:123:24]
wire next_uop_2_is_amo; // @[rename-stage.scala:123:24]
wire next_uop_2_is_fencei; // @[rename-stage.scala:123:24]
wire next_uop_2_is_fence; // @[rename-stage.scala:123:24]
wire next_uop_2_mem_signed; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_2_mem_size; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_2_mem_cmd; // @[rename-stage.scala:123:24]
wire next_uop_2_bypassable; // @[rename-stage.scala:123:24]
wire [63:0] next_uop_2_exc_cause; // @[rename-stage.scala:123:24]
wire next_uop_2_exception; // @[rename-stage.scala:123:24]
wire next_uop_2_ppred_busy; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_2_ppred; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_2_pdst; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_2_rxq_idx; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_2_stq_idx; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_2_ldq_idx; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_2_rob_idx; // @[rename-stage.scala:123:24]
wire [11:0] next_uop_2_csr_addr; // @[rename-stage.scala:123:24]
wire [19:0] next_uop_2_imm_packed; // @[rename-stage.scala:123:24]
wire next_uop_2_taken; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_2_pc_lob; // @[rename-stage.scala:123:24]
wire next_uop_2_edge_inst; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_2_ftq_idx; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_2_br_tag; // @[rename-stage.scala:123:24]
wire [15:0] next_uop_2_br_mask; // @[rename-stage.scala:123:24]
wire next_uop_2_is_sfb; // @[rename-stage.scala:123:24]
wire next_uop_2_is_jal; // @[rename-stage.scala:123:24]
wire next_uop_2_is_jalr; // @[rename-stage.scala:123:24]
wire next_uop_2_is_br; // @[rename-stage.scala:123:24]
wire next_uop_2_iw_p2_poisoned; // @[rename-stage.scala:123:24]
wire next_uop_2_iw_p1_poisoned; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_2_iw_state; // @[rename-stage.scala:123:24]
wire [9:0] next_uop_2_fu_code; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_2_iq_type; // @[rename-stage.scala:123:24]
wire [39:0] next_uop_2_debug_pc; // @[rename-stage.scala:123:24]
wire next_uop_2_is_rvc; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_2_debug_inst; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_2_inst; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_2_uopc; // @[rename-stage.scala:123:24]
wire next_uop_2_ctrl_is_std; // @[rename-stage.scala:123:24]
wire next_uop_2_ctrl_is_sta; // @[rename-stage.scala:123:24]
wire next_uop_2_ctrl_is_load; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:123:24]
wire next_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_2_ctrl_op_fcn; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_2_ctrl_imm_sel; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_2_ctrl_op2_sel; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_2_ctrl_op1_sel; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_2_ctrl_br_type; // @[rename-stage.scala:123:24]
wire [6:0] r_uop_bypassed_uop_1_stale_pdst; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_1_prs2_busy; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_1_prs1_busy; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_bypassed_uop_1_prs2; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_bypassed_uop_1_prs1; // @[rename-stage.scala:174:28]
wire [1:0] next_uop_1_debug_tsrc; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_1_debug_fsrc; // @[rename-stage.scala:123:24]
wire next_uop_1_bp_xcpt_if; // @[rename-stage.scala:123:24]
wire next_uop_1_bp_debug_if; // @[rename-stage.scala:123:24]
wire next_uop_1_xcpt_ma_if; // @[rename-stage.scala:123:24]
wire next_uop_1_xcpt_ae_if; // @[rename-stage.scala:123:24]
wire next_uop_1_xcpt_pf_if; // @[rename-stage.scala:123:24]
wire next_uop_1_fp_single; // @[rename-stage.scala:123:24]
wire next_uop_1_fp_val; // @[rename-stage.scala:123:24]
wire next_uop_1_frs3_en; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_1_lrs2_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_1_lrs1_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_1_dst_rtype; // @[rename-stage.scala:123:24]
wire next_uop_1_ldst_val; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_1_lrs3; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_1_lrs2; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_1_lrs1; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_1_ldst; // @[rename-stage.scala:123:24]
wire next_uop_1_ldst_is_rs1; // @[rename-stage.scala:123:24]
wire next_uop_1_flush_on_commit; // @[rename-stage.scala:123:24]
wire next_uop_1_is_unique; // @[rename-stage.scala:123:24]
wire next_uop_1_is_sys_pc2epc; // @[rename-stage.scala:123:24]
wire next_uop_1_uses_stq; // @[rename-stage.scala:123:24]
wire next_uop_1_uses_ldq; // @[rename-stage.scala:123:24]
wire next_uop_1_is_amo; // @[rename-stage.scala:123:24]
wire next_uop_1_is_fencei; // @[rename-stage.scala:123:24]
wire next_uop_1_is_fence; // @[rename-stage.scala:123:24]
wire next_uop_1_mem_signed; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_1_mem_size; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_1_mem_cmd; // @[rename-stage.scala:123:24]
wire next_uop_1_bypassable; // @[rename-stage.scala:123:24]
wire [63:0] next_uop_1_exc_cause; // @[rename-stage.scala:123:24]
wire next_uop_1_exception; // @[rename-stage.scala:123:24]
wire next_uop_1_ppred_busy; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_1_ppred; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_1_pdst; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_1_rxq_idx; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_1_stq_idx; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_1_ldq_idx; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_1_rob_idx; // @[rename-stage.scala:123:24]
wire [11:0] next_uop_1_csr_addr; // @[rename-stage.scala:123:24]
wire [19:0] next_uop_1_imm_packed; // @[rename-stage.scala:123:24]
wire next_uop_1_taken; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_1_pc_lob; // @[rename-stage.scala:123:24]
wire next_uop_1_edge_inst; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_1_ftq_idx; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_1_br_tag; // @[rename-stage.scala:123:24]
wire [15:0] next_uop_1_br_mask; // @[rename-stage.scala:123:24]
wire next_uop_1_is_sfb; // @[rename-stage.scala:123:24]
wire next_uop_1_is_jal; // @[rename-stage.scala:123:24]
wire next_uop_1_is_jalr; // @[rename-stage.scala:123:24]
wire next_uop_1_is_br; // @[rename-stage.scala:123:24]
wire next_uop_1_iw_p2_poisoned; // @[rename-stage.scala:123:24]
wire next_uop_1_iw_p1_poisoned; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_1_iw_state; // @[rename-stage.scala:123:24]
wire [9:0] next_uop_1_fu_code; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_1_iq_type; // @[rename-stage.scala:123:24]
wire [39:0] next_uop_1_debug_pc; // @[rename-stage.scala:123:24]
wire next_uop_1_is_rvc; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_1_debug_inst; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_1_inst; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_1_uopc; // @[rename-stage.scala:123:24]
wire next_uop_1_ctrl_is_std; // @[rename-stage.scala:123:24]
wire next_uop_1_ctrl_is_sta; // @[rename-stage.scala:123:24]
wire next_uop_1_ctrl_is_load; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:123:24]
wire next_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_1_ctrl_op_fcn; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_1_ctrl_imm_sel; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_1_ctrl_op2_sel; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_1_ctrl_op1_sel; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_1_ctrl_br_type; // @[rename-stage.scala:123:24]
wire [6:0] r_uop_bypassed_uop_stale_pdst; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_prs2_busy; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_prs1_busy; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_bypassed_uop_prs2; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_bypassed_uop_prs1; // @[rename-stage.scala:174:28]
wire [1:0] next_uop_debug_tsrc; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_debug_fsrc; // @[rename-stage.scala:123:24]
wire next_uop_bp_xcpt_if; // @[rename-stage.scala:123:24]
wire next_uop_bp_debug_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_ma_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_ae_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_pf_if; // @[rename-stage.scala:123:24]
wire next_uop_fp_single; // @[rename-stage.scala:123:24]
wire next_uop_fp_val; // @[rename-stage.scala:123:24]
wire next_uop_frs3_en; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_lrs2_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_lrs1_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_dst_rtype; // @[rename-stage.scala:123:24]
wire next_uop_ldst_val; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs3; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs2; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs1; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_ldst; // @[rename-stage.scala:123:24]
wire next_uop_ldst_is_rs1; // @[rename-stage.scala:123:24]
wire next_uop_flush_on_commit; // @[rename-stage.scala:123:24]
wire next_uop_is_unique; // @[rename-stage.scala:123:24]
wire next_uop_is_sys_pc2epc; // @[rename-stage.scala:123:24]
wire next_uop_uses_stq; // @[rename-stage.scala:123:24]
wire next_uop_uses_ldq; // @[rename-stage.scala:123:24]
wire next_uop_is_amo; // @[rename-stage.scala:123:24]
wire next_uop_is_fencei; // @[rename-stage.scala:123:24]
wire next_uop_is_fence; // @[rename-stage.scala:123:24]
wire next_uop_mem_signed; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_mem_size; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_mem_cmd; // @[rename-stage.scala:123:24]
wire next_uop_bypassable; // @[rename-stage.scala:123:24]
wire [63:0] next_uop_exc_cause; // @[rename-stage.scala:123:24]
wire next_uop_exception; // @[rename-stage.scala:123:24]
wire next_uop_ppred_busy; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_ppred; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_pdst; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_rxq_idx; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_stq_idx; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_ldq_idx; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_rob_idx; // @[rename-stage.scala:123:24]
wire [11:0] next_uop_csr_addr; // @[rename-stage.scala:123:24]
wire [19:0] next_uop_imm_packed; // @[rename-stage.scala:123:24]
wire next_uop_taken; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_pc_lob; // @[rename-stage.scala:123:24]
wire next_uop_edge_inst; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_ftq_idx; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_br_tag; // @[rename-stage.scala:123:24]
wire [15:0] next_uop_br_mask; // @[rename-stage.scala:123:24]
wire next_uop_is_sfb; // @[rename-stage.scala:123:24]
wire next_uop_is_jal; // @[rename-stage.scala:123:24]
wire next_uop_is_jalr; // @[rename-stage.scala:123:24]
wire next_uop_is_br; // @[rename-stage.scala:123:24]
wire next_uop_iw_p2_poisoned; // @[rename-stage.scala:123:24]
wire next_uop_iw_p1_poisoned; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_iw_state; // @[rename-stage.scala:123:24]
wire [9:0] next_uop_fu_code; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_iq_type; // @[rename-stage.scala:123:24]
wire [39:0] next_uop_debug_pc; // @[rename-stage.scala:123:24]
wire next_uop_is_rvc; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_debug_inst; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_inst; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_uopc; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_std; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_sta; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_load; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_csr_cmd; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_fcn_dw; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_ctrl_op_fcn; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_imm_sel; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_op2_sel; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_ctrl_op1_sel; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_ctrl_br_type; // @[rename-stage.scala:123:24]
wire [1:0] ren2_uops_2_debug_tsrc; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_2_debug_fsrc; // @[rename-stage.scala:108:29]
wire ren2_uops_2_bp_xcpt_if; // @[rename-stage.scala:108:29]
wire ren2_uops_2_bp_debug_if; // @[rename-stage.scala:108:29]
wire ren2_uops_2_xcpt_ma_if; // @[rename-stage.scala:108:29]
wire ren2_uops_2_xcpt_ae_if; // @[rename-stage.scala:108:29]
wire ren2_uops_2_xcpt_pf_if; // @[rename-stage.scala:108:29]
wire ren2_uops_2_fp_single; // @[rename-stage.scala:108:29]
wire ren2_uops_2_fp_val; // @[rename-stage.scala:108:29]
wire ren2_uops_2_frs3_en; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_2_lrs2_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_2_lrs1_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_2_dst_rtype; // @[rename-stage.scala:108:29]
wire ren2_uops_2_ldst_val; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_2_lrs3; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_2_lrs2; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_2_lrs1; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_2_ldst; // @[rename-stage.scala:108:29]
wire ren2_uops_2_ldst_is_rs1; // @[rename-stage.scala:108:29]
wire ren2_uops_2_flush_on_commit; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_unique; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_sys_pc2epc; // @[rename-stage.scala:108:29]
wire ren2_uops_2_uses_stq; // @[rename-stage.scala:108:29]
wire ren2_uops_2_uses_ldq; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_amo; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_fencei; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_fence; // @[rename-stage.scala:108:29]
wire ren2_uops_2_mem_signed; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_2_mem_size; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_2_mem_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_2_bypassable; // @[rename-stage.scala:108:29]
wire [63:0] ren2_uops_2_exc_cause; // @[rename-stage.scala:108:29]
wire ren2_uops_2_exception; // @[rename-stage.scala:108:29]
wire ren2_uops_2_ppred_busy; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_2_ppred; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_2_pdst; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_2_rxq_idx; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_2_stq_idx; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_2_ldq_idx; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_2_rob_idx; // @[rename-stage.scala:108:29]
wire [11:0] ren2_uops_2_csr_addr; // @[rename-stage.scala:108:29]
wire [19:0] ren2_uops_2_imm_packed; // @[rename-stage.scala:108:29]
wire ren2_uops_2_taken; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_2_pc_lob; // @[rename-stage.scala:108:29]
wire ren2_uops_2_edge_inst; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_2_ftq_idx; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_2_br_tag; // @[rename-stage.scala:108:29]
wire [15:0] ren2_uops_2_br_mask; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_sfb; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_jal; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_jalr; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_br; // @[rename-stage.scala:108:29]
wire ren2_uops_2_iw_p2_poisoned; // @[rename-stage.scala:108:29]
wire ren2_uops_2_iw_p1_poisoned; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_2_iw_state; // @[rename-stage.scala:108:29]
wire [9:0] ren2_uops_2_fu_code; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_2_iq_type; // @[rename-stage.scala:108:29]
wire [39:0] ren2_uops_2_debug_pc; // @[rename-stage.scala:108:29]
wire ren2_uops_2_is_rvc; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_2_debug_inst; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_2_inst; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_2_uopc; // @[rename-stage.scala:108:29]
wire ren2_uops_2_ctrl_is_std; // @[rename-stage.scala:108:29]
wire ren2_uops_2_ctrl_is_sta; // @[rename-stage.scala:108:29]
wire ren2_uops_2_ctrl_is_load; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_2_ctrl_csr_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_2_ctrl_fcn_dw; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_2_ctrl_op_fcn; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_2_ctrl_imm_sel; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_2_ctrl_op2_sel; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_2_ctrl_op1_sel; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_2_ctrl_br_type; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_debug_tsrc; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_debug_fsrc; // @[rename-stage.scala:108:29]
wire ren2_uops_1_bp_xcpt_if; // @[rename-stage.scala:108:29]
wire ren2_uops_1_bp_debug_if; // @[rename-stage.scala:108:29]
wire ren2_uops_1_xcpt_ma_if; // @[rename-stage.scala:108:29]
wire ren2_uops_1_xcpt_ae_if; // @[rename-stage.scala:108:29]
wire ren2_uops_1_xcpt_pf_if; // @[rename-stage.scala:108:29]
wire ren2_uops_1_fp_single; // @[rename-stage.scala:108:29]
wire ren2_uops_1_fp_val; // @[rename-stage.scala:108:29]
wire ren2_uops_1_frs3_en; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_lrs2_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_lrs1_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_dst_rtype; // @[rename-stage.scala:108:29]
wire ren2_uops_1_ldst_val; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_1_lrs3; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_1_lrs2; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_1_lrs1; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_1_ldst; // @[rename-stage.scala:108:29]
wire ren2_uops_1_ldst_is_rs1; // @[rename-stage.scala:108:29]
wire ren2_uops_1_flush_on_commit; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_unique; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_sys_pc2epc; // @[rename-stage.scala:108:29]
wire ren2_uops_1_uses_stq; // @[rename-stage.scala:108:29]
wire ren2_uops_1_uses_ldq; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_amo; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_fencei; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_fence; // @[rename-stage.scala:108:29]
wire ren2_uops_1_mem_signed; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_mem_size; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_1_mem_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_1_bypassable; // @[rename-stage.scala:108:29]
wire [63:0] ren2_uops_1_exc_cause; // @[rename-stage.scala:108:29]
wire ren2_uops_1_exception; // @[rename-stage.scala:108:29]
wire ren2_uops_1_ppred_busy; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_1_ppred; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_1_pdst; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_rxq_idx; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_1_stq_idx; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_1_ldq_idx; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_1_rob_idx; // @[rename-stage.scala:108:29]
wire [11:0] ren2_uops_1_csr_addr; // @[rename-stage.scala:108:29]
wire [19:0] ren2_uops_1_imm_packed; // @[rename-stage.scala:108:29]
wire ren2_uops_1_taken; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_1_pc_lob; // @[rename-stage.scala:108:29]
wire ren2_uops_1_edge_inst; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_1_ftq_idx; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_1_br_tag; // @[rename-stage.scala:108:29]
wire [15:0] ren2_uops_1_br_mask; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_sfb; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_jal; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_jalr; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_br; // @[rename-stage.scala:108:29]
wire ren2_uops_1_iw_p2_poisoned; // @[rename-stage.scala:108:29]
wire ren2_uops_1_iw_p1_poisoned; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_iw_state; // @[rename-stage.scala:108:29]
wire [9:0] ren2_uops_1_fu_code; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_1_iq_type; // @[rename-stage.scala:108:29]
wire [39:0] ren2_uops_1_debug_pc; // @[rename-stage.scala:108:29]
wire ren2_uops_1_is_rvc; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_1_debug_inst; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_1_inst; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_1_uopc; // @[rename-stage.scala:108:29]
wire ren2_uops_1_ctrl_is_std; // @[rename-stage.scala:108:29]
wire ren2_uops_1_ctrl_is_sta; // @[rename-stage.scala:108:29]
wire ren2_uops_1_ctrl_is_load; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_1_ctrl_csr_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_1_ctrl_fcn_dw; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_1_ctrl_op_fcn; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_1_ctrl_imm_sel; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_1_ctrl_op2_sel; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_1_ctrl_op1_sel; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_1_ctrl_br_type; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_debug_tsrc; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_debug_fsrc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bp_debug_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_fp_single; // @[rename-stage.scala:108:29]
wire ren2_uops_0_fp_val; // @[rename-stage.scala:108:29]
wire ren2_uops_0_frs3_en; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_dst_rtype; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ldst_val; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs3; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs2; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs1; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_ldst; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:108:29]
wire ren2_uops_0_flush_on_commit; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_unique; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_uses_stq; // @[rename-stage.scala:108:29]
wire ren2_uops_0_uses_ldq; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_amo; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_fencei; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_fence; // @[rename-stage.scala:108:29]
wire ren2_uops_0_mem_signed; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_mem_size; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_mem_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bypassable; // @[rename-stage.scala:108:29]
wire [63:0] ren2_uops_0_exc_cause; // @[rename-stage.scala:108:29]
wire ren2_uops_0_exception; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_0_stale_pdst; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ppred_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_0_prs2_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_0_prs1_busy; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_ppred; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_0_prs2; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_0_prs1; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_0_pdst; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_rxq_idx; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_stq_idx; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_ldq_idx; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_0_rob_idx; // @[rename-stage.scala:108:29]
wire [11:0] ren2_uops_0_csr_addr; // @[rename-stage.scala:108:29]
wire [19:0] ren2_uops_0_imm_packed; // @[rename-stage.scala:108:29]
wire ren2_uops_0_taken; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_pc_lob; // @[rename-stage.scala:108:29]
wire ren2_uops_0_edge_inst; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_ftq_idx; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_0_br_tag; // @[rename-stage.scala:108:29]
wire [15:0] ren2_uops_0_br_mask; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_jal; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_br; // @[rename-stage.scala:108:29]
wire ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:108:29]
wire ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_iw_state; // @[rename-stage.scala:108:29]
wire [9:0] ren2_uops_0_fu_code; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_iq_type; // @[rename-stage.scala:108:29]
wire [39:0] ren2_uops_0_debug_pc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_rvc; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_0_debug_inst; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_0_inst; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_0_uopc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:108:29]
wire _busytable_io_busy_resps_0_prs1_busy; // @[rename-stage.scala:224:25]
wire _busytable_io_busy_resps_0_prs2_busy; // @[rename-stage.scala:224:25]
wire _busytable_io_busy_resps_1_prs1_busy; // @[rename-stage.scala:224:25]
wire _busytable_io_busy_resps_1_prs2_busy; // @[rename-stage.scala:224:25]
wire _busytable_io_busy_resps_2_prs1_busy; // @[rename-stage.scala:224:25]
wire _busytable_io_busy_resps_2_prs2_busy; // @[rename-stage.scala:224:25]
wire _freelist_io_alloc_pregs_0_valid; // @[rename-stage.scala:220:24]
wire [6:0] _freelist_io_alloc_pregs_0_bits; // @[rename-stage.scala:220:24]
wire _freelist_io_alloc_pregs_1_valid; // @[rename-stage.scala:220:24]
wire [6:0] _freelist_io_alloc_pregs_1_bits; // @[rename-stage.scala:220:24]
wire _freelist_io_alloc_pregs_2_valid; // @[rename-stage.scala:220:24]
wire [6:0] _freelist_io_alloc_pregs_2_bits; // @[rename-stage.scala:220:24]
wire io_kill_0 = io_kill; // @[rename-stage.scala:160:7]
wire io_dec_fire_0_0 = io_dec_fire_0; // @[rename-stage.scala:160:7]
wire io_dec_fire_1_0 = io_dec_fire_1; // @[rename-stage.scala:160:7]
wire io_dec_fire_2_0 = io_dec_fire_2; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_0_uopc_0 = io_dec_uops_0_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_dec_uops_0_inst_0 = io_dec_uops_0_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_dec_uops_0_debug_inst_0 = io_dec_uops_0_debug_inst; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_rvc_0 = io_dec_uops_0_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_dec_uops_0_debug_pc_0 = io_dec_uops_0_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_iq_type_0 = io_dec_uops_0_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_dec_uops_0_fu_code_0 = io_dec_uops_0_fu_code; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_br_0 = io_dec_uops_0_is_br; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_jalr_0 = io_dec_uops_0_is_jalr; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_jal_0 = io_dec_uops_0_is_jal; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_sfb_0 = io_dec_uops_0_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_dec_uops_0_br_mask_0 = io_dec_uops_0_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_0_br_tag_0 = io_dec_uops_0_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_0_ftq_idx_0 = io_dec_uops_0_ftq_idx; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_edge_inst_0 = io_dec_uops_0_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_pc_lob_0 = io_dec_uops_0_pc_lob; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_taken_0 = io_dec_uops_0_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_dec_uops_0_imm_packed_0 = io_dec_uops_0_imm_packed; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_exception_0 = io_dec_uops_0_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_dec_uops_0_exc_cause_0 = io_dec_uops_0_exc_cause; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_bypassable_0 = io_dec_uops_0_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_0_mem_cmd_0 = io_dec_uops_0_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_mem_size_0 = io_dec_uops_0_mem_size; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_mem_signed_0 = io_dec_uops_0_mem_signed; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_fence_0 = io_dec_uops_0_is_fence; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_fencei_0 = io_dec_uops_0_is_fencei; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_amo_0 = io_dec_uops_0_is_amo; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_uses_ldq_0 = io_dec_uops_0_uses_ldq; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_uses_stq_0 = io_dec_uops_0_uses_stq; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_sys_pc2epc_0 = io_dec_uops_0_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_unique_0 = io_dec_uops_0_is_unique; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_flush_on_commit_0 = io_dec_uops_0_flush_on_commit; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_ldst_0 = io_dec_uops_0_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_lrs1_0 = io_dec_uops_0_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_lrs2_0 = io_dec_uops_0_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_lrs3_0 = io_dec_uops_0_lrs3; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ldst_val_0 = io_dec_uops_0_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_dst_rtype_0 = io_dec_uops_0_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_lrs1_rtype_0 = io_dec_uops_0_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_lrs2_rtype_0 = io_dec_uops_0_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_frs3_en_0 = io_dec_uops_0_frs3_en; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_fp_val_0 = io_dec_uops_0_fp_val; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_fp_single_0 = io_dec_uops_0_fp_single; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_xcpt_pf_if_0 = io_dec_uops_0_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_xcpt_ae_if_0 = io_dec_uops_0_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_bp_debug_if_0 = io_dec_uops_0_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_bp_xcpt_if_0 = io_dec_uops_0_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_debug_fsrc_0 = io_dec_uops_0_debug_fsrc; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_1_uopc_0 = io_dec_uops_1_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_dec_uops_1_inst_0 = io_dec_uops_1_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_dec_uops_1_debug_inst_0 = io_dec_uops_1_debug_inst; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_rvc_0 = io_dec_uops_1_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_dec_uops_1_debug_pc_0 = io_dec_uops_1_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_1_iq_type_0 = io_dec_uops_1_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_dec_uops_1_fu_code_0 = io_dec_uops_1_fu_code; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_br_0 = io_dec_uops_1_is_br; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_jalr_0 = io_dec_uops_1_is_jalr; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_jal_0 = io_dec_uops_1_is_jal; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_sfb_0 = io_dec_uops_1_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_dec_uops_1_br_mask_0 = io_dec_uops_1_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_1_br_tag_0 = io_dec_uops_1_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_1_ftq_idx_0 = io_dec_uops_1_ftq_idx; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_edge_inst_0 = io_dec_uops_1_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_1_pc_lob_0 = io_dec_uops_1_pc_lob; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_taken_0 = io_dec_uops_1_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_dec_uops_1_imm_packed_0 = io_dec_uops_1_imm_packed; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_exception_0 = io_dec_uops_1_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_dec_uops_1_exc_cause_0 = io_dec_uops_1_exc_cause; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_bypassable_0 = io_dec_uops_1_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_1_mem_cmd_0 = io_dec_uops_1_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_mem_size_0 = io_dec_uops_1_mem_size; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_mem_signed_0 = io_dec_uops_1_mem_signed; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_fence_0 = io_dec_uops_1_is_fence; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_fencei_0 = io_dec_uops_1_is_fencei; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_amo_0 = io_dec_uops_1_is_amo; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_uses_ldq_0 = io_dec_uops_1_uses_ldq; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_uses_stq_0 = io_dec_uops_1_uses_stq; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_sys_pc2epc_0 = io_dec_uops_1_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_is_unique_0 = io_dec_uops_1_is_unique; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_flush_on_commit_0 = io_dec_uops_1_flush_on_commit; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_1_ldst_0 = io_dec_uops_1_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_1_lrs1_0 = io_dec_uops_1_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_1_lrs2_0 = io_dec_uops_1_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_1_lrs3_0 = io_dec_uops_1_lrs3; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_ldst_val_0 = io_dec_uops_1_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_dst_rtype_0 = io_dec_uops_1_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_lrs1_rtype_0 = io_dec_uops_1_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_lrs2_rtype_0 = io_dec_uops_1_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_frs3_en_0 = io_dec_uops_1_frs3_en; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_fp_val_0 = io_dec_uops_1_fp_val; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_fp_single_0 = io_dec_uops_1_fp_single; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_xcpt_pf_if_0 = io_dec_uops_1_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_xcpt_ae_if_0 = io_dec_uops_1_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_bp_debug_if_0 = io_dec_uops_1_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_bp_xcpt_if_0 = io_dec_uops_1_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_debug_fsrc_0 = io_dec_uops_1_debug_fsrc; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_2_uopc_0 = io_dec_uops_2_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_dec_uops_2_inst_0 = io_dec_uops_2_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_dec_uops_2_debug_inst_0 = io_dec_uops_2_debug_inst; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_rvc_0 = io_dec_uops_2_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_dec_uops_2_debug_pc_0 = io_dec_uops_2_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_2_iq_type_0 = io_dec_uops_2_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_dec_uops_2_fu_code_0 = io_dec_uops_2_fu_code; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_br_0 = io_dec_uops_2_is_br; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_jalr_0 = io_dec_uops_2_is_jalr; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_jal_0 = io_dec_uops_2_is_jal; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_sfb_0 = io_dec_uops_2_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_dec_uops_2_br_mask_0 = io_dec_uops_2_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_2_br_tag_0 = io_dec_uops_2_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_2_ftq_idx_0 = io_dec_uops_2_ftq_idx; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_edge_inst_0 = io_dec_uops_2_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_2_pc_lob_0 = io_dec_uops_2_pc_lob; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_taken_0 = io_dec_uops_2_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_dec_uops_2_imm_packed_0 = io_dec_uops_2_imm_packed; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_exception_0 = io_dec_uops_2_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_dec_uops_2_exc_cause_0 = io_dec_uops_2_exc_cause; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_bypassable_0 = io_dec_uops_2_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_2_mem_cmd_0 = io_dec_uops_2_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_mem_size_0 = io_dec_uops_2_mem_size; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_mem_signed_0 = io_dec_uops_2_mem_signed; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_fence_0 = io_dec_uops_2_is_fence; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_fencei_0 = io_dec_uops_2_is_fencei; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_amo_0 = io_dec_uops_2_is_amo; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_uses_ldq_0 = io_dec_uops_2_uses_ldq; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_uses_stq_0 = io_dec_uops_2_uses_stq; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_sys_pc2epc_0 = io_dec_uops_2_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_is_unique_0 = io_dec_uops_2_is_unique; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_flush_on_commit_0 = io_dec_uops_2_flush_on_commit; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_2_ldst_0 = io_dec_uops_2_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_2_lrs1_0 = io_dec_uops_2_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_2_lrs2_0 = io_dec_uops_2_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_2_lrs3_0 = io_dec_uops_2_lrs3; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_ldst_val_0 = io_dec_uops_2_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_dst_rtype_0 = io_dec_uops_2_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_lrs1_rtype_0 = io_dec_uops_2_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_lrs2_rtype_0 = io_dec_uops_2_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_frs3_en_0 = io_dec_uops_2_frs3_en; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_fp_val_0 = io_dec_uops_2_fp_val; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_fp_single_0 = io_dec_uops_2_fp_single; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_xcpt_pf_if_0 = io_dec_uops_2_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_xcpt_ae_if_0 = io_dec_uops_2_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_bp_debug_if_0 = io_dec_uops_2_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_bp_xcpt_if_0 = io_dec_uops_2_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_debug_fsrc_0 = io_dec_uops_2_debug_fsrc; // @[rename-stage.scala:160:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-stage.scala:160:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-stage.scala:160:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-stage.scala:160:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-stage.scala:160:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-stage.scala:160:7]
wire io_dis_fire_0_0 = io_dis_fire_0; // @[rename-stage.scala:160:7]
wire io_dis_fire_1_0 = io_dis_fire_1; // @[rename-stage.scala:160:7]
wire io_dis_fire_2_0 = io_dis_fire_2; // @[rename-stage.scala:160:7]
wire io_dis_ready_0 = io_dis_ready; // @[rename-stage.scala:160:7]
wire io_wakeups_0_valid_0 = io_wakeups_0_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_uop_uopc_0 = io_wakeups_0_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_0_bits_uop_inst_0 = io_wakeups_0_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_0_bits_uop_debug_inst_0 = io_wakeups_0_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_rvc_0 = io_wakeups_0_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_0_bits_uop_debug_pc_0 = io_wakeups_0_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_iq_type_0 = io_wakeups_0_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_0_bits_uop_fu_code_0 = io_wakeups_0_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_uop_ctrl_br_type_0 = io_wakeups_0_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_ctrl_op1_sel_0 = io_wakeups_0_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_op2_sel_0 = io_wakeups_0_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_imm_sel_0 = io_wakeups_0_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_ctrl_op_fcn_0 = io_wakeups_0_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ctrl_fcn_dw_0 = io_wakeups_0_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_csr_cmd_0 = io_wakeups_0_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ctrl_is_load_0 = io_wakeups_0_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ctrl_is_sta_0 = io_wakeups_0_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ctrl_is_std_0 = io_wakeups_0_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_iw_state_0 = io_wakeups_0_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_iw_p1_poisoned_0 = io_wakeups_0_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_iw_p2_poisoned_0 = io_wakeups_0_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_br_0 = io_wakeups_0_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_jalr_0 = io_wakeups_0_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_jal_0 = io_wakeups_0_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_sfb_0 = io_wakeups_0_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_0_bits_uop_br_mask_0 = io_wakeups_0_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_uop_br_tag_0 = io_wakeups_0_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_ftq_idx_0 = io_wakeups_0_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_edge_inst_0 = io_wakeups_0_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_pc_lob_0 = io_wakeups_0_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_taken_0 = io_wakeups_0_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_0_bits_uop_imm_packed_0 = io_wakeups_0_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_0_bits_uop_csr_addr_0 = io_wakeups_0_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_uop_rob_idx_0 = io_wakeups_0_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_ldq_idx_0 = io_wakeups_0_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_stq_idx_0 = io_wakeups_0_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0 = io_wakeups_0_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_uop_pdst_0 = io_wakeups_0_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_uop_prs1_0 = io_wakeups_0_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_uop_prs2_0 = io_wakeups_0_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_uop_prs3_0 = io_wakeups_0_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_ppred_0 = io_wakeups_0_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_prs1_busy_0 = io_wakeups_0_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_prs2_busy_0 = io_wakeups_0_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_prs3_busy_0 = io_wakeups_0_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ppred_busy_0 = io_wakeups_0_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_uop_stale_pdst_0 = io_wakeups_0_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_exception_0 = io_wakeups_0_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_0_bits_uop_exc_cause_0 = io_wakeups_0_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_bypassable_0 = io_wakeups_0_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0 = io_wakeups_0_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_mem_size_0 = io_wakeups_0_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_mem_signed_0 = io_wakeups_0_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_fence_0 = io_wakeups_0_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_fencei_0 = io_wakeups_0_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_amo_0 = io_wakeups_0_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_uses_ldq_0 = io_wakeups_0_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_uses_stq_0 = io_wakeups_0_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_unique_0 = io_wakeups_0_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_ldst_0 = io_wakeups_0_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_lrs1_0 = io_wakeups_0_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_lrs2_0 = io_wakeups_0_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_lrs3_0 = io_wakeups_0_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ldst_val_0 = io_wakeups_0_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0 = io_wakeups_0_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_frs3_en_0 = io_wakeups_0_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_fp_val_0 = io_wakeups_0_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_fp_single_0 = io_wakeups_0_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_0_bits_data_0 = io_wakeups_0_bits_data; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_predicated_0 = io_wakeups_0_bits_predicated; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_valid_0 = io_wakeups_0_bits_fflags_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_uopc_0 = io_wakeups_0_bits_fflags_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_0_bits_fflags_bits_uop_inst_0 = io_wakeups_0_bits_fflags_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_0_bits_fflags_bits_uop_debug_inst_0 = io_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_rvc_0 = io_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_0_bits_fflags_bits_uop_debug_pc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_iq_type_0 = io_wakeups_0_bits_fflags_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_0_bits_fflags_bits_uop_fu_code_0 = io_wakeups_0_bits_fflags_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_iw_state_0 = io_wakeups_0_bits_fflags_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_br_0 = io_wakeups_0_bits_fflags_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_jalr_0 = io_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_jal_0 = io_wakeups_0_bits_fflags_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_sfb_0 = io_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_0_bits_fflags_bits_uop_br_mask_0 = io_wakeups_0_bits_fflags_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_fflags_bits_uop_br_tag_0 = io_wakeups_0_bits_fflags_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ftq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_edge_inst_0 = io_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_pc_lob_0 = io_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_taken_0 = io_wakeups_0_bits_fflags_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_0_bits_fflags_bits_uop_imm_packed_0 = io_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_0_bits_fflags_bits_uop_csr_addr_0 = io_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_rob_idx_0 = io_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ldq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_stq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_rxq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_pdst_0 = io_wakeups_0_bits_fflags_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_prs1_0 = io_wakeups_0_bits_fflags_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_prs2_0 = io_wakeups_0_bits_fflags_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_prs3_0 = io_wakeups_0_bits_fflags_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ppred_0 = io_wakeups_0_bits_fflags_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs1_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs2_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs3_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ppred_busy_0 = io_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_stale_pdst_0 = io_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_exception_0 = io_wakeups_0_bits_fflags_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_0_bits_fflags_bits_uop_exc_cause_0 = io_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_bypassable_0 = io_wakeups_0_bits_fflags_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_mem_cmd_0 = io_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_mem_size_0 = io_wakeups_0_bits_fflags_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_mem_signed_0 = io_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_fence_0 = io_wakeups_0_bits_fflags_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_fencei_0 = io_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_amo_0 = io_wakeups_0_bits_fflags_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_uses_ldq_0 = io_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_uses_stq_0 = io_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_unique_0 = io_wakeups_0_bits_fflags_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_ldst_0 = io_wakeups_0_bits_fflags_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_0 = io_wakeups_0_bits_fflags_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_0 = io_wakeups_0_bits_fflags_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs3_0 = io_wakeups_0_bits_fflags_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ldst_val_0 = io_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_dst_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_frs3_en_0 = io_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_fp_val_0 = io_wakeups_0_bits_fflags_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_fp_single_0 = io_wakeups_0_bits_fflags_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_flags_0 = io_wakeups_0_bits_fflags_bits_flags; // @[rename-stage.scala:160:7]
wire io_wakeups_1_valid_0 = io_wakeups_1_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_uop_uopc_0 = io_wakeups_1_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_1_bits_uop_inst_0 = io_wakeups_1_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_1_bits_uop_debug_inst_0 = io_wakeups_1_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_rvc_0 = io_wakeups_1_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_1_bits_uop_debug_pc_0 = io_wakeups_1_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_iq_type_0 = io_wakeups_1_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_1_bits_uop_fu_code_0 = io_wakeups_1_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_uop_ctrl_br_type_0 = io_wakeups_1_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_ctrl_op1_sel_0 = io_wakeups_1_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_ctrl_op2_sel_0 = io_wakeups_1_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_ctrl_imm_sel_0 = io_wakeups_1_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_ctrl_op_fcn_0 = io_wakeups_1_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ctrl_fcn_dw_0 = io_wakeups_1_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_ctrl_csr_cmd_0 = io_wakeups_1_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ctrl_is_load_0 = io_wakeups_1_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ctrl_is_sta_0 = io_wakeups_1_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ctrl_is_std_0 = io_wakeups_1_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_iw_state_0 = io_wakeups_1_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_iw_p1_poisoned_0 = io_wakeups_1_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_iw_p2_poisoned_0 = io_wakeups_1_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_br_0 = io_wakeups_1_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_jalr_0 = io_wakeups_1_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_jal_0 = io_wakeups_1_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_sfb_0 = io_wakeups_1_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_1_bits_uop_br_mask_0 = io_wakeups_1_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_uop_br_tag_0 = io_wakeups_1_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_ftq_idx_0 = io_wakeups_1_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_edge_inst_0 = io_wakeups_1_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_pc_lob_0 = io_wakeups_1_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_taken_0 = io_wakeups_1_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_1_bits_uop_imm_packed_0 = io_wakeups_1_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_1_bits_uop_csr_addr_0 = io_wakeups_1_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_uop_rob_idx_0 = io_wakeups_1_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_ldq_idx_0 = io_wakeups_1_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_stq_idx_0 = io_wakeups_1_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0 = io_wakeups_1_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_uop_pdst_0 = io_wakeups_1_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_uop_prs1_0 = io_wakeups_1_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_uop_prs2_0 = io_wakeups_1_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_uop_prs3_0 = io_wakeups_1_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_ppred_0 = io_wakeups_1_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_prs1_busy_0 = io_wakeups_1_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_prs2_busy_0 = io_wakeups_1_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_prs3_busy_0 = io_wakeups_1_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ppred_busy_0 = io_wakeups_1_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_uop_stale_pdst_0 = io_wakeups_1_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_exception_0 = io_wakeups_1_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_1_bits_uop_exc_cause_0 = io_wakeups_1_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_bypassable_0 = io_wakeups_1_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0 = io_wakeups_1_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_mem_size_0 = io_wakeups_1_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_mem_signed_0 = io_wakeups_1_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_fence_0 = io_wakeups_1_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_fencei_0 = io_wakeups_1_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_amo_0 = io_wakeups_1_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_uses_ldq_0 = io_wakeups_1_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_uses_stq_0 = io_wakeups_1_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_unique_0 = io_wakeups_1_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_ldst_0 = io_wakeups_1_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_lrs1_0 = io_wakeups_1_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_lrs2_0 = io_wakeups_1_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_lrs3_0 = io_wakeups_1_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ldst_val_0 = io_wakeups_1_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0 = io_wakeups_1_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_frs3_en_0 = io_wakeups_1_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_fp_val_0 = io_wakeups_1_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_fp_single_0 = io_wakeups_1_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_wakeups_2_valid_0 = io_wakeups_2_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_uop_uopc_0 = io_wakeups_2_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_2_bits_uop_inst_0 = io_wakeups_2_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_2_bits_uop_debug_inst_0 = io_wakeups_2_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_rvc_0 = io_wakeups_2_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_2_bits_uop_debug_pc_0 = io_wakeups_2_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_2_bits_uop_iq_type_0 = io_wakeups_2_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_2_bits_uop_fu_code_0 = io_wakeups_2_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_2_bits_uop_ctrl_br_type_0 = io_wakeups_2_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_ctrl_op1_sel_0 = io_wakeups_2_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_2_bits_uop_ctrl_op2_sel_0 = io_wakeups_2_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_2_bits_uop_ctrl_imm_sel_0 = io_wakeups_2_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_uop_ctrl_op_fcn_0 = io_wakeups_2_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_ctrl_fcn_dw_0 = io_wakeups_2_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_2_bits_uop_ctrl_csr_cmd_0 = io_wakeups_2_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_ctrl_is_load_0 = io_wakeups_2_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_ctrl_is_sta_0 = io_wakeups_2_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_ctrl_is_std_0 = io_wakeups_2_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_iw_state_0 = io_wakeups_2_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_iw_p1_poisoned_0 = io_wakeups_2_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_iw_p2_poisoned_0 = io_wakeups_2_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_br_0 = io_wakeups_2_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_jalr_0 = io_wakeups_2_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_jal_0 = io_wakeups_2_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_sfb_0 = io_wakeups_2_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_2_bits_uop_br_mask_0 = io_wakeups_2_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_2_bits_uop_br_tag_0 = io_wakeups_2_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_uop_ftq_idx_0 = io_wakeups_2_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_edge_inst_0 = io_wakeups_2_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_uop_pc_lob_0 = io_wakeups_2_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_taken_0 = io_wakeups_2_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_2_bits_uop_imm_packed_0 = io_wakeups_2_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_2_bits_uop_csr_addr_0 = io_wakeups_2_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_uop_rob_idx_0 = io_wakeups_2_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_uop_ldq_idx_0 = io_wakeups_2_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_uop_stq_idx_0 = io_wakeups_2_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_rxq_idx_0 = io_wakeups_2_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_uop_pdst_0 = io_wakeups_2_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_uop_prs1_0 = io_wakeups_2_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_uop_prs2_0 = io_wakeups_2_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_uop_prs3_0 = io_wakeups_2_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_uop_ppred_0 = io_wakeups_2_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_prs1_busy_0 = io_wakeups_2_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_prs2_busy_0 = io_wakeups_2_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_prs3_busy_0 = io_wakeups_2_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_ppred_busy_0 = io_wakeups_2_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_uop_stale_pdst_0 = io_wakeups_2_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_exception_0 = io_wakeups_2_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_2_bits_uop_exc_cause_0 = io_wakeups_2_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_bypassable_0 = io_wakeups_2_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_uop_mem_cmd_0 = io_wakeups_2_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_mem_size_0 = io_wakeups_2_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_mem_signed_0 = io_wakeups_2_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_fence_0 = io_wakeups_2_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_fencei_0 = io_wakeups_2_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_amo_0 = io_wakeups_2_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_uses_ldq_0 = io_wakeups_2_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_uses_stq_0 = io_wakeups_2_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_sys_pc2epc_0 = io_wakeups_2_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_is_unique_0 = io_wakeups_2_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_flush_on_commit_0 = io_wakeups_2_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_ldst_is_rs1_0 = io_wakeups_2_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_uop_ldst_0 = io_wakeups_2_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_uop_lrs1_0 = io_wakeups_2_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_uop_lrs2_0 = io_wakeups_2_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_uop_lrs3_0 = io_wakeups_2_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_ldst_val_0 = io_wakeups_2_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_dst_rtype_0 = io_wakeups_2_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_lrs1_rtype_0 = io_wakeups_2_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_lrs2_rtype_0 = io_wakeups_2_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_frs3_en_0 = io_wakeups_2_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_fp_val_0 = io_wakeups_2_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_fp_single_0 = io_wakeups_2_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_xcpt_pf_if_0 = io_wakeups_2_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_xcpt_ae_if_0 = io_wakeups_2_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_xcpt_ma_if_0 = io_wakeups_2_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_bp_debug_if_0 = io_wakeups_2_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_uop_bp_xcpt_if_0 = io_wakeups_2_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_debug_fsrc_0 = io_wakeups_2_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_uop_debug_tsrc_0 = io_wakeups_2_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_wakeups_3_valid_0 = io_wakeups_3_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_uop_uopc_0 = io_wakeups_3_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_3_bits_uop_inst_0 = io_wakeups_3_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_3_bits_uop_debug_inst_0 = io_wakeups_3_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_rvc_0 = io_wakeups_3_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_3_bits_uop_debug_pc_0 = io_wakeups_3_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_3_bits_uop_iq_type_0 = io_wakeups_3_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_3_bits_uop_fu_code_0 = io_wakeups_3_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_3_bits_uop_ctrl_br_type_0 = io_wakeups_3_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_ctrl_op1_sel_0 = io_wakeups_3_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_3_bits_uop_ctrl_op2_sel_0 = io_wakeups_3_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_3_bits_uop_ctrl_imm_sel_0 = io_wakeups_3_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_uop_ctrl_op_fcn_0 = io_wakeups_3_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_ctrl_fcn_dw_0 = io_wakeups_3_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_3_bits_uop_ctrl_csr_cmd_0 = io_wakeups_3_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_ctrl_is_load_0 = io_wakeups_3_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_ctrl_is_sta_0 = io_wakeups_3_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_ctrl_is_std_0 = io_wakeups_3_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_iw_state_0 = io_wakeups_3_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_iw_p1_poisoned_0 = io_wakeups_3_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_iw_p2_poisoned_0 = io_wakeups_3_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_br_0 = io_wakeups_3_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_jalr_0 = io_wakeups_3_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_jal_0 = io_wakeups_3_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_sfb_0 = io_wakeups_3_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_3_bits_uop_br_mask_0 = io_wakeups_3_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_3_bits_uop_br_tag_0 = io_wakeups_3_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_uop_ftq_idx_0 = io_wakeups_3_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_edge_inst_0 = io_wakeups_3_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_uop_pc_lob_0 = io_wakeups_3_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_taken_0 = io_wakeups_3_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_3_bits_uop_imm_packed_0 = io_wakeups_3_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_3_bits_uop_csr_addr_0 = io_wakeups_3_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_uop_rob_idx_0 = io_wakeups_3_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_uop_ldq_idx_0 = io_wakeups_3_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_uop_stq_idx_0 = io_wakeups_3_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_rxq_idx_0 = io_wakeups_3_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_uop_pdst_0 = io_wakeups_3_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_uop_prs1_0 = io_wakeups_3_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_uop_prs2_0 = io_wakeups_3_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_uop_prs3_0 = io_wakeups_3_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_uop_ppred_0 = io_wakeups_3_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_prs1_busy_0 = io_wakeups_3_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_prs2_busy_0 = io_wakeups_3_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_prs3_busy_0 = io_wakeups_3_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_ppred_busy_0 = io_wakeups_3_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_uop_stale_pdst_0 = io_wakeups_3_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_exception_0 = io_wakeups_3_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_3_bits_uop_exc_cause_0 = io_wakeups_3_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_bypassable_0 = io_wakeups_3_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_uop_mem_cmd_0 = io_wakeups_3_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_mem_size_0 = io_wakeups_3_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_mem_signed_0 = io_wakeups_3_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_fence_0 = io_wakeups_3_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_fencei_0 = io_wakeups_3_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_amo_0 = io_wakeups_3_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_uses_ldq_0 = io_wakeups_3_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_uses_stq_0 = io_wakeups_3_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_sys_pc2epc_0 = io_wakeups_3_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_is_unique_0 = io_wakeups_3_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_flush_on_commit_0 = io_wakeups_3_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_ldst_is_rs1_0 = io_wakeups_3_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_uop_ldst_0 = io_wakeups_3_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_uop_lrs1_0 = io_wakeups_3_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_uop_lrs2_0 = io_wakeups_3_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_uop_lrs3_0 = io_wakeups_3_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_ldst_val_0 = io_wakeups_3_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_dst_rtype_0 = io_wakeups_3_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_lrs1_rtype_0 = io_wakeups_3_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_lrs2_rtype_0 = io_wakeups_3_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_frs3_en_0 = io_wakeups_3_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_fp_val_0 = io_wakeups_3_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_fp_single_0 = io_wakeups_3_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_xcpt_pf_if_0 = io_wakeups_3_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_xcpt_ae_if_0 = io_wakeups_3_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_xcpt_ma_if_0 = io_wakeups_3_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_bp_debug_if_0 = io_wakeups_3_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_uop_bp_xcpt_if_0 = io_wakeups_3_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_debug_fsrc_0 = io_wakeups_3_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_uop_debug_tsrc_0 = io_wakeups_3_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_wakeups_4_valid_0 = io_wakeups_4_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_uop_uopc_0 = io_wakeups_4_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_4_bits_uop_inst_0 = io_wakeups_4_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_4_bits_uop_debug_inst_0 = io_wakeups_4_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_rvc_0 = io_wakeups_4_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_4_bits_uop_debug_pc_0 = io_wakeups_4_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_4_bits_uop_iq_type_0 = io_wakeups_4_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_4_bits_uop_fu_code_0 = io_wakeups_4_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_4_bits_uop_ctrl_br_type_0 = io_wakeups_4_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_ctrl_op1_sel_0 = io_wakeups_4_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_4_bits_uop_ctrl_op2_sel_0 = io_wakeups_4_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_4_bits_uop_ctrl_imm_sel_0 = io_wakeups_4_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_uop_ctrl_op_fcn_0 = io_wakeups_4_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_ctrl_fcn_dw_0 = io_wakeups_4_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_4_bits_uop_ctrl_csr_cmd_0 = io_wakeups_4_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_ctrl_is_load_0 = io_wakeups_4_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_ctrl_is_sta_0 = io_wakeups_4_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_ctrl_is_std_0 = io_wakeups_4_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_iw_state_0 = io_wakeups_4_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_iw_p1_poisoned_0 = io_wakeups_4_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_iw_p2_poisoned_0 = io_wakeups_4_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_br_0 = io_wakeups_4_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_jalr_0 = io_wakeups_4_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_jal_0 = io_wakeups_4_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_sfb_0 = io_wakeups_4_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_4_bits_uop_br_mask_0 = io_wakeups_4_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_4_bits_uop_br_tag_0 = io_wakeups_4_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_uop_ftq_idx_0 = io_wakeups_4_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_edge_inst_0 = io_wakeups_4_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_uop_pc_lob_0 = io_wakeups_4_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_taken_0 = io_wakeups_4_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_4_bits_uop_imm_packed_0 = io_wakeups_4_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_4_bits_uop_csr_addr_0 = io_wakeups_4_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_uop_rob_idx_0 = io_wakeups_4_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_uop_ldq_idx_0 = io_wakeups_4_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_uop_stq_idx_0 = io_wakeups_4_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_rxq_idx_0 = io_wakeups_4_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_uop_pdst_0 = io_wakeups_4_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_uop_prs1_0 = io_wakeups_4_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_uop_prs2_0 = io_wakeups_4_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_uop_prs3_0 = io_wakeups_4_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_uop_ppred_0 = io_wakeups_4_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_prs1_busy_0 = io_wakeups_4_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_prs2_busy_0 = io_wakeups_4_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_prs3_busy_0 = io_wakeups_4_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_ppred_busy_0 = io_wakeups_4_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_uop_stale_pdst_0 = io_wakeups_4_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_exception_0 = io_wakeups_4_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_4_bits_uop_exc_cause_0 = io_wakeups_4_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_bypassable_0 = io_wakeups_4_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_uop_mem_cmd_0 = io_wakeups_4_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_mem_size_0 = io_wakeups_4_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_mem_signed_0 = io_wakeups_4_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_fence_0 = io_wakeups_4_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_fencei_0 = io_wakeups_4_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_amo_0 = io_wakeups_4_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_uses_ldq_0 = io_wakeups_4_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_uses_stq_0 = io_wakeups_4_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_sys_pc2epc_0 = io_wakeups_4_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_is_unique_0 = io_wakeups_4_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_flush_on_commit_0 = io_wakeups_4_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_ldst_is_rs1_0 = io_wakeups_4_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_uop_ldst_0 = io_wakeups_4_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_uop_lrs1_0 = io_wakeups_4_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_uop_lrs2_0 = io_wakeups_4_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_uop_lrs3_0 = io_wakeups_4_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_ldst_val_0 = io_wakeups_4_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_dst_rtype_0 = io_wakeups_4_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_lrs1_rtype_0 = io_wakeups_4_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_lrs2_rtype_0 = io_wakeups_4_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_frs3_en_0 = io_wakeups_4_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_fp_val_0 = io_wakeups_4_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_fp_single_0 = io_wakeups_4_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_xcpt_pf_if_0 = io_wakeups_4_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_xcpt_ae_if_0 = io_wakeups_4_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_xcpt_ma_if_0 = io_wakeups_4_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_bp_debug_if_0 = io_wakeups_4_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_uop_bp_xcpt_if_0 = io_wakeups_4_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_debug_fsrc_0 = io_wakeups_4_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_uop_debug_tsrc_0 = io_wakeups_4_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_wakeups_5_valid_0 = io_wakeups_5_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_uop_uopc_0 = io_wakeups_5_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_5_bits_uop_inst_0 = io_wakeups_5_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_5_bits_uop_debug_inst_0 = io_wakeups_5_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_rvc_0 = io_wakeups_5_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_5_bits_uop_debug_pc_0 = io_wakeups_5_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_5_bits_uop_iq_type_0 = io_wakeups_5_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_5_bits_uop_fu_code_0 = io_wakeups_5_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_5_bits_uop_ctrl_br_type_0 = io_wakeups_5_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_ctrl_op1_sel_0 = io_wakeups_5_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_5_bits_uop_ctrl_op2_sel_0 = io_wakeups_5_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_5_bits_uop_ctrl_imm_sel_0 = io_wakeups_5_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_uop_ctrl_op_fcn_0 = io_wakeups_5_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_ctrl_fcn_dw_0 = io_wakeups_5_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_5_bits_uop_ctrl_csr_cmd_0 = io_wakeups_5_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_ctrl_is_load_0 = io_wakeups_5_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_ctrl_is_sta_0 = io_wakeups_5_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_ctrl_is_std_0 = io_wakeups_5_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_iw_state_0 = io_wakeups_5_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_iw_p1_poisoned_0 = io_wakeups_5_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_iw_p2_poisoned_0 = io_wakeups_5_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_br_0 = io_wakeups_5_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_jalr_0 = io_wakeups_5_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_jal_0 = io_wakeups_5_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_sfb_0 = io_wakeups_5_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_5_bits_uop_br_mask_0 = io_wakeups_5_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_5_bits_uop_br_tag_0 = io_wakeups_5_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_uop_ftq_idx_0 = io_wakeups_5_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_edge_inst_0 = io_wakeups_5_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_uop_pc_lob_0 = io_wakeups_5_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_taken_0 = io_wakeups_5_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_5_bits_uop_imm_packed_0 = io_wakeups_5_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_5_bits_uop_csr_addr_0 = io_wakeups_5_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_uop_rob_idx_0 = io_wakeups_5_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_uop_ldq_idx_0 = io_wakeups_5_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_uop_stq_idx_0 = io_wakeups_5_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_rxq_idx_0 = io_wakeups_5_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_uop_pdst_0 = io_wakeups_5_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_uop_prs1_0 = io_wakeups_5_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_uop_prs2_0 = io_wakeups_5_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_uop_prs3_0 = io_wakeups_5_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_uop_ppred_0 = io_wakeups_5_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_prs1_busy_0 = io_wakeups_5_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_prs2_busy_0 = io_wakeups_5_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_prs3_busy_0 = io_wakeups_5_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_ppred_busy_0 = io_wakeups_5_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_uop_stale_pdst_0 = io_wakeups_5_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_exception_0 = io_wakeups_5_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_5_bits_uop_exc_cause_0 = io_wakeups_5_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_bypassable_0 = io_wakeups_5_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_uop_mem_cmd_0 = io_wakeups_5_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_mem_size_0 = io_wakeups_5_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_mem_signed_0 = io_wakeups_5_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_fence_0 = io_wakeups_5_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_fencei_0 = io_wakeups_5_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_amo_0 = io_wakeups_5_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_uses_ldq_0 = io_wakeups_5_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_uses_stq_0 = io_wakeups_5_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_sys_pc2epc_0 = io_wakeups_5_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_is_unique_0 = io_wakeups_5_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_flush_on_commit_0 = io_wakeups_5_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_ldst_is_rs1_0 = io_wakeups_5_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_uop_ldst_0 = io_wakeups_5_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_uop_lrs1_0 = io_wakeups_5_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_uop_lrs2_0 = io_wakeups_5_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_uop_lrs3_0 = io_wakeups_5_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_ldst_val_0 = io_wakeups_5_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_dst_rtype_0 = io_wakeups_5_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_lrs1_rtype_0 = io_wakeups_5_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_lrs2_rtype_0 = io_wakeups_5_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_frs3_en_0 = io_wakeups_5_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_fp_val_0 = io_wakeups_5_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_fp_single_0 = io_wakeups_5_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_xcpt_pf_if_0 = io_wakeups_5_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_xcpt_ae_if_0 = io_wakeups_5_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_xcpt_ma_if_0 = io_wakeups_5_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_bp_debug_if_0 = io_wakeups_5_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_uop_bp_xcpt_if_0 = io_wakeups_5_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_debug_fsrc_0 = io_wakeups_5_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_uop_debug_tsrc_0 = io_wakeups_5_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_wakeups_6_valid_0 = io_wakeups_6_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_uop_uopc_0 = io_wakeups_6_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_6_bits_uop_inst_0 = io_wakeups_6_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_6_bits_uop_debug_inst_0 = io_wakeups_6_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_rvc_0 = io_wakeups_6_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_6_bits_uop_debug_pc_0 = io_wakeups_6_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_6_bits_uop_iq_type_0 = io_wakeups_6_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_6_bits_uop_fu_code_0 = io_wakeups_6_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_6_bits_uop_ctrl_br_type_0 = io_wakeups_6_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_ctrl_op1_sel_0 = io_wakeups_6_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_6_bits_uop_ctrl_op2_sel_0 = io_wakeups_6_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_6_bits_uop_ctrl_imm_sel_0 = io_wakeups_6_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_uop_ctrl_op_fcn_0 = io_wakeups_6_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_ctrl_fcn_dw_0 = io_wakeups_6_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_6_bits_uop_ctrl_csr_cmd_0 = io_wakeups_6_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_ctrl_is_load_0 = io_wakeups_6_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_ctrl_is_sta_0 = io_wakeups_6_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_ctrl_is_std_0 = io_wakeups_6_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_iw_state_0 = io_wakeups_6_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_iw_p1_poisoned_0 = io_wakeups_6_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_iw_p2_poisoned_0 = io_wakeups_6_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_br_0 = io_wakeups_6_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_jalr_0 = io_wakeups_6_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_jal_0 = io_wakeups_6_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_sfb_0 = io_wakeups_6_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_6_bits_uop_br_mask_0 = io_wakeups_6_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_6_bits_uop_br_tag_0 = io_wakeups_6_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_uop_ftq_idx_0 = io_wakeups_6_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_edge_inst_0 = io_wakeups_6_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_uop_pc_lob_0 = io_wakeups_6_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_taken_0 = io_wakeups_6_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_6_bits_uop_imm_packed_0 = io_wakeups_6_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_6_bits_uop_csr_addr_0 = io_wakeups_6_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_uop_rob_idx_0 = io_wakeups_6_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_uop_ldq_idx_0 = io_wakeups_6_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_uop_stq_idx_0 = io_wakeups_6_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_rxq_idx_0 = io_wakeups_6_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_uop_pdst_0 = io_wakeups_6_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_uop_prs1_0 = io_wakeups_6_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_uop_prs2_0 = io_wakeups_6_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_uop_prs3_0 = io_wakeups_6_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_uop_ppred_0 = io_wakeups_6_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_prs1_busy_0 = io_wakeups_6_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_prs2_busy_0 = io_wakeups_6_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_prs3_busy_0 = io_wakeups_6_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_ppred_busy_0 = io_wakeups_6_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_uop_stale_pdst_0 = io_wakeups_6_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_exception_0 = io_wakeups_6_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_6_bits_uop_exc_cause_0 = io_wakeups_6_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_bypassable_0 = io_wakeups_6_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_uop_mem_cmd_0 = io_wakeups_6_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_mem_size_0 = io_wakeups_6_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_mem_signed_0 = io_wakeups_6_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_fence_0 = io_wakeups_6_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_fencei_0 = io_wakeups_6_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_amo_0 = io_wakeups_6_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_uses_ldq_0 = io_wakeups_6_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_uses_stq_0 = io_wakeups_6_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_sys_pc2epc_0 = io_wakeups_6_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_is_unique_0 = io_wakeups_6_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_flush_on_commit_0 = io_wakeups_6_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_ldst_is_rs1_0 = io_wakeups_6_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_uop_ldst_0 = io_wakeups_6_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_uop_lrs1_0 = io_wakeups_6_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_uop_lrs2_0 = io_wakeups_6_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_uop_lrs3_0 = io_wakeups_6_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_ldst_val_0 = io_wakeups_6_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_dst_rtype_0 = io_wakeups_6_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_lrs1_rtype_0 = io_wakeups_6_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_lrs2_rtype_0 = io_wakeups_6_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_frs3_en_0 = io_wakeups_6_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_fp_val_0 = io_wakeups_6_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_fp_single_0 = io_wakeups_6_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_xcpt_pf_if_0 = io_wakeups_6_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_xcpt_ae_if_0 = io_wakeups_6_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_xcpt_ma_if_0 = io_wakeups_6_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_bp_debug_if_0 = io_wakeups_6_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_uop_bp_xcpt_if_0 = io_wakeups_6_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_debug_fsrc_0 = io_wakeups_6_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_uop_debug_tsrc_0 = io_wakeups_6_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_com_valids_0_0 = io_com_valids_0; // @[rename-stage.scala:160:7]
wire io_com_valids_1_0 = io_com_valids_1; // @[rename-stage.scala:160:7]
wire io_com_valids_2_0 = io_com_valids_2; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_0_uopc_0 = io_com_uops_0_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_com_uops_0_inst_0 = io_com_uops_0_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_com_uops_0_debug_inst_0 = io_com_uops_0_debug_inst; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_rvc_0 = io_com_uops_0_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_com_uops_0_debug_pc_0 = io_com_uops_0_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_iq_type_0 = io_com_uops_0_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_com_uops_0_fu_code_0 = io_com_uops_0_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_0_ctrl_br_type_0 = io_com_uops_0_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_ctrl_op1_sel_0 = io_com_uops_0_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_ctrl_op2_sel_0 = io_com_uops_0_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_ctrl_imm_sel_0 = io_com_uops_0_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_ctrl_op_fcn_0 = io_com_uops_0_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ctrl_fcn_dw_0 = io_com_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_ctrl_csr_cmd_0 = io_com_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ctrl_is_load_0 = io_com_uops_0_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ctrl_is_sta_0 = io_com_uops_0_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ctrl_is_std_0 = io_com_uops_0_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_iw_state_0 = io_com_uops_0_iw_state; // @[rename-stage.scala:160:7]
wire io_com_uops_0_iw_p1_poisoned_0 = io_com_uops_0_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_com_uops_0_iw_p2_poisoned_0 = io_com_uops_0_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_br_0 = io_com_uops_0_is_br; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_jalr_0 = io_com_uops_0_is_jalr; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_jal_0 = io_com_uops_0_is_jal; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_sfb_0 = io_com_uops_0_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_com_uops_0_br_mask_0 = io_com_uops_0_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_0_br_tag_0 = io_com_uops_0_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_ftq_idx_0 = io_com_uops_0_ftq_idx; // @[rename-stage.scala:160:7]
wire io_com_uops_0_edge_inst_0 = io_com_uops_0_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_pc_lob_0 = io_com_uops_0_pc_lob; // @[rename-stage.scala:160:7]
wire io_com_uops_0_taken_0 = io_com_uops_0_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_com_uops_0_imm_packed_0 = io_com_uops_0_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_com_uops_0_csr_addr_0 = io_com_uops_0_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_0_rob_idx_0 = io_com_uops_0_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_ldq_idx_0 = io_com_uops_0_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_stq_idx_0 = io_com_uops_0_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_rxq_idx_0 = io_com_uops_0_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_0_pdst_0 = io_com_uops_0_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_0_prs1_0 = io_com_uops_0_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_0_prs2_0 = io_com_uops_0_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_0_prs3_0 = io_com_uops_0_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_ppred_0 = io_com_uops_0_ppred; // @[rename-stage.scala:160:7]
wire io_com_uops_0_prs1_busy_0 = io_com_uops_0_prs1_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_0_prs2_busy_0 = io_com_uops_0_prs2_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_0_prs3_busy_0 = io_com_uops_0_prs3_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ppred_busy_0 = io_com_uops_0_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_0_stale_pdst_0 = io_com_uops_0_stale_pdst; // @[rename-stage.scala:160:7]
wire io_com_uops_0_exception_0 = io_com_uops_0_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_com_uops_0_exc_cause_0 = io_com_uops_0_exc_cause; // @[rename-stage.scala:160:7]
wire io_com_uops_0_bypassable_0 = io_com_uops_0_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_mem_cmd_0 = io_com_uops_0_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_mem_size_0 = io_com_uops_0_mem_size; // @[rename-stage.scala:160:7]
wire io_com_uops_0_mem_signed_0 = io_com_uops_0_mem_signed; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_fence_0 = io_com_uops_0_is_fence; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_fencei_0 = io_com_uops_0_is_fencei; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_amo_0 = io_com_uops_0_is_amo; // @[rename-stage.scala:160:7]
wire io_com_uops_0_uses_ldq_0 = io_com_uops_0_uses_ldq; // @[rename-stage.scala:160:7]
wire io_com_uops_0_uses_stq_0 = io_com_uops_0_uses_stq; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_sys_pc2epc_0 = io_com_uops_0_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_unique_0 = io_com_uops_0_is_unique; // @[rename-stage.scala:160:7]
wire io_com_uops_0_flush_on_commit_0 = io_com_uops_0_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ldst_is_rs1_0 = io_com_uops_0_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_ldst_0 = io_com_uops_0_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_lrs1_0 = io_com_uops_0_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_lrs2_0 = io_com_uops_0_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_lrs3_0 = io_com_uops_0_lrs3; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ldst_val_0 = io_com_uops_0_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_dst_rtype_0 = io_com_uops_0_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_lrs1_rtype_0 = io_com_uops_0_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_lrs2_rtype_0 = io_com_uops_0_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_com_uops_0_frs3_en_0 = io_com_uops_0_frs3_en; // @[rename-stage.scala:160:7]
wire io_com_uops_0_fp_val_0 = io_com_uops_0_fp_val; // @[rename-stage.scala:160:7]
wire io_com_uops_0_fp_single_0 = io_com_uops_0_fp_single; // @[rename-stage.scala:160:7]
wire io_com_uops_0_xcpt_pf_if_0 = io_com_uops_0_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_com_uops_0_xcpt_ae_if_0 = io_com_uops_0_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_com_uops_0_xcpt_ma_if_0 = io_com_uops_0_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_com_uops_0_bp_debug_if_0 = io_com_uops_0_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_com_uops_0_bp_xcpt_if_0 = io_com_uops_0_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_debug_fsrc_0 = io_com_uops_0_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_debug_tsrc_0 = io_com_uops_0_debug_tsrc; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_1_uopc_0 = io_com_uops_1_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_com_uops_1_inst_0 = io_com_uops_1_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_com_uops_1_debug_inst_0 = io_com_uops_1_debug_inst; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_rvc_0 = io_com_uops_1_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_com_uops_1_debug_pc_0 = io_com_uops_1_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_1_iq_type_0 = io_com_uops_1_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_com_uops_1_fu_code_0 = io_com_uops_1_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_1_ctrl_br_type_0 = io_com_uops_1_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_ctrl_op1_sel_0 = io_com_uops_1_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_1_ctrl_op2_sel_0 = io_com_uops_1_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_1_ctrl_imm_sel_0 = io_com_uops_1_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_1_ctrl_op_fcn_0 = io_com_uops_1_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_com_uops_1_ctrl_fcn_dw_0 = io_com_uops_1_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_1_ctrl_csr_cmd_0 = io_com_uops_1_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_com_uops_1_ctrl_is_load_0 = io_com_uops_1_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_com_uops_1_ctrl_is_sta_0 = io_com_uops_1_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_com_uops_1_ctrl_is_std_0 = io_com_uops_1_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_iw_state_0 = io_com_uops_1_iw_state; // @[rename-stage.scala:160:7]
wire io_com_uops_1_iw_p1_poisoned_0 = io_com_uops_1_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_com_uops_1_iw_p2_poisoned_0 = io_com_uops_1_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_br_0 = io_com_uops_1_is_br; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_jalr_0 = io_com_uops_1_is_jalr; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_jal_0 = io_com_uops_1_is_jal; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_sfb_0 = io_com_uops_1_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_com_uops_1_br_mask_0 = io_com_uops_1_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_1_br_tag_0 = io_com_uops_1_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_1_ftq_idx_0 = io_com_uops_1_ftq_idx; // @[rename-stage.scala:160:7]
wire io_com_uops_1_edge_inst_0 = io_com_uops_1_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_1_pc_lob_0 = io_com_uops_1_pc_lob; // @[rename-stage.scala:160:7]
wire io_com_uops_1_taken_0 = io_com_uops_1_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_com_uops_1_imm_packed_0 = io_com_uops_1_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_com_uops_1_csr_addr_0 = io_com_uops_1_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_1_rob_idx_0 = io_com_uops_1_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_1_ldq_idx_0 = io_com_uops_1_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_1_stq_idx_0 = io_com_uops_1_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_rxq_idx_0 = io_com_uops_1_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_1_pdst_0 = io_com_uops_1_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_1_prs1_0 = io_com_uops_1_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_1_prs2_0 = io_com_uops_1_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_1_prs3_0 = io_com_uops_1_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_1_ppred_0 = io_com_uops_1_ppred; // @[rename-stage.scala:160:7]
wire io_com_uops_1_prs1_busy_0 = io_com_uops_1_prs1_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_1_prs2_busy_0 = io_com_uops_1_prs2_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_1_prs3_busy_0 = io_com_uops_1_prs3_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_1_ppred_busy_0 = io_com_uops_1_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_1_stale_pdst_0 = io_com_uops_1_stale_pdst; // @[rename-stage.scala:160:7]
wire io_com_uops_1_exception_0 = io_com_uops_1_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_com_uops_1_exc_cause_0 = io_com_uops_1_exc_cause; // @[rename-stage.scala:160:7]
wire io_com_uops_1_bypassable_0 = io_com_uops_1_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_1_mem_cmd_0 = io_com_uops_1_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_mem_size_0 = io_com_uops_1_mem_size; // @[rename-stage.scala:160:7]
wire io_com_uops_1_mem_signed_0 = io_com_uops_1_mem_signed; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_fence_0 = io_com_uops_1_is_fence; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_fencei_0 = io_com_uops_1_is_fencei; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_amo_0 = io_com_uops_1_is_amo; // @[rename-stage.scala:160:7]
wire io_com_uops_1_uses_ldq_0 = io_com_uops_1_uses_ldq; // @[rename-stage.scala:160:7]
wire io_com_uops_1_uses_stq_0 = io_com_uops_1_uses_stq; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_sys_pc2epc_0 = io_com_uops_1_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_com_uops_1_is_unique_0 = io_com_uops_1_is_unique; // @[rename-stage.scala:160:7]
wire io_com_uops_1_flush_on_commit_0 = io_com_uops_1_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_com_uops_1_ldst_is_rs1_0 = io_com_uops_1_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_1_ldst_0 = io_com_uops_1_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_1_lrs1_0 = io_com_uops_1_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_1_lrs2_0 = io_com_uops_1_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_1_lrs3_0 = io_com_uops_1_lrs3; // @[rename-stage.scala:160:7]
wire io_com_uops_1_ldst_val_0 = io_com_uops_1_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_dst_rtype_0 = io_com_uops_1_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_lrs1_rtype_0 = io_com_uops_1_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_lrs2_rtype_0 = io_com_uops_1_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_com_uops_1_frs3_en_0 = io_com_uops_1_frs3_en; // @[rename-stage.scala:160:7]
wire io_com_uops_1_fp_val_0 = io_com_uops_1_fp_val; // @[rename-stage.scala:160:7]
wire io_com_uops_1_fp_single_0 = io_com_uops_1_fp_single; // @[rename-stage.scala:160:7]
wire io_com_uops_1_xcpt_pf_if_0 = io_com_uops_1_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_com_uops_1_xcpt_ae_if_0 = io_com_uops_1_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_com_uops_1_xcpt_ma_if_0 = io_com_uops_1_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_com_uops_1_bp_debug_if_0 = io_com_uops_1_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_com_uops_1_bp_xcpt_if_0 = io_com_uops_1_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_debug_fsrc_0 = io_com_uops_1_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_1_debug_tsrc_0 = io_com_uops_1_debug_tsrc; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_2_uopc_0 = io_com_uops_2_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_com_uops_2_inst_0 = io_com_uops_2_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_com_uops_2_debug_inst_0 = io_com_uops_2_debug_inst; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_rvc_0 = io_com_uops_2_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_com_uops_2_debug_pc_0 = io_com_uops_2_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_2_iq_type_0 = io_com_uops_2_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_com_uops_2_fu_code_0 = io_com_uops_2_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_2_ctrl_br_type_0 = io_com_uops_2_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_ctrl_op1_sel_0 = io_com_uops_2_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_2_ctrl_op2_sel_0 = io_com_uops_2_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_2_ctrl_imm_sel_0 = io_com_uops_2_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_2_ctrl_op_fcn_0 = io_com_uops_2_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_com_uops_2_ctrl_fcn_dw_0 = io_com_uops_2_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_2_ctrl_csr_cmd_0 = io_com_uops_2_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_com_uops_2_ctrl_is_load_0 = io_com_uops_2_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_com_uops_2_ctrl_is_sta_0 = io_com_uops_2_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_com_uops_2_ctrl_is_std_0 = io_com_uops_2_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_iw_state_0 = io_com_uops_2_iw_state; // @[rename-stage.scala:160:7]
wire io_com_uops_2_iw_p1_poisoned_0 = io_com_uops_2_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_com_uops_2_iw_p2_poisoned_0 = io_com_uops_2_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_br_0 = io_com_uops_2_is_br; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_jalr_0 = io_com_uops_2_is_jalr; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_jal_0 = io_com_uops_2_is_jal; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_sfb_0 = io_com_uops_2_is_sfb; // @[rename-stage.scala:160:7]
wire [15:0] io_com_uops_2_br_mask_0 = io_com_uops_2_br_mask; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_2_br_tag_0 = io_com_uops_2_br_tag; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_2_ftq_idx_0 = io_com_uops_2_ftq_idx; // @[rename-stage.scala:160:7]
wire io_com_uops_2_edge_inst_0 = io_com_uops_2_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_2_pc_lob_0 = io_com_uops_2_pc_lob; // @[rename-stage.scala:160:7]
wire io_com_uops_2_taken_0 = io_com_uops_2_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_com_uops_2_imm_packed_0 = io_com_uops_2_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_com_uops_2_csr_addr_0 = io_com_uops_2_csr_addr; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_2_rob_idx_0 = io_com_uops_2_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_2_ldq_idx_0 = io_com_uops_2_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_2_stq_idx_0 = io_com_uops_2_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_rxq_idx_0 = io_com_uops_2_rxq_idx; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_2_pdst_0 = io_com_uops_2_pdst; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_2_prs1_0 = io_com_uops_2_prs1; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_2_prs2_0 = io_com_uops_2_prs2; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_2_prs3_0 = io_com_uops_2_prs3; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_2_ppred_0 = io_com_uops_2_ppred; // @[rename-stage.scala:160:7]
wire io_com_uops_2_prs1_busy_0 = io_com_uops_2_prs1_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_2_prs2_busy_0 = io_com_uops_2_prs2_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_2_prs3_busy_0 = io_com_uops_2_prs3_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_2_ppred_busy_0 = io_com_uops_2_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_2_stale_pdst_0 = io_com_uops_2_stale_pdst; // @[rename-stage.scala:160:7]
wire io_com_uops_2_exception_0 = io_com_uops_2_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_com_uops_2_exc_cause_0 = io_com_uops_2_exc_cause; // @[rename-stage.scala:160:7]
wire io_com_uops_2_bypassable_0 = io_com_uops_2_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_2_mem_cmd_0 = io_com_uops_2_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_mem_size_0 = io_com_uops_2_mem_size; // @[rename-stage.scala:160:7]
wire io_com_uops_2_mem_signed_0 = io_com_uops_2_mem_signed; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_fence_0 = io_com_uops_2_is_fence; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_fencei_0 = io_com_uops_2_is_fencei; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_amo_0 = io_com_uops_2_is_amo; // @[rename-stage.scala:160:7]
wire io_com_uops_2_uses_ldq_0 = io_com_uops_2_uses_ldq; // @[rename-stage.scala:160:7]
wire io_com_uops_2_uses_stq_0 = io_com_uops_2_uses_stq; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_sys_pc2epc_0 = io_com_uops_2_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_com_uops_2_is_unique_0 = io_com_uops_2_is_unique; // @[rename-stage.scala:160:7]
wire io_com_uops_2_flush_on_commit_0 = io_com_uops_2_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_com_uops_2_ldst_is_rs1_0 = io_com_uops_2_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_2_ldst_0 = io_com_uops_2_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_2_lrs1_0 = io_com_uops_2_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_2_lrs2_0 = io_com_uops_2_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_2_lrs3_0 = io_com_uops_2_lrs3; // @[rename-stage.scala:160:7]
wire io_com_uops_2_ldst_val_0 = io_com_uops_2_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_dst_rtype_0 = io_com_uops_2_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_lrs1_rtype_0 = io_com_uops_2_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_lrs2_rtype_0 = io_com_uops_2_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_com_uops_2_frs3_en_0 = io_com_uops_2_frs3_en; // @[rename-stage.scala:160:7]
wire io_com_uops_2_fp_val_0 = io_com_uops_2_fp_val; // @[rename-stage.scala:160:7]
wire io_com_uops_2_fp_single_0 = io_com_uops_2_fp_single; // @[rename-stage.scala:160:7]
wire io_com_uops_2_xcpt_pf_if_0 = io_com_uops_2_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_com_uops_2_xcpt_ae_if_0 = io_com_uops_2_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_com_uops_2_xcpt_ma_if_0 = io_com_uops_2_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_com_uops_2_bp_debug_if_0 = io_com_uops_2_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_com_uops_2_bp_xcpt_if_0 = io_com_uops_2_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_debug_fsrc_0 = io_com_uops_2_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_2_debug_tsrc_0 = io_com_uops_2_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_rbk_valids_0_0 = io_rbk_valids_0; // @[rename-stage.scala:160:7]
wire io_rbk_valids_1_0 = io_rbk_valids_1; // @[rename-stage.scala:160:7]
wire io_rbk_valids_2_0 = io_rbk_valids_2; // @[rename-stage.scala:160:7]
wire io_rollback_0 = io_rollback; // @[rename-stage.scala:160:7]
wire io_debug_rob_empty_0 = io_debug_rob_empty; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_0_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_1_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_2_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] ren1_uops_0_ctrl_br_type = 4'h0; // @[rename-stage.scala:101:29]
wire [3:0] ren1_uops_1_ctrl_br_type = 4'h0; // @[rename-stage.scala:101:29]
wire [3:0] ren1_uops_2_ctrl_br_type = 4'h0; // @[rename-stage.scala:101:29]
wire [1:0] io_dec_uops_0_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_1_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_2_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] ren1_uops_0_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_iw_state = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_debug_tsrc = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_1_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_1_iw_state = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_1_rxq_idx = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_1_debug_tsrc = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_2_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_2_iw_state = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_2_rxq_idx = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_2_debug_tsrc = 2'h0; // @[rename-stage.scala:101:29]
wire [2:0] io_dec_uops_0_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_1_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_1_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_1_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_2_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_2_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_2_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] ren1_uops_0_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_1_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_1_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_1_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_2_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_2_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_2_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:101:29]
wire [4:0] io_dec_uops_0_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_0_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_0_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_0_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_1_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_1_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_1_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_1_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_2_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_2_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_2_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_2_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_3_bits_fflags_bits_flags = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_4_bits_fflags_bits_flags = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_5_bits_fflags_bits_flags = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_6_bits_fflags_bits_flags = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] ren1_uops_0_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_0_ldq_idx = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_0_stq_idx = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_0_ppred = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_1_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_1_ldq_idx = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_1_stq_idx = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_1_ppred = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_2_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_2_ldq_idx = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_2_stq_idx = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_2_ppred = 5'h0; // @[rename-stage.scala:101:29]
wire io_dec_uops_0_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_1_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_2_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_predicated = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_valid = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_predicated = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_valid = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_predicated = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_valid = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_taken = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_exception = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_predicated = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_valid = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_taken = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_exception = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_predicated = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_valid = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_taken = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_exception = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_predicated = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_valid = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_taken = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_exception = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rename-stage.scala:160:7]
wire ren1_uops_0_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_load = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_sta = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_std = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_ctrl_is_load = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_ctrl_is_sta = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_ctrl_is_std = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_prs1_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_prs2_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_prs3_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_ppred_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_1_xcpt_ma_if = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_ctrl_is_load = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_ctrl_is_sta = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_ctrl_is_std = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_prs1_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_prs2_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_prs3_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_ppred_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_2_xcpt_ma_if = 1'h0; // @[rename-stage.scala:101:29]
wire ren2_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:108:29]
wire ren2_uops_1_prs3_busy = 1'h0; // @[rename-stage.scala:108:29]
wire ren2_uops_2_prs3_busy = 1'h0; // @[rename-stage.scala:108:29]
wire next_uop_prs3_busy = 1'h0; // @[rename-stage.scala:123:24]
wire r_uop_bypassed_uop_prs3_busy = 1'h0; // @[rename-stage.scala:174:28]
wire r_uop_newuop_prs3_busy = 1'h0; // @[util.scala:73:26]
wire next_uop_1_prs3_busy = 1'h0; // @[rename-stage.scala:123:24]
wire r_uop_bypassed_uop_1_prs3_busy = 1'h0; // @[rename-stage.scala:174:28]
wire r_uop_newuop_1_prs3_busy = 1'h0; // @[util.scala:73:26]
wire next_uop_2_prs3_busy = 1'h0; // @[rename-stage.scala:123:24]
wire r_uop_bypassed_uop_2_prs3_busy = 1'h0; // @[rename-stage.scala:174:28]
wire r_uop_newuop_2_prs3_busy = 1'h0; // @[util.scala:73:26]
wire _ren2_uops_0_prs3_busy_T = 1'h0; // @[rename-stage.scala:325:34]
wire _ren2_uops_1_prs3_busy_T = 1'h0; // @[rename-stage.scala:325:34]
wire _ren2_uops_2_prs3_busy_T = 1'h0; // @[rename-stage.scala:325:34]
wire bypassed_uop_prs3_busy = 1'h0; // @[rename-stage.scala:341:28]
wire io_ren2_uops_0_newuop_prs3_busy = 1'h0; // @[util.scala:73:26]
wire bypassed_uop_1_prs3_busy = 1'h0; // @[rename-stage.scala:341:28]
wire bypassed_uop_bypassed_uop_prs3_busy = 1'h0; // @[rename-stage.scala:174:28]
wire io_ren2_uops_1_newuop_prs3_busy = 1'h0; // @[util.scala:73:26]
wire bypassed_uop_2_prs3_busy = 1'h0; // @[rename-stage.scala:341:28]
wire bypassed_uop_bypassed_uop_1_prs3_busy = 1'h0; // @[rename-stage.scala:174:28]
wire io_ren2_uops_2_newuop_prs3_busy = 1'h0; // @[util.scala:73:26]
wire [11:0] io_dec_uops_0_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] io_dec_uops_1_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] io_dec_uops_2_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] ren1_uops_0_csr_addr = 12'h0; // @[rename-stage.scala:101:29]
wire [11:0] ren1_uops_1_csr_addr = 12'h0; // @[rename-stage.scala:101:29]
wire [11:0] ren1_uops_2_csr_addr = 12'h0; // @[rename-stage.scala:101:29]
wire [6:0] io_dec_uops_0_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_0_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_0_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_0_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_0_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_0_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_1_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_1_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_1_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_1_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_1_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_1_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_2_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_2_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_2_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_2_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_2_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_2_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_0_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_1_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_2_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rename-stage.scala:160:7]
wire [6:0] ren1_uops_0_rob_idx = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_0_pdst = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_0_prs3 = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_1_rob_idx = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_1_pdst = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_1_prs3 = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_2_rob_idx = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_2_pdst = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_2_prs3 = 7'h0; // @[rename-stage.scala:101:29]
wire [6:0] ren2_uops_0_prs3 = 7'h0; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_1_prs3 = 7'h0; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_2_prs3 = 7'h0; // @[rename-stage.scala:108:29]
wire [6:0] next_uop_prs3 = 7'h0; // @[rename-stage.scala:123:24]
wire [6:0] r_uop_bypassed_uop_prs3 = 7'h0; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_newuop_prs3 = 7'h0; // @[util.scala:73:26]
wire [6:0] next_uop_1_prs3 = 7'h0; // @[rename-stage.scala:123:24]
wire [6:0] r_uop_bypassed_uop_1_prs3 = 7'h0; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_newuop_1_prs3 = 7'h0; // @[util.scala:73:26]
wire [6:0] next_uop_2_prs3 = 7'h0; // @[rename-stage.scala:123:24]
wire [6:0] r_uop_bypassed_uop_2_prs3 = 7'h0; // @[rename-stage.scala:174:28]
wire [6:0] r_uop_newuop_2_prs3 = 7'h0; // @[util.scala:73:26]
wire [6:0] bypassed_uop_prs3 = 7'h0; // @[rename-stage.scala:341:28]
wire [6:0] io_ren2_uops_0_newuop_prs3 = 7'h0; // @[util.scala:73:26]
wire [6:0] bypassed_uop_1_prs3 = 7'h0; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_bypassed_uop_prs3 = 7'h0; // @[rename-stage.scala:174:28]
wire [6:0] io_ren2_uops_1_newuop_prs3 = 7'h0; // @[util.scala:73:26]
wire [6:0] bypassed_uop_2_prs3 = 7'h0; // @[rename-stage.scala:341:28]
wire [6:0] bypassed_uop_bypassed_uop_1_prs3 = 7'h0; // @[rename-stage.scala:174:28]
wire [6:0] io_ren2_uops_2_newuop_prs3 = 7'h0; // @[util.scala:73:26]
wire [63:0] io_wakeups_1_bits_data = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_2_bits_data = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_3_bits_data = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_4_bits_data = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_5_bits_data = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_6_bits_data = 64'h0; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_3_bits_fflags_bits_uop_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_4_bits_fflags_bits_uop_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_5_bits_fflags_bits_uop_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_6_bits_fflags_bits_uop_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0; // @[rename-stage.scala:160:7]
wire [15:0] io_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rename-stage.scala:160:7]
wire [99:0] io_debug_isprlist = 100'h0; // @[rename-stage.scala:160:7]
wire _io_ren_stalls_0_T_2; // @[rename-stage.scala:339:60]
wire _io_ren_stalls_1_T_2; // @[rename-stage.scala:339:60]
wire _io_ren_stalls_2_T_2; // @[rename-stage.scala:339:60]
wire ren1_fire_0 = io_dec_fire_0_0; // @[rename-stage.scala:100:29, :160:7]
wire ren1_fire_1 = io_dec_fire_1_0; // @[rename-stage.scala:100:29, :160:7]
wire ren1_fire_2 = io_dec_fire_2_0; // @[rename-stage.scala:100:29, :160:7]
wire [6:0] ren1_uops_0_uopc = io_dec_uops_0_uopc_0; // @[rename-stage.scala:101:29, :160:7]
wire [31:0] ren1_uops_0_inst = io_dec_uops_0_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire [31:0] ren1_uops_0_debug_inst = io_dec_uops_0_debug_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_rvc = io_dec_uops_0_is_rvc_0; // @[rename-stage.scala:101:29, :160:7]
wire [39:0] ren1_uops_0_debug_pc = io_dec_uops_0_debug_pc_0; // @[rename-stage.scala:101:29, :160:7]
wire [2:0] ren1_uops_0_iq_type = io_dec_uops_0_iq_type_0; // @[rename-stage.scala:101:29, :160:7]
wire [9:0] ren1_uops_0_fu_code = io_dec_uops_0_fu_code_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_br = io_dec_uops_0_is_br_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_jalr = io_dec_uops_0_is_jalr_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_jal = io_dec_uops_0_is_jal_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_sfb = io_dec_uops_0_is_sfb_0; // @[rename-stage.scala:101:29, :160:7]
wire [15:0] ren1_uops_0_br_mask = io_dec_uops_0_br_mask_0; // @[rename-stage.scala:101:29, :160:7]
wire [3:0] ren1_uops_0_br_tag = io_dec_uops_0_br_tag_0; // @[rename-stage.scala:101:29, :160:7]
wire [4:0] ren1_uops_0_ftq_idx = io_dec_uops_0_ftq_idx_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_edge_inst = io_dec_uops_0_edge_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_pc_lob = io_dec_uops_0_pc_lob_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_taken = io_dec_uops_0_taken_0; // @[rename-stage.scala:101:29, :160:7]
wire [19:0] ren1_uops_0_imm_packed = io_dec_uops_0_imm_packed_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_exception = io_dec_uops_0_exception_0; // @[rename-stage.scala:101:29, :160:7]
wire [63:0] ren1_uops_0_exc_cause = io_dec_uops_0_exc_cause_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_bypassable = io_dec_uops_0_bypassable_0; // @[rename-stage.scala:101:29, :160:7]
wire [4:0] ren1_uops_0_mem_cmd = io_dec_uops_0_mem_cmd_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_mem_size = io_dec_uops_0_mem_size_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_mem_signed = io_dec_uops_0_mem_signed_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_fence = io_dec_uops_0_is_fence_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_fencei = io_dec_uops_0_is_fencei_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_amo = io_dec_uops_0_is_amo_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_uses_ldq = io_dec_uops_0_uses_ldq_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_uses_stq = io_dec_uops_0_uses_stq_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_sys_pc2epc = io_dec_uops_0_is_sys_pc2epc_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_unique = io_dec_uops_0_is_unique_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_flush_on_commit = io_dec_uops_0_flush_on_commit_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_ldst = io_dec_uops_0_ldst_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_lrs1 = io_dec_uops_0_lrs1_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_lrs2 = io_dec_uops_0_lrs2_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_lrs3 = io_dec_uops_0_lrs3_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_ldst_val = io_dec_uops_0_ldst_val_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_dst_rtype = io_dec_uops_0_dst_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_lrs1_rtype = io_dec_uops_0_lrs1_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_lrs2_rtype = io_dec_uops_0_lrs2_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_frs3_en = io_dec_uops_0_frs3_en_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_fp_val = io_dec_uops_0_fp_val_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_fp_single = io_dec_uops_0_fp_single_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_xcpt_pf_if = io_dec_uops_0_xcpt_pf_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_xcpt_ae_if = io_dec_uops_0_xcpt_ae_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_bp_debug_if = io_dec_uops_0_bp_debug_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_bp_xcpt_if = io_dec_uops_0_bp_xcpt_if_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_debug_fsrc = io_dec_uops_0_debug_fsrc_0; // @[rename-stage.scala:101:29, :160:7]
wire [6:0] ren1_uops_1_uopc = io_dec_uops_1_uopc_0; // @[rename-stage.scala:101:29, :160:7]
wire [31:0] ren1_uops_1_inst = io_dec_uops_1_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire [31:0] ren1_uops_1_debug_inst = io_dec_uops_1_debug_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_rvc = io_dec_uops_1_is_rvc_0; // @[rename-stage.scala:101:29, :160:7]
wire [39:0] ren1_uops_1_debug_pc = io_dec_uops_1_debug_pc_0; // @[rename-stage.scala:101:29, :160:7]
wire [2:0] ren1_uops_1_iq_type = io_dec_uops_1_iq_type_0; // @[rename-stage.scala:101:29, :160:7]
wire [9:0] ren1_uops_1_fu_code = io_dec_uops_1_fu_code_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_br = io_dec_uops_1_is_br_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_jalr = io_dec_uops_1_is_jalr_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_jal = io_dec_uops_1_is_jal_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_sfb = io_dec_uops_1_is_sfb_0; // @[rename-stage.scala:101:29, :160:7]
wire [15:0] ren1_uops_1_br_mask = io_dec_uops_1_br_mask_0; // @[rename-stage.scala:101:29, :160:7]
wire [3:0] ren1_uops_1_br_tag = io_dec_uops_1_br_tag_0; // @[rename-stage.scala:101:29, :160:7]
wire [4:0] ren1_uops_1_ftq_idx = io_dec_uops_1_ftq_idx_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_edge_inst = io_dec_uops_1_edge_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_1_pc_lob = io_dec_uops_1_pc_lob_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_taken = io_dec_uops_1_taken_0; // @[rename-stage.scala:101:29, :160:7]
wire [19:0] ren1_uops_1_imm_packed = io_dec_uops_1_imm_packed_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_exception = io_dec_uops_1_exception_0; // @[rename-stage.scala:101:29, :160:7]
wire [63:0] ren1_uops_1_exc_cause = io_dec_uops_1_exc_cause_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_bypassable = io_dec_uops_1_bypassable_0; // @[rename-stage.scala:101:29, :160:7]
wire [4:0] ren1_uops_1_mem_cmd = io_dec_uops_1_mem_cmd_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_1_mem_size = io_dec_uops_1_mem_size_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_mem_signed = io_dec_uops_1_mem_signed_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_fence = io_dec_uops_1_is_fence_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_fencei = io_dec_uops_1_is_fencei_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_amo = io_dec_uops_1_is_amo_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_uses_ldq = io_dec_uops_1_uses_ldq_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_uses_stq = io_dec_uops_1_uses_stq_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_sys_pc2epc = io_dec_uops_1_is_sys_pc2epc_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_is_unique = io_dec_uops_1_is_unique_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_flush_on_commit = io_dec_uops_1_flush_on_commit_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_1_ldst = io_dec_uops_1_ldst_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_1_lrs1 = io_dec_uops_1_lrs1_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_1_lrs2 = io_dec_uops_1_lrs2_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_1_lrs3 = io_dec_uops_1_lrs3_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_ldst_val = io_dec_uops_1_ldst_val_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_1_dst_rtype = io_dec_uops_1_dst_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_1_lrs1_rtype = io_dec_uops_1_lrs1_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_1_lrs2_rtype = io_dec_uops_1_lrs2_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_frs3_en = io_dec_uops_1_frs3_en_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_fp_val = io_dec_uops_1_fp_val_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_fp_single = io_dec_uops_1_fp_single_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_xcpt_pf_if = io_dec_uops_1_xcpt_pf_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_xcpt_ae_if = io_dec_uops_1_xcpt_ae_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_bp_debug_if = io_dec_uops_1_bp_debug_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_1_bp_xcpt_if = io_dec_uops_1_bp_xcpt_if_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_1_debug_fsrc = io_dec_uops_1_debug_fsrc_0; // @[rename-stage.scala:101:29, :160:7]
wire [6:0] ren1_uops_2_uopc = io_dec_uops_2_uopc_0; // @[rename-stage.scala:101:29, :160:7]
wire [31:0] ren1_uops_2_inst = io_dec_uops_2_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire [31:0] ren1_uops_2_debug_inst = io_dec_uops_2_debug_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_rvc = io_dec_uops_2_is_rvc_0; // @[rename-stage.scala:101:29, :160:7]
wire [39:0] ren1_uops_2_debug_pc = io_dec_uops_2_debug_pc_0; // @[rename-stage.scala:101:29, :160:7]
wire [2:0] ren1_uops_2_iq_type = io_dec_uops_2_iq_type_0; // @[rename-stage.scala:101:29, :160:7]
wire [9:0] ren1_uops_2_fu_code = io_dec_uops_2_fu_code_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_br = io_dec_uops_2_is_br_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_jalr = io_dec_uops_2_is_jalr_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_jal = io_dec_uops_2_is_jal_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_sfb = io_dec_uops_2_is_sfb_0; // @[rename-stage.scala:101:29, :160:7]
wire [15:0] ren1_uops_2_br_mask = io_dec_uops_2_br_mask_0; // @[rename-stage.scala:101:29, :160:7]
wire [3:0] ren1_uops_2_br_tag = io_dec_uops_2_br_tag_0; // @[rename-stage.scala:101:29, :160:7]
wire [4:0] ren1_uops_2_ftq_idx = io_dec_uops_2_ftq_idx_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_edge_inst = io_dec_uops_2_edge_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_2_pc_lob = io_dec_uops_2_pc_lob_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_taken = io_dec_uops_2_taken_0; // @[rename-stage.scala:101:29, :160:7]
wire [19:0] ren1_uops_2_imm_packed = io_dec_uops_2_imm_packed_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_exception = io_dec_uops_2_exception_0; // @[rename-stage.scala:101:29, :160:7]
wire [63:0] ren1_uops_2_exc_cause = io_dec_uops_2_exc_cause_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_bypassable = io_dec_uops_2_bypassable_0; // @[rename-stage.scala:101:29, :160:7]
wire [4:0] ren1_uops_2_mem_cmd = io_dec_uops_2_mem_cmd_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_2_mem_size = io_dec_uops_2_mem_size_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_mem_signed = io_dec_uops_2_mem_signed_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_fence = io_dec_uops_2_is_fence_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_fencei = io_dec_uops_2_is_fencei_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_amo = io_dec_uops_2_is_amo_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_uses_ldq = io_dec_uops_2_uses_ldq_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_uses_stq = io_dec_uops_2_uses_stq_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_sys_pc2epc = io_dec_uops_2_is_sys_pc2epc_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_is_unique = io_dec_uops_2_is_unique_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_flush_on_commit = io_dec_uops_2_flush_on_commit_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_2_ldst = io_dec_uops_2_ldst_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_2_lrs1 = io_dec_uops_2_lrs1_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_2_lrs2 = io_dec_uops_2_lrs2_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_2_lrs3 = io_dec_uops_2_lrs3_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_ldst_val = io_dec_uops_2_ldst_val_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_2_dst_rtype = io_dec_uops_2_dst_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_2_lrs1_rtype = io_dec_uops_2_lrs1_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_2_lrs2_rtype = io_dec_uops_2_lrs2_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_frs3_en = io_dec_uops_2_frs3_en_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_fp_val = io_dec_uops_2_fp_val_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_fp_single = io_dec_uops_2_fp_single_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_xcpt_pf_if = io_dec_uops_2_xcpt_pf_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_xcpt_ae_if = io_dec_uops_2_xcpt_ae_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_bp_debug_if = io_dec_uops_2_bp_debug_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_2_bp_xcpt_if = io_dec_uops_2_bp_xcpt_if_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_2_debug_fsrc = io_dec_uops_2_debug_fsrc_0; // @[rename-stage.scala:101:29, :160:7]
wire ren2_valids_0; // @[rename-stage.scala:107:29]
wire ren2_valids_1; // @[rename-stage.scala:107:29]
wire ren2_valids_2; // @[rename-stage.scala:107:29]
wire [6:0] io_ren2_uops_0_newuop_uopc; // @[util.scala:73:26]
wire [31:0] io_ren2_uops_0_newuop_inst; // @[util.scala:73:26]
wire [31:0] io_ren2_uops_0_newuop_debug_inst; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_rvc; // @[util.scala:73:26]
wire [39:0] io_ren2_uops_0_newuop_debug_pc; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_iq_type; // @[util.scala:73:26]
wire [9:0] io_ren2_uops_0_newuop_fu_code; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_0_newuop_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_ctrl_op_fcn; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_ctrl_csr_cmd; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ctrl_is_load; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ctrl_is_sta; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_iw_state; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_iw_p1_poisoned; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_iw_p2_poisoned; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_br; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_jalr; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_jal; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_sfb; // @[util.scala:73:26]
wire [15:0] io_ren2_uops_0_newuop_br_mask; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_0_newuop_br_tag; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_ftq_idx; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_edge_inst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_pc_lob; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_taken; // @[util.scala:73:26]
wire [19:0] io_ren2_uops_0_newuop_imm_packed; // @[util.scala:73:26]
wire [11:0] io_ren2_uops_0_newuop_csr_addr; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_0_newuop_rob_idx; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_ldq_idx; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_stq_idx; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_rxq_idx; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_0_newuop_pdst; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_0_newuop_prs1; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_0_newuop_prs2; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_ppred; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_prs1_busy; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_prs2_busy; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ppred_busy; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_0_newuop_stale_pdst; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_exception; // @[util.scala:73:26]
wire [63:0] io_ren2_uops_0_newuop_exc_cause; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_bypassable; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_mem_cmd; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_mem_size; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_mem_signed; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_fence; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_fencei; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_amo; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_uses_ldq; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_uses_stq; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_sys_pc2epc; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_unique; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_flush_on_commit; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_ldst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_lrs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_lrs2; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_lrs3; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ldst_val; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_dst_rtype; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_lrs2_rtype; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_frs3_en; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_fp_val; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_fp_single; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_xcpt_pf_if; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_xcpt_ae_if; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_xcpt_ma_if; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_bp_debug_if; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_debug_fsrc; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_debug_tsrc; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_1_newuop_uopc; // @[util.scala:73:26]
wire [31:0] io_ren2_uops_1_newuop_inst; // @[util.scala:73:26]
wire [31:0] io_ren2_uops_1_newuop_debug_inst; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_rvc; // @[util.scala:73:26]
wire [39:0] io_ren2_uops_1_newuop_debug_pc; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_1_newuop_iq_type; // @[util.scala:73:26]
wire [9:0] io_ren2_uops_1_newuop_fu_code; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_1_newuop_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_1_newuop_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_1_newuop_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_1_newuop_ctrl_op_fcn; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_1_newuop_ctrl_csr_cmd; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_ctrl_is_load; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_ctrl_is_sta; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_iw_state; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_iw_p1_poisoned; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_iw_p2_poisoned; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_br; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_jalr; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_jal; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_sfb; // @[util.scala:73:26]
wire [15:0] io_ren2_uops_1_newuop_br_mask; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_1_newuop_br_tag; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_1_newuop_ftq_idx; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_edge_inst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_1_newuop_pc_lob; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_taken; // @[util.scala:73:26]
wire [19:0] io_ren2_uops_1_newuop_imm_packed; // @[util.scala:73:26]
wire [11:0] io_ren2_uops_1_newuop_csr_addr; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_1_newuop_rob_idx; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_1_newuop_ldq_idx; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_1_newuop_stq_idx; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_rxq_idx; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_1_newuop_pdst; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_1_newuop_prs1; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_1_newuop_prs2; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_1_newuop_ppred; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_prs1_busy; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_prs2_busy; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_ppred_busy; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_1_newuop_stale_pdst; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_exception; // @[util.scala:73:26]
wire [63:0] io_ren2_uops_1_newuop_exc_cause; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_bypassable; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_1_newuop_mem_cmd; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_mem_size; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_mem_signed; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_fence; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_fencei; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_amo; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_uses_ldq; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_uses_stq; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_sys_pc2epc; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_is_unique; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_flush_on_commit; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_1_newuop_ldst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_1_newuop_lrs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_1_newuop_lrs2; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_1_newuop_lrs3; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_ldst_val; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_dst_rtype; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_lrs2_rtype; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_frs3_en; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_fp_val; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_fp_single; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_xcpt_pf_if; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_xcpt_ae_if; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_xcpt_ma_if; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_bp_debug_if; // @[util.scala:73:26]
wire io_ren2_uops_1_newuop_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_debug_fsrc; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_1_newuop_debug_tsrc; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_2_newuop_uopc; // @[util.scala:73:26]
wire [31:0] io_ren2_uops_2_newuop_inst; // @[util.scala:73:26]
wire [31:0] io_ren2_uops_2_newuop_debug_inst; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_rvc; // @[util.scala:73:26]
wire [39:0] io_ren2_uops_2_newuop_debug_pc; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_2_newuop_iq_type; // @[util.scala:73:26]
wire [9:0] io_ren2_uops_2_newuop_fu_code; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_2_newuop_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_2_newuop_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_2_newuop_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_2_newuop_ctrl_op_fcn; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_2_newuop_ctrl_csr_cmd; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_ctrl_is_load; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_ctrl_is_sta; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_iw_state; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_iw_p1_poisoned; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_iw_p2_poisoned; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_br; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_jalr; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_jal; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_sfb; // @[util.scala:73:26]
wire [15:0] io_ren2_uops_2_newuop_br_mask; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_2_newuop_br_tag; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_2_newuop_ftq_idx; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_edge_inst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_2_newuop_pc_lob; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_taken; // @[util.scala:73:26]
wire [19:0] io_ren2_uops_2_newuop_imm_packed; // @[util.scala:73:26]
wire [11:0] io_ren2_uops_2_newuop_csr_addr; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_2_newuop_rob_idx; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_2_newuop_ldq_idx; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_2_newuop_stq_idx; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_rxq_idx; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_2_newuop_pdst; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_2_newuop_prs1; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_2_newuop_prs2; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_2_newuop_ppred; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_prs1_busy; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_prs2_busy; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_ppred_busy; // @[util.scala:73:26]
wire [6:0] io_ren2_uops_2_newuop_stale_pdst; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_exception; // @[util.scala:73:26]
wire [63:0] io_ren2_uops_2_newuop_exc_cause; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_bypassable; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_2_newuop_mem_cmd; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_mem_size; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_mem_signed; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_fence; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_fencei; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_amo; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_uses_ldq; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_uses_stq; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_sys_pc2epc; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_is_unique; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_flush_on_commit; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_2_newuop_ldst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_2_newuop_lrs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_2_newuop_lrs2; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_2_newuop_lrs3; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_ldst_val; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_dst_rtype; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_lrs2_rtype; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_frs3_en; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_fp_val; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_fp_single; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_xcpt_pf_if; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_xcpt_ae_if; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_xcpt_ma_if; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_bp_debug_if; // @[util.scala:73:26]
wire io_ren2_uops_2_newuop_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_debug_fsrc; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_2_newuop_debug_tsrc; // @[util.scala:73:26]
wire io_ren_stalls_0_0; // @[rename-stage.scala:160:7]
wire io_ren_stalls_1_0; // @[rename-stage.scala:160:7]
wire io_ren_stalls_2_0; // @[rename-stage.scala:160:7]
wire io_ren2_mask_0_0; // @[rename-stage.scala:160:7]
wire io_ren2_mask_1_0; // @[rename-stage.scala:160:7]
wire io_ren2_mask_2_0; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_0_ctrl_br_type_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_ctrl_op1_sel_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_ctrl_op2_sel_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_ctrl_imm_sel_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_ctrl_op_fcn_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ctrl_fcn_dw_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_ctrl_csr_cmd_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ctrl_is_load_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ctrl_is_sta_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ctrl_is_std_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_0_uopc_0; // @[rename-stage.scala:160:7]
wire [31:0] io_ren2_uops_0_inst_0; // @[rename-stage.scala:160:7]
wire [31:0] io_ren2_uops_0_debug_inst_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_rvc_0; // @[rename-stage.scala:160:7]
wire [39:0] io_ren2_uops_0_debug_pc_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_iq_type_0; // @[rename-stage.scala:160:7]
wire [9:0] io_ren2_uops_0_fu_code_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_iw_state_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_iw_p1_poisoned_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_iw_p2_poisoned_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_br_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_jalr_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_jal_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_sfb_0; // @[rename-stage.scala:160:7]
wire [15:0] io_ren2_uops_0_br_mask_0; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_0_br_tag_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_ftq_idx_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_edge_inst_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_pc_lob_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_taken_0; // @[rename-stage.scala:160:7]
wire [19:0] io_ren2_uops_0_imm_packed_0; // @[rename-stage.scala:160:7]
wire [11:0] io_ren2_uops_0_csr_addr_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_0_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_rxq_idx_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_0_pdst_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_0_prs1_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_0_prs2_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_ppred; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_prs1_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_prs2_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_0_stale_pdst_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_exception_0; // @[rename-stage.scala:160:7]
wire [63:0] io_ren2_uops_0_exc_cause_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_bypassable_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_mem_cmd_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_mem_size_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_mem_signed_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_fence_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_fencei_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_amo_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_uses_ldq_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_uses_stq_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_sys_pc2epc_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_unique_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_flush_on_commit_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ldst_is_rs1_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_ldst_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_lrs1_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_lrs2_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_lrs3_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ldst_val_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_dst_rtype_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_lrs1_rtype_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_lrs2_rtype_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_frs3_en_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_fp_val_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_fp_single_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_xcpt_pf_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_xcpt_ae_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_xcpt_ma_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_bp_debug_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_bp_xcpt_if_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_debug_fsrc_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_debug_tsrc_0; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_1_ctrl_br_type_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_ctrl_op1_sel_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_1_ctrl_op2_sel_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_1_ctrl_imm_sel_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_1_ctrl_op_fcn_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_ctrl_fcn_dw_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_1_ctrl_csr_cmd_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_ctrl_is_load_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_ctrl_is_sta_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_ctrl_is_std_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_1_uopc_0; // @[rename-stage.scala:160:7]
wire [31:0] io_ren2_uops_1_inst_0; // @[rename-stage.scala:160:7]
wire [31:0] io_ren2_uops_1_debug_inst_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_rvc_0; // @[rename-stage.scala:160:7]
wire [39:0] io_ren2_uops_1_debug_pc_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_1_iq_type_0; // @[rename-stage.scala:160:7]
wire [9:0] io_ren2_uops_1_fu_code_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_iw_state_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_iw_p1_poisoned_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_iw_p2_poisoned_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_br_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_jalr_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_jal_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_sfb_0; // @[rename-stage.scala:160:7]
wire [15:0] io_ren2_uops_1_br_mask_0; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_1_br_tag_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_1_ftq_idx_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_edge_inst_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_1_pc_lob_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_taken_0; // @[rename-stage.scala:160:7]
wire [19:0] io_ren2_uops_1_imm_packed_0; // @[rename-stage.scala:160:7]
wire [11:0] io_ren2_uops_1_csr_addr_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_1_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_1_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_1_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_rxq_idx_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_1_pdst_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_1_prs1_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_1_prs2_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_1_ppred; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_prs1_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_prs2_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_1_stale_pdst_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_exception_0; // @[rename-stage.scala:160:7]
wire [63:0] io_ren2_uops_1_exc_cause_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_bypassable_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_1_mem_cmd_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_mem_size_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_mem_signed_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_fence_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_fencei_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_amo_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_uses_ldq_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_uses_stq_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_sys_pc2epc_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_is_unique_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_flush_on_commit_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_ldst_is_rs1_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_1_ldst_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_1_lrs1_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_1_lrs2_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_1_lrs3_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_ldst_val_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_dst_rtype_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_lrs1_rtype_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_lrs2_rtype_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_frs3_en_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_fp_val_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_fp_single_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_xcpt_pf_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_xcpt_ae_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_xcpt_ma_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_bp_debug_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_1_bp_xcpt_if_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_debug_fsrc_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_1_debug_tsrc_0; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_2_ctrl_br_type_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_ctrl_op1_sel_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_2_ctrl_op2_sel_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_2_ctrl_imm_sel_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_2_ctrl_op_fcn_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_ctrl_fcn_dw_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_2_ctrl_csr_cmd_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_ctrl_is_load_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_ctrl_is_sta_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_ctrl_is_std_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_2_uopc_0; // @[rename-stage.scala:160:7]
wire [31:0] io_ren2_uops_2_inst_0; // @[rename-stage.scala:160:7]
wire [31:0] io_ren2_uops_2_debug_inst_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_rvc_0; // @[rename-stage.scala:160:7]
wire [39:0] io_ren2_uops_2_debug_pc_0; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_2_iq_type_0; // @[rename-stage.scala:160:7]
wire [9:0] io_ren2_uops_2_fu_code_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_iw_state_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_iw_p1_poisoned_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_iw_p2_poisoned_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_br_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_jalr_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_jal_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_sfb_0; // @[rename-stage.scala:160:7]
wire [15:0] io_ren2_uops_2_br_mask_0; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_2_br_tag_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_2_ftq_idx_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_edge_inst_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_2_pc_lob_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_taken_0; // @[rename-stage.scala:160:7]
wire [19:0] io_ren2_uops_2_imm_packed_0; // @[rename-stage.scala:160:7]
wire [11:0] io_ren2_uops_2_csr_addr_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_2_rob_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_2_ldq_idx; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_2_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_rxq_idx_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_2_pdst_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_2_prs1_0; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_2_prs2_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_2_ppred; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_prs1_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_prs2_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_ppred_busy; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_2_stale_pdst_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_exception_0; // @[rename-stage.scala:160:7]
wire [63:0] io_ren2_uops_2_exc_cause_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_bypassable_0; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_2_mem_cmd_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_mem_size_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_mem_signed_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_fence_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_fencei_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_amo_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_uses_ldq_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_uses_stq_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_sys_pc2epc_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_is_unique_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_flush_on_commit_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_ldst_is_rs1_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_2_ldst_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_2_lrs1_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_2_lrs2_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_2_lrs3_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_ldst_val_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_dst_rtype_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_lrs1_rtype_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_lrs2_rtype_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_frs3_en_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_fp_val_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_fp_single_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_xcpt_pf_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_xcpt_ae_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_xcpt_ma_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_bp_debug_if_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_2_bp_xcpt_if_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_debug_fsrc_0; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_2_debug_tsrc_0; // @[rename-stage.scala:160:7]
wire [99:0] io_debug_freelist; // @[rename-stage.scala:160:7]
wire [99:0] io_debug_busytable; // @[rename-stage.scala:160:7]
wire [5:0] map_reqs_0_ldst = ren1_uops_0_ldst; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_0_lrs1 = ren1_uops_0_lrs1; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_0_lrs2 = ren1_uops_0_lrs2; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_0_lrs3 = ren1_uops_0_lrs3; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_1_ldst = ren1_uops_1_ldst; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_1_lrs1 = ren1_uops_1_lrs1; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_1_lrs2 = ren1_uops_1_lrs2; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_1_lrs3 = ren1_uops_1_lrs3; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_2_ldst = ren1_uops_2_ldst; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_2_lrs1 = ren1_uops_2_lrs1; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_2_lrs2 = ren1_uops_2_lrs2; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_2_lrs3 = ren1_uops_2_lrs3; // @[rename-stage.scala:101:29, :252:24]
wire [6:0] ren1_uops_0_prs1; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_0_prs2; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_0_stale_pdst; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_1_prs1; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_1_prs2; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_1_stale_pdst; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_2_prs1; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_2_prs2; // @[rename-stage.scala:101:29]
wire [6:0] ren1_uops_2_stale_pdst; // @[rename-stage.scala:101:29]
assign io_ren2_mask_0_0 = ren2_valids_0; // @[rename-stage.scala:107:29, :160:7]
assign io_ren2_mask_1_0 = ren2_valids_1; // @[rename-stage.scala:107:29, :160:7]
assign io_ren2_mask_2_0 = ren2_valids_2; // @[rename-stage.scala:107:29, :160:7]
wire [6:0] bypassed_uop_uopc = ren2_uops_0_uopc; // @[rename-stage.scala:108:29, :341:28]
wire [31:0] bypassed_uop_inst = ren2_uops_0_inst; // @[rename-stage.scala:108:29, :341:28]
wire [31:0] bypassed_uop_debug_inst = ren2_uops_0_debug_inst; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_rvc = ren2_uops_0_is_rvc; // @[rename-stage.scala:108:29, :341:28]
wire [39:0] bypassed_uop_debug_pc = ren2_uops_0_debug_pc; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_iq_type = ren2_uops_0_iq_type; // @[rename-stage.scala:108:29, :341:28]
wire [9:0] bypassed_uop_fu_code = ren2_uops_0_fu_code; // @[rename-stage.scala:108:29, :341:28]
wire [3:0] bypassed_uop_ctrl_br_type = ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_ctrl_op1_sel = ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_ctrl_op2_sel = ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_ctrl_imm_sel = ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:108:29, :341:28]
wire [4:0] bypassed_uop_ctrl_op_fcn = ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ctrl_fcn_dw = ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_ctrl_csr_cmd = ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ctrl_is_load = ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ctrl_is_sta = ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ctrl_is_std = ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_iw_state = ren2_uops_0_iw_state; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_iw_p1_poisoned = ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_iw_p2_poisoned = ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_br = ren2_uops_0_is_br; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_jalr = ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_jal = ren2_uops_0_is_jal; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_sfb = ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29, :341:28]
wire [15:0] bypassed_uop_br_mask = ren2_uops_0_br_mask; // @[rename-stage.scala:108:29, :341:28]
wire [3:0] ren2_br_tags_0_bits = ren2_uops_0_br_tag; // @[rename-stage.scala:108:29, :233:29]
wire [3:0] bypassed_uop_br_tag = ren2_uops_0_br_tag; // @[rename-stage.scala:108:29, :341:28]
wire [4:0] bypassed_uop_ftq_idx = ren2_uops_0_ftq_idx; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_edge_inst = ren2_uops_0_edge_inst; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_pc_lob = ren2_uops_0_pc_lob; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_taken = ren2_uops_0_taken; // @[rename-stage.scala:108:29, :341:28]
wire [19:0] bypassed_uop_imm_packed = ren2_uops_0_imm_packed; // @[rename-stage.scala:108:29, :341:28]
wire [11:0] bypassed_uop_csr_addr = ren2_uops_0_csr_addr; // @[rename-stage.scala:108:29, :341:28]
wire [6:0] bypassed_uop_rob_idx = ren2_uops_0_rob_idx; // @[rename-stage.scala:108:29, :341:28]
wire [4:0] bypassed_uop_ldq_idx = ren2_uops_0_ldq_idx; // @[rename-stage.scala:108:29, :341:28]
wire [4:0] bypassed_uop_stq_idx = ren2_uops_0_stq_idx; // @[rename-stage.scala:108:29, :341:28]
wire [6:0] _ren2_uops_0_pdst_T_2; // @[rename-stage.scala:306:20]
wire [1:0] bypassed_uop_rxq_idx = ren2_uops_0_rxq_idx; // @[rename-stage.scala:108:29, :341:28]
wire [6:0] bypassed_uop_pdst = ren2_uops_0_pdst; // @[rename-stage.scala:108:29, :341:28]
wire [6:0] bypassed_uop_prs1 = ren2_uops_0_prs1; // @[rename-stage.scala:108:29, :341:28]
wire [6:0] bypassed_uop_prs2 = ren2_uops_0_prs2; // @[rename-stage.scala:108:29, :341:28]
wire _ren2_uops_0_prs1_busy_T_1; // @[rename-stage.scala:323:47]
wire [4:0] bypassed_uop_ppred = ren2_uops_0_ppred; // @[rename-stage.scala:108:29, :341:28]
wire _ren2_uops_0_prs2_busy_T_1; // @[rename-stage.scala:324:47]
wire bypassed_uop_prs1_busy = ren2_uops_0_prs1_busy; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_prs2_busy = ren2_uops_0_prs2_busy; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ppred_busy = ren2_uops_0_ppred_busy; // @[rename-stage.scala:108:29, :341:28]
wire [6:0] bypassed_uop_stale_pdst = ren2_uops_0_stale_pdst; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_exception = ren2_uops_0_exception; // @[rename-stage.scala:108:29, :341:28]
wire [63:0] bypassed_uop_exc_cause = ren2_uops_0_exc_cause; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_bypassable = ren2_uops_0_bypassable; // @[rename-stage.scala:108:29, :341:28]
wire [4:0] bypassed_uop_mem_cmd = ren2_uops_0_mem_cmd; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_mem_size = ren2_uops_0_mem_size; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_mem_signed = ren2_uops_0_mem_signed; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_fence = ren2_uops_0_is_fence; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_fencei = ren2_uops_0_is_fencei; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_amo = ren2_uops_0_is_amo; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_uses_ldq = ren2_uops_0_uses_ldq; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_uses_stq = ren2_uops_0_uses_stq; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_sys_pc2epc = ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_unique = ren2_uops_0_is_unique; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_flush_on_commit = ren2_uops_0_flush_on_commit; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ldst_is_rs1 = ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_ldst = ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_lrs1 = ren2_uops_0_lrs1; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_lrs2 = ren2_uops_0_lrs2; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_lrs3 = ren2_uops_0_lrs3; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ldst_val = ren2_uops_0_ldst_val; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_dst_rtype = ren2_uops_0_dst_rtype; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_lrs1_rtype = ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_lrs2_rtype = ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_frs3_en = ren2_uops_0_frs3_en; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_fp_val = ren2_uops_0_fp_val; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_fp_single = ren2_uops_0_fp_single; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_xcpt_pf_if = ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_xcpt_ae_if = ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_xcpt_ma_if = ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_bp_debug_if = ren2_uops_0_bp_debug_if; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_bp_xcpt_if = ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_debug_fsrc = ren2_uops_0_debug_fsrc; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_debug_tsrc = ren2_uops_0_debug_tsrc; // @[rename-stage.scala:108:29, :341:28]
wire [6:0] bypassed_uop_bypassed_uop_uopc = ren2_uops_1_uopc; // @[rename-stage.scala:108:29, :174:28]
wire [31:0] bypassed_uop_bypassed_uop_inst = ren2_uops_1_inst; // @[rename-stage.scala:108:29, :174:28]
wire [31:0] bypassed_uop_bypassed_uop_debug_inst = ren2_uops_1_debug_inst; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_rvc = ren2_uops_1_is_rvc; // @[rename-stage.scala:108:29, :174:28]
wire [39:0] bypassed_uop_bypassed_uop_debug_pc = ren2_uops_1_debug_pc; // @[rename-stage.scala:108:29, :174:28]
wire [2:0] bypassed_uop_bypassed_uop_iq_type = ren2_uops_1_iq_type; // @[rename-stage.scala:108:29, :174:28]
wire [9:0] bypassed_uop_bypassed_uop_fu_code = ren2_uops_1_fu_code; // @[rename-stage.scala:108:29, :174:28]
wire [3:0] bypassed_uop_bypassed_uop_ctrl_br_type = ren2_uops_1_ctrl_br_type; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_ctrl_op1_sel = ren2_uops_1_ctrl_op1_sel; // @[rename-stage.scala:108:29, :174:28]
wire [2:0] bypassed_uop_bypassed_uop_ctrl_op2_sel = ren2_uops_1_ctrl_op2_sel; // @[rename-stage.scala:108:29, :174:28]
wire [2:0] bypassed_uop_bypassed_uop_ctrl_imm_sel = ren2_uops_1_ctrl_imm_sel; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_ctrl_op_fcn = ren2_uops_1_ctrl_op_fcn; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_ctrl_fcn_dw = ren2_uops_1_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :174:28]
wire [2:0] bypassed_uop_bypassed_uop_ctrl_csr_cmd = ren2_uops_1_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_ctrl_is_load = ren2_uops_1_ctrl_is_load; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_ctrl_is_sta = ren2_uops_1_ctrl_is_sta; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_ctrl_is_std = ren2_uops_1_ctrl_is_std; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_iw_state = ren2_uops_1_iw_state; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_iw_p1_poisoned = ren2_uops_1_iw_p1_poisoned; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_iw_p2_poisoned = ren2_uops_1_iw_p2_poisoned; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_br = ren2_uops_1_is_br; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_jalr = ren2_uops_1_is_jalr; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_jal = ren2_uops_1_is_jal; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_sfb = ren2_uops_1_is_sfb; // @[rename-stage.scala:108:29, :174:28]
wire [15:0] bypassed_uop_bypassed_uop_br_mask = ren2_uops_1_br_mask; // @[rename-stage.scala:108:29, :174:28]
wire [3:0] ren2_br_tags_1_bits = ren2_uops_1_br_tag; // @[rename-stage.scala:108:29, :233:29]
wire [3:0] bypassed_uop_bypassed_uop_br_tag = ren2_uops_1_br_tag; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_ftq_idx = ren2_uops_1_ftq_idx; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_edge_inst = ren2_uops_1_edge_inst; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_pc_lob = ren2_uops_1_pc_lob; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_taken = ren2_uops_1_taken; // @[rename-stage.scala:108:29, :174:28]
wire [19:0] bypassed_uop_bypassed_uop_imm_packed = ren2_uops_1_imm_packed; // @[rename-stage.scala:108:29, :174:28]
wire [11:0] bypassed_uop_bypassed_uop_csr_addr = ren2_uops_1_csr_addr; // @[rename-stage.scala:108:29, :174:28]
wire [6:0] bypassed_uop_bypassed_uop_rob_idx = ren2_uops_1_rob_idx; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_ldq_idx = ren2_uops_1_ldq_idx; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_stq_idx = ren2_uops_1_stq_idx; // @[rename-stage.scala:108:29, :174:28]
wire [6:0] _ren2_uops_1_pdst_T_2; // @[rename-stage.scala:306:20]
wire [1:0] bypassed_uop_bypassed_uop_rxq_idx = ren2_uops_1_rxq_idx; // @[rename-stage.scala:108:29, :174:28]
wire [6:0] bypassed_uop_bypassed_uop_pdst = ren2_uops_1_pdst; // @[rename-stage.scala:108:29, :174:28]
wire _ren2_uops_1_prs1_busy_T_1; // @[rename-stage.scala:323:47]
wire [4:0] bypassed_uop_bypassed_uop_ppred = ren2_uops_1_ppred; // @[rename-stage.scala:108:29, :174:28]
wire _ren2_uops_1_prs2_busy_T_1; // @[rename-stage.scala:324:47]
wire bypassed_uop_bypassed_uop_ppred_busy = ren2_uops_1_ppred_busy; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_exception = ren2_uops_1_exception; // @[rename-stage.scala:108:29, :174:28]
wire [63:0] bypassed_uop_bypassed_uop_exc_cause = ren2_uops_1_exc_cause; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_bypassable = ren2_uops_1_bypassable; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_mem_cmd = ren2_uops_1_mem_cmd; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_mem_size = ren2_uops_1_mem_size; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_mem_signed = ren2_uops_1_mem_signed; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_fence = ren2_uops_1_is_fence; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_fencei = ren2_uops_1_is_fencei; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_amo = ren2_uops_1_is_amo; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_uses_ldq = ren2_uops_1_uses_ldq; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_uses_stq = ren2_uops_1_uses_stq; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_sys_pc2epc = ren2_uops_1_is_sys_pc2epc; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_is_unique = ren2_uops_1_is_unique; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_flush_on_commit = ren2_uops_1_flush_on_commit; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_ldst_is_rs1 = ren2_uops_1_ldst_is_rs1; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_ldst = ren2_uops_1_ldst; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_lrs1 = ren2_uops_1_lrs1; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_lrs2 = ren2_uops_1_lrs2; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_lrs3 = ren2_uops_1_lrs3; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_ldst_val = ren2_uops_1_ldst_val; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_dst_rtype = ren2_uops_1_dst_rtype; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_lrs1_rtype = ren2_uops_1_lrs1_rtype; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_lrs2_rtype = ren2_uops_1_lrs2_rtype; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_frs3_en = ren2_uops_1_frs3_en; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_fp_val = ren2_uops_1_fp_val; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_fp_single = ren2_uops_1_fp_single; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_xcpt_pf_if = ren2_uops_1_xcpt_pf_if; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_xcpt_ae_if = ren2_uops_1_xcpt_ae_if; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_xcpt_ma_if = ren2_uops_1_xcpt_ma_if; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_bp_debug_if = ren2_uops_1_bp_debug_if; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_bp_xcpt_if = ren2_uops_1_bp_xcpt_if; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_debug_fsrc = ren2_uops_1_debug_fsrc; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_debug_tsrc = ren2_uops_1_debug_tsrc; // @[rename-stage.scala:108:29, :174:28]
wire [6:0] bypassed_uop_bypassed_uop_1_uopc = ren2_uops_2_uopc; // @[rename-stage.scala:108:29, :174:28]
wire [31:0] bypassed_uop_bypassed_uop_1_inst = ren2_uops_2_inst; // @[rename-stage.scala:108:29, :174:28]
wire [31:0] bypassed_uop_bypassed_uop_1_debug_inst = ren2_uops_2_debug_inst; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_rvc = ren2_uops_2_is_rvc; // @[rename-stage.scala:108:29, :174:28]
wire [39:0] bypassed_uop_bypassed_uop_1_debug_pc = ren2_uops_2_debug_pc; // @[rename-stage.scala:108:29, :174:28]
wire [2:0] bypassed_uop_bypassed_uop_1_iq_type = ren2_uops_2_iq_type; // @[rename-stage.scala:108:29, :174:28]
wire [9:0] bypassed_uop_bypassed_uop_1_fu_code = ren2_uops_2_fu_code; // @[rename-stage.scala:108:29, :174:28]
wire [3:0] bypassed_uop_bypassed_uop_1_ctrl_br_type = ren2_uops_2_ctrl_br_type; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_1_ctrl_op1_sel = ren2_uops_2_ctrl_op1_sel; // @[rename-stage.scala:108:29, :174:28]
wire [2:0] bypassed_uop_bypassed_uop_1_ctrl_op2_sel = ren2_uops_2_ctrl_op2_sel; // @[rename-stage.scala:108:29, :174:28]
wire [2:0] bypassed_uop_bypassed_uop_1_ctrl_imm_sel = ren2_uops_2_ctrl_imm_sel; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_1_ctrl_op_fcn = ren2_uops_2_ctrl_op_fcn; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_ctrl_fcn_dw = ren2_uops_2_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :174:28]
wire [2:0] bypassed_uop_bypassed_uop_1_ctrl_csr_cmd = ren2_uops_2_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_ctrl_is_load = ren2_uops_2_ctrl_is_load; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_ctrl_is_sta = ren2_uops_2_ctrl_is_sta; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_ctrl_is_std = ren2_uops_2_ctrl_is_std; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_1_iw_state = ren2_uops_2_iw_state; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_iw_p1_poisoned = ren2_uops_2_iw_p1_poisoned; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_iw_p2_poisoned = ren2_uops_2_iw_p2_poisoned; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_br = ren2_uops_2_is_br; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_jalr = ren2_uops_2_is_jalr; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_jal = ren2_uops_2_is_jal; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_sfb = ren2_uops_2_is_sfb; // @[rename-stage.scala:108:29, :174:28]
wire [15:0] bypassed_uop_bypassed_uop_1_br_mask = ren2_uops_2_br_mask; // @[rename-stage.scala:108:29, :174:28]
wire [3:0] ren2_br_tags_2_bits = ren2_uops_2_br_tag; // @[rename-stage.scala:108:29, :233:29]
wire [3:0] bypassed_uop_bypassed_uop_1_br_tag = ren2_uops_2_br_tag; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_1_ftq_idx = ren2_uops_2_ftq_idx; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_edge_inst = ren2_uops_2_edge_inst; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_1_pc_lob = ren2_uops_2_pc_lob; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_taken = ren2_uops_2_taken; // @[rename-stage.scala:108:29, :174:28]
wire [19:0] bypassed_uop_bypassed_uop_1_imm_packed = ren2_uops_2_imm_packed; // @[rename-stage.scala:108:29, :174:28]
wire [11:0] bypassed_uop_bypassed_uop_1_csr_addr = ren2_uops_2_csr_addr; // @[rename-stage.scala:108:29, :174:28]
wire [6:0] bypassed_uop_bypassed_uop_1_rob_idx = ren2_uops_2_rob_idx; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_1_ldq_idx = ren2_uops_2_ldq_idx; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_1_stq_idx = ren2_uops_2_stq_idx; // @[rename-stage.scala:108:29, :174:28]
wire [6:0] _ren2_uops_2_pdst_T_2; // @[rename-stage.scala:306:20]
wire [1:0] bypassed_uop_bypassed_uop_1_rxq_idx = ren2_uops_2_rxq_idx; // @[rename-stage.scala:108:29, :174:28]
wire [6:0] bypassed_uop_bypassed_uop_1_pdst = ren2_uops_2_pdst; // @[rename-stage.scala:108:29, :174:28]
wire _ren2_uops_2_prs1_busy_T_1; // @[rename-stage.scala:323:47]
wire [4:0] bypassed_uop_bypassed_uop_1_ppred = ren2_uops_2_ppred; // @[rename-stage.scala:108:29, :174:28]
wire _ren2_uops_2_prs2_busy_T_1; // @[rename-stage.scala:324:47]
wire bypassed_uop_bypassed_uop_1_ppred_busy = ren2_uops_2_ppred_busy; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_exception = ren2_uops_2_exception; // @[rename-stage.scala:108:29, :174:28]
wire [63:0] bypassed_uop_bypassed_uop_1_exc_cause = ren2_uops_2_exc_cause; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_bypassable = ren2_uops_2_bypassable; // @[rename-stage.scala:108:29, :174:28]
wire [4:0] bypassed_uop_bypassed_uop_1_mem_cmd = ren2_uops_2_mem_cmd; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_1_mem_size = ren2_uops_2_mem_size; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_mem_signed = ren2_uops_2_mem_signed; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_fence = ren2_uops_2_is_fence; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_fencei = ren2_uops_2_is_fencei; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_amo = ren2_uops_2_is_amo; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_uses_ldq = ren2_uops_2_uses_ldq; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_uses_stq = ren2_uops_2_uses_stq; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_sys_pc2epc = ren2_uops_2_is_sys_pc2epc; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_is_unique = ren2_uops_2_is_unique; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_flush_on_commit = ren2_uops_2_flush_on_commit; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_ldst_is_rs1 = ren2_uops_2_ldst_is_rs1; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_1_ldst = ren2_uops_2_ldst; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_1_lrs1 = ren2_uops_2_lrs1; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_1_lrs2 = ren2_uops_2_lrs2; // @[rename-stage.scala:108:29, :174:28]
wire [5:0] bypassed_uop_bypassed_uop_1_lrs3 = ren2_uops_2_lrs3; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_ldst_val = ren2_uops_2_ldst_val; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_1_dst_rtype = ren2_uops_2_dst_rtype; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_1_lrs1_rtype = ren2_uops_2_lrs1_rtype; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_1_lrs2_rtype = ren2_uops_2_lrs2_rtype; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_frs3_en = ren2_uops_2_frs3_en; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_fp_val = ren2_uops_2_fp_val; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_fp_single = ren2_uops_2_fp_single; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_xcpt_pf_if = ren2_uops_2_xcpt_pf_if; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_xcpt_ae_if = ren2_uops_2_xcpt_ae_if; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_xcpt_ma_if = ren2_uops_2_xcpt_ma_if; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_bp_debug_if = ren2_uops_2_bp_debug_if; // @[rename-stage.scala:108:29, :174:28]
wire bypassed_uop_bypassed_uop_1_bp_xcpt_if = ren2_uops_2_bp_xcpt_if; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_1_debug_fsrc = ren2_uops_2_debug_fsrc; // @[rename-stage.scala:108:29, :174:28]
wire [1:0] bypassed_uop_bypassed_uop_1_debug_tsrc = ren2_uops_2_debug_tsrc; // @[rename-stage.scala:108:29, :174:28]
wire [6:0] ren2_uops_1_prs1; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_1_prs2; // @[rename-stage.scala:108:29]
wire ren2_uops_1_prs1_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_1_prs2_busy; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_1_stale_pdst; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_2_prs1; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_2_prs2; // @[rename-stage.scala:108:29]
wire ren2_uops_2_prs1_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_2_prs2_busy; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_2_stale_pdst; // @[rename-stage.scala:108:29]
wire _ren2_alloc_reqs_0_T_2; // @[rename-stage.scala:240:88]
wire _ren2_alloc_reqs_1_T_2; // @[rename-stage.scala:240:88]
wire _ren2_alloc_reqs_2_T_2; // @[rename-stage.scala:240:88]
wire ren2_alloc_reqs_0; // @[rename-stage.scala:109:29]
wire ren2_alloc_reqs_1; // @[rename-stage.scala:109:29]
wire ren2_alloc_reqs_2; // @[rename-stage.scala:109:29]
reg r_valid; // @[rename-stage.scala:121:27]
assign ren2_valids_0 = r_valid; // @[rename-stage.scala:107:29, :121:27]
reg [6:0] r_uop_uopc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uopc = r_uop_uopc; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_inst = r_uop_inst; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_debug_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_inst = r_uop_debug_inst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_rvc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_rvc = r_uop_is_rvc; // @[rename-stage.scala:108:29, :122:23]
reg [39:0] r_uop_debug_pc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_pc = r_uop_debug_pc; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_iq_type; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iq_type = r_uop_iq_type; // @[rename-stage.scala:108:29, :122:23]
reg [9:0] r_uop_fu_code; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fu_code = r_uop_fu_code; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_ctrl_br_type; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_br_type = r_uop_ctrl_br_type; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_ctrl_op1_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op1_sel = r_uop_ctrl_op1_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_op2_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op2_sel = r_uop_ctrl_op2_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_imm_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_imm_sel = r_uop_ctrl_imm_sel; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_ctrl_op_fcn; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op_fcn = r_uop_ctrl_op_fcn; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_fcn_dw; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_fcn_dw = r_uop_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_csr_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_csr_cmd = r_uop_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_load; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_load = r_uop_ctrl_is_load; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_sta; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_sta = r_uop_ctrl_is_sta; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_std; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_std = r_uop_ctrl_is_std; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_iw_state; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_state = r_uop_iw_state; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_iw_p1_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_p1_poisoned = r_uop_iw_p1_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_iw_p2_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_p2_poisoned = r_uop_iw_p2_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_br; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_br = r_uop_is_br; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_jalr; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_jalr = r_uop_is_jalr; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_jal; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_jal = r_uop_is_jal; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_sfb; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_sfb = r_uop_is_sfb; // @[rename-stage.scala:108:29, :122:23]
reg [15:0] r_uop_br_mask; // @[rename-stage.scala:122:23]
assign ren2_uops_0_br_mask = r_uop_br_mask; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_br_tag; // @[rename-stage.scala:122:23]
assign ren2_uops_0_br_tag = r_uop_br_tag; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_ftq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ftq_idx = r_uop_ftq_idx; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_edge_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_edge_inst = r_uop_edge_inst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_pc_lob; // @[rename-stage.scala:122:23]
assign ren2_uops_0_pc_lob = r_uop_pc_lob; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_taken; // @[rename-stage.scala:122:23]
assign ren2_uops_0_taken = r_uop_taken; // @[rename-stage.scala:108:29, :122:23]
reg [19:0] r_uop_imm_packed; // @[rename-stage.scala:122:23]
assign ren2_uops_0_imm_packed = r_uop_imm_packed; // @[rename-stage.scala:108:29, :122:23]
reg [11:0] r_uop_csr_addr; // @[rename-stage.scala:122:23]
assign ren2_uops_0_csr_addr = r_uop_csr_addr; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_rob_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_rob_idx = r_uop_rob_idx; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_ldq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldq_idx = r_uop_ldq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_stq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_stq_idx = r_uop_stq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_rxq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_rxq_idx = r_uop_rxq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_pdst; // @[rename-stage.scala:122:23]
reg [6:0] r_uop_prs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs1 = r_uop_prs1; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_prs2; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs2 = r_uop_prs2; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_ppred; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ppred = r_uop_ppred; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_prs1_busy; // @[rename-stage.scala:122:23]
reg r_uop_prs2_busy; // @[rename-stage.scala:122:23]
reg r_uop_ppred_busy; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ppred_busy = r_uop_ppred_busy; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_stale_pdst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_stale_pdst = r_uop_stale_pdst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_exception; // @[rename-stage.scala:122:23]
assign ren2_uops_0_exception = r_uop_exception; // @[rename-stage.scala:108:29, :122:23]
reg [63:0] r_uop_exc_cause; // @[rename-stage.scala:122:23]
assign ren2_uops_0_exc_cause = r_uop_exc_cause; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bypassable; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bypassable = r_uop_bypassable; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_mem_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_cmd = r_uop_mem_cmd; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_mem_size; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_size = r_uop_mem_size; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_mem_signed; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_signed = r_uop_mem_signed; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_fence; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_fence = r_uop_is_fence; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_fencei; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_fencei = r_uop_is_fencei; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_amo; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_amo = r_uop_is_amo; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_uses_ldq; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uses_ldq = r_uop_uses_ldq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_uses_stq; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uses_stq = r_uop_uses_stq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_sys_pc2epc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_sys_pc2epc = r_uop_is_sys_pc2epc; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_unique; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_unique = r_uop_is_unique; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_flush_on_commit; // @[rename-stage.scala:122:23]
assign ren2_uops_0_flush_on_commit = r_uop_flush_on_commit; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ldst_is_rs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst_is_rs1 = r_uop_ldst_is_rs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_ldst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst = r_uop_ldst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs1 = r_uop_lrs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs2; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs2 = r_uop_lrs2; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs3; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs3 = r_uop_lrs3; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ldst_val; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst_val = r_uop_ldst_val; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_dst_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_dst_rtype = r_uop_dst_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_lrs1_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs1_rtype = r_uop_lrs1_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_lrs2_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs2_rtype = r_uop_lrs2_rtype; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_frs3_en; // @[rename-stage.scala:122:23]
assign ren2_uops_0_frs3_en = r_uop_frs3_en; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_fp_val; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fp_val = r_uop_fp_val; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_fp_single; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fp_single = r_uop_fp_single; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_pf_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_pf_if = r_uop_xcpt_pf_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_ae_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_ae_if = r_uop_xcpt_ae_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_ma_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_ma_if = r_uop_xcpt_ma_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bp_debug_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bp_debug_if = r_uop_bp_debug_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bp_xcpt_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bp_xcpt_if = r_uop_bp_xcpt_if; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_debug_fsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_fsrc = r_uop_debug_fsrc; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_debug_tsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_tsrc = r_uop_debug_tsrc; // @[rename-stage.scala:108:29, :122:23]
wire [6:0] r_uop_bypassed_uop_uopc = next_uop_uopc; // @[rename-stage.scala:123:24, :174:28]
wire [31:0] r_uop_bypassed_uop_inst = next_uop_inst; // @[rename-stage.scala:123:24, :174:28]
wire [31:0] r_uop_bypassed_uop_debug_inst = next_uop_debug_inst; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_rvc = next_uop_is_rvc; // @[rename-stage.scala:123:24, :174:28]
wire [39:0] r_uop_bypassed_uop_debug_pc = next_uop_debug_pc; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_iq_type = next_uop_iq_type; // @[rename-stage.scala:123:24, :174:28]
wire [9:0] r_uop_bypassed_uop_fu_code = next_uop_fu_code; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_ctrl_br_type = next_uop_ctrl_br_type; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_ctrl_op1_sel = next_uop_ctrl_op1_sel; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_ctrl_op2_sel = next_uop_ctrl_op2_sel; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_ctrl_imm_sel = next_uop_ctrl_imm_sel; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_ctrl_op_fcn = next_uop_ctrl_op_fcn; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ctrl_fcn_dw = next_uop_ctrl_fcn_dw; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_ctrl_csr_cmd = next_uop_ctrl_csr_cmd; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ctrl_is_load = next_uop_ctrl_is_load; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ctrl_is_sta = next_uop_ctrl_is_sta; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ctrl_is_std = next_uop_ctrl_is_std; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_iw_state = next_uop_iw_state; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_iw_p1_poisoned = next_uop_iw_p1_poisoned; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_iw_p2_poisoned = next_uop_iw_p2_poisoned; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_br = next_uop_is_br; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_jalr = next_uop_is_jalr; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_jal = next_uop_is_jal; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_sfb = next_uop_is_sfb; // @[rename-stage.scala:123:24, :174:28]
wire [15:0] r_uop_bypassed_uop_br_mask = next_uop_br_mask; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_br_tag = next_uop_br_tag; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_ftq_idx = next_uop_ftq_idx; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_edge_inst = next_uop_edge_inst; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_pc_lob = next_uop_pc_lob; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_taken = next_uop_taken; // @[rename-stage.scala:123:24, :174:28]
wire [19:0] r_uop_bypassed_uop_imm_packed = next_uop_imm_packed; // @[rename-stage.scala:123:24, :174:28]
wire [11:0] r_uop_bypassed_uop_csr_addr = next_uop_csr_addr; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] r_uop_bypassed_uop_rob_idx = next_uop_rob_idx; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_ldq_idx = next_uop_ldq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_stq_idx = next_uop_stq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_rxq_idx = next_uop_rxq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] r_uop_bypassed_uop_pdst = next_uop_pdst; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_ppred = next_uop_ppred; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ppred_busy = next_uop_ppred_busy; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_exception = next_uop_exception; // @[rename-stage.scala:123:24, :174:28]
wire [63:0] r_uop_bypassed_uop_exc_cause = next_uop_exc_cause; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_bypassable = next_uop_bypassable; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_mem_cmd = next_uop_mem_cmd; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_mem_size = next_uop_mem_size; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_mem_signed = next_uop_mem_signed; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_fence = next_uop_is_fence; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_fencei = next_uop_is_fencei; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_amo = next_uop_is_amo; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_uses_ldq = next_uop_uses_ldq; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_uses_stq = next_uop_uses_stq; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_sys_pc2epc = next_uop_is_sys_pc2epc; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_unique = next_uop_is_unique; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_flush_on_commit = next_uop_flush_on_commit; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ldst_is_rs1 = next_uop_ldst_is_rs1; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_ldst = next_uop_ldst; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_lrs1 = next_uop_lrs1; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_lrs2 = next_uop_lrs2; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_lrs3 = next_uop_lrs3; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ldst_val = next_uop_ldst_val; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_dst_rtype = next_uop_dst_rtype; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_lrs1_rtype = next_uop_lrs1_rtype; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_lrs2_rtype = next_uop_lrs2_rtype; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_frs3_en = next_uop_frs3_en; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_fp_val = next_uop_fp_val; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_fp_single = next_uop_fp_single; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_xcpt_pf_if = next_uop_xcpt_pf_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_xcpt_ae_if = next_uop_xcpt_ae_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_xcpt_ma_if = next_uop_xcpt_ma_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_bp_debug_if = next_uop_bp_debug_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_bp_xcpt_if = next_uop_bp_xcpt_if; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_debug_fsrc = next_uop_debug_fsrc; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_debug_tsrc = next_uop_debug_tsrc; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] next_uop_prs1; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_prs2; // @[rename-stage.scala:123:24]
wire next_uop_prs1_busy; // @[rename-stage.scala:123:24]
wire next_uop_prs2_busy; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_stale_pdst; // @[rename-stage.scala:123:24]
wire _r_valid_T = ~io_dis_fire_0_0; // @[rename-stage.scala:133:29, :160:7]
wire _r_valid_T_1 = r_valid & _r_valid_T; // @[rename-stage.scala:121:27, :133:{26,29}]
wire _GEN = io_kill_0 | ~io_dis_ready_0; // @[rename-stage.scala:125:14, :127:20, :129:30, :160:7]
assign next_uop_uopc = _GEN ? r_uop_uopc : ren1_uops_0_uopc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_inst = _GEN ? r_uop_inst : ren1_uops_0_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_inst = _GEN ? r_uop_debug_inst : ren1_uops_0_debug_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_rvc = _GEN ? r_uop_is_rvc : ren1_uops_0_is_rvc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_pc = _GEN ? r_uop_debug_pc : ren1_uops_0_debug_pc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iq_type = _GEN ? r_uop_iq_type : ren1_uops_0_iq_type; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fu_code = _GEN ? r_uop_fu_code : ren1_uops_0_fu_code; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_br_type = _GEN ? r_uop_ctrl_br_type : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op1_sel = _GEN ? r_uop_ctrl_op1_sel : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op2_sel = _GEN ? r_uop_ctrl_op2_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_imm_sel = _GEN ? r_uop_ctrl_imm_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op_fcn = _GEN ? r_uop_ctrl_op_fcn : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_fcn_dw = _GEN & r_uop_ctrl_fcn_dw; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_csr_cmd = _GEN ? r_uop_ctrl_csr_cmd : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_load = _GEN & r_uop_ctrl_is_load; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_sta = _GEN & r_uop_ctrl_is_sta; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_std = _GEN & r_uop_ctrl_is_std; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_state = _GEN ? r_uop_iw_state : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_p1_poisoned = _GEN & r_uop_iw_p1_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_p2_poisoned = _GEN & r_uop_iw_p2_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_br = _GEN ? r_uop_is_br : ren1_uops_0_is_br; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_jalr = _GEN ? r_uop_is_jalr : ren1_uops_0_is_jalr; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_jal = _GEN ? r_uop_is_jal : ren1_uops_0_is_jal; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_sfb = _GEN ? r_uop_is_sfb : ren1_uops_0_is_sfb; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_br_mask = _GEN ? r_uop_br_mask : ren1_uops_0_br_mask; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_br_tag = _GEN ? r_uop_br_tag : ren1_uops_0_br_tag; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ftq_idx = _GEN ? r_uop_ftq_idx : ren1_uops_0_ftq_idx; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_edge_inst = _GEN ? r_uop_edge_inst : ren1_uops_0_edge_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_pc_lob = _GEN ? r_uop_pc_lob : ren1_uops_0_pc_lob; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_taken = _GEN ? r_uop_taken : ren1_uops_0_taken; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_imm_packed = _GEN ? r_uop_imm_packed : ren1_uops_0_imm_packed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_csr_addr = _GEN ? r_uop_csr_addr : 12'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_rob_idx = _GEN ? r_uop_rob_idx : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldq_idx = _GEN ? r_uop_ldq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_stq_idx = _GEN ? r_uop_stq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_rxq_idx = _GEN ? r_uop_rxq_idx : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_pdst = _GEN ? r_uop_pdst : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs1 = _GEN ? r_uop_prs1 : ren1_uops_0_prs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs2 = _GEN ? r_uop_prs2 : ren1_uops_0_prs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ppred = _GEN ? r_uop_ppred : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs1_busy = _GEN & r_uop_prs1_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs2_busy = _GEN & r_uop_prs2_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ppred_busy = _GEN & r_uop_ppred_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_stale_pdst = _GEN ? r_uop_stale_pdst : ren1_uops_0_stale_pdst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_exception = _GEN ? r_uop_exception : ren1_uops_0_exception; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_exc_cause = _GEN ? r_uop_exc_cause : ren1_uops_0_exc_cause; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bypassable = _GEN ? r_uop_bypassable : ren1_uops_0_bypassable; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_cmd = _GEN ? r_uop_mem_cmd : ren1_uops_0_mem_cmd; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_size = _GEN ? r_uop_mem_size : ren1_uops_0_mem_size; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_signed = _GEN ? r_uop_mem_signed : ren1_uops_0_mem_signed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_fence = _GEN ? r_uop_is_fence : ren1_uops_0_is_fence; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_fencei = _GEN ? r_uop_is_fencei : ren1_uops_0_is_fencei; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_amo = _GEN ? r_uop_is_amo : ren1_uops_0_is_amo; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_uses_ldq = _GEN ? r_uop_uses_ldq : ren1_uops_0_uses_ldq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_uses_stq = _GEN ? r_uop_uses_stq : ren1_uops_0_uses_stq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_sys_pc2epc = _GEN ? r_uop_is_sys_pc2epc : ren1_uops_0_is_sys_pc2epc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_unique = _GEN ? r_uop_is_unique : ren1_uops_0_is_unique; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_flush_on_commit = _GEN ? r_uop_flush_on_commit : ren1_uops_0_flush_on_commit; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst_is_rs1 = _GEN & r_uop_ldst_is_rs1; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst = _GEN ? r_uop_ldst : ren1_uops_0_ldst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs1 = _GEN ? r_uop_lrs1 : ren1_uops_0_lrs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs2 = _GEN ? r_uop_lrs2 : ren1_uops_0_lrs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs3 = _GEN ? r_uop_lrs3 : ren1_uops_0_lrs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst_val = _GEN ? r_uop_ldst_val : ren1_uops_0_ldst_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_dst_rtype = _GEN ? r_uop_dst_rtype : ren1_uops_0_dst_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs1_rtype = _GEN ? r_uop_lrs1_rtype : ren1_uops_0_lrs1_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs2_rtype = _GEN ? r_uop_lrs2_rtype : ren1_uops_0_lrs2_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_frs3_en = _GEN ? r_uop_frs3_en : ren1_uops_0_frs3_en; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fp_val = _GEN ? r_uop_fp_val : ren1_uops_0_fp_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fp_single = _GEN ? r_uop_fp_single : ren1_uops_0_fp_single; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_pf_if = _GEN ? r_uop_xcpt_pf_if : ren1_uops_0_xcpt_pf_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_ae_if = _GEN ? r_uop_xcpt_ae_if : ren1_uops_0_xcpt_ae_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_ma_if = _GEN & r_uop_xcpt_ma_if; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bp_debug_if = _GEN ? r_uop_bp_debug_if : ren1_uops_0_bp_debug_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bp_xcpt_if = _GEN ? r_uop_bp_xcpt_if : ren1_uops_0_bp_xcpt_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_fsrc = _GEN ? r_uop_debug_fsrc : ren1_uops_0_debug_fsrc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_tsrc = _GEN ? r_uop_debug_tsrc : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
wire [6:0] r_uop_newuop_uopc = r_uop_bypassed_uop_uopc; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_inst = r_uop_bypassed_uop_inst; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_debug_inst = r_uop_bypassed_uop_debug_inst; // @[util.scala:73:26]
wire r_uop_newuop_is_rvc = r_uop_bypassed_uop_is_rvc; // @[util.scala:73:26]
wire [39:0] r_uop_newuop_debug_pc = r_uop_bypassed_uop_debug_pc; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_iq_type = r_uop_bypassed_uop_iq_type; // @[util.scala:73:26]
wire [9:0] r_uop_newuop_fu_code = r_uop_bypassed_uop_fu_code; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_ctrl_br_type = r_uop_bypassed_uop_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_ctrl_op1_sel = r_uop_bypassed_uop_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_op2_sel = r_uop_bypassed_uop_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_imm_sel = r_uop_bypassed_uop_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_ctrl_op_fcn = r_uop_bypassed_uop_ctrl_op_fcn; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_fcn_dw = r_uop_bypassed_uop_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_csr_cmd = r_uop_bypassed_uop_ctrl_csr_cmd; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_load = r_uop_bypassed_uop_ctrl_is_load; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_sta = r_uop_bypassed_uop_ctrl_is_sta; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_std = r_uop_bypassed_uop_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_iw_state = r_uop_bypassed_uop_iw_state; // @[util.scala:73:26]
wire r_uop_newuop_iw_p1_poisoned = r_uop_bypassed_uop_iw_p1_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_iw_p2_poisoned = r_uop_bypassed_uop_iw_p2_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_is_br = r_uop_bypassed_uop_is_br; // @[util.scala:73:26]
wire r_uop_newuop_is_jalr = r_uop_bypassed_uop_is_jalr; // @[util.scala:73:26]
wire r_uop_newuop_is_jal = r_uop_bypassed_uop_is_jal; // @[util.scala:73:26]
wire r_uop_newuop_is_sfb = r_uop_bypassed_uop_is_sfb; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_br_tag = r_uop_bypassed_uop_br_tag; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_ftq_idx = r_uop_bypassed_uop_ftq_idx; // @[util.scala:73:26]
wire r_uop_newuop_edge_inst = r_uop_bypassed_uop_edge_inst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_pc_lob = r_uop_bypassed_uop_pc_lob; // @[util.scala:73:26]
wire r_uop_newuop_taken = r_uop_bypassed_uop_taken; // @[util.scala:73:26]
wire [19:0] r_uop_newuop_imm_packed = r_uop_bypassed_uop_imm_packed; // @[util.scala:73:26]
wire [11:0] r_uop_newuop_csr_addr = r_uop_bypassed_uop_csr_addr; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_rob_idx = r_uop_bypassed_uop_rob_idx; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_ldq_idx = r_uop_bypassed_uop_ldq_idx; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_stq_idx = r_uop_bypassed_uop_stq_idx; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_rxq_idx = r_uop_bypassed_uop_rxq_idx; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_pdst = r_uop_bypassed_uop_pdst; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_prs1 = r_uop_bypassed_uop_prs1; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_prs2 = r_uop_bypassed_uop_prs2; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs1_busy_T; // @[rename-stage.scala:199:45]
wire [4:0] r_uop_newuop_ppred = r_uop_bypassed_uop_ppred; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs2_busy_T; // @[rename-stage.scala:200:45]
wire r_uop_newuop_prs1_busy = r_uop_bypassed_uop_prs1_busy; // @[util.scala:73:26]
wire r_uop_newuop_prs2_busy = r_uop_bypassed_uop_prs2_busy; // @[util.scala:73:26]
wire r_uop_newuop_ppred_busy = r_uop_bypassed_uop_ppred_busy; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_stale_pdst = r_uop_bypassed_uop_stale_pdst; // @[util.scala:73:26]
wire r_uop_newuop_exception = r_uop_bypassed_uop_exception; // @[util.scala:73:26]
wire [63:0] r_uop_newuop_exc_cause = r_uop_bypassed_uop_exc_cause; // @[util.scala:73:26]
wire r_uop_newuop_bypassable = r_uop_bypassed_uop_bypassable; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_mem_cmd = r_uop_bypassed_uop_mem_cmd; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_mem_size = r_uop_bypassed_uop_mem_size; // @[util.scala:73:26]
wire r_uop_newuop_mem_signed = r_uop_bypassed_uop_mem_signed; // @[util.scala:73:26]
wire r_uop_newuop_is_fence = r_uop_bypassed_uop_is_fence; // @[util.scala:73:26]
wire r_uop_newuop_is_fencei = r_uop_bypassed_uop_is_fencei; // @[util.scala:73:26]
wire r_uop_newuop_is_amo = r_uop_bypassed_uop_is_amo; // @[util.scala:73:26]
wire r_uop_newuop_uses_ldq = r_uop_bypassed_uop_uses_ldq; // @[util.scala:73:26]
wire r_uop_newuop_uses_stq = r_uop_bypassed_uop_uses_stq; // @[util.scala:73:26]
wire r_uop_newuop_is_sys_pc2epc = r_uop_bypassed_uop_is_sys_pc2epc; // @[util.scala:73:26]
wire r_uop_newuop_is_unique = r_uop_bypassed_uop_is_unique; // @[util.scala:73:26]
wire r_uop_newuop_flush_on_commit = r_uop_bypassed_uop_flush_on_commit; // @[util.scala:73:26]
wire r_uop_newuop_ldst_is_rs1 = r_uop_bypassed_uop_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_ldst = r_uop_bypassed_uop_ldst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs1 = r_uop_bypassed_uop_lrs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs2 = r_uop_bypassed_uop_lrs2; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs3 = r_uop_bypassed_uop_lrs3; // @[util.scala:73:26]
wire r_uop_newuop_ldst_val = r_uop_bypassed_uop_ldst_val; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_dst_rtype = r_uop_bypassed_uop_dst_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_lrs1_rtype = r_uop_bypassed_uop_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_lrs2_rtype = r_uop_bypassed_uop_lrs2_rtype; // @[util.scala:73:26]
wire r_uop_newuop_frs3_en = r_uop_bypassed_uop_frs3_en; // @[util.scala:73:26]
wire r_uop_newuop_fp_val = r_uop_bypassed_uop_fp_val; // @[util.scala:73:26]
wire r_uop_newuop_fp_single = r_uop_bypassed_uop_fp_single; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_pf_if = r_uop_bypassed_uop_xcpt_pf_if; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_ae_if = r_uop_bypassed_uop_xcpt_ae_if; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_ma_if = r_uop_bypassed_uop_xcpt_ma_if; // @[util.scala:73:26]
wire r_uop_newuop_bp_debug_if = r_uop_bypassed_uop_bp_debug_if; // @[util.scala:73:26]
wire r_uop_newuop_bp_xcpt_if = r_uop_bypassed_uop_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_debug_fsrc = r_uop_bypassed_uop_debug_fsrc; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_debug_tsrc = r_uop_bypassed_uop_debug_tsrc; // @[util.scala:73:26]
wire _r_uop_bypass_hits_rs1_T = ren2_uops_0_ldst == next_uop_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs1_T; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs1_T_1 = ren2_uops_1_ldst == next_uop_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs1_T_1; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs1_T_2 = ren2_uops_2_ldst == next_uop_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs1_T_2; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs2_T = ren2_uops_0_ldst == next_uop_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs2_T; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs2_T_1 = ren2_uops_1_ldst == next_uop_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs2_T_1; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs2_T_2 = ren2_uops_2_ldst == next_uop_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs2_T_2; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs3_T = ren2_uops_0_ldst == next_uop_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs3_T; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_rs3_T_1 = ren2_uops_1_ldst == next_uop_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs3_T_1; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_rs3_T_2 = ren2_uops_2_ldst == next_uop_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs3_T_2; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_dst_T = ren2_uops_0_ldst == next_uop_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_dst_T; // @[rename-stage.scala:109:29, :180:{77,87}]
wire _r_uop_bypass_hits_dst_T_1 = ren2_uops_1_ldst == next_uop_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_dst_T_1; // @[rename-stage.scala:109:29, :180:{77,87}]
wire _r_uop_bypass_hits_dst_T_2 = ren2_uops_2_ldst == next_uop_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_dst_T_2; // @[rename-stage.scala:109:29, :180:{77,87}]
wire [2:0] _r_uop_bypass_sel_rs1_enc_T = {r_uop_bypass_hits_rs1_0, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs1_enc_T_1 = r_uop_bypass_hits_rs1_1 ? 3'h2 : _r_uop_bypass_sel_rs1_enc_T; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs1_enc = r_uop_bypass_hits_rs1_2 ? 3'h1 : _r_uop_bypass_sel_rs1_enc_T_1; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs1_2 = r_uop_bypass_sel_rs1_enc[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs1_1 = r_uop_bypass_sel_rs1_enc[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs1_0 = r_uop_bypass_sel_rs1_enc[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_rs2_enc_T = {r_uop_bypass_hits_rs2_0, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs2_enc_T_1 = r_uop_bypass_hits_rs2_1 ? 3'h2 : _r_uop_bypass_sel_rs2_enc_T; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs2_enc = r_uop_bypass_hits_rs2_2 ? 3'h1 : _r_uop_bypass_sel_rs2_enc_T_1; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs2_2 = r_uop_bypass_sel_rs2_enc[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs2_1 = r_uop_bypass_sel_rs2_enc[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs2_0 = r_uop_bypass_sel_rs2_enc[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_rs3_enc_T = {r_uop_bypass_hits_rs3_0, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs3_enc_T_1 = r_uop_bypass_hits_rs3_1 ? 3'h2 : _r_uop_bypass_sel_rs3_enc_T; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs3_enc = r_uop_bypass_hits_rs3_2 ? 3'h1 : _r_uop_bypass_sel_rs3_enc_T_1; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs3_2 = r_uop_bypass_sel_rs3_enc[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs3_1 = r_uop_bypass_sel_rs3_enc[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs3_0 = r_uop_bypass_sel_rs3_enc[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_dst_enc_T = {r_uop_bypass_hits_dst_0, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_dst_enc_T_1 = r_uop_bypass_hits_dst_1 ? 3'h2 : _r_uop_bypass_sel_dst_enc_T; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_dst_enc = r_uop_bypass_hits_dst_2 ? 3'h1 : _r_uop_bypass_sel_dst_enc_T_1; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_dst_2 = r_uop_bypass_sel_dst_enc[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_dst_1 = r_uop_bypass_sel_dst_enc[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_dst_0 = r_uop_bypass_sel_dst_enc[2]; // @[OneHot.scala:83:30]
wire _r_uop_do_bypass_rs1_T = r_uop_bypass_hits_rs1_0 | r_uop_bypass_hits_rs1_1; // @[rename-stage.scala:177:77, :187:49]
wire r_uop_do_bypass_rs1 = _r_uop_do_bypass_rs1_T | r_uop_bypass_hits_rs1_2; // @[rename-stage.scala:177:77, :187:49]
wire _r_uop_do_bypass_rs2_T = r_uop_bypass_hits_rs2_0 | r_uop_bypass_hits_rs2_1; // @[rename-stage.scala:178:77, :188:49]
wire r_uop_do_bypass_rs2 = _r_uop_do_bypass_rs2_T | r_uop_bypass_hits_rs2_2; // @[rename-stage.scala:178:77, :188:49]
wire _r_uop_do_bypass_rs3_T = r_uop_bypass_hits_rs3_0 | r_uop_bypass_hits_rs3_1; // @[rename-stage.scala:179:77, :189:49]
wire r_uop_do_bypass_rs3 = _r_uop_do_bypass_rs3_T | r_uop_bypass_hits_rs3_2; // @[rename-stage.scala:179:77, :189:49]
wire _r_uop_bypassed_uop_prs3_busy_T = r_uop_do_bypass_rs3; // @[rename-stage.scala:189:49, :201:45]
wire _r_uop_do_bypass_dst_T = r_uop_bypass_hits_dst_0 | r_uop_bypass_hits_dst_1; // @[rename-stage.scala:180:77, :190:49]
wire r_uop_do_bypass_dst = _r_uop_do_bypass_dst_T | r_uop_bypass_hits_dst_2; // @[rename-stage.scala:180:77, :190:49]
wire [6:0] _r_uop_bypassed_uop_prs1_T = r_uop_bypass_sel_rs1_0 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_1 = r_uop_bypass_sel_rs1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_2 = r_uop_bypass_sel_rs1_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_3 = _r_uop_bypassed_uop_prs1_T | _r_uop_bypassed_uop_prs1_T_1; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs1_T_4 = _r_uop_bypassed_uop_prs1_T_3 | _r_uop_bypassed_uop_prs1_T_2; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs1_WIRE = _r_uop_bypassed_uop_prs1_T_4; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_prs1 = r_uop_do_bypass_rs1 ? _r_uop_bypassed_uop_prs1_WIRE : next_uop_prs1; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_T = r_uop_bypass_sel_rs2_0 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_1 = r_uop_bypass_sel_rs2_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_2 = r_uop_bypass_sel_rs2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_3 = _r_uop_bypassed_uop_prs2_T | _r_uop_bypassed_uop_prs2_T_1; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_T_4 = _r_uop_bypassed_uop_prs2_T_3 | _r_uop_bypassed_uop_prs2_T_2; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_WIRE = _r_uop_bypassed_uop_prs2_T_4; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_prs2 = r_uop_do_bypass_rs2 ? _r_uop_bypassed_uop_prs2_WIRE : next_uop_prs2; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_T = r_uop_bypass_sel_rs3_0 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_1 = r_uop_bypass_sel_rs3_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_2 = r_uop_bypass_sel_rs3_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_3 = _r_uop_bypassed_uop_prs3_T | _r_uop_bypassed_uop_prs3_T_1; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_T_4 = _r_uop_bypassed_uop_prs3_T_3 | _r_uop_bypassed_uop_prs3_T_2; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_WIRE = _r_uop_bypassed_uop_prs3_T_4; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T = r_uop_bypass_sel_dst_0 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_1 = r_uop_bypass_sel_dst_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_2 = r_uop_bypass_sel_dst_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_3 = _r_uop_bypassed_uop_stale_pdst_T | _r_uop_bypassed_uop_stale_pdst_T_1; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_4 = _r_uop_bypassed_uop_stale_pdst_T_3 | _r_uop_bypassed_uop_stale_pdst_T_2; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_WIRE = _r_uop_bypassed_uop_stale_pdst_T_4; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_stale_pdst = r_uop_do_bypass_dst ? _r_uop_bypassed_uop_stale_pdst_WIRE : next_uop_stale_pdst; // @[Mux.scala:30:73]
assign _r_uop_bypassed_uop_prs1_busy_T = next_uop_prs1_busy | r_uop_do_bypass_rs1; // @[rename-stage.scala:123:24, :187:49, :199:45]
assign r_uop_bypassed_uop_prs1_busy = _r_uop_bypassed_uop_prs1_busy_T; // @[rename-stage.scala:174:28, :199:45]
assign _r_uop_bypassed_uop_prs2_busy_T = next_uop_prs2_busy | r_uop_do_bypass_rs2; // @[rename-stage.scala:123:24, :188:49, :200:45]
assign r_uop_bypassed_uop_prs2_busy = _r_uop_bypassed_uop_prs2_busy_T; // @[rename-stage.scala:174:28, :200:45]
wire [15:0] _r_uop_newuop_br_mask_T_1; // @[util.scala:74:35]
wire [15:0] r_uop_newuop_br_mask; // @[util.scala:73:26]
wire [15:0] _r_uop_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37]
assign _r_uop_newuop_br_mask_T_1 = r_uop_bypassed_uop_br_mask & _r_uop_newuop_br_mask_T; // @[util.scala:74:{35,37}]
assign r_uop_newuop_br_mask = _r_uop_newuop_br_mask_T_1; // @[util.scala:73:26, :74:35]
reg r_valid_1; // @[rename-stage.scala:121:27]
assign ren2_valids_1 = r_valid_1; // @[rename-stage.scala:107:29, :121:27]
reg [6:0] r_uop_1_uopc; // @[rename-stage.scala:122:23]
assign ren2_uops_1_uopc = r_uop_1_uopc; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_1_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_1_inst = r_uop_1_inst; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_1_debug_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_1_debug_inst = r_uop_1_debug_inst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_rvc; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_rvc = r_uop_1_is_rvc; // @[rename-stage.scala:108:29, :122:23]
reg [39:0] r_uop_1_debug_pc; // @[rename-stage.scala:122:23]
assign ren2_uops_1_debug_pc = r_uop_1_debug_pc; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_1_iq_type; // @[rename-stage.scala:122:23]
assign ren2_uops_1_iq_type = r_uop_1_iq_type; // @[rename-stage.scala:108:29, :122:23]
reg [9:0] r_uop_1_fu_code; // @[rename-stage.scala:122:23]
assign ren2_uops_1_fu_code = r_uop_1_fu_code; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_1_ctrl_br_type; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_br_type = r_uop_1_ctrl_br_type; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_ctrl_op1_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_op1_sel = r_uop_1_ctrl_op1_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_1_ctrl_op2_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_op2_sel = r_uop_1_ctrl_op2_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_1_ctrl_imm_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_imm_sel = r_uop_1_ctrl_imm_sel; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_1_ctrl_op_fcn; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_op_fcn = r_uop_1_ctrl_op_fcn; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_fcn_dw = r_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_csr_cmd = r_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_ctrl_is_load; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_is_load = r_uop_1_ctrl_is_load; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_ctrl_is_sta; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_is_sta = r_uop_1_ctrl_is_sta; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_ctrl_is_std; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ctrl_is_std = r_uop_1_ctrl_is_std; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_iw_state; // @[rename-stage.scala:122:23]
assign ren2_uops_1_iw_state = r_uop_1_iw_state; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_iw_p1_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_1_iw_p1_poisoned = r_uop_1_iw_p1_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_iw_p2_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_1_iw_p2_poisoned = r_uop_1_iw_p2_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_br; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_br = r_uop_1_is_br; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_jalr; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_jalr = r_uop_1_is_jalr; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_jal; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_jal = r_uop_1_is_jal; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_sfb; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_sfb = r_uop_1_is_sfb; // @[rename-stage.scala:108:29, :122:23]
reg [15:0] r_uop_1_br_mask; // @[rename-stage.scala:122:23]
assign ren2_uops_1_br_mask = r_uop_1_br_mask; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_1_br_tag; // @[rename-stage.scala:122:23]
assign ren2_uops_1_br_tag = r_uop_1_br_tag; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_1_ftq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ftq_idx = r_uop_1_ftq_idx; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_edge_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_1_edge_inst = r_uop_1_edge_inst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_1_pc_lob; // @[rename-stage.scala:122:23]
assign ren2_uops_1_pc_lob = r_uop_1_pc_lob; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_taken; // @[rename-stage.scala:122:23]
assign ren2_uops_1_taken = r_uop_1_taken; // @[rename-stage.scala:108:29, :122:23]
reg [19:0] r_uop_1_imm_packed; // @[rename-stage.scala:122:23]
assign ren2_uops_1_imm_packed = r_uop_1_imm_packed; // @[rename-stage.scala:108:29, :122:23]
reg [11:0] r_uop_1_csr_addr; // @[rename-stage.scala:122:23]
assign ren2_uops_1_csr_addr = r_uop_1_csr_addr; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_1_rob_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_1_rob_idx = r_uop_1_rob_idx; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_1_ldq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ldq_idx = r_uop_1_ldq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_1_stq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_1_stq_idx = r_uop_1_stq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_rxq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_1_rxq_idx = r_uop_1_rxq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_1_pdst; // @[rename-stage.scala:122:23]
reg [6:0] r_uop_1_prs1; // @[rename-stage.scala:122:23]
assign ren2_uops_1_prs1 = r_uop_1_prs1; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_1_prs2; // @[rename-stage.scala:122:23]
assign ren2_uops_1_prs2 = r_uop_1_prs2; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_1_ppred; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ppred = r_uop_1_ppred; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_prs1_busy; // @[rename-stage.scala:122:23]
reg r_uop_1_prs2_busy; // @[rename-stage.scala:122:23]
reg r_uop_1_ppred_busy; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ppred_busy = r_uop_1_ppred_busy; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_1_stale_pdst; // @[rename-stage.scala:122:23]
assign ren2_uops_1_stale_pdst = r_uop_1_stale_pdst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_exception; // @[rename-stage.scala:122:23]
assign ren2_uops_1_exception = r_uop_1_exception; // @[rename-stage.scala:108:29, :122:23]
reg [63:0] r_uop_1_exc_cause; // @[rename-stage.scala:122:23]
assign ren2_uops_1_exc_cause = r_uop_1_exc_cause; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_bypassable; // @[rename-stage.scala:122:23]
assign ren2_uops_1_bypassable = r_uop_1_bypassable; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_1_mem_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_1_mem_cmd = r_uop_1_mem_cmd; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_mem_size; // @[rename-stage.scala:122:23]
assign ren2_uops_1_mem_size = r_uop_1_mem_size; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_mem_signed; // @[rename-stage.scala:122:23]
assign ren2_uops_1_mem_signed = r_uop_1_mem_signed; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_fence; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_fence = r_uop_1_is_fence; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_fencei; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_fencei = r_uop_1_is_fencei; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_amo; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_amo = r_uop_1_is_amo; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_uses_ldq; // @[rename-stage.scala:122:23]
assign ren2_uops_1_uses_ldq = r_uop_1_uses_ldq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_uses_stq; // @[rename-stage.scala:122:23]
assign ren2_uops_1_uses_stq = r_uop_1_uses_stq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_sys_pc2epc; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_sys_pc2epc = r_uop_1_is_sys_pc2epc; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_is_unique; // @[rename-stage.scala:122:23]
assign ren2_uops_1_is_unique = r_uop_1_is_unique; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_flush_on_commit; // @[rename-stage.scala:122:23]
assign ren2_uops_1_flush_on_commit = r_uop_1_flush_on_commit; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_ldst_is_rs1; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ldst_is_rs1 = r_uop_1_ldst_is_rs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_1_ldst; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ldst = r_uop_1_ldst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_1_lrs1; // @[rename-stage.scala:122:23]
assign ren2_uops_1_lrs1 = r_uop_1_lrs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_1_lrs2; // @[rename-stage.scala:122:23]
assign ren2_uops_1_lrs2 = r_uop_1_lrs2; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_1_lrs3; // @[rename-stage.scala:122:23]
assign ren2_uops_1_lrs3 = r_uop_1_lrs3; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_ldst_val; // @[rename-stage.scala:122:23]
assign ren2_uops_1_ldst_val = r_uop_1_ldst_val; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_dst_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_1_dst_rtype = r_uop_1_dst_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_lrs1_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_1_lrs1_rtype = r_uop_1_lrs1_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_lrs2_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_1_lrs2_rtype = r_uop_1_lrs2_rtype; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_frs3_en; // @[rename-stage.scala:122:23]
assign ren2_uops_1_frs3_en = r_uop_1_frs3_en; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_fp_val; // @[rename-stage.scala:122:23]
assign ren2_uops_1_fp_val = r_uop_1_fp_val; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_fp_single; // @[rename-stage.scala:122:23]
assign ren2_uops_1_fp_single = r_uop_1_fp_single; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_xcpt_pf_if; // @[rename-stage.scala:122:23]
assign ren2_uops_1_xcpt_pf_if = r_uop_1_xcpt_pf_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_xcpt_ae_if; // @[rename-stage.scala:122:23]
assign ren2_uops_1_xcpt_ae_if = r_uop_1_xcpt_ae_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_xcpt_ma_if; // @[rename-stage.scala:122:23]
assign ren2_uops_1_xcpt_ma_if = r_uop_1_xcpt_ma_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_bp_debug_if; // @[rename-stage.scala:122:23]
assign ren2_uops_1_bp_debug_if = r_uop_1_bp_debug_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_1_bp_xcpt_if; // @[rename-stage.scala:122:23]
assign ren2_uops_1_bp_xcpt_if = r_uop_1_bp_xcpt_if; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_debug_fsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_1_debug_fsrc = r_uop_1_debug_fsrc; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_1_debug_tsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_1_debug_tsrc = r_uop_1_debug_tsrc; // @[rename-stage.scala:108:29, :122:23]
wire [6:0] r_uop_bypassed_uop_1_uopc = next_uop_1_uopc; // @[rename-stage.scala:123:24, :174:28]
wire [31:0] r_uop_bypassed_uop_1_inst = next_uop_1_inst; // @[rename-stage.scala:123:24, :174:28]
wire [31:0] r_uop_bypassed_uop_1_debug_inst = next_uop_1_debug_inst; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_rvc = next_uop_1_is_rvc; // @[rename-stage.scala:123:24, :174:28]
wire [39:0] r_uop_bypassed_uop_1_debug_pc = next_uop_1_debug_pc; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_1_iq_type = next_uop_1_iq_type; // @[rename-stage.scala:123:24, :174:28]
wire [9:0] r_uop_bypassed_uop_1_fu_code = next_uop_1_fu_code; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_1_ctrl_br_type = next_uop_1_ctrl_br_type; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_ctrl_op1_sel = next_uop_1_ctrl_op1_sel; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_1_ctrl_op2_sel = next_uop_1_ctrl_op2_sel; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_1_ctrl_imm_sel = next_uop_1_ctrl_imm_sel; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_1_ctrl_op_fcn = next_uop_1_ctrl_op_fcn; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_ctrl_fcn_dw = next_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_1_ctrl_csr_cmd = next_uop_1_ctrl_csr_cmd; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_ctrl_is_load = next_uop_1_ctrl_is_load; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_ctrl_is_sta = next_uop_1_ctrl_is_sta; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_ctrl_is_std = next_uop_1_ctrl_is_std; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_iw_state = next_uop_1_iw_state; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_iw_p1_poisoned = next_uop_1_iw_p1_poisoned; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_iw_p2_poisoned = next_uop_1_iw_p2_poisoned; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_br = next_uop_1_is_br; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_jalr = next_uop_1_is_jalr; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_jal = next_uop_1_is_jal; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_sfb = next_uop_1_is_sfb; // @[rename-stage.scala:123:24, :174:28]
wire [15:0] r_uop_bypassed_uop_1_br_mask = next_uop_1_br_mask; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_1_br_tag = next_uop_1_br_tag; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_1_ftq_idx = next_uop_1_ftq_idx; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_edge_inst = next_uop_1_edge_inst; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_1_pc_lob = next_uop_1_pc_lob; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_taken = next_uop_1_taken; // @[rename-stage.scala:123:24, :174:28]
wire [19:0] r_uop_bypassed_uop_1_imm_packed = next_uop_1_imm_packed; // @[rename-stage.scala:123:24, :174:28]
wire [11:0] r_uop_bypassed_uop_1_csr_addr = next_uop_1_csr_addr; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] r_uop_bypassed_uop_1_rob_idx = next_uop_1_rob_idx; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_1_ldq_idx = next_uop_1_ldq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_1_stq_idx = next_uop_1_stq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_rxq_idx = next_uop_1_rxq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] r_uop_bypassed_uop_1_pdst = next_uop_1_pdst; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_1_ppred = next_uop_1_ppred; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_ppred_busy = next_uop_1_ppred_busy; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_exception = next_uop_1_exception; // @[rename-stage.scala:123:24, :174:28]
wire [63:0] r_uop_bypassed_uop_1_exc_cause = next_uop_1_exc_cause; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_bypassable = next_uop_1_bypassable; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_1_mem_cmd = next_uop_1_mem_cmd; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_mem_size = next_uop_1_mem_size; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_mem_signed = next_uop_1_mem_signed; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_fence = next_uop_1_is_fence; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_fencei = next_uop_1_is_fencei; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_amo = next_uop_1_is_amo; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_uses_ldq = next_uop_1_uses_ldq; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_uses_stq = next_uop_1_uses_stq; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_sys_pc2epc = next_uop_1_is_sys_pc2epc; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_is_unique = next_uop_1_is_unique; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_flush_on_commit = next_uop_1_flush_on_commit; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_ldst_is_rs1 = next_uop_1_ldst_is_rs1; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_1_ldst = next_uop_1_ldst; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_1_lrs1 = next_uop_1_lrs1; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_1_lrs2 = next_uop_1_lrs2; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_1_lrs3 = next_uop_1_lrs3; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_ldst_val = next_uop_1_ldst_val; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_dst_rtype = next_uop_1_dst_rtype; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_lrs1_rtype = next_uop_1_lrs1_rtype; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_lrs2_rtype = next_uop_1_lrs2_rtype; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_frs3_en = next_uop_1_frs3_en; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_fp_val = next_uop_1_fp_val; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_fp_single = next_uop_1_fp_single; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_xcpt_pf_if = next_uop_1_xcpt_pf_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_xcpt_ae_if = next_uop_1_xcpt_ae_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_xcpt_ma_if = next_uop_1_xcpt_ma_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_bp_debug_if = next_uop_1_bp_debug_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_1_bp_xcpt_if = next_uop_1_bp_xcpt_if; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_debug_fsrc = next_uop_1_debug_fsrc; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_1_debug_tsrc = next_uop_1_debug_tsrc; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] next_uop_1_prs1; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_1_prs2; // @[rename-stage.scala:123:24]
wire next_uop_1_prs1_busy; // @[rename-stage.scala:123:24]
wire next_uop_1_prs2_busy; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_1_stale_pdst; // @[rename-stage.scala:123:24]
wire _r_valid_T_2 = ~io_dis_fire_1_0; // @[rename-stage.scala:133:29, :160:7]
wire _r_valid_T_3 = r_valid_1 & _r_valid_T_2; // @[rename-stage.scala:121:27, :133:{26,29}]
assign next_uop_1_uopc = _GEN ? r_uop_1_uopc : ren1_uops_1_uopc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_inst = _GEN ? r_uop_1_inst : ren1_uops_1_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_debug_inst = _GEN ? r_uop_1_debug_inst : ren1_uops_1_debug_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_rvc = _GEN ? r_uop_1_is_rvc : ren1_uops_1_is_rvc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_debug_pc = _GEN ? r_uop_1_debug_pc : ren1_uops_1_debug_pc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_iq_type = _GEN ? r_uop_1_iq_type : ren1_uops_1_iq_type; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_fu_code = _GEN ? r_uop_1_fu_code : ren1_uops_1_fu_code; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_br_type = _GEN ? r_uop_1_ctrl_br_type : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_op1_sel = _GEN ? r_uop_1_ctrl_op1_sel : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_op2_sel = _GEN ? r_uop_1_ctrl_op2_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_imm_sel = _GEN ? r_uop_1_ctrl_imm_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_op_fcn = _GEN ? r_uop_1_ctrl_op_fcn : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_fcn_dw = _GEN & r_uop_1_ctrl_fcn_dw; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_csr_cmd = _GEN ? r_uop_1_ctrl_csr_cmd : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_is_load = _GEN & r_uop_1_ctrl_is_load; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_is_sta = _GEN & r_uop_1_ctrl_is_sta; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ctrl_is_std = _GEN & r_uop_1_ctrl_is_std; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_iw_state = _GEN ? r_uop_1_iw_state : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_iw_p1_poisoned = _GEN & r_uop_1_iw_p1_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_iw_p2_poisoned = _GEN & r_uop_1_iw_p2_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_br = _GEN ? r_uop_1_is_br : ren1_uops_1_is_br; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_jalr = _GEN ? r_uop_1_is_jalr : ren1_uops_1_is_jalr; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_jal = _GEN ? r_uop_1_is_jal : ren1_uops_1_is_jal; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_sfb = _GEN ? r_uop_1_is_sfb : ren1_uops_1_is_sfb; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_br_mask = _GEN ? r_uop_1_br_mask : ren1_uops_1_br_mask; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_br_tag = _GEN ? r_uop_1_br_tag : ren1_uops_1_br_tag; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ftq_idx = _GEN ? r_uop_1_ftq_idx : ren1_uops_1_ftq_idx; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_edge_inst = _GEN ? r_uop_1_edge_inst : ren1_uops_1_edge_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_pc_lob = _GEN ? r_uop_1_pc_lob : ren1_uops_1_pc_lob; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_taken = _GEN ? r_uop_1_taken : ren1_uops_1_taken; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_imm_packed = _GEN ? r_uop_1_imm_packed : ren1_uops_1_imm_packed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_csr_addr = _GEN ? r_uop_1_csr_addr : 12'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_rob_idx = _GEN ? r_uop_1_rob_idx : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ldq_idx = _GEN ? r_uop_1_ldq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_stq_idx = _GEN ? r_uop_1_stq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_rxq_idx = _GEN ? r_uop_1_rxq_idx : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_pdst = _GEN ? r_uop_1_pdst : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_prs1 = _GEN ? r_uop_1_prs1 : ren1_uops_1_prs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_prs2 = _GEN ? r_uop_1_prs2 : ren1_uops_1_prs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ppred = _GEN ? r_uop_1_ppred : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_prs1_busy = _GEN & r_uop_1_prs1_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_prs2_busy = _GEN & r_uop_1_prs2_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ppred_busy = _GEN & r_uop_1_ppred_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_stale_pdst = _GEN ? r_uop_1_stale_pdst : ren1_uops_1_stale_pdst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_exception = _GEN ? r_uop_1_exception : ren1_uops_1_exception; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_exc_cause = _GEN ? r_uop_1_exc_cause : ren1_uops_1_exc_cause; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_bypassable = _GEN ? r_uop_1_bypassable : ren1_uops_1_bypassable; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_mem_cmd = _GEN ? r_uop_1_mem_cmd : ren1_uops_1_mem_cmd; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_mem_size = _GEN ? r_uop_1_mem_size : ren1_uops_1_mem_size; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_mem_signed = _GEN ? r_uop_1_mem_signed : ren1_uops_1_mem_signed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_fence = _GEN ? r_uop_1_is_fence : ren1_uops_1_is_fence; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_fencei = _GEN ? r_uop_1_is_fencei : ren1_uops_1_is_fencei; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_amo = _GEN ? r_uop_1_is_amo : ren1_uops_1_is_amo; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_uses_ldq = _GEN ? r_uop_1_uses_ldq : ren1_uops_1_uses_ldq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_uses_stq = _GEN ? r_uop_1_uses_stq : ren1_uops_1_uses_stq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_sys_pc2epc = _GEN ? r_uop_1_is_sys_pc2epc : ren1_uops_1_is_sys_pc2epc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_is_unique = _GEN ? r_uop_1_is_unique : ren1_uops_1_is_unique; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_flush_on_commit = _GEN ? r_uop_1_flush_on_commit : ren1_uops_1_flush_on_commit; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ldst_is_rs1 = _GEN & r_uop_1_ldst_is_rs1; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ldst = _GEN ? r_uop_1_ldst : ren1_uops_1_ldst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_lrs1 = _GEN ? r_uop_1_lrs1 : ren1_uops_1_lrs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_lrs2 = _GEN ? r_uop_1_lrs2 : ren1_uops_1_lrs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_lrs3 = _GEN ? r_uop_1_lrs3 : ren1_uops_1_lrs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_ldst_val = _GEN ? r_uop_1_ldst_val : ren1_uops_1_ldst_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_dst_rtype = _GEN ? r_uop_1_dst_rtype : ren1_uops_1_dst_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_lrs1_rtype = _GEN ? r_uop_1_lrs1_rtype : ren1_uops_1_lrs1_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_lrs2_rtype = _GEN ? r_uop_1_lrs2_rtype : ren1_uops_1_lrs2_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_frs3_en = _GEN ? r_uop_1_frs3_en : ren1_uops_1_frs3_en; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_fp_val = _GEN ? r_uop_1_fp_val : ren1_uops_1_fp_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_fp_single = _GEN ? r_uop_1_fp_single : ren1_uops_1_fp_single; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_xcpt_pf_if = _GEN ? r_uop_1_xcpt_pf_if : ren1_uops_1_xcpt_pf_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_xcpt_ae_if = _GEN ? r_uop_1_xcpt_ae_if : ren1_uops_1_xcpt_ae_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_xcpt_ma_if = _GEN & r_uop_1_xcpt_ma_if; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_bp_debug_if = _GEN ? r_uop_1_bp_debug_if : ren1_uops_1_bp_debug_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_bp_xcpt_if = _GEN ? r_uop_1_bp_xcpt_if : ren1_uops_1_bp_xcpt_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_debug_fsrc = _GEN ? r_uop_1_debug_fsrc : ren1_uops_1_debug_fsrc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_1_debug_tsrc = _GEN ? r_uop_1_debug_tsrc : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
wire [6:0] r_uop_newuop_1_uopc = r_uop_bypassed_uop_1_uopc; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_1_inst = r_uop_bypassed_uop_1_inst; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_1_debug_inst = r_uop_bypassed_uop_1_debug_inst; // @[util.scala:73:26]
wire r_uop_newuop_1_is_rvc = r_uop_bypassed_uop_1_is_rvc; // @[util.scala:73:26]
wire [39:0] r_uop_newuop_1_debug_pc = r_uop_bypassed_uop_1_debug_pc; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_1_iq_type = r_uop_bypassed_uop_1_iq_type; // @[util.scala:73:26]
wire [9:0] r_uop_newuop_1_fu_code = r_uop_bypassed_uop_1_fu_code; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_1_ctrl_br_type = r_uop_bypassed_uop_1_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_ctrl_op1_sel = r_uop_bypassed_uop_1_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_1_ctrl_op2_sel = r_uop_bypassed_uop_1_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_1_ctrl_imm_sel = r_uop_bypassed_uop_1_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_1_ctrl_op_fcn = r_uop_bypassed_uop_1_ctrl_op_fcn; // @[util.scala:73:26]
wire r_uop_newuop_1_ctrl_fcn_dw = r_uop_bypassed_uop_1_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_1_ctrl_csr_cmd = r_uop_bypassed_uop_1_ctrl_csr_cmd; // @[util.scala:73:26]
wire r_uop_newuop_1_ctrl_is_load = r_uop_bypassed_uop_1_ctrl_is_load; // @[util.scala:73:26]
wire r_uop_newuop_1_ctrl_is_sta = r_uop_bypassed_uop_1_ctrl_is_sta; // @[util.scala:73:26]
wire r_uop_newuop_1_ctrl_is_std = r_uop_bypassed_uop_1_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_iw_state = r_uop_bypassed_uop_1_iw_state; // @[util.scala:73:26]
wire r_uop_newuop_1_iw_p1_poisoned = r_uop_bypassed_uop_1_iw_p1_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_1_iw_p2_poisoned = r_uop_bypassed_uop_1_iw_p2_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_1_is_br = r_uop_bypassed_uop_1_is_br; // @[util.scala:73:26]
wire r_uop_newuop_1_is_jalr = r_uop_bypassed_uop_1_is_jalr; // @[util.scala:73:26]
wire r_uop_newuop_1_is_jal = r_uop_bypassed_uop_1_is_jal; // @[util.scala:73:26]
wire r_uop_newuop_1_is_sfb = r_uop_bypassed_uop_1_is_sfb; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_1_br_tag = r_uop_bypassed_uop_1_br_tag; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_1_ftq_idx = r_uop_bypassed_uop_1_ftq_idx; // @[util.scala:73:26]
wire r_uop_newuop_1_edge_inst = r_uop_bypassed_uop_1_edge_inst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_1_pc_lob = r_uop_bypassed_uop_1_pc_lob; // @[util.scala:73:26]
wire r_uop_newuop_1_taken = r_uop_bypassed_uop_1_taken; // @[util.scala:73:26]
wire [19:0] r_uop_newuop_1_imm_packed = r_uop_bypassed_uop_1_imm_packed; // @[util.scala:73:26]
wire [11:0] r_uop_newuop_1_csr_addr = r_uop_bypassed_uop_1_csr_addr; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_1_rob_idx = r_uop_bypassed_uop_1_rob_idx; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_1_ldq_idx = r_uop_bypassed_uop_1_ldq_idx; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_1_stq_idx = r_uop_bypassed_uop_1_stq_idx; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_rxq_idx = r_uop_bypassed_uop_1_rxq_idx; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_1_pdst = r_uop_bypassed_uop_1_pdst; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_1_prs1 = r_uop_bypassed_uop_1_prs1; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_1_prs2 = r_uop_bypassed_uop_1_prs2; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs1_busy_T_1; // @[rename-stage.scala:199:45]
wire [4:0] r_uop_newuop_1_ppred = r_uop_bypassed_uop_1_ppred; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs2_busy_T_1; // @[rename-stage.scala:200:45]
wire r_uop_newuop_1_prs1_busy = r_uop_bypassed_uop_1_prs1_busy; // @[util.scala:73:26]
wire r_uop_newuop_1_prs2_busy = r_uop_bypassed_uop_1_prs2_busy; // @[util.scala:73:26]
wire r_uop_newuop_1_ppred_busy = r_uop_bypassed_uop_1_ppred_busy; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_1_stale_pdst = r_uop_bypassed_uop_1_stale_pdst; // @[util.scala:73:26]
wire r_uop_newuop_1_exception = r_uop_bypassed_uop_1_exception; // @[util.scala:73:26]
wire [63:0] r_uop_newuop_1_exc_cause = r_uop_bypassed_uop_1_exc_cause; // @[util.scala:73:26]
wire r_uop_newuop_1_bypassable = r_uop_bypassed_uop_1_bypassable; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_1_mem_cmd = r_uop_bypassed_uop_1_mem_cmd; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_mem_size = r_uop_bypassed_uop_1_mem_size; // @[util.scala:73:26]
wire r_uop_newuop_1_mem_signed = r_uop_bypassed_uop_1_mem_signed; // @[util.scala:73:26]
wire r_uop_newuop_1_is_fence = r_uop_bypassed_uop_1_is_fence; // @[util.scala:73:26]
wire r_uop_newuop_1_is_fencei = r_uop_bypassed_uop_1_is_fencei; // @[util.scala:73:26]
wire r_uop_newuop_1_is_amo = r_uop_bypassed_uop_1_is_amo; // @[util.scala:73:26]
wire r_uop_newuop_1_uses_ldq = r_uop_bypassed_uop_1_uses_ldq; // @[util.scala:73:26]
wire r_uop_newuop_1_uses_stq = r_uop_bypassed_uop_1_uses_stq; // @[util.scala:73:26]
wire r_uop_newuop_1_is_sys_pc2epc = r_uop_bypassed_uop_1_is_sys_pc2epc; // @[util.scala:73:26]
wire r_uop_newuop_1_is_unique = r_uop_bypassed_uop_1_is_unique; // @[util.scala:73:26]
wire r_uop_newuop_1_flush_on_commit = r_uop_bypassed_uop_1_flush_on_commit; // @[util.scala:73:26]
wire r_uop_newuop_1_ldst_is_rs1 = r_uop_bypassed_uop_1_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_1_ldst = r_uop_bypassed_uop_1_ldst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_1_lrs1 = r_uop_bypassed_uop_1_lrs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_1_lrs2 = r_uop_bypassed_uop_1_lrs2; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_1_lrs3 = r_uop_bypassed_uop_1_lrs3; // @[util.scala:73:26]
wire r_uop_newuop_1_ldst_val = r_uop_bypassed_uop_1_ldst_val; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_dst_rtype = r_uop_bypassed_uop_1_dst_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_lrs1_rtype = r_uop_bypassed_uop_1_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_lrs2_rtype = r_uop_bypassed_uop_1_lrs2_rtype; // @[util.scala:73:26]
wire r_uop_newuop_1_frs3_en = r_uop_bypassed_uop_1_frs3_en; // @[util.scala:73:26]
wire r_uop_newuop_1_fp_val = r_uop_bypassed_uop_1_fp_val; // @[util.scala:73:26]
wire r_uop_newuop_1_fp_single = r_uop_bypassed_uop_1_fp_single; // @[util.scala:73:26]
wire r_uop_newuop_1_xcpt_pf_if = r_uop_bypassed_uop_1_xcpt_pf_if; // @[util.scala:73:26]
wire r_uop_newuop_1_xcpt_ae_if = r_uop_bypassed_uop_1_xcpt_ae_if; // @[util.scala:73:26]
wire r_uop_newuop_1_xcpt_ma_if = r_uop_bypassed_uop_1_xcpt_ma_if; // @[util.scala:73:26]
wire r_uop_newuop_1_bp_debug_if = r_uop_bypassed_uop_1_bp_debug_if; // @[util.scala:73:26]
wire r_uop_newuop_1_bp_xcpt_if = r_uop_bypassed_uop_1_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_debug_fsrc = r_uop_bypassed_uop_1_debug_fsrc; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_1_debug_tsrc = r_uop_bypassed_uop_1_debug_tsrc; // @[util.scala:73:26]
wire _r_uop_bypass_hits_rs1_T_3 = ren2_uops_0_ldst == next_uop_1_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_0_1 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs1_T_3; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs1_T_4 = ren2_uops_1_ldst == next_uop_1_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs1_T_4; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs1_T_5 = ren2_uops_2_ldst == next_uop_1_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_2_1 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs1_T_5; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs2_T_3 = ren2_uops_0_ldst == next_uop_1_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_0_1 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs2_T_3; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs2_T_4 = ren2_uops_1_ldst == next_uop_1_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs2_T_4; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs2_T_5 = ren2_uops_2_ldst == next_uop_1_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_2_1 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs2_T_5; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs3_T_3 = ren2_uops_0_ldst == next_uop_1_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_0_1 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs3_T_3; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_rs3_T_4 = ren2_uops_1_ldst == next_uop_1_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs3_T_4; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_rs3_T_5 = ren2_uops_2_ldst == next_uop_1_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_2_1 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs3_T_5; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_dst_T_3 = ren2_uops_0_ldst == next_uop_1_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_0_1 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_dst_T_3; // @[rename-stage.scala:109:29, :180:{77,87}]
wire _r_uop_bypass_hits_dst_T_4 = ren2_uops_1_ldst == next_uop_1_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_1_1 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_dst_T_4; // @[rename-stage.scala:109:29, :180:{77,87}]
wire _r_uop_bypass_hits_dst_T_5 = ren2_uops_2_ldst == next_uop_1_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_2_1 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_dst_T_5; // @[rename-stage.scala:109:29, :180:{77,87}]
wire [2:0] _r_uop_bypass_sel_rs1_enc_T_2 = {r_uop_bypass_hits_rs1_0_1, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs1_enc_T_3 = r_uop_bypass_hits_rs1_1_1 ? 3'h2 : _r_uop_bypass_sel_rs1_enc_T_2; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs1_enc_1 = r_uop_bypass_hits_rs1_2_1 ? 3'h1 : _r_uop_bypass_sel_rs1_enc_T_3; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs1_2_1 = r_uop_bypass_sel_rs1_enc_1[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs1_1_1 = r_uop_bypass_sel_rs1_enc_1[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs1_0_1 = r_uop_bypass_sel_rs1_enc_1[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_rs2_enc_T_2 = {r_uop_bypass_hits_rs2_0_1, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs2_enc_T_3 = r_uop_bypass_hits_rs2_1_1 ? 3'h2 : _r_uop_bypass_sel_rs2_enc_T_2; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs2_enc_1 = r_uop_bypass_hits_rs2_2_1 ? 3'h1 : _r_uop_bypass_sel_rs2_enc_T_3; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs2_2_1 = r_uop_bypass_sel_rs2_enc_1[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs2_1_1 = r_uop_bypass_sel_rs2_enc_1[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs2_0_1 = r_uop_bypass_sel_rs2_enc_1[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_rs3_enc_T_2 = {r_uop_bypass_hits_rs3_0_1, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs3_enc_T_3 = r_uop_bypass_hits_rs3_1_1 ? 3'h2 : _r_uop_bypass_sel_rs3_enc_T_2; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs3_enc_1 = r_uop_bypass_hits_rs3_2_1 ? 3'h1 : _r_uop_bypass_sel_rs3_enc_T_3; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs3_2_1 = r_uop_bypass_sel_rs3_enc_1[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs3_1_1 = r_uop_bypass_sel_rs3_enc_1[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs3_0_1 = r_uop_bypass_sel_rs3_enc_1[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_dst_enc_T_2 = {r_uop_bypass_hits_dst_0_1, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_dst_enc_T_3 = r_uop_bypass_hits_dst_1_1 ? 3'h2 : _r_uop_bypass_sel_dst_enc_T_2; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_dst_enc_1 = r_uop_bypass_hits_dst_2_1 ? 3'h1 : _r_uop_bypass_sel_dst_enc_T_3; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_dst_2_1 = r_uop_bypass_sel_dst_enc_1[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_dst_1_1 = r_uop_bypass_sel_dst_enc_1[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_dst_0_1 = r_uop_bypass_sel_dst_enc_1[2]; // @[OneHot.scala:83:30]
wire _r_uop_do_bypass_rs1_T_1 = r_uop_bypass_hits_rs1_0_1 | r_uop_bypass_hits_rs1_1_1; // @[rename-stage.scala:177:77, :187:49]
wire r_uop_do_bypass_rs1_1 = _r_uop_do_bypass_rs1_T_1 | r_uop_bypass_hits_rs1_2_1; // @[rename-stage.scala:177:77, :187:49]
wire _r_uop_do_bypass_rs2_T_1 = r_uop_bypass_hits_rs2_0_1 | r_uop_bypass_hits_rs2_1_1; // @[rename-stage.scala:178:77, :188:49]
wire r_uop_do_bypass_rs2_1 = _r_uop_do_bypass_rs2_T_1 | r_uop_bypass_hits_rs2_2_1; // @[rename-stage.scala:178:77, :188:49]
wire _r_uop_do_bypass_rs3_T_1 = r_uop_bypass_hits_rs3_0_1 | r_uop_bypass_hits_rs3_1_1; // @[rename-stage.scala:179:77, :189:49]
wire r_uop_do_bypass_rs3_1 = _r_uop_do_bypass_rs3_T_1 | r_uop_bypass_hits_rs3_2_1; // @[rename-stage.scala:179:77, :189:49]
wire _r_uop_bypassed_uop_prs3_busy_T_1 = r_uop_do_bypass_rs3_1; // @[rename-stage.scala:189:49, :201:45]
wire _r_uop_do_bypass_dst_T_1 = r_uop_bypass_hits_dst_0_1 | r_uop_bypass_hits_dst_1_1; // @[rename-stage.scala:180:77, :190:49]
wire r_uop_do_bypass_dst_1 = _r_uop_do_bypass_dst_T_1 | r_uop_bypass_hits_dst_2_1; // @[rename-stage.scala:180:77, :190:49]
wire [6:0] _r_uop_bypassed_uop_prs1_T_5 = r_uop_bypass_sel_rs1_0_1 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_6 = r_uop_bypass_sel_rs1_1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_7 = r_uop_bypass_sel_rs1_2_1 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_8 = _r_uop_bypassed_uop_prs1_T_5 | _r_uop_bypassed_uop_prs1_T_6; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs1_T_9 = _r_uop_bypassed_uop_prs1_T_8 | _r_uop_bypassed_uop_prs1_T_7; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs1_WIRE_1 = _r_uop_bypassed_uop_prs1_T_9; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_1_prs1 = r_uop_do_bypass_rs1_1 ? _r_uop_bypassed_uop_prs1_WIRE_1 : next_uop_1_prs1; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_T_5 = r_uop_bypass_sel_rs2_0_1 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_6 = r_uop_bypass_sel_rs2_1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_7 = r_uop_bypass_sel_rs2_2_1 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_8 = _r_uop_bypassed_uop_prs2_T_5 | _r_uop_bypassed_uop_prs2_T_6; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_T_9 = _r_uop_bypassed_uop_prs2_T_8 | _r_uop_bypassed_uop_prs2_T_7; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_WIRE_1 = _r_uop_bypassed_uop_prs2_T_9; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_1_prs2 = r_uop_do_bypass_rs2_1 ? _r_uop_bypassed_uop_prs2_WIRE_1 : next_uop_1_prs2; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_T_5 = r_uop_bypass_sel_rs3_0_1 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_6 = r_uop_bypass_sel_rs3_1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_7 = r_uop_bypass_sel_rs3_2_1 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_8 = _r_uop_bypassed_uop_prs3_T_5 | _r_uop_bypassed_uop_prs3_T_6; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_T_9 = _r_uop_bypassed_uop_prs3_T_8 | _r_uop_bypassed_uop_prs3_T_7; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_WIRE_1 = _r_uop_bypassed_uop_prs3_T_9; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_5 = r_uop_bypass_sel_dst_0_1 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_6 = r_uop_bypass_sel_dst_1_1 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_7 = r_uop_bypass_sel_dst_2_1 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_8 = _r_uop_bypassed_uop_stale_pdst_T_5 | _r_uop_bypassed_uop_stale_pdst_T_6; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_9 = _r_uop_bypassed_uop_stale_pdst_T_8 | _r_uop_bypassed_uop_stale_pdst_T_7; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_WIRE_1 = _r_uop_bypassed_uop_stale_pdst_T_9; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_1_stale_pdst = r_uop_do_bypass_dst_1 ? _r_uop_bypassed_uop_stale_pdst_WIRE_1 : next_uop_1_stale_pdst; // @[Mux.scala:30:73]
assign _r_uop_bypassed_uop_prs1_busy_T_1 = next_uop_1_prs1_busy | r_uop_do_bypass_rs1_1; // @[rename-stage.scala:123:24, :187:49, :199:45]
assign r_uop_bypassed_uop_1_prs1_busy = _r_uop_bypassed_uop_prs1_busy_T_1; // @[rename-stage.scala:174:28, :199:45]
assign _r_uop_bypassed_uop_prs2_busy_T_1 = next_uop_1_prs2_busy | r_uop_do_bypass_rs2_1; // @[rename-stage.scala:123:24, :188:49, :200:45]
assign r_uop_bypassed_uop_1_prs2_busy = _r_uop_bypassed_uop_prs2_busy_T_1; // @[rename-stage.scala:174:28, :200:45]
wire [15:0] _r_uop_newuop_br_mask_T_3; // @[util.scala:74:35]
wire [15:0] r_uop_newuop_1_br_mask; // @[util.scala:73:26]
wire [15:0] _r_uop_newuop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37]
assign _r_uop_newuop_br_mask_T_3 = r_uop_bypassed_uop_1_br_mask & _r_uop_newuop_br_mask_T_2; // @[util.scala:74:{35,37}]
assign r_uop_newuop_1_br_mask = _r_uop_newuop_br_mask_T_3; // @[util.scala:73:26, :74:35]
reg r_valid_2; // @[rename-stage.scala:121:27]
assign ren2_valids_2 = r_valid_2; // @[rename-stage.scala:107:29, :121:27]
reg [6:0] r_uop_2_uopc; // @[rename-stage.scala:122:23]
assign ren2_uops_2_uopc = r_uop_2_uopc; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_2_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_2_inst = r_uop_2_inst; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_2_debug_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_2_debug_inst = r_uop_2_debug_inst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_rvc; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_rvc = r_uop_2_is_rvc; // @[rename-stage.scala:108:29, :122:23]
reg [39:0] r_uop_2_debug_pc; // @[rename-stage.scala:122:23]
assign ren2_uops_2_debug_pc = r_uop_2_debug_pc; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_2_iq_type; // @[rename-stage.scala:122:23]
assign ren2_uops_2_iq_type = r_uop_2_iq_type; // @[rename-stage.scala:108:29, :122:23]
reg [9:0] r_uop_2_fu_code; // @[rename-stage.scala:122:23]
assign ren2_uops_2_fu_code = r_uop_2_fu_code; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_2_ctrl_br_type; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_br_type = r_uop_2_ctrl_br_type; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_ctrl_op1_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_op1_sel = r_uop_2_ctrl_op1_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_2_ctrl_op2_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_op2_sel = r_uop_2_ctrl_op2_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_2_ctrl_imm_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_imm_sel = r_uop_2_ctrl_imm_sel; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_2_ctrl_op_fcn; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_op_fcn = r_uop_2_ctrl_op_fcn; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_fcn_dw = r_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_csr_cmd = r_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_ctrl_is_load; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_is_load = r_uop_2_ctrl_is_load; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_ctrl_is_sta; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_is_sta = r_uop_2_ctrl_is_sta; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_ctrl_is_std; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ctrl_is_std = r_uop_2_ctrl_is_std; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_iw_state; // @[rename-stage.scala:122:23]
assign ren2_uops_2_iw_state = r_uop_2_iw_state; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_iw_p1_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_2_iw_p1_poisoned = r_uop_2_iw_p1_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_iw_p2_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_2_iw_p2_poisoned = r_uop_2_iw_p2_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_br; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_br = r_uop_2_is_br; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_jalr; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_jalr = r_uop_2_is_jalr; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_jal; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_jal = r_uop_2_is_jal; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_sfb; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_sfb = r_uop_2_is_sfb; // @[rename-stage.scala:108:29, :122:23]
reg [15:0] r_uop_2_br_mask; // @[rename-stage.scala:122:23]
assign ren2_uops_2_br_mask = r_uop_2_br_mask; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_2_br_tag; // @[rename-stage.scala:122:23]
assign ren2_uops_2_br_tag = r_uop_2_br_tag; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_2_ftq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ftq_idx = r_uop_2_ftq_idx; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_edge_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_2_edge_inst = r_uop_2_edge_inst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_2_pc_lob; // @[rename-stage.scala:122:23]
assign ren2_uops_2_pc_lob = r_uop_2_pc_lob; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_taken; // @[rename-stage.scala:122:23]
assign ren2_uops_2_taken = r_uop_2_taken; // @[rename-stage.scala:108:29, :122:23]
reg [19:0] r_uop_2_imm_packed; // @[rename-stage.scala:122:23]
assign ren2_uops_2_imm_packed = r_uop_2_imm_packed; // @[rename-stage.scala:108:29, :122:23]
reg [11:0] r_uop_2_csr_addr; // @[rename-stage.scala:122:23]
assign ren2_uops_2_csr_addr = r_uop_2_csr_addr; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_2_rob_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_2_rob_idx = r_uop_2_rob_idx; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_2_ldq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ldq_idx = r_uop_2_ldq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_2_stq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_2_stq_idx = r_uop_2_stq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_rxq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_2_rxq_idx = r_uop_2_rxq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_2_pdst; // @[rename-stage.scala:122:23]
reg [6:0] r_uop_2_prs1; // @[rename-stage.scala:122:23]
assign ren2_uops_2_prs1 = r_uop_2_prs1; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_2_prs2; // @[rename-stage.scala:122:23]
assign ren2_uops_2_prs2 = r_uop_2_prs2; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_2_ppred; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ppred = r_uop_2_ppred; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_prs1_busy; // @[rename-stage.scala:122:23]
reg r_uop_2_prs2_busy; // @[rename-stage.scala:122:23]
reg r_uop_2_ppred_busy; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ppred_busy = r_uop_2_ppred_busy; // @[rename-stage.scala:108:29, :122:23]
reg [6:0] r_uop_2_stale_pdst; // @[rename-stage.scala:122:23]
assign ren2_uops_2_stale_pdst = r_uop_2_stale_pdst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_exception; // @[rename-stage.scala:122:23]
assign ren2_uops_2_exception = r_uop_2_exception; // @[rename-stage.scala:108:29, :122:23]
reg [63:0] r_uop_2_exc_cause; // @[rename-stage.scala:122:23]
assign ren2_uops_2_exc_cause = r_uop_2_exc_cause; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_bypassable; // @[rename-stage.scala:122:23]
assign ren2_uops_2_bypassable = r_uop_2_bypassable; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_2_mem_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_2_mem_cmd = r_uop_2_mem_cmd; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_mem_size; // @[rename-stage.scala:122:23]
assign ren2_uops_2_mem_size = r_uop_2_mem_size; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_mem_signed; // @[rename-stage.scala:122:23]
assign ren2_uops_2_mem_signed = r_uop_2_mem_signed; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_fence; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_fence = r_uop_2_is_fence; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_fencei; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_fencei = r_uop_2_is_fencei; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_amo; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_amo = r_uop_2_is_amo; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_uses_ldq; // @[rename-stage.scala:122:23]
assign ren2_uops_2_uses_ldq = r_uop_2_uses_ldq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_uses_stq; // @[rename-stage.scala:122:23]
assign ren2_uops_2_uses_stq = r_uop_2_uses_stq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_sys_pc2epc; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_sys_pc2epc = r_uop_2_is_sys_pc2epc; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_is_unique; // @[rename-stage.scala:122:23]
assign ren2_uops_2_is_unique = r_uop_2_is_unique; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_flush_on_commit; // @[rename-stage.scala:122:23]
assign ren2_uops_2_flush_on_commit = r_uop_2_flush_on_commit; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_ldst_is_rs1; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ldst_is_rs1 = r_uop_2_ldst_is_rs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_2_ldst; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ldst = r_uop_2_ldst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_2_lrs1; // @[rename-stage.scala:122:23]
assign ren2_uops_2_lrs1 = r_uop_2_lrs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_2_lrs2; // @[rename-stage.scala:122:23]
assign ren2_uops_2_lrs2 = r_uop_2_lrs2; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_2_lrs3; // @[rename-stage.scala:122:23]
assign ren2_uops_2_lrs3 = r_uop_2_lrs3; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_ldst_val; // @[rename-stage.scala:122:23]
assign ren2_uops_2_ldst_val = r_uop_2_ldst_val; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_dst_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_2_dst_rtype = r_uop_2_dst_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_lrs1_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_2_lrs1_rtype = r_uop_2_lrs1_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_lrs2_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_2_lrs2_rtype = r_uop_2_lrs2_rtype; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_frs3_en; // @[rename-stage.scala:122:23]
assign ren2_uops_2_frs3_en = r_uop_2_frs3_en; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_fp_val; // @[rename-stage.scala:122:23]
assign ren2_uops_2_fp_val = r_uop_2_fp_val; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_fp_single; // @[rename-stage.scala:122:23]
assign ren2_uops_2_fp_single = r_uop_2_fp_single; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_xcpt_pf_if; // @[rename-stage.scala:122:23]
assign ren2_uops_2_xcpt_pf_if = r_uop_2_xcpt_pf_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_xcpt_ae_if; // @[rename-stage.scala:122:23]
assign ren2_uops_2_xcpt_ae_if = r_uop_2_xcpt_ae_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_xcpt_ma_if; // @[rename-stage.scala:122:23]
assign ren2_uops_2_xcpt_ma_if = r_uop_2_xcpt_ma_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_bp_debug_if; // @[rename-stage.scala:122:23]
assign ren2_uops_2_bp_debug_if = r_uop_2_bp_debug_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_2_bp_xcpt_if; // @[rename-stage.scala:122:23]
assign ren2_uops_2_bp_xcpt_if = r_uop_2_bp_xcpt_if; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_debug_fsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_2_debug_fsrc = r_uop_2_debug_fsrc; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_2_debug_tsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_2_debug_tsrc = r_uop_2_debug_tsrc; // @[rename-stage.scala:108:29, :122:23]
wire [6:0] r_uop_bypassed_uop_2_uopc = next_uop_2_uopc; // @[rename-stage.scala:123:24, :174:28]
wire [31:0] r_uop_bypassed_uop_2_inst = next_uop_2_inst; // @[rename-stage.scala:123:24, :174:28]
wire [31:0] r_uop_bypassed_uop_2_debug_inst = next_uop_2_debug_inst; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_rvc = next_uop_2_is_rvc; // @[rename-stage.scala:123:24, :174:28]
wire [39:0] r_uop_bypassed_uop_2_debug_pc = next_uop_2_debug_pc; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_2_iq_type = next_uop_2_iq_type; // @[rename-stage.scala:123:24, :174:28]
wire [9:0] r_uop_bypassed_uop_2_fu_code = next_uop_2_fu_code; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_2_ctrl_br_type = next_uop_2_ctrl_br_type; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_ctrl_op1_sel = next_uop_2_ctrl_op1_sel; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_2_ctrl_op2_sel = next_uop_2_ctrl_op2_sel; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_2_ctrl_imm_sel = next_uop_2_ctrl_imm_sel; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_2_ctrl_op_fcn = next_uop_2_ctrl_op_fcn; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_ctrl_fcn_dw = next_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_2_ctrl_csr_cmd = next_uop_2_ctrl_csr_cmd; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_ctrl_is_load = next_uop_2_ctrl_is_load; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_ctrl_is_sta = next_uop_2_ctrl_is_sta; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_ctrl_is_std = next_uop_2_ctrl_is_std; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_iw_state = next_uop_2_iw_state; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_iw_p1_poisoned = next_uop_2_iw_p1_poisoned; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_iw_p2_poisoned = next_uop_2_iw_p2_poisoned; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_br = next_uop_2_is_br; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_jalr = next_uop_2_is_jalr; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_jal = next_uop_2_is_jal; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_sfb = next_uop_2_is_sfb; // @[rename-stage.scala:123:24, :174:28]
wire [15:0] r_uop_bypassed_uop_2_br_mask = next_uop_2_br_mask; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_2_br_tag = next_uop_2_br_tag; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_2_ftq_idx = next_uop_2_ftq_idx; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_edge_inst = next_uop_2_edge_inst; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_2_pc_lob = next_uop_2_pc_lob; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_taken = next_uop_2_taken; // @[rename-stage.scala:123:24, :174:28]
wire [19:0] r_uop_bypassed_uop_2_imm_packed = next_uop_2_imm_packed; // @[rename-stage.scala:123:24, :174:28]
wire [11:0] r_uop_bypassed_uop_2_csr_addr = next_uop_2_csr_addr; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] r_uop_bypassed_uop_2_rob_idx = next_uop_2_rob_idx; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_2_ldq_idx = next_uop_2_ldq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_2_stq_idx = next_uop_2_stq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_rxq_idx = next_uop_2_rxq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] r_uop_bypassed_uop_2_pdst = next_uop_2_pdst; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_2_ppred = next_uop_2_ppred; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_ppred_busy = next_uop_2_ppred_busy; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_exception = next_uop_2_exception; // @[rename-stage.scala:123:24, :174:28]
wire [63:0] r_uop_bypassed_uop_2_exc_cause = next_uop_2_exc_cause; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_bypassable = next_uop_2_bypassable; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_2_mem_cmd = next_uop_2_mem_cmd; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_mem_size = next_uop_2_mem_size; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_mem_signed = next_uop_2_mem_signed; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_fence = next_uop_2_is_fence; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_fencei = next_uop_2_is_fencei; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_amo = next_uop_2_is_amo; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_uses_ldq = next_uop_2_uses_ldq; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_uses_stq = next_uop_2_uses_stq; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_sys_pc2epc = next_uop_2_is_sys_pc2epc; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_is_unique = next_uop_2_is_unique; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_flush_on_commit = next_uop_2_flush_on_commit; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_ldst_is_rs1 = next_uop_2_ldst_is_rs1; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_2_ldst = next_uop_2_ldst; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_2_lrs1 = next_uop_2_lrs1; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_2_lrs2 = next_uop_2_lrs2; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_2_lrs3 = next_uop_2_lrs3; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_ldst_val = next_uop_2_ldst_val; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_dst_rtype = next_uop_2_dst_rtype; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_lrs1_rtype = next_uop_2_lrs1_rtype; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_lrs2_rtype = next_uop_2_lrs2_rtype; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_frs3_en = next_uop_2_frs3_en; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_fp_val = next_uop_2_fp_val; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_fp_single = next_uop_2_fp_single; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_xcpt_pf_if = next_uop_2_xcpt_pf_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_xcpt_ae_if = next_uop_2_xcpt_ae_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_xcpt_ma_if = next_uop_2_xcpt_ma_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_bp_debug_if = next_uop_2_bp_debug_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_2_bp_xcpt_if = next_uop_2_bp_xcpt_if; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_debug_fsrc = next_uop_2_debug_fsrc; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_2_debug_tsrc = next_uop_2_debug_tsrc; // @[rename-stage.scala:123:24, :174:28]
wire [6:0] next_uop_2_prs1; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_2_prs2; // @[rename-stage.scala:123:24]
wire next_uop_2_prs1_busy; // @[rename-stage.scala:123:24]
wire next_uop_2_prs2_busy; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_2_stale_pdst; // @[rename-stage.scala:123:24]
wire _r_valid_T_4 = ~io_dis_fire_2_0; // @[rename-stage.scala:133:29, :160:7]
wire _r_valid_T_5 = r_valid_2 & _r_valid_T_4; // @[rename-stage.scala:121:27, :133:{26,29}]
assign next_uop_2_uopc = _GEN ? r_uop_2_uopc : ren1_uops_2_uopc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_inst = _GEN ? r_uop_2_inst : ren1_uops_2_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_debug_inst = _GEN ? r_uop_2_debug_inst : ren1_uops_2_debug_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_rvc = _GEN ? r_uop_2_is_rvc : ren1_uops_2_is_rvc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_debug_pc = _GEN ? r_uop_2_debug_pc : ren1_uops_2_debug_pc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_iq_type = _GEN ? r_uop_2_iq_type : ren1_uops_2_iq_type; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_fu_code = _GEN ? r_uop_2_fu_code : ren1_uops_2_fu_code; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_br_type = _GEN ? r_uop_2_ctrl_br_type : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_op1_sel = _GEN ? r_uop_2_ctrl_op1_sel : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_op2_sel = _GEN ? r_uop_2_ctrl_op2_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_imm_sel = _GEN ? r_uop_2_ctrl_imm_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_op_fcn = _GEN ? r_uop_2_ctrl_op_fcn : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_fcn_dw = _GEN & r_uop_2_ctrl_fcn_dw; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_csr_cmd = _GEN ? r_uop_2_ctrl_csr_cmd : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_is_load = _GEN & r_uop_2_ctrl_is_load; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_is_sta = _GEN & r_uop_2_ctrl_is_sta; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ctrl_is_std = _GEN & r_uop_2_ctrl_is_std; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_iw_state = _GEN ? r_uop_2_iw_state : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_iw_p1_poisoned = _GEN & r_uop_2_iw_p1_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_iw_p2_poisoned = _GEN & r_uop_2_iw_p2_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_br = _GEN ? r_uop_2_is_br : ren1_uops_2_is_br; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_jalr = _GEN ? r_uop_2_is_jalr : ren1_uops_2_is_jalr; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_jal = _GEN ? r_uop_2_is_jal : ren1_uops_2_is_jal; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_sfb = _GEN ? r_uop_2_is_sfb : ren1_uops_2_is_sfb; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_br_mask = _GEN ? r_uop_2_br_mask : ren1_uops_2_br_mask; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_br_tag = _GEN ? r_uop_2_br_tag : ren1_uops_2_br_tag; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ftq_idx = _GEN ? r_uop_2_ftq_idx : ren1_uops_2_ftq_idx; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_edge_inst = _GEN ? r_uop_2_edge_inst : ren1_uops_2_edge_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_pc_lob = _GEN ? r_uop_2_pc_lob : ren1_uops_2_pc_lob; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_taken = _GEN ? r_uop_2_taken : ren1_uops_2_taken; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_imm_packed = _GEN ? r_uop_2_imm_packed : ren1_uops_2_imm_packed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_csr_addr = _GEN ? r_uop_2_csr_addr : 12'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_rob_idx = _GEN ? r_uop_2_rob_idx : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ldq_idx = _GEN ? r_uop_2_ldq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_stq_idx = _GEN ? r_uop_2_stq_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_rxq_idx = _GEN ? r_uop_2_rxq_idx : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_pdst = _GEN ? r_uop_2_pdst : 7'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_prs1 = _GEN ? r_uop_2_prs1 : ren1_uops_2_prs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_prs2 = _GEN ? r_uop_2_prs2 : ren1_uops_2_prs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ppred = _GEN ? r_uop_2_ppred : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_prs1_busy = _GEN & r_uop_2_prs1_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_prs2_busy = _GEN & r_uop_2_prs2_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ppred_busy = _GEN & r_uop_2_ppred_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_stale_pdst = _GEN ? r_uop_2_stale_pdst : ren1_uops_2_stale_pdst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_exception = _GEN ? r_uop_2_exception : ren1_uops_2_exception; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_exc_cause = _GEN ? r_uop_2_exc_cause : ren1_uops_2_exc_cause; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_bypassable = _GEN ? r_uop_2_bypassable : ren1_uops_2_bypassable; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_mem_cmd = _GEN ? r_uop_2_mem_cmd : ren1_uops_2_mem_cmd; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_mem_size = _GEN ? r_uop_2_mem_size : ren1_uops_2_mem_size; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_mem_signed = _GEN ? r_uop_2_mem_signed : ren1_uops_2_mem_signed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_fence = _GEN ? r_uop_2_is_fence : ren1_uops_2_is_fence; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_fencei = _GEN ? r_uop_2_is_fencei : ren1_uops_2_is_fencei; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_amo = _GEN ? r_uop_2_is_amo : ren1_uops_2_is_amo; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_uses_ldq = _GEN ? r_uop_2_uses_ldq : ren1_uops_2_uses_ldq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_uses_stq = _GEN ? r_uop_2_uses_stq : ren1_uops_2_uses_stq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_sys_pc2epc = _GEN ? r_uop_2_is_sys_pc2epc : ren1_uops_2_is_sys_pc2epc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_is_unique = _GEN ? r_uop_2_is_unique : ren1_uops_2_is_unique; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_flush_on_commit = _GEN ? r_uop_2_flush_on_commit : ren1_uops_2_flush_on_commit; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ldst_is_rs1 = _GEN & r_uop_2_ldst_is_rs1; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ldst = _GEN ? r_uop_2_ldst : ren1_uops_2_ldst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_lrs1 = _GEN ? r_uop_2_lrs1 : ren1_uops_2_lrs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_lrs2 = _GEN ? r_uop_2_lrs2 : ren1_uops_2_lrs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_lrs3 = _GEN ? r_uop_2_lrs3 : ren1_uops_2_lrs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_ldst_val = _GEN ? r_uop_2_ldst_val : ren1_uops_2_ldst_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_dst_rtype = _GEN ? r_uop_2_dst_rtype : ren1_uops_2_dst_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_lrs1_rtype = _GEN ? r_uop_2_lrs1_rtype : ren1_uops_2_lrs1_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_lrs2_rtype = _GEN ? r_uop_2_lrs2_rtype : ren1_uops_2_lrs2_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_frs3_en = _GEN ? r_uop_2_frs3_en : ren1_uops_2_frs3_en; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_fp_val = _GEN ? r_uop_2_fp_val : ren1_uops_2_fp_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_fp_single = _GEN ? r_uop_2_fp_single : ren1_uops_2_fp_single; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_xcpt_pf_if = _GEN ? r_uop_2_xcpt_pf_if : ren1_uops_2_xcpt_pf_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_xcpt_ae_if = _GEN ? r_uop_2_xcpt_ae_if : ren1_uops_2_xcpt_ae_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_xcpt_ma_if = _GEN & r_uop_2_xcpt_ma_if; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_bp_debug_if = _GEN ? r_uop_2_bp_debug_if : ren1_uops_2_bp_debug_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_bp_xcpt_if = _GEN ? r_uop_2_bp_xcpt_if : ren1_uops_2_bp_xcpt_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_debug_fsrc = _GEN ? r_uop_2_debug_fsrc : ren1_uops_2_debug_fsrc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_2_debug_tsrc = _GEN ? r_uop_2_debug_tsrc : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
wire [6:0] r_uop_newuop_2_uopc = r_uop_bypassed_uop_2_uopc; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_2_inst = r_uop_bypassed_uop_2_inst; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_2_debug_inst = r_uop_bypassed_uop_2_debug_inst; // @[util.scala:73:26]
wire r_uop_newuop_2_is_rvc = r_uop_bypassed_uop_2_is_rvc; // @[util.scala:73:26]
wire [39:0] r_uop_newuop_2_debug_pc = r_uop_bypassed_uop_2_debug_pc; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_2_iq_type = r_uop_bypassed_uop_2_iq_type; // @[util.scala:73:26]
wire [9:0] r_uop_newuop_2_fu_code = r_uop_bypassed_uop_2_fu_code; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_2_ctrl_br_type = r_uop_bypassed_uop_2_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_ctrl_op1_sel = r_uop_bypassed_uop_2_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_2_ctrl_op2_sel = r_uop_bypassed_uop_2_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_2_ctrl_imm_sel = r_uop_bypassed_uop_2_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_2_ctrl_op_fcn = r_uop_bypassed_uop_2_ctrl_op_fcn; // @[util.scala:73:26]
wire r_uop_newuop_2_ctrl_fcn_dw = r_uop_bypassed_uop_2_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_2_ctrl_csr_cmd = r_uop_bypassed_uop_2_ctrl_csr_cmd; // @[util.scala:73:26]
wire r_uop_newuop_2_ctrl_is_load = r_uop_bypassed_uop_2_ctrl_is_load; // @[util.scala:73:26]
wire r_uop_newuop_2_ctrl_is_sta = r_uop_bypassed_uop_2_ctrl_is_sta; // @[util.scala:73:26]
wire r_uop_newuop_2_ctrl_is_std = r_uop_bypassed_uop_2_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_iw_state = r_uop_bypassed_uop_2_iw_state; // @[util.scala:73:26]
wire r_uop_newuop_2_iw_p1_poisoned = r_uop_bypassed_uop_2_iw_p1_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_2_iw_p2_poisoned = r_uop_bypassed_uop_2_iw_p2_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_2_is_br = r_uop_bypassed_uop_2_is_br; // @[util.scala:73:26]
wire r_uop_newuop_2_is_jalr = r_uop_bypassed_uop_2_is_jalr; // @[util.scala:73:26]
wire r_uop_newuop_2_is_jal = r_uop_bypassed_uop_2_is_jal; // @[util.scala:73:26]
wire r_uop_newuop_2_is_sfb = r_uop_bypassed_uop_2_is_sfb; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_2_br_tag = r_uop_bypassed_uop_2_br_tag; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_2_ftq_idx = r_uop_bypassed_uop_2_ftq_idx; // @[util.scala:73:26]
wire r_uop_newuop_2_edge_inst = r_uop_bypassed_uop_2_edge_inst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_2_pc_lob = r_uop_bypassed_uop_2_pc_lob; // @[util.scala:73:26]
wire r_uop_newuop_2_taken = r_uop_bypassed_uop_2_taken; // @[util.scala:73:26]
wire [19:0] r_uop_newuop_2_imm_packed = r_uop_bypassed_uop_2_imm_packed; // @[util.scala:73:26]
wire [11:0] r_uop_newuop_2_csr_addr = r_uop_bypassed_uop_2_csr_addr; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_2_rob_idx = r_uop_bypassed_uop_2_rob_idx; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_2_ldq_idx = r_uop_bypassed_uop_2_ldq_idx; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_2_stq_idx = r_uop_bypassed_uop_2_stq_idx; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_rxq_idx = r_uop_bypassed_uop_2_rxq_idx; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_2_pdst = r_uop_bypassed_uop_2_pdst; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_2_prs1 = r_uop_bypassed_uop_2_prs1; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_2_prs2 = r_uop_bypassed_uop_2_prs2; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs1_busy_T_2; // @[rename-stage.scala:199:45]
wire [4:0] r_uop_newuop_2_ppred = r_uop_bypassed_uop_2_ppred; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs2_busy_T_2; // @[rename-stage.scala:200:45]
wire r_uop_newuop_2_prs1_busy = r_uop_bypassed_uop_2_prs1_busy; // @[util.scala:73:26]
wire r_uop_newuop_2_prs2_busy = r_uop_bypassed_uop_2_prs2_busy; // @[util.scala:73:26]
wire r_uop_newuop_2_ppred_busy = r_uop_bypassed_uop_2_ppred_busy; // @[util.scala:73:26]
wire [6:0] r_uop_newuop_2_stale_pdst = r_uop_bypassed_uop_2_stale_pdst; // @[util.scala:73:26]
wire r_uop_newuop_2_exception = r_uop_bypassed_uop_2_exception; // @[util.scala:73:26]
wire [63:0] r_uop_newuop_2_exc_cause = r_uop_bypassed_uop_2_exc_cause; // @[util.scala:73:26]
wire r_uop_newuop_2_bypassable = r_uop_bypassed_uop_2_bypassable; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_2_mem_cmd = r_uop_bypassed_uop_2_mem_cmd; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_mem_size = r_uop_bypassed_uop_2_mem_size; // @[util.scala:73:26]
wire r_uop_newuop_2_mem_signed = r_uop_bypassed_uop_2_mem_signed; // @[util.scala:73:26]
wire r_uop_newuop_2_is_fence = r_uop_bypassed_uop_2_is_fence; // @[util.scala:73:26]
wire r_uop_newuop_2_is_fencei = r_uop_bypassed_uop_2_is_fencei; // @[util.scala:73:26]
wire r_uop_newuop_2_is_amo = r_uop_bypassed_uop_2_is_amo; // @[util.scala:73:26]
wire r_uop_newuop_2_uses_ldq = r_uop_bypassed_uop_2_uses_ldq; // @[util.scala:73:26]
wire r_uop_newuop_2_uses_stq = r_uop_bypassed_uop_2_uses_stq; // @[util.scala:73:26]
wire r_uop_newuop_2_is_sys_pc2epc = r_uop_bypassed_uop_2_is_sys_pc2epc; // @[util.scala:73:26]
wire r_uop_newuop_2_is_unique = r_uop_bypassed_uop_2_is_unique; // @[util.scala:73:26]
wire r_uop_newuop_2_flush_on_commit = r_uop_bypassed_uop_2_flush_on_commit; // @[util.scala:73:26]
wire r_uop_newuop_2_ldst_is_rs1 = r_uop_bypassed_uop_2_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_2_ldst = r_uop_bypassed_uop_2_ldst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_2_lrs1 = r_uop_bypassed_uop_2_lrs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_2_lrs2 = r_uop_bypassed_uop_2_lrs2; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_2_lrs3 = r_uop_bypassed_uop_2_lrs3; // @[util.scala:73:26]
wire r_uop_newuop_2_ldst_val = r_uop_bypassed_uop_2_ldst_val; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_dst_rtype = r_uop_bypassed_uop_2_dst_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_lrs1_rtype = r_uop_bypassed_uop_2_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_lrs2_rtype = r_uop_bypassed_uop_2_lrs2_rtype; // @[util.scala:73:26]
wire r_uop_newuop_2_frs3_en = r_uop_bypassed_uop_2_frs3_en; // @[util.scala:73:26]
wire r_uop_newuop_2_fp_val = r_uop_bypassed_uop_2_fp_val; // @[util.scala:73:26]
wire r_uop_newuop_2_fp_single = r_uop_bypassed_uop_2_fp_single; // @[util.scala:73:26]
wire r_uop_newuop_2_xcpt_pf_if = r_uop_bypassed_uop_2_xcpt_pf_if; // @[util.scala:73:26]
wire r_uop_newuop_2_xcpt_ae_if = r_uop_bypassed_uop_2_xcpt_ae_if; // @[util.scala:73:26]
wire r_uop_newuop_2_xcpt_ma_if = r_uop_bypassed_uop_2_xcpt_ma_if; // @[util.scala:73:26]
wire r_uop_newuop_2_bp_debug_if = r_uop_bypassed_uop_2_bp_debug_if; // @[util.scala:73:26]
wire r_uop_newuop_2_bp_xcpt_if = r_uop_bypassed_uop_2_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_debug_fsrc = r_uop_bypassed_uop_2_debug_fsrc; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_2_debug_tsrc = r_uop_bypassed_uop_2_debug_tsrc; // @[util.scala:73:26]
wire _r_uop_bypass_hits_rs1_T_6 = ren2_uops_0_ldst == next_uop_2_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_0_2 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs1_T_6; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs1_T_7 = ren2_uops_1_ldst == next_uop_2_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_1_2 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs1_T_7; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs1_T_8 = ren2_uops_2_ldst == next_uop_2_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs1_T_8; // @[rename-stage.scala:109:29, :177:{77,87}]
wire _r_uop_bypass_hits_rs2_T_6 = ren2_uops_0_ldst == next_uop_2_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_0_2 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs2_T_6; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs2_T_7 = ren2_uops_1_ldst == next_uop_2_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_1_2 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs2_T_7; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs2_T_8 = ren2_uops_2_ldst == next_uop_2_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs2_T_8; // @[rename-stage.scala:109:29, :178:{77,87}]
wire _r_uop_bypass_hits_rs3_T_6 = ren2_uops_0_ldst == next_uop_2_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_0_2 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs3_T_6; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_rs3_T_7 = ren2_uops_1_ldst == next_uop_2_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_1_2 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_rs3_T_7; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_rs3_T_8 = ren2_uops_2_ldst == next_uop_2_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_rs3_T_8; // @[rename-stage.scala:109:29, :179:{77,87}]
wire _r_uop_bypass_hits_dst_T_6 = ren2_uops_0_ldst == next_uop_2_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_0_2 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_dst_T_6; // @[rename-stage.scala:109:29, :180:{77,87}]
wire _r_uop_bypass_hits_dst_T_7 = ren2_uops_1_ldst == next_uop_2_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_1_2 = ren2_alloc_reqs_1 & _r_uop_bypass_hits_dst_T_7; // @[rename-stage.scala:109:29, :180:{77,87}]
wire _r_uop_bypass_hits_dst_T_8 = ren2_uops_2_ldst == next_uop_2_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_2_2 = ren2_alloc_reqs_2 & _r_uop_bypass_hits_dst_T_8; // @[rename-stage.scala:109:29, :180:{77,87}]
wire [2:0] _r_uop_bypass_sel_rs1_enc_T_4 = {r_uop_bypass_hits_rs1_0_2, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs1_enc_T_5 = r_uop_bypass_hits_rs1_1_2 ? 3'h2 : _r_uop_bypass_sel_rs1_enc_T_4; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs1_enc_2 = r_uop_bypass_hits_rs1_2_2 ? 3'h1 : _r_uop_bypass_sel_rs1_enc_T_5; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs1_2_2 = r_uop_bypass_sel_rs1_enc_2[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs1_1_2 = r_uop_bypass_sel_rs1_enc_2[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs1_0_2 = r_uop_bypass_sel_rs1_enc_2[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_rs2_enc_T_4 = {r_uop_bypass_hits_rs2_0_2, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs2_enc_T_5 = r_uop_bypass_hits_rs2_1_2 ? 3'h2 : _r_uop_bypass_sel_rs2_enc_T_4; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs2_enc_2 = r_uop_bypass_hits_rs2_2_2 ? 3'h1 : _r_uop_bypass_sel_rs2_enc_T_5; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs2_2_2 = r_uop_bypass_sel_rs2_enc_2[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs2_1_2 = r_uop_bypass_sel_rs2_enc_2[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs2_0_2 = r_uop_bypass_sel_rs2_enc_2[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_rs3_enc_T_4 = {r_uop_bypass_hits_rs3_0_2, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_rs3_enc_T_5 = r_uop_bypass_hits_rs3_1_2 ? 3'h2 : _r_uop_bypass_sel_rs3_enc_T_4; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_rs3_enc_2 = r_uop_bypass_hits_rs3_2_2 ? 3'h1 : _r_uop_bypass_sel_rs3_enc_T_5; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs3_2_2 = r_uop_bypass_sel_rs3_enc_2[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs3_1_2 = r_uop_bypass_sel_rs3_enc_2[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs3_0_2 = r_uop_bypass_sel_rs3_enc_2[2]; // @[OneHot.scala:83:30]
wire [2:0] _r_uop_bypass_sel_dst_enc_T_4 = {r_uop_bypass_hits_dst_0_2, 2'h0}; // @[Mux.scala:50:70]
wire [2:0] _r_uop_bypass_sel_dst_enc_T_5 = r_uop_bypass_hits_dst_1_2 ? 3'h2 : _r_uop_bypass_sel_dst_enc_T_4; // @[Mux.scala:50:70]
wire [2:0] r_uop_bypass_sel_dst_enc_2 = r_uop_bypass_hits_dst_2_2 ? 3'h1 : _r_uop_bypass_sel_dst_enc_T_5; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_dst_2_2 = r_uop_bypass_sel_dst_enc_2[0]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_dst_1_2 = r_uop_bypass_sel_dst_enc_2[1]; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_dst_0_2 = r_uop_bypass_sel_dst_enc_2[2]; // @[OneHot.scala:83:30]
wire _r_uop_do_bypass_rs1_T_2 = r_uop_bypass_hits_rs1_0_2 | r_uop_bypass_hits_rs1_1_2; // @[rename-stage.scala:177:77, :187:49]
wire r_uop_do_bypass_rs1_2 = _r_uop_do_bypass_rs1_T_2 | r_uop_bypass_hits_rs1_2_2; // @[rename-stage.scala:177:77, :187:49]
wire _r_uop_do_bypass_rs2_T_2 = r_uop_bypass_hits_rs2_0_2 | r_uop_bypass_hits_rs2_1_2; // @[rename-stage.scala:178:77, :188:49]
wire r_uop_do_bypass_rs2_2 = _r_uop_do_bypass_rs2_T_2 | r_uop_bypass_hits_rs2_2_2; // @[rename-stage.scala:178:77, :188:49]
wire _r_uop_do_bypass_rs3_T_2 = r_uop_bypass_hits_rs3_0_2 | r_uop_bypass_hits_rs3_1_2; // @[rename-stage.scala:179:77, :189:49]
wire r_uop_do_bypass_rs3_2 = _r_uop_do_bypass_rs3_T_2 | r_uop_bypass_hits_rs3_2_2; // @[rename-stage.scala:179:77, :189:49]
wire _r_uop_bypassed_uop_prs3_busy_T_2 = r_uop_do_bypass_rs3_2; // @[rename-stage.scala:189:49, :201:45]
wire _r_uop_do_bypass_dst_T_2 = r_uop_bypass_hits_dst_0_2 | r_uop_bypass_hits_dst_1_2; // @[rename-stage.scala:180:77, :190:49]
wire r_uop_do_bypass_dst_2 = _r_uop_do_bypass_dst_T_2 | r_uop_bypass_hits_dst_2_2; // @[rename-stage.scala:180:77, :190:49]
wire [6:0] _r_uop_bypassed_uop_prs1_T_10 = r_uop_bypass_sel_rs1_0_2 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_11 = r_uop_bypass_sel_rs1_1_2 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_12 = r_uop_bypass_sel_rs1_2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs1_T_13 = _r_uop_bypassed_uop_prs1_T_10 | _r_uop_bypassed_uop_prs1_T_11; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs1_T_14 = _r_uop_bypassed_uop_prs1_T_13 | _r_uop_bypassed_uop_prs1_T_12; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs1_WIRE_2 = _r_uop_bypassed_uop_prs1_T_14; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_2_prs1 = r_uop_do_bypass_rs1_2 ? _r_uop_bypassed_uop_prs1_WIRE_2 : next_uop_2_prs1; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_T_10 = r_uop_bypass_sel_rs2_0_2 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_11 = r_uop_bypass_sel_rs2_1_2 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_12 = r_uop_bypass_sel_rs2_2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs2_T_13 = _r_uop_bypassed_uop_prs2_T_10 | _r_uop_bypassed_uop_prs2_T_11; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_T_14 = _r_uop_bypassed_uop_prs2_T_13 | _r_uop_bypassed_uop_prs2_T_12; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs2_WIRE_2 = _r_uop_bypassed_uop_prs2_T_14; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_2_prs2 = r_uop_do_bypass_rs2_2 ? _r_uop_bypassed_uop_prs2_WIRE_2 : next_uop_2_prs2; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_T_10 = r_uop_bypass_sel_rs3_0_2 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_11 = r_uop_bypass_sel_rs3_1_2 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_12 = r_uop_bypass_sel_rs3_2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_prs3_T_13 = _r_uop_bypassed_uop_prs3_T_10 | _r_uop_bypassed_uop_prs3_T_11; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_T_14 = _r_uop_bypassed_uop_prs3_T_13 | _r_uop_bypassed_uop_prs3_T_12; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_prs3_WIRE_2 = _r_uop_bypassed_uop_prs3_T_14; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_10 = r_uop_bypass_sel_dst_0_2 ? ren2_uops_0_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_11 = r_uop_bypass_sel_dst_1_2 ? ren2_uops_1_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_12 = r_uop_bypass_sel_dst_2_2 ? ren2_uops_2_pdst : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_13 = _r_uop_bypassed_uop_stale_pdst_T_10 | _r_uop_bypassed_uop_stale_pdst_T_11; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_T_14 = _r_uop_bypassed_uop_stale_pdst_T_13 | _r_uop_bypassed_uop_stale_pdst_T_12; // @[Mux.scala:30:73]
wire [6:0] _r_uop_bypassed_uop_stale_pdst_WIRE_2 = _r_uop_bypassed_uop_stale_pdst_T_14; // @[Mux.scala:30:73]
assign r_uop_bypassed_uop_2_stale_pdst = r_uop_do_bypass_dst_2 ? _r_uop_bypassed_uop_stale_pdst_WIRE_2 : next_uop_2_stale_pdst; // @[Mux.scala:30:73]
assign _r_uop_bypassed_uop_prs1_busy_T_2 = next_uop_2_prs1_busy | r_uop_do_bypass_rs1_2; // @[rename-stage.scala:123:24, :187:49, :199:45]
assign r_uop_bypassed_uop_2_prs1_busy = _r_uop_bypassed_uop_prs1_busy_T_2; // @[rename-stage.scala:174:28, :199:45]
assign _r_uop_bypassed_uop_prs2_busy_T_2 = next_uop_2_prs2_busy | r_uop_do_bypass_rs2_2; // @[rename-stage.scala:123:24, :188:49, :200:45]
assign r_uop_bypassed_uop_2_prs2_busy = _r_uop_bypassed_uop_prs2_busy_T_2; // @[rename-stage.scala:174:28, :200:45]
wire [15:0] _r_uop_newuop_br_mask_T_5; // @[util.scala:74:35]
wire [15:0] r_uop_newuop_2_br_mask; // @[util.scala:73:26]
wire [15:0] _r_uop_newuop_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37]
assign _r_uop_newuop_br_mask_T_5 = r_uop_bypassed_uop_2_br_mask & _r_uop_newuop_br_mask_T_4; // @[util.scala:74:{35,37}]
assign r_uop_newuop_2_br_mask = _r_uop_newuop_br_mask_T_5; // @[util.scala:73:26, :74:35]
wire _ren2_br_tags_0_valid_T_3; // @[rename-stage.scala:241:43]
wire _ren2_br_tags_1_valid_T_3; // @[rename-stage.scala:241:43]
wire _ren2_br_tags_2_valid_T_3; // @[rename-stage.scala:241:43]
wire ren2_br_tags_0_valid; // @[rename-stage.scala:233:29]
wire ren2_br_tags_1_valid; // @[rename-stage.scala:233:29]
wire ren2_br_tags_2_valid; // @[rename-stage.scala:233:29]
wire _com_valids_0_T_2; // @[rename-stage.scala:243:92]
wire _com_valids_1_T_2; // @[rename-stage.scala:243:92]
wire _com_valids_2_T_2; // @[rename-stage.scala:243:92]
wire com_valids_0; // @[rename-stage.scala:236:29]
wire com_valids_1; // @[rename-stage.scala:236:29]
wire com_valids_2; // @[rename-stage.scala:236:29]
wire _rbk_valids_0_T_2; // @[rename-stage.scala:244:92]
wire _rbk_valids_1_T_2; // @[rename-stage.scala:244:92]
wire _rbk_valids_2_T_2; // @[rename-stage.scala:244:92]
wire rbk_valids_0; // @[rename-stage.scala:237:29]
wire rbk_valids_1; // @[rename-stage.scala:237:29]
wire rbk_valids_2; // @[rename-stage.scala:237:29]
wire _GEN_0 = ren2_uops_0_dst_rtype == 2'h0; // @[rename-stage.scala:108:29, :240:78]
wire _ren2_alloc_reqs_0_T; // @[rename-stage.scala:240:78]
assign _ren2_alloc_reqs_0_T = _GEN_0; // @[rename-stage.scala:240:78]
wire _io_ren_stalls_0_T; // @[rename-stage.scala:339:49]
assign _io_ren_stalls_0_T = _GEN_0; // @[rename-stage.scala:240:78, :339:49]
wire _ren2_alloc_reqs_0_T_1 = ren2_uops_0_ldst_val & _ren2_alloc_reqs_0_T; // @[rename-stage.scala:108:29, :240:{52,78}]
assign _ren2_alloc_reqs_0_T_2 = _ren2_alloc_reqs_0_T_1 & io_dis_fire_0_0; // @[rename-stage.scala:160:7, :240:{52,88}]
assign ren2_alloc_reqs_0 = _ren2_alloc_reqs_0_T_2; // @[rename-stage.scala:109:29, :240:88]
wire _ren2_br_tags_0_valid_T = ~ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29]
wire _ren2_br_tags_0_valid_T_1 = ren2_uops_0_is_br & _ren2_br_tags_0_valid_T; // @[rename-stage.scala:108:29]
wire _ren2_br_tags_0_valid_T_2 = _ren2_br_tags_0_valid_T_1 | ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29]
assign _ren2_br_tags_0_valid_T_3 = io_dis_fire_0_0 & _ren2_br_tags_0_valid_T_2; // @[rename-stage.scala:160:7, :241:43]
assign ren2_br_tags_0_valid = _ren2_br_tags_0_valid_T_3; // @[rename-stage.scala:233:29, :241:43]
wire _GEN_1 = io_com_uops_0_dst_rtype_0 == 2'h0; // @[rename-stage.scala:160:7, :243:82]
wire _com_valids_0_T; // @[rename-stage.scala:243:82]
assign _com_valids_0_T = _GEN_1; // @[rename-stage.scala:243:82]
wire _rbk_valids_0_T; // @[rename-stage.scala:244:82]
assign _rbk_valids_0_T = _GEN_1; // @[rename-stage.scala:243:82, :244:82]
wire _com_valids_0_T_1 = io_com_uops_0_ldst_val_0 & _com_valids_0_T; // @[rename-stage.scala:160:7, :243:{54,82}]
assign _com_valids_0_T_2 = _com_valids_0_T_1 & io_com_valids_0_0; // @[rename-stage.scala:160:7, :243:{54,92}]
assign com_valids_0 = _com_valids_0_T_2; // @[rename-stage.scala:236:29, :243:92]
wire _rbk_valids_0_T_1 = io_com_uops_0_ldst_val_0 & _rbk_valids_0_T; // @[rename-stage.scala:160:7, :244:{54,82}]
assign _rbk_valids_0_T_2 = _rbk_valids_0_T_1 & io_rbk_valids_0_0; // @[rename-stage.scala:160:7, :244:{54,92}]
assign rbk_valids_0 = _rbk_valids_0_T_2; // @[rename-stage.scala:237:29, :244:92]
wire _GEN_2 = ren2_uops_1_dst_rtype == 2'h0; // @[rename-stage.scala:108:29, :240:78]
wire _ren2_alloc_reqs_1_T; // @[rename-stage.scala:240:78]
assign _ren2_alloc_reqs_1_T = _GEN_2; // @[rename-stage.scala:240:78]
wire _io_ren_stalls_1_T; // @[rename-stage.scala:339:49]
assign _io_ren_stalls_1_T = _GEN_2; // @[rename-stage.scala:240:78, :339:49]
wire _ren2_alloc_reqs_1_T_1 = ren2_uops_1_ldst_val & _ren2_alloc_reqs_1_T; // @[rename-stage.scala:108:29, :240:{52,78}]
assign _ren2_alloc_reqs_1_T_2 = _ren2_alloc_reqs_1_T_1 & io_dis_fire_1_0; // @[rename-stage.scala:160:7, :240:{52,88}]
assign ren2_alloc_reqs_1 = _ren2_alloc_reqs_1_T_2; // @[rename-stage.scala:109:29, :240:88]
wire _ren2_br_tags_1_valid_T = ~ren2_uops_1_is_sfb; // @[rename-stage.scala:108:29]
wire _ren2_br_tags_1_valid_T_1 = ren2_uops_1_is_br & _ren2_br_tags_1_valid_T; // @[rename-stage.scala:108:29]
wire _ren2_br_tags_1_valid_T_2 = _ren2_br_tags_1_valid_T_1 | ren2_uops_1_is_jalr; // @[rename-stage.scala:108:29]
assign _ren2_br_tags_1_valid_T_3 = io_dis_fire_1_0 & _ren2_br_tags_1_valid_T_2; // @[rename-stage.scala:160:7, :241:43]
assign ren2_br_tags_1_valid = _ren2_br_tags_1_valid_T_3; // @[rename-stage.scala:233:29, :241:43]
wire _GEN_3 = io_com_uops_1_dst_rtype_0 == 2'h0; // @[rename-stage.scala:160:7, :243:82]
wire _com_valids_1_T; // @[rename-stage.scala:243:82]
assign _com_valids_1_T = _GEN_3; // @[rename-stage.scala:243:82]
wire _rbk_valids_1_T; // @[rename-stage.scala:244:82]
assign _rbk_valids_1_T = _GEN_3; // @[rename-stage.scala:243:82, :244:82]
wire _com_valids_1_T_1 = io_com_uops_1_ldst_val_0 & _com_valids_1_T; // @[rename-stage.scala:160:7, :243:{54,82}]
assign _com_valids_1_T_2 = _com_valids_1_T_1 & io_com_valids_1_0; // @[rename-stage.scala:160:7, :243:{54,92}]
assign com_valids_1 = _com_valids_1_T_2; // @[rename-stage.scala:236:29, :243:92]
wire _rbk_valids_1_T_1 = io_com_uops_1_ldst_val_0 & _rbk_valids_1_T; // @[rename-stage.scala:160:7, :244:{54,82}]
assign _rbk_valids_1_T_2 = _rbk_valids_1_T_1 & io_rbk_valids_1_0; // @[rename-stage.scala:160:7, :244:{54,92}]
assign rbk_valids_1 = _rbk_valids_1_T_2; // @[rename-stage.scala:237:29, :244:92]
wire _GEN_4 = ren2_uops_2_dst_rtype == 2'h0; // @[rename-stage.scala:108:29, :240:78]
wire _ren2_alloc_reqs_2_T; // @[rename-stage.scala:240:78]
assign _ren2_alloc_reqs_2_T = _GEN_4; // @[rename-stage.scala:240:78]
wire _io_ren_stalls_2_T; // @[rename-stage.scala:339:49]
assign _io_ren_stalls_2_T = _GEN_4; // @[rename-stage.scala:240:78, :339:49]
wire _ren2_alloc_reqs_2_T_1 = ren2_uops_2_ldst_val & _ren2_alloc_reqs_2_T; // @[rename-stage.scala:108:29, :240:{52,78}]
assign _ren2_alloc_reqs_2_T_2 = _ren2_alloc_reqs_2_T_1 & io_dis_fire_2_0; // @[rename-stage.scala:160:7, :240:{52,88}]
assign ren2_alloc_reqs_2 = _ren2_alloc_reqs_2_T_2; // @[rename-stage.scala:109:29, :240:88]
wire _ren2_br_tags_2_valid_T = ~ren2_uops_2_is_sfb; // @[rename-stage.scala:108:29]
wire _ren2_br_tags_2_valid_T_1 = ren2_uops_2_is_br & _ren2_br_tags_2_valid_T; // @[rename-stage.scala:108:29]
wire _ren2_br_tags_2_valid_T_2 = _ren2_br_tags_2_valid_T_1 | ren2_uops_2_is_jalr; // @[rename-stage.scala:108:29]
assign _ren2_br_tags_2_valid_T_3 = io_dis_fire_2_0 & _ren2_br_tags_2_valid_T_2; // @[rename-stage.scala:160:7, :241:43]
assign ren2_br_tags_2_valid = _ren2_br_tags_2_valid_T_3; // @[rename-stage.scala:233:29, :241:43]
wire _GEN_5 = io_com_uops_2_dst_rtype_0 == 2'h0; // @[rename-stage.scala:160:7, :243:82]
wire _com_valids_2_T; // @[rename-stage.scala:243:82]
assign _com_valids_2_T = _GEN_5; // @[rename-stage.scala:243:82]
wire _rbk_valids_2_T; // @[rename-stage.scala:244:82]
assign _rbk_valids_2_T = _GEN_5; // @[rename-stage.scala:243:82, :244:82]
wire _com_valids_2_T_1 = io_com_uops_2_ldst_val_0 & _com_valids_2_T; // @[rename-stage.scala:160:7, :243:{54,82}]
assign _com_valids_2_T_2 = _com_valids_2_T_1 & io_com_valids_2_0; // @[rename-stage.scala:160:7, :243:{54,92}]
assign com_valids_2 = _com_valids_2_T_2; // @[rename-stage.scala:236:29, :243:92]
wire _rbk_valids_2_T_1 = io_com_uops_2_ldst_val_0 & _rbk_valids_2_T; // @[rename-stage.scala:160:7, :244:{54,82}]
assign _rbk_valids_2_T_2 = _rbk_valids_2_T_1 & io_rbk_valids_2_0; // @[rename-stage.scala:160:7, :244:{54,92}]
assign rbk_valids_2 = _rbk_valids_2_T_2; // @[rename-stage.scala:237:29, :244:92]
wire [5:0] _remap_reqs_0_ldst_T; // @[rename-stage.scala:262:30]
wire [6:0] _remap_reqs_0_pdst_T; // @[rename-stage.scala:263:30]
wire _remap_reqs_0_valid_T; // @[rename-stage.scala:266:38]
wire [5:0] _remap_reqs_1_ldst_T; // @[rename-stage.scala:262:30]
wire [6:0] _remap_reqs_1_pdst_T; // @[rename-stage.scala:263:30]
wire _remap_reqs_1_valid_T; // @[rename-stage.scala:266:38]
wire [5:0] _remap_reqs_2_ldst_T; // @[rename-stage.scala:262:30]
wire [6:0] _remap_reqs_2_pdst_T; // @[rename-stage.scala:263:30]
wire _remap_reqs_2_valid_T; // @[rename-stage.scala:266:38]
wire [5:0] remap_reqs_0_ldst; // @[rename-stage.scala:253:24]
wire [6:0] remap_reqs_0_pdst; // @[rename-stage.scala:253:24]
wire remap_reqs_0_valid; // @[rename-stage.scala:253:24]
wire [5:0] remap_reqs_1_ldst; // @[rename-stage.scala:253:24]
wire [6:0] remap_reqs_1_pdst; // @[rename-stage.scala:253:24]
wire remap_reqs_1_valid; // @[rename-stage.scala:253:24]
wire [5:0] remap_reqs_2_ldst; // @[rename-stage.scala:253:24]
wire [6:0] remap_reqs_2_pdst; // @[rename-stage.scala:253:24]
wire remap_reqs_2_valid; // @[rename-stage.scala:253:24]
assign _remap_reqs_0_ldst_T = io_rollback_0 ? io_com_uops_2_ldst_0 : ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :160:7, :262:30]
assign remap_reqs_0_ldst = _remap_reqs_0_ldst_T; // @[rename-stage.scala:253:24, :262:30]
assign _remap_reqs_0_pdst_T = io_rollback_0 ? io_com_uops_2_stale_pdst_0 : ren2_uops_0_pdst; // @[rename-stage.scala:108:29, :160:7, :263:30]
assign remap_reqs_0_pdst = _remap_reqs_0_pdst_T; // @[rename-stage.scala:253:24, :263:30]
assign _remap_reqs_1_ldst_T = io_rollback_0 ? io_com_uops_1_ldst_0 : ren2_uops_1_ldst; // @[rename-stage.scala:108:29, :160:7, :262:30]
assign remap_reqs_1_ldst = _remap_reqs_1_ldst_T; // @[rename-stage.scala:253:24, :262:30]
assign _remap_reqs_1_pdst_T = io_rollback_0 ? io_com_uops_1_stale_pdst_0 : ren2_uops_1_pdst; // @[rename-stage.scala:108:29, :160:7, :263:30]
assign remap_reqs_1_pdst = _remap_reqs_1_pdst_T; // @[rename-stage.scala:253:24, :263:30]
assign _remap_reqs_2_ldst_T = io_rollback_0 ? io_com_uops_0_ldst_0 : ren2_uops_2_ldst; // @[rename-stage.scala:108:29, :160:7, :262:30]
assign remap_reqs_2_ldst = _remap_reqs_2_ldst_T; // @[rename-stage.scala:253:24, :262:30]
assign _remap_reqs_2_pdst_T = io_rollback_0 ? io_com_uops_0_stale_pdst_0 : ren2_uops_2_pdst; // @[rename-stage.scala:108:29, :160:7, :263:30]
assign remap_reqs_2_pdst = _remap_reqs_2_pdst_T; // @[rename-stage.scala:253:24, :263:30]
assign _remap_reqs_0_valid_T = ren2_alloc_reqs_0 | rbk_valids_2; // @[rename-stage.scala:109:29, :237:29, :266:38]
assign remap_reqs_0_valid = _remap_reqs_0_valid_T; // @[rename-stage.scala:253:24, :266:38]
assign _remap_reqs_1_valid_T = ren2_alloc_reqs_1 | rbk_valids_1; // @[rename-stage.scala:109:29, :237:29, :266:38]
assign remap_reqs_1_valid = _remap_reqs_1_valid_T; // @[rename-stage.scala:253:24, :266:38]
assign _remap_reqs_2_valid_T = ren2_alloc_reqs_2 | rbk_valids_0; // @[rename-stage.scala:109:29, :237:29, :266:38]
assign remap_reqs_2_valid = _remap_reqs_2_valid_T; // @[rename-stage.scala:253:24, :266:38]
wire _freelist_io_dealloc_pregs_0_valid_T = com_valids_0 | rbk_valids_0; // @[rename-stage.scala:236:29, :237:29, :293:37]
wire _freelist_io_dealloc_pregs_1_valid_T = com_valids_1 | rbk_valids_1; // @[rename-stage.scala:236:29, :237:29, :293:37]
wire _freelist_io_dealloc_pregs_2_valid_T = com_valids_2 | rbk_valids_2; // @[rename-stage.scala:236:29, :237:29, :293:37]
wire [6:0] _freelist_io_dealloc_pregs_0_bits_T = io_rollback_0 ? io_com_uops_0_pdst_0 : io_com_uops_0_stale_pdst_0; // @[rename-stage.scala:160:7, :295:33]
wire [6:0] _freelist_io_dealloc_pregs_1_bits_T = io_rollback_0 ? io_com_uops_1_pdst_0 : io_com_uops_1_stale_pdst_0; // @[rename-stage.scala:160:7, :295:33]
wire [6:0] _freelist_io_dealloc_pregs_2_bits_T = io_rollback_0 ? io_com_uops_2_pdst_0 : io_com_uops_2_stale_pdst_0; // @[rename-stage.scala:160:7, :295:33]
wire _ren2_uops_0_pdst_T = |ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :306:30]
wire _ren2_uops_0_pdst_T_1 = _ren2_uops_0_pdst_T; // @[rename-stage.scala:306:{30,38}]
assign _ren2_uops_0_pdst_T_2 = _ren2_uops_0_pdst_T_1 ? _freelist_io_alloc_pregs_0_bits : 7'h0; // @[rename-stage.scala:220:24, :306:{20,38}]
assign ren2_uops_0_pdst = _ren2_uops_0_pdst_T_2; // @[rename-stage.scala:108:29, :306:20]
wire _ren2_uops_1_pdst_T = |ren2_uops_1_ldst; // @[rename-stage.scala:108:29, :306:30]
wire _ren2_uops_1_pdst_T_1 = _ren2_uops_1_pdst_T; // @[rename-stage.scala:306:{30,38}]
assign _ren2_uops_1_pdst_T_2 = _ren2_uops_1_pdst_T_1 ? _freelist_io_alloc_pregs_1_bits : 7'h0; // @[rename-stage.scala:220:24, :306:{20,38}]
assign ren2_uops_1_pdst = _ren2_uops_1_pdst_T_2; // @[rename-stage.scala:108:29, :306:20]
wire _ren2_uops_2_pdst_T = |ren2_uops_2_ldst; // @[rename-stage.scala:108:29, :306:30]
wire _ren2_uops_2_pdst_T_1 = _ren2_uops_2_pdst_T; // @[rename-stage.scala:306:{30,38}]
assign _ren2_uops_2_pdst_T_2 = _ren2_uops_2_pdst_T_1 ? _freelist_io_alloc_pregs_2_bits : 7'h0; // @[rename-stage.scala:220:24, :306:{20,38}]
assign ren2_uops_2_pdst = _ren2_uops_2_pdst_T_2; // @[rename-stage.scala:108:29, :306:20]
wire _ren2_uops_0_prs1_busy_T = ren2_uops_0_lrs1_rtype == 2'h0; // @[rename-stage.scala:108:29, :323:37]
assign _ren2_uops_0_prs1_busy_T_1 = _ren2_uops_0_prs1_busy_T & _busytable_io_busy_resps_0_prs1_busy; // @[rename-stage.scala:224:25, :323:{37,47}]
assign ren2_uops_0_prs1_busy = _ren2_uops_0_prs1_busy_T_1; // @[rename-stage.scala:108:29, :323:47]
wire _ren2_uops_0_prs2_busy_T = ren2_uops_0_lrs2_rtype == 2'h0; // @[rename-stage.scala:108:29, :324:37]
assign _ren2_uops_0_prs2_busy_T_1 = _ren2_uops_0_prs2_busy_T & _busytable_io_busy_resps_0_prs2_busy; // @[rename-stage.scala:224:25, :324:{37,47}]
assign ren2_uops_0_prs2_busy = _ren2_uops_0_prs2_busy_T_1; // @[rename-stage.scala:108:29, :324:47]
wire _ren2_uops_1_prs1_busy_T = ren2_uops_1_lrs1_rtype == 2'h0; // @[rename-stage.scala:108:29, :323:37]
assign _ren2_uops_1_prs1_busy_T_1 = _ren2_uops_1_prs1_busy_T & _busytable_io_busy_resps_1_prs1_busy; // @[rename-stage.scala:224:25, :323:{37,47}]
assign ren2_uops_1_prs1_busy = _ren2_uops_1_prs1_busy_T_1; // @[rename-stage.scala:108:29, :323:47]
wire _ren2_uops_1_prs2_busy_T = ren2_uops_1_lrs2_rtype == 2'h0; // @[rename-stage.scala:108:29, :324:37]
assign _ren2_uops_1_prs2_busy_T_1 = _ren2_uops_1_prs2_busy_T & _busytable_io_busy_resps_1_prs2_busy; // @[rename-stage.scala:224:25, :324:{37,47}]
assign ren2_uops_1_prs2_busy = _ren2_uops_1_prs2_busy_T_1; // @[rename-stage.scala:108:29, :324:47]
wire _ren2_uops_2_prs1_busy_T = ren2_uops_2_lrs1_rtype == 2'h0; // @[rename-stage.scala:108:29, :323:37]
assign _ren2_uops_2_prs1_busy_T_1 = _ren2_uops_2_prs1_busy_T & _busytable_io_busy_resps_2_prs1_busy; // @[rename-stage.scala:224:25, :323:{37,47}]
assign ren2_uops_2_prs1_busy = _ren2_uops_2_prs1_busy_T_1; // @[rename-stage.scala:108:29, :323:47]
wire _ren2_uops_2_prs2_busy_T = ren2_uops_2_lrs2_rtype == 2'h0; // @[rename-stage.scala:108:29, :324:37]
assign _ren2_uops_2_prs2_busy_T_1 = _ren2_uops_2_prs2_busy_T & _busytable_io_busy_resps_2_prs2_busy; // @[rename-stage.scala:224:25, :324:{37,47}]
assign ren2_uops_2_prs2_busy = _ren2_uops_2_prs2_busy_T_1; // @[rename-stage.scala:108:29, :324:47] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncScratchPadMemory :
input clock : Clock
input reset : Reset
output io : { flip core_ports : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}[2], flip debug_port : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}}
cmem mem : UInt<8>[4] [524288]
connect io.core_ports[0].resp.valid, io.core_ports[0].req.valid
connect io.core_ports[0].req.ready, UInt<1>(0h1)
connect io.core_ports[1].resp.valid, io.core_ports[1].req.valid
connect io.core_ports[1].req.ready, UInt<1>(0h1)
node _dport_wen_T = eq(io.core_ports[0].req.bits.fcn, UInt<1>(0h1))
node dport_wen = and(io.core_ports[0].req.valid, _dport_wen_T)
node _io_core_ports_0_resp_bits_data_T = sub(io.core_ports[0].req.bits.typ, UInt<1>(0h1))
node _io_core_ports_0_resp_bits_data_T_1 = tail(_io_core_ports_0_resp_bits_data_T, 1)
node _io_core_ports_0_resp_bits_data_T_2 = bits(_io_core_ports_0_resp_bits_data_T_1, 1, 0)
node _io_core_ports_0_resp_bits_data_T_3 = sub(io.core_ports[0].req.bits.typ, UInt<1>(0h1))
node _io_core_ports_0_resp_bits_data_T_4 = tail(_io_core_ports_0_resp_bits_data_T_3, 1)
node _io_core_ports_0_resp_bits_data_T_5 = bits(_io_core_ports_0_resp_bits_data_T_4, 2, 2)
node _io_core_ports_0_resp_bits_data_T_6 = not(_io_core_ports_0_resp_bits_data_T_5)
inst io_core_ports_0_resp_bits_data_memreader of MemReader
connect io_core_ports_0_resp_bits_data_memreader.clock, clock
connect io_core_ports_0_resp_bits_data_memreader.reset, reset
connect io_core_ports_0_resp_bits_data_memreader.io.addr, io.core_ports[0].req.bits.addr
connect io_core_ports_0_resp_bits_data_memreader.io.size, _io_core_ports_0_resp_bits_data_T_2
connect io_core_ports_0_resp_bits_data_memreader.io.signed, _io_core_ports_0_resp_bits_data_T_6
read mport io_core_ports_0_resp_bits_data_MPORT = mem[io_core_ports_0_resp_bits_data_memreader.io.mem_addr], clock
connect io_core_ports_0_resp_bits_data_memreader.io.mem_data[0], io_core_ports_0_resp_bits_data_MPORT[0]
connect io_core_ports_0_resp_bits_data_memreader.io.mem_data[1], io_core_ports_0_resp_bits_data_MPORT[1]
connect io_core_ports_0_resp_bits_data_memreader.io.mem_data[2], io_core_ports_0_resp_bits_data_MPORT[2]
connect io_core_ports_0_resp_bits_data_memreader.io.mem_data[3], io_core_ports_0_resp_bits_data_MPORT[3]
connect io.core_ports[0].resp.bits.data, io_core_ports_0_resp_bits_data_memreader.io.data
node _T = sub(io.core_ports[0].req.bits.typ, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = bits(_T_1, 1, 0)
inst memwriter of MemWriter
connect memwriter.clock, clock
connect memwriter.reset, reset
connect memwriter.io.addr, io.core_ports[0].req.bits.addr
connect memwriter.io.data, io.core_ports[0].req.bits.data
connect memwriter.io.size, _T_2
connect memwriter.io.en, dport_wen
when dport_wen :
write mport MPORT = mem[memwriter.io.mem_addr], clock
when memwriter.io.mem_masks[0] :
connect MPORT[0], memwriter.io.mem_data[0]
when memwriter.io.mem_masks[1] :
connect MPORT[1], memwriter.io.mem_data[1]
when memwriter.io.mem_masks[2] :
connect MPORT[2], memwriter.io.mem_data[2]
when memwriter.io.mem_masks[3] :
connect MPORT[3], memwriter.io.mem_data[3]
node _io_core_ports_1_resp_bits_data_T = sub(io.core_ports[1].req.bits.typ, UInt<1>(0h1))
node _io_core_ports_1_resp_bits_data_T_1 = tail(_io_core_ports_1_resp_bits_data_T, 1)
node _io_core_ports_1_resp_bits_data_T_2 = bits(_io_core_ports_1_resp_bits_data_T_1, 1, 0)
node _io_core_ports_1_resp_bits_data_T_3 = sub(io.core_ports[1].req.bits.typ, UInt<1>(0h1))
node _io_core_ports_1_resp_bits_data_T_4 = tail(_io_core_ports_1_resp_bits_data_T_3, 1)
node _io_core_ports_1_resp_bits_data_T_5 = bits(_io_core_ports_1_resp_bits_data_T_4, 2, 2)
node _io_core_ports_1_resp_bits_data_T_6 = not(_io_core_ports_1_resp_bits_data_T_5)
inst io_core_ports_1_resp_bits_data_memreader of MemReader_1
connect io_core_ports_1_resp_bits_data_memreader.clock, clock
connect io_core_ports_1_resp_bits_data_memreader.reset, reset
connect io_core_ports_1_resp_bits_data_memreader.io.addr, io.core_ports[1].req.bits.addr
connect io_core_ports_1_resp_bits_data_memreader.io.size, _io_core_ports_1_resp_bits_data_T_2
connect io_core_ports_1_resp_bits_data_memreader.io.signed, _io_core_ports_1_resp_bits_data_T_6
read mport io_core_ports_1_resp_bits_data_MPORT = mem[io_core_ports_1_resp_bits_data_memreader.io.mem_addr], clock
connect io_core_ports_1_resp_bits_data_memreader.io.mem_data[0], io_core_ports_1_resp_bits_data_MPORT[0]
connect io_core_ports_1_resp_bits_data_memreader.io.mem_data[1], io_core_ports_1_resp_bits_data_MPORT[1]
connect io_core_ports_1_resp_bits_data_memreader.io.mem_data[2], io_core_ports_1_resp_bits_data_MPORT[2]
connect io_core_ports_1_resp_bits_data_memreader.io.mem_data[3], io_core_ports_1_resp_bits_data_MPORT[3]
connect io.core_ports[1].resp.bits.data, io_core_ports_1_resp_bits_data_memreader.io.data
connect io.debug_port.req.ready, UInt<1>(0h1)
connect io.debug_port.resp.valid, io.debug_port.req.valid
node _debug_port_wen_T = eq(io.debug_port.req.bits.fcn, UInt<1>(0h1))
node debug_port_wen = and(io.debug_port.req.valid, _debug_port_wen_T)
node _io_debug_port_resp_bits_data_T = sub(io.debug_port.req.bits.typ, UInt<1>(0h1))
node _io_debug_port_resp_bits_data_T_1 = tail(_io_debug_port_resp_bits_data_T, 1)
node _io_debug_port_resp_bits_data_T_2 = bits(_io_debug_port_resp_bits_data_T_1, 1, 0)
node _io_debug_port_resp_bits_data_T_3 = sub(io.debug_port.req.bits.typ, UInt<1>(0h1))
node _io_debug_port_resp_bits_data_T_4 = tail(_io_debug_port_resp_bits_data_T_3, 1)
node _io_debug_port_resp_bits_data_T_5 = bits(_io_debug_port_resp_bits_data_T_4, 2, 2)
node _io_debug_port_resp_bits_data_T_6 = not(_io_debug_port_resp_bits_data_T_5)
inst io_debug_port_resp_bits_data_memreader of MemReader_2
connect io_debug_port_resp_bits_data_memreader.clock, clock
connect io_debug_port_resp_bits_data_memreader.reset, reset
connect io_debug_port_resp_bits_data_memreader.io.addr, io.debug_port.req.bits.addr
connect io_debug_port_resp_bits_data_memreader.io.size, _io_debug_port_resp_bits_data_T_2
connect io_debug_port_resp_bits_data_memreader.io.signed, _io_debug_port_resp_bits_data_T_6
read mport io_debug_port_resp_bits_data_MPORT = mem[io_debug_port_resp_bits_data_memreader.io.mem_addr], clock
connect io_debug_port_resp_bits_data_memreader.io.mem_data[0], io_debug_port_resp_bits_data_MPORT[0]
connect io_debug_port_resp_bits_data_memreader.io.mem_data[1], io_debug_port_resp_bits_data_MPORT[1]
connect io_debug_port_resp_bits_data_memreader.io.mem_data[2], io_debug_port_resp_bits_data_MPORT[2]
connect io_debug_port_resp_bits_data_memreader.io.mem_data[3], io_debug_port_resp_bits_data_MPORT[3]
connect io.debug_port.resp.bits.data, io_debug_port_resp_bits_data_memreader.io.data
node _T_3 = sub(io.debug_port.req.bits.typ, UInt<1>(0h1))
node _T_4 = tail(_T_3, 1)
node _T_5 = bits(_T_4, 1, 0)
inst memwriter_1 of MemWriter_1
connect memwriter_1.clock, clock
connect memwriter_1.reset, reset
connect memwriter_1.io.addr, io.debug_port.req.bits.addr
connect memwriter_1.io.data, io.debug_port.req.bits.data
connect memwriter_1.io.size, _T_5
connect memwriter_1.io.en, debug_port_wen
when debug_port_wen :
write mport MPORT_1 = mem[memwriter_1.io.mem_addr], clock
when memwriter_1.io.mem_masks[0] :
connect MPORT_1[0], memwriter_1.io.mem_data[0]
when memwriter_1.io.mem_masks[1] :
connect MPORT_1[1], memwriter_1.io.mem_data[1]
when memwriter_1.io.mem_masks[2] :
connect MPORT_1[2], memwriter_1.io.mem_data[2]
when memwriter_1.io.mem_masks[3] :
connect MPORT_1[3], memwriter_1.io.mem_data[3] | module AsyncScratchPadMemory( // @[memory.scala:215:7]
input clock, // @[memory.scala:215:7]
input reset, // @[memory.scala:215:7]
input io_core_ports_0_req_valid, // @[memory.scala:174:15]
input [31:0] io_core_ports_0_req_bits_addr, // @[memory.scala:174:15]
input [31:0] io_core_ports_0_req_bits_data, // @[memory.scala:174:15]
input io_core_ports_0_req_bits_fcn, // @[memory.scala:174:15]
input [2:0] io_core_ports_0_req_bits_typ, // @[memory.scala:174:15]
output io_core_ports_0_resp_valid, // @[memory.scala:174:15]
output [31:0] io_core_ports_0_resp_bits_data, // @[memory.scala:174:15]
input io_core_ports_1_req_valid, // @[memory.scala:174:15]
input [31:0] io_core_ports_1_req_bits_addr, // @[memory.scala:174:15]
output io_core_ports_1_resp_valid, // @[memory.scala:174:15]
output [31:0] io_core_ports_1_resp_bits_data, // @[memory.scala:174:15]
input io_debug_port_req_valid, // @[memory.scala:174:15]
input [31:0] io_debug_port_req_bits_addr, // @[memory.scala:174:15]
input [31:0] io_debug_port_req_bits_data, // @[memory.scala:174:15]
input io_debug_port_req_bits_fcn, // @[memory.scala:174:15]
input [2:0] io_debug_port_req_bits_typ, // @[memory.scala:174:15]
output io_debug_port_resp_valid, // @[memory.scala:174:15]
output [31:0] io_debug_port_resp_bits_data // @[memory.scala:174:15]
);
wire [18:0] _memwriter_1_io_mem_addr; // @[memory.scala:156:29]
wire [7:0] _memwriter_1_io_mem_data_0; // @[memory.scala:156:29]
wire [7:0] _memwriter_1_io_mem_data_1; // @[memory.scala:156:29]
wire [7:0] _memwriter_1_io_mem_data_2; // @[memory.scala:156:29]
wire [7:0] _memwriter_1_io_mem_data_3; // @[memory.scala:156:29]
wire _memwriter_1_io_mem_masks_0; // @[memory.scala:156:29]
wire _memwriter_1_io_mem_masks_1; // @[memory.scala:156:29]
wire _memwriter_1_io_mem_masks_2; // @[memory.scala:156:29]
wire _memwriter_1_io_mem_masks_3; // @[memory.scala:156:29]
wire [18:0] _io_debug_port_resp_bits_data_memreader_io_mem_addr; // @[memory.scala:120:29]
wire [18:0] _io_core_ports_1_resp_bits_data_memreader_io_mem_addr; // @[memory.scala:120:29]
wire [18:0] _memwriter_io_mem_addr; // @[memory.scala:156:29]
wire [7:0] _memwriter_io_mem_data_0; // @[memory.scala:156:29]
wire [7:0] _memwriter_io_mem_data_1; // @[memory.scala:156:29]
wire [7:0] _memwriter_io_mem_data_2; // @[memory.scala:156:29]
wire [7:0] _memwriter_io_mem_data_3; // @[memory.scala:156:29]
wire _memwriter_io_mem_masks_0; // @[memory.scala:156:29]
wire _memwriter_io_mem_masks_1; // @[memory.scala:156:29]
wire _memwriter_io_mem_masks_2; // @[memory.scala:156:29]
wire _memwriter_io_mem_masks_3; // @[memory.scala:156:29]
wire [18:0] _io_core_ports_0_resp_bits_data_memreader_io_mem_addr; // @[memory.scala:120:29]
wire [31:0] _mem_ext_R0_data; // @[memory.scala:73:31]
wire [31:0] _mem_ext_R1_data; // @[memory.scala:73:31]
wire [31:0] _mem_ext_R2_data; // @[memory.scala:73:31]
wire io_core_ports_0_req_valid_0 = io_core_ports_0_req_valid; // @[memory.scala:215:7]
wire [31:0] io_core_ports_0_req_bits_addr_0 = io_core_ports_0_req_bits_addr; // @[memory.scala:215:7]
wire [31:0] io_core_ports_0_req_bits_data_0 = io_core_ports_0_req_bits_data; // @[memory.scala:215:7]
wire io_core_ports_0_req_bits_fcn_0 = io_core_ports_0_req_bits_fcn; // @[memory.scala:215:7]
wire [2:0] io_core_ports_0_req_bits_typ_0 = io_core_ports_0_req_bits_typ; // @[memory.scala:215:7]
wire io_core_ports_1_req_valid_0 = io_core_ports_1_req_valid; // @[memory.scala:215:7]
wire [31:0] io_core_ports_1_req_bits_addr_0 = io_core_ports_1_req_bits_addr; // @[memory.scala:215:7]
wire io_debug_port_req_valid_0 = io_debug_port_req_valid; // @[memory.scala:215:7]
wire [31:0] io_debug_port_req_bits_addr_0 = io_debug_port_req_bits_addr; // @[memory.scala:215:7]
wire [31:0] io_debug_port_req_bits_data_0 = io_debug_port_req_bits_data; // @[memory.scala:215:7]
wire io_debug_port_req_bits_fcn_0 = io_debug_port_req_bits_fcn; // @[memory.scala:215:7]
wire [2:0] io_debug_port_req_bits_typ_0 = io_debug_port_req_bits_typ; // @[memory.scala:215:7]
wire io_core_ports_0_req_ready = 1'h1; // @[memory.scala:215:7]
wire io_core_ports_1_req_ready = 1'h1; // @[memory.scala:215:7]
wire io_debug_port_req_ready = 1'h1; // @[memory.scala:215:7]
wire _io_core_ports_1_resp_bits_data_T_5 = 1'h1; // @[memory.scala:61:33, :215:7]
wire [3:0] _io_core_ports_1_resp_bits_data_T = 4'h6; // @[memory.scala:60:24, :61:27]
wire [3:0] _io_core_ports_1_resp_bits_data_T_3 = 4'h6; // @[memory.scala:60:24, :61:27]
wire [2:0] _io_core_ports_1_resp_bits_data_T_1 = 3'h6; // @[memory.scala:60:24, :61:27]
wire [2:0] _io_core_ports_1_resp_bits_data_T_4 = 3'h6; // @[memory.scala:60:24, :61:27]
wire [1:0] _io_core_ports_1_resp_bits_data_T_2 = 2'h2; // @[memory.scala:60:30, :120:29]
wire [2:0] io_core_ports_1_req_bits_typ = 3'h7; // @[memory.scala:174:15, :215:7]
wire io_core_ports_1_req_bits_fcn = 1'h0; // @[memory.scala:61:21, :120:29, :174:15, :215:7]
wire _io_core_ports_1_resp_bits_data_T_6 = 1'h0; // @[memory.scala:61:21, :120:29, :174:15, :215:7]
wire [31:0] io_core_ports_1_req_bits_data = 32'h0; // @[memory.scala:174:15, :215:7]
wire io_core_ports_0_resp_valid_0 = io_core_ports_0_req_valid_0; // @[memory.scala:215:7]
wire _dport_wen_T = io_core_ports_0_req_bits_fcn_0; // @[memory.scala:193:68, :215:7]
wire io_core_ports_1_resp_valid_0 = io_core_ports_1_req_valid_0; // @[memory.scala:215:7]
wire io_debug_port_resp_valid_0 = io_debug_port_req_valid_0; // @[memory.scala:215:7]
wire _debug_port_wen_T = io_debug_port_req_bits_fcn_0; // @[memory.scala:210:71, :215:7]
wire [31:0] io_core_ports_0_resp_bits_data_0; // @[memory.scala:215:7]
wire [31:0] io_core_ports_1_resp_bits_data_0; // @[memory.scala:215:7]
wire [31:0] io_debug_port_resp_bits_data_0; // @[memory.scala:215:7]
wire dport_wen = io_core_ports_0_req_valid_0 & _dport_wen_T; // @[memory.scala:193:{51,68}, :215:7]
wire [3:0] _T = {1'h0, io_core_ports_0_req_bits_typ_0} - 4'h1; // @[memory.scala:60:24, :61:21, :120:29, :174:15, :215:7]
wire [3:0] _io_core_ports_0_resp_bits_data_T; // @[memory.scala:60:24]
assign _io_core_ports_0_resp_bits_data_T = _T; // @[memory.scala:60:24]
wire [3:0] _io_core_ports_0_resp_bits_data_T_3; // @[memory.scala:61:27]
assign _io_core_ports_0_resp_bits_data_T_3 = _T; // @[memory.scala:60:24, :61:27]
wire [2:0] _io_core_ports_0_resp_bits_data_T_1 = _io_core_ports_0_resp_bits_data_T[2:0]; // @[memory.scala:60:24]
wire [1:0] _io_core_ports_0_resp_bits_data_T_2 = _io_core_ports_0_resp_bits_data_T_1[1:0]; // @[memory.scala:60:{24,30}]
wire [2:0] _io_core_ports_0_resp_bits_data_T_4 = _io_core_ports_0_resp_bits_data_T_3[2:0]; // @[memory.scala:61:27]
wire _io_core_ports_0_resp_bits_data_T_5 = _io_core_ports_0_resp_bits_data_T_4[2]; // @[memory.scala:61:{27,33}]
wire _io_core_ports_0_resp_bits_data_T_6 = ~_io_core_ports_0_resp_bits_data_T_5; // @[memory.scala:61:{21,33}]
wire debug_port_wen = io_debug_port_req_valid_0 & _debug_port_wen_T; // @[memory.scala:210:{49,71}, :215:7]
wire [3:0] _T_3 = {1'h0, io_debug_port_req_bits_typ_0} - 4'h1; // @[memory.scala:60:24, :61:21, :120:29, :174:15, :215:7]
wire [3:0] _io_debug_port_resp_bits_data_T; // @[memory.scala:60:24]
assign _io_debug_port_resp_bits_data_T = _T_3; // @[memory.scala:60:24]
wire [3:0] _io_debug_port_resp_bits_data_T_3; // @[memory.scala:61:27]
assign _io_debug_port_resp_bits_data_T_3 = _T_3; // @[memory.scala:60:24, :61:27]
wire [2:0] _io_debug_port_resp_bits_data_T_1 = _io_debug_port_resp_bits_data_T[2:0]; // @[memory.scala:60:24]
wire [1:0] _io_debug_port_resp_bits_data_T_2 = _io_debug_port_resp_bits_data_T_1[1:0]; // @[memory.scala:60:{24,30}]
wire [2:0] _io_debug_port_resp_bits_data_T_4 = _io_debug_port_resp_bits_data_T_3[2:0]; // @[memory.scala:61:27]
wire _io_debug_port_resp_bits_data_T_5 = _io_debug_port_resp_bits_data_T_4[2]; // @[memory.scala:61:{27,33}]
wire _io_debug_port_resp_bits_data_T_6 = ~_io_debug_port_resp_bits_data_T_5; // @[memory.scala:61:{21,33}]
mem_524288x32 mem_ext ( // @[memory.scala:73:31]
.R0_addr (_io_debug_port_resp_bits_data_memreader_io_mem_addr), // @[memory.scala:120:29]
.R0_en (1'h1), // @[memory.scala:215:7]
.R0_clk (clock),
.R0_data (_mem_ext_R0_data),
.R1_addr (_io_core_ports_1_resp_bits_data_memreader_io_mem_addr), // @[memory.scala:120:29]
.R1_en (1'h1), // @[memory.scala:215:7]
.R1_clk (clock),
.R1_data (_mem_ext_R1_data),
.R2_addr (_io_core_ports_0_resp_bits_data_memreader_io_mem_addr), // @[memory.scala:120:29]
.R2_en (1'h1), // @[memory.scala:215:7]
.R2_clk (clock),
.R2_data (_mem_ext_R2_data),
.W0_addr (_memwriter_1_io_mem_addr), // @[memory.scala:156:29]
.W0_en (debug_port_wen), // @[memory.scala:210:49]
.W0_clk (clock),
.W0_data ({_memwriter_1_io_mem_data_3, _memwriter_1_io_mem_data_2, _memwriter_1_io_mem_data_1, _memwriter_1_io_mem_data_0}), // @[memory.scala:73:31, :156:29]
.W0_mask ({_memwriter_1_io_mem_masks_3, _memwriter_1_io_mem_masks_2, _memwriter_1_io_mem_masks_1, _memwriter_1_io_mem_masks_0}), // @[memory.scala:73:31, :156:29]
.W1_addr (_memwriter_io_mem_addr), // @[memory.scala:156:29]
.W1_en (dport_wen), // @[memory.scala:193:51]
.W1_clk (clock),
.W1_data ({_memwriter_io_mem_data_3, _memwriter_io_mem_data_2, _memwriter_io_mem_data_1, _memwriter_io_mem_data_0}), // @[memory.scala:73:31, :156:29]
.W1_mask ({_memwriter_io_mem_masks_3, _memwriter_io_mem_masks_2, _memwriter_io_mem_masks_1, _memwriter_io_mem_masks_0}) // @[memory.scala:73:31, :156:29]
); // @[memory.scala:73:31]
MemReader io_core_ports_0_resp_bits_data_memreader ( // @[memory.scala:120:29]
.clock (clock),
.reset (reset),
.io_addr (io_core_ports_0_req_bits_addr_0[20:0]), // @[memory.scala:121:25, :215:7]
.io_size (_io_core_ports_0_resp_bits_data_T_2), // @[memory.scala:60:30]
.io_signed (_io_core_ports_0_resp_bits_data_T_6), // @[memory.scala:61:21]
.io_data (io_core_ports_0_resp_bits_data_0),
.io_mem_addr (_io_core_ports_0_resp_bits_data_memreader_io_mem_addr),
.io_mem_data_0 (_mem_ext_R2_data[7:0]), // @[memory.scala:73:31]
.io_mem_data_1 (_mem_ext_R2_data[15:8]), // @[memory.scala:73:31]
.io_mem_data_2 (_mem_ext_R2_data[23:16]), // @[memory.scala:73:31]
.io_mem_data_3 (_mem_ext_R2_data[31:24]) // @[memory.scala:73:31]
); // @[memory.scala:120:29]
MemWriter memwriter ( // @[memory.scala:156:29]
.clock (clock),
.reset (reset),
.io_addr (io_core_ports_0_req_bits_addr_0[20:0]), // @[memory.scala:121:25, :215:7]
.io_data (io_core_ports_0_req_bits_data_0), // @[memory.scala:215:7]
.io_size (_T[1:0]), // @[memory.scala:60:{24,30}]
.io_en (dport_wen), // @[memory.scala:193:51]
.io_mem_addr (_memwriter_io_mem_addr),
.io_mem_data_0 (_memwriter_io_mem_data_0),
.io_mem_data_1 (_memwriter_io_mem_data_1),
.io_mem_data_2 (_memwriter_io_mem_data_2),
.io_mem_data_3 (_memwriter_io_mem_data_3),
.io_mem_masks_0 (_memwriter_io_mem_masks_0),
.io_mem_masks_1 (_memwriter_io_mem_masks_1),
.io_mem_masks_2 (_memwriter_io_mem_masks_2),
.io_mem_masks_3 (_memwriter_io_mem_masks_3)
); // @[memory.scala:156:29]
MemReader_1 io_core_ports_1_resp_bits_data_memreader ( // @[memory.scala:120:29]
.clock (clock),
.reset (reset),
.io_addr (io_core_ports_1_req_bits_addr_0[20:0]), // @[memory.scala:121:25, :215:7]
.io_data (io_core_ports_1_resp_bits_data_0),
.io_mem_addr (_io_core_ports_1_resp_bits_data_memreader_io_mem_addr),
.io_mem_data_0 (_mem_ext_R1_data[7:0]), // @[memory.scala:73:31]
.io_mem_data_1 (_mem_ext_R1_data[15:8]), // @[memory.scala:73:31]
.io_mem_data_2 (_mem_ext_R1_data[23:16]), // @[memory.scala:73:31]
.io_mem_data_3 (_mem_ext_R1_data[31:24]) // @[memory.scala:73:31]
); // @[memory.scala:120:29]
MemReader_2 io_debug_port_resp_bits_data_memreader ( // @[memory.scala:120:29]
.clock (clock),
.reset (reset),
.io_addr (io_debug_port_req_bits_addr_0[20:0]), // @[memory.scala:121:25, :215:7]
.io_size (_io_debug_port_resp_bits_data_T_2), // @[memory.scala:60:30]
.io_signed (_io_debug_port_resp_bits_data_T_6), // @[memory.scala:61:21]
.io_data (io_debug_port_resp_bits_data_0),
.io_mem_addr (_io_debug_port_resp_bits_data_memreader_io_mem_addr),
.io_mem_data_0 (_mem_ext_R0_data[7:0]), // @[memory.scala:73:31]
.io_mem_data_1 (_mem_ext_R0_data[15:8]), // @[memory.scala:73:31]
.io_mem_data_2 (_mem_ext_R0_data[23:16]), // @[memory.scala:73:31]
.io_mem_data_3 (_mem_ext_R0_data[31:24]) // @[memory.scala:73:31]
); // @[memory.scala:120:29]
MemWriter_1 memwriter_1 ( // @[memory.scala:156:29]
.clock (clock),
.reset (reset),
.io_addr (io_debug_port_req_bits_addr_0[20:0]), // @[memory.scala:121:25, :215:7]
.io_data (io_debug_port_req_bits_data_0), // @[memory.scala:215:7]
.io_size (_T_3[1:0]), // @[memory.scala:60:{24,30}]
.io_en (debug_port_wen), // @[memory.scala:210:49]
.io_mem_addr (_memwriter_1_io_mem_addr),
.io_mem_data_0 (_memwriter_1_io_mem_data_0),
.io_mem_data_1 (_memwriter_1_io_mem_data_1),
.io_mem_data_2 (_memwriter_1_io_mem_data_2),
.io_mem_data_3 (_memwriter_1_io_mem_data_3),
.io_mem_masks_0 (_memwriter_1_io_mem_masks_0),
.io_mem_masks_1 (_memwriter_1_io_mem_masks_1),
.io_mem_masks_2 (_memwriter_1_io_mem_masks_2),
.io_mem_masks_3 (_memwriter_1_io_mem_masks_3)
); // @[memory.scala:156:29]
assign io_core_ports_0_resp_valid = io_core_ports_0_resp_valid_0; // @[memory.scala:215:7]
assign io_core_ports_0_resp_bits_data = io_core_ports_0_resp_bits_data_0; // @[memory.scala:215:7]
assign io_core_ports_1_resp_valid = io_core_ports_1_resp_valid_0; // @[memory.scala:215:7]
assign io_core_ports_1_resp_bits_data = io_core_ports_1_resp_bits_data_0; // @[memory.scala:215:7]
assign io_debug_port_resp_valid = io_debug_port_resp_valid_0; // @[memory.scala:215:7]
assign io_debug_port_resp_bits_data = io_debug_port_resp_bits_data_0; // @[memory.scala:215:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_QueuedRequest_q36_e28_4 :
input clock : Clock
input reset : Reset
output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}}}, valid : UInt<36>, flip pop : { valid : UInt<1>, bits : UInt<6>}, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}}
regreset valid : UInt<36>, clock, reset, UInt<36>(0h0)
cmem head : UInt<5> [36]
cmem tail : UInt<5> [36]
regreset used : UInt<28>, clock, reset, UInt<28>(0h0)
cmem next : UInt<5> [28]
cmem data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} [28]
node _freeOH_T = not(used)
node _freeOH_T_1 = shl(_freeOH_T, 1)
node _freeOH_T_2 = bits(_freeOH_T_1, 27, 0)
node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2)
node _freeOH_T_4 = shl(_freeOH_T_3, 2)
node _freeOH_T_5 = bits(_freeOH_T_4, 27, 0)
node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5)
node _freeOH_T_7 = shl(_freeOH_T_6, 4)
node _freeOH_T_8 = bits(_freeOH_T_7, 27, 0)
node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8)
node _freeOH_T_10 = shl(_freeOH_T_9, 8)
node _freeOH_T_11 = bits(_freeOH_T_10, 27, 0)
node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11)
node _freeOH_T_13 = shl(_freeOH_T_12, 16)
node _freeOH_T_14 = bits(_freeOH_T_13, 27, 0)
node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14)
node _freeOH_T_16 = bits(_freeOH_T_15, 27, 0)
node _freeOH_T_17 = shl(_freeOH_T_16, 1)
node _freeOH_T_18 = not(_freeOH_T_17)
node _freeOH_T_19 = not(used)
node freeOH = and(_freeOH_T_18, _freeOH_T_19)
node freeIdx_hi = bits(freeOH, 28, 16)
node freeIdx_lo = bits(freeOH, 15, 0)
node _freeIdx_T = orr(freeIdx_hi)
node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo)
node freeIdx_hi_1 = bits(_freeIdx_T_1, 15, 8)
node freeIdx_lo_1 = bits(_freeIdx_T_1, 7, 0)
node _freeIdx_T_2 = orr(freeIdx_hi_1)
node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1)
node freeIdx_hi_2 = bits(_freeIdx_T_3, 7, 4)
node freeIdx_lo_2 = bits(_freeIdx_T_3, 3, 0)
node _freeIdx_T_4 = orr(freeIdx_hi_2)
node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2)
node freeIdx_hi_3 = bits(_freeIdx_T_5, 3, 2)
node freeIdx_lo_3 = bits(_freeIdx_T_5, 1, 0)
node _freeIdx_T_6 = orr(freeIdx_hi_3)
node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3)
node _freeIdx_T_8 = bits(_freeIdx_T_7, 1, 1)
node _freeIdx_T_9 = cat(_freeIdx_T_6, _freeIdx_T_8)
node _freeIdx_T_10 = cat(_freeIdx_T_4, _freeIdx_T_9)
node _freeIdx_T_11 = cat(_freeIdx_T_2, _freeIdx_T_10)
node freeIdx = cat(_freeIdx_T, _freeIdx_T_11)
wire valid_set : UInt<36>
connect valid_set, UInt<36>(0h0)
wire valid_clr : UInt<36>
connect valid_clr, UInt<36>(0h0)
wire used_set : UInt<28>
connect used_set, UInt<28>(0h0)
wire used_clr : UInt<28>
connect used_clr, UInt<28>(0h0)
read mport push_tail = tail[io.push.bits.index], clock
node _push_valid_T = dshr(valid, io.push.bits.index)
node push_valid = bits(_push_valid_T, 0, 0)
node _io_push_ready_T = andr(used)
node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0))
connect io.push.ready, _io_push_ready_T_1
node _T = and(io.push.ready, io.push.valid)
when _T :
node valid_set_shiftAmount = bits(io.push.bits.index, 5, 0)
node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount)
node _valid_set_T_1 = bits(_valid_set_T, 35, 0)
connect valid_set, _valid_set_T_1
connect used_set, freeOH
write mport MPORT = data[freeIdx], clock
connect MPORT, io.push.bits.data
when push_valid :
write mport MPORT_1 = next[push_tail], clock
connect MPORT_1, freeIdx
else :
write mport MPORT_2 = head[io.push.bits.index], clock
connect MPORT_2, freeIdx
write mport MPORT_3 = tail[io.push.bits.index], clock
connect MPORT_3, freeIdx
read mport pop_head = head[io.pop.bits], clock
node _pop_valid_T = dshr(valid, io.pop.bits)
node pop_valid = bits(_pop_valid_T, 0, 0)
read mport io_data_MPORT = data[pop_head], clock
connect io.data, io_data_MPORT
connect io.valid, valid
node _T_1 = eq(io.pop.valid, UInt<1>(0h0))
node _T_2 = dshr(io.valid, io.pop.bits)
node _T_3 = bits(_T_2, 0, 0)
node _T_4 = or(_T_1, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
when io.pop.valid :
node used_clr_shiftAmount = bits(pop_head, 4, 0)
node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount)
node _used_clr_T_1 = bits(_used_clr_T, 27, 0)
connect used_clr, _used_clr_T_1
read mport MPORT_4 = tail[io.pop.bits], clock
node _T_8 = eq(pop_head, MPORT_4)
when _T_8 :
node valid_clr_shiftAmount = bits(io.pop.bits, 5, 0)
node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount)
node _valid_clr_T_1 = bits(_valid_clr_T, 35, 0)
connect valid_clr, _valid_clr_T_1
node _T_9 = and(io.push.ready, io.push.valid)
node _T_10 = and(_T_9, push_valid)
node _T_11 = eq(push_tail, pop_head)
node _T_12 = and(_T_10, _T_11)
read mport MPORT_5 = next[pop_head], clock
node _T_13 = mux(_T_12, freeIdx, MPORT_5)
write mport MPORT_6 = head[io.pop.bits], clock
connect MPORT_6, _T_13
node _T_14 = eq(io.pop.valid, UInt<1>(0h0))
node _T_15 = or(UInt<1>(0h1), _T_14)
node _T_16 = or(_T_15, pop_valid)
when _T_16 :
node _used_T = not(used_clr)
node _used_T_1 = and(used, _used_T)
node _used_T_2 = or(_used_T_1, used_set)
connect used, _used_T_2
node _valid_T = not(valid_clr)
node _valid_T_1 = and(valid, _valid_T)
node _valid_T_2 = or(_valid_T_1, valid_set)
connect valid, _valid_T_2 | module ListBuffer_QueuedRequest_q36_e28_4( // @[ListBuffer.scala:36:7]
input clock, // @[ListBuffer.scala:36:7]
input reset, // @[ListBuffer.scala:36:7]
output io_push_ready, // @[ListBuffer.scala:39:14]
input io_push_valid, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14]
input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14]
input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14]
input io_push_bits_data_control, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14]
input [8:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14]
output [35:0] io_valid, // @[ListBuffer.scala:39:14]
input io_pop_valid, // @[ListBuffer.scala:39:14]
input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14]
output io_data_prio_0, // @[ListBuffer.scala:39:14]
output io_data_prio_1, // @[ListBuffer.scala:39:14]
output io_data_prio_2, // @[ListBuffer.scala:39:14]
output io_data_control, // @[ListBuffer.scala:39:14]
output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14]
output [2:0] io_data_param, // @[ListBuffer.scala:39:14]
output [2:0] io_data_size, // @[ListBuffer.scala:39:14]
output [5:0] io_data_source, // @[ListBuffer.scala:39:14]
output [8:0] io_data_tag, // @[ListBuffer.scala:39:14]
output [5:0] io_data_offset, // @[ListBuffer.scala:39:14]
output [5:0] io_data_put // @[ListBuffer.scala:39:14]
);
wire [39:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18]
wire [4:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18]
wire [4:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18]
wire [4:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18]
wire [4:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18]
wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_0_0 = io_push_bits_data_prio_0; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_2_0 = io_push_bits_data_prio_2; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_control_0 = io_push_bits_data_control; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_opcode_0 = io_push_bits_data_opcode; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_param_0 = io_push_bits_data_param; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_size_0 = io_push_bits_data_size; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_source_0 = io_push_bits_data_source; // @[ListBuffer.scala:36:7]
wire [8:0] io_push_bits_data_tag_0 = io_push_bits_data_tag; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_offset_0 = io_push_bits_data_offset; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_put_0 = io_push_bits_data_put; // @[ListBuffer.scala:36:7]
wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7]
wire [5:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_1 = 1'h0; // @[ListBuffer.scala:36:7]
wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20]
wire [5:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49]
wire [5:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49]
wire io_push_ready_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_0_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_1_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_2_0; // @[ListBuffer.scala:36:7]
wire io_data_control_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_opcode_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_param_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_size_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_source_0; // @[ListBuffer.scala:36:7]
wire [8:0] io_data_tag_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_offset_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_put_0; // @[ListBuffer.scala:36:7]
wire [35:0] io_valid_0; // @[ListBuffer.scala:36:7]
reg [35:0] valid; // @[ListBuffer.scala:47:22]
assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22]
reg [27:0] used; // @[ListBuffer.scala:50:22]
assign io_data_prio_0_0 = _data_ext_R0_data[0]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_prio_1_0 = _data_ext_R0_data[1]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_prio_2_0 = _data_ext_R0_data[2]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_control_0 = _data_ext_R0_data[3]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_opcode_0 = _data_ext_R0_data[6:4]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_param_0 = _data_ext_R0_data[9:7]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_size_0 = _data_ext_R0_data[12:10]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_source_0 = _data_ext_R0_data[18:13]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_tag_0 = _data_ext_R0_data[27:19]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_offset_0 = _data_ext_R0_data[33:28]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_put_0 = _data_ext_R0_data[39:34]; // @[ListBuffer.scala:36:7, :52:18]
wire [27:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25]
wire [28:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48]
wire [27:0] _freeOH_T_2 = _freeOH_T_1[27:0]; // @[package.scala:253:{48,53}]
wire [27:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}]
wire [29:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [27:0] _freeOH_T_5 = _freeOH_T_4[27:0]; // @[package.scala:253:{48,53}]
wire [27:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}]
wire [31:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [27:0] _freeOH_T_8 = _freeOH_T_7[27:0]; // @[package.scala:253:{48,53}]
wire [27:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}]
wire [35:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [27:0] _freeOH_T_11 = _freeOH_T_10[27:0]; // @[package.scala:253:{48,53}]
wire [27:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}]
wire [43:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}]
wire [27:0] _freeOH_T_14 = _freeOH_T_13[27:0]; // @[package.scala:253:{48,53}]
wire [27:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}]
wire [27:0] _freeOH_T_16 = _freeOH_T_15; // @[package.scala:253:43, :254:17]
wire [28:0] _freeOH_T_17 = {_freeOH_T_16, 1'h0}; // @[package.scala:254:17]
wire [28:0] _freeOH_T_18 = ~_freeOH_T_17; // @[ListBuffer.scala:54:{16,32}]
wire [27:0] _freeOH_T_19 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}]
wire [28:0] freeOH = {1'h0, _freeOH_T_18[27:0] & _freeOH_T_19}; // @[ListBuffer.scala:54:{16,38,40}]
wire [12:0] freeIdx_hi = freeOH[28:16]; // @[OneHot.scala:30:18]
wire [15:0] freeIdx_lo = freeOH[15:0]; // @[OneHot.scala:31:18]
wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _freeIdx_T_1 = {3'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] freeIdx_hi_1 = _freeIdx_T_1[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] freeIdx_lo_1 = _freeIdx_T_1[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] freeIdx_hi_2 = _freeIdx_T_3[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] freeIdx_lo_2 = _freeIdx_T_3[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] freeIdx_hi_3 = _freeIdx_T_5[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] freeIdx_lo_3 = _freeIdx_T_5[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _freeIdx_T_8 = _freeIdx_T_7[1]; // @[OneHot.scala:32:28]
wire [1:0] _freeIdx_T_9 = {_freeIdx_T_6, _freeIdx_T_8}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _freeIdx_T_10 = {_freeIdx_T_4, _freeIdx_T_9}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _freeIdx_T_11 = {_freeIdx_T_2, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}]
wire [4:0] freeIdx = {_freeIdx_T, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}]
wire [35:0] valid_set; // @[ListBuffer.scala:57:30]
wire [35:0] valid_clr; // @[ListBuffer.scala:58:30]
wire [27:0] used_set; // @[ListBuffer.scala:59:30]
wire [27:0] used_clr; // @[ListBuffer.scala:60:30]
wire [35:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25]
wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25]
wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26]
assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}]
assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20]
wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35]
wire [63:0] _valid_set_T = 64'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [35:0] _valid_set_T_1 = _valid_set_T[35:0]; // @[OneHot.scala:65:{12,27}]
assign valid_set = data_MPORT_en ? _valid_set_T_1 : 36'h0; // @[OneHot.scala:65:27]
assign used_set = data_MPORT_en ? freeOH[27:0] : 28'h0; // @[Decoupled.scala:51:35]
wire [35:0] _GEN = {30'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24]
wire [35:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24]
wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24] |
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_6 :
input clock : Clock
input reset : Reset
output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>}
regreset state : UInt<5>, clock, reset, UInt<5>(0h0)
reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 9, 6)
node req_tag = shr(req.addr, 10)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd)
node _T = and(io.mem_grant.ready, io.mem_grant.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 3)
node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0))
node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_3 = eq(state, UInt<5>(0h0))
node _sec_rdy_T_4 = eq(state, UInt<5>(0hd))
node _sec_rdy_T_5 = eq(state, UInt<5>(0he))
node _sec_rdy_T_6 = eq(state, UInt<5>(0hf))
node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4)
node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5)
node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6)
node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0))
node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10)
inst rpq of BranchKillableQueue_6
connect rpq.clock, clock
connect rpq.reset, reset
connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken
connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid
connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect rpq.io.flush, io.exception
node _T_1 = eq(state, UInt<5>(0h0))
node _T_2 = eq(rpq.io.empty, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req.sdq_id
connect rpq.io.enq.bits.way_en, io.req.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req.tag_match
connect rpq.io.enq.bits.is_hella, io.req.is_hella
connect rpq.io.enq.bits.data, io.req.data
connect rpq.io.enq.bits.addr, io.req.addr
connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc
connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc
connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if
connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if
connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if
connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if
connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if
connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single
connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val
connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en
connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype
connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype
connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype
connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val
connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3
connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2
connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1
connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst
connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1
connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit
connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique
connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc
connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq
connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq
connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo
connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei
connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence
connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed
connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size
connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd
connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable
connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause
connect rpq.io.enq.bits.uop.exception, io.req.uop.exception
connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst
connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy
connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy
connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy
connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy
connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred
connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3
connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2
connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1
connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst
connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx
connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx
connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx
connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx
connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr
connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed
connect rpq.io.enq.bits.uop.taken, io.req.uop.taken
connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob
connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst
connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx
connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag
connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask
connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb
connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal
connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr
connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br
connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned
connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned
connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state
connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std
connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta
connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load
connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd
connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw
connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn
connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel
connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel
connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel
connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type
connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code
connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type
connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc
connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc
connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst
connect rpq.io.enq.bits.uop.inst, io.req.uop.inst
connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc
connect rpq.io.deq.ready, UInt<1>(0h0)
reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock
reg refill_ctr : UInt<3>, clock
reg commit_line : UInt<1>, clock
reg grant_had_data : UInt<1>, clock
reg finish_to_prefetch : UInt<1>, clock
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_8 = neq(meta_hazard, UInt<1>(0h0))
when _T_8 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_9 = and(io.meta_write.ready, io.meta_write.valid)
when _T_9 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0))
node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1))
node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2))
node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3))
node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2)
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4)
node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4))
node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid)
node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_idx_valid_T = neq(state, UInt<5>(0h0))
connect io.idx.valid, _io_idx_valid_T
node _io_tag_valid_T = neq(state, UInt<5>(0h0))
connect io.tag.valid, _io_tag_valid_T
node _io_way_valid_T = eq(state, UInt<5>(0h0))
node _io_way_valid_T_1 = eq(state, UInt<5>(0h11))
node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1)
node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0))
connect io.way.valid, _io_way_valid_T_3
connect io.idx.bits, req_idx
connect io.tag.bits, req_tag
connect io.way.bits, req.way_en
connect io.meta_write.valid, UInt<1>(0h0)
invalidate io.meta_write.bits.data.tag
invalidate io.meta_write.bits.data.coh.state
invalidate io.meta_write.bits.tag
invalidate io.meta_write.bits.way_en
invalidate io.meta_write.bits.idx
connect io.req_pri_rdy, UInt<1>(0h0)
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
connect io.mem_acquire.valid, UInt<1>(0h0)
invalidate io.mem_acquire.bits.corrupt
invalidate io.mem_acquire.bits.data
invalidate io.mem_acquire.bits.mask
invalidate io.mem_acquire.bits.address
invalidate io.mem_acquire.bits.source
invalidate io.mem_acquire.bits.size
invalidate io.mem_acquire.bits.param
invalidate io.mem_acquire.bits.opcode
connect io.refill.valid, UInt<1>(0h0)
invalidate io.refill.bits.data
invalidate io.refill.bits.wmask
invalidate io.refill.bits.addr
invalidate io.refill.bits.way_en
connect io.replay.valid, UInt<1>(0h0)
invalidate io.replay.bits.sdq_id
invalidate io.replay.bits.way_en
invalidate io.replay.bits.old_meta.tag
invalidate io.replay.bits.old_meta.coh.state
invalidate io.replay.bits.tag_match
invalidate io.replay.bits.is_hella
invalidate io.replay.bits.data
invalidate io.replay.bits.addr
invalidate io.replay.bits.uop.debug_tsrc
invalidate io.replay.bits.uop.debug_fsrc
invalidate io.replay.bits.uop.bp_xcpt_if
invalidate io.replay.bits.uop.bp_debug_if
invalidate io.replay.bits.uop.xcpt_ma_if
invalidate io.replay.bits.uop.xcpt_ae_if
invalidate io.replay.bits.uop.xcpt_pf_if
invalidate io.replay.bits.uop.fp_single
invalidate io.replay.bits.uop.fp_val
invalidate io.replay.bits.uop.frs3_en
invalidate io.replay.bits.uop.lrs2_rtype
invalidate io.replay.bits.uop.lrs1_rtype
invalidate io.replay.bits.uop.dst_rtype
invalidate io.replay.bits.uop.ldst_val
invalidate io.replay.bits.uop.lrs3
invalidate io.replay.bits.uop.lrs2
invalidate io.replay.bits.uop.lrs1
invalidate io.replay.bits.uop.ldst
invalidate io.replay.bits.uop.ldst_is_rs1
invalidate io.replay.bits.uop.flush_on_commit
invalidate io.replay.bits.uop.is_unique
invalidate io.replay.bits.uop.is_sys_pc2epc
invalidate io.replay.bits.uop.uses_stq
invalidate io.replay.bits.uop.uses_ldq
invalidate io.replay.bits.uop.is_amo
invalidate io.replay.bits.uop.is_fencei
invalidate io.replay.bits.uop.is_fence
invalidate io.replay.bits.uop.mem_signed
invalidate io.replay.bits.uop.mem_size
invalidate io.replay.bits.uop.mem_cmd
invalidate io.replay.bits.uop.bypassable
invalidate io.replay.bits.uop.exc_cause
invalidate io.replay.bits.uop.exception
invalidate io.replay.bits.uop.stale_pdst
invalidate io.replay.bits.uop.ppred_busy
invalidate io.replay.bits.uop.prs3_busy
invalidate io.replay.bits.uop.prs2_busy
invalidate io.replay.bits.uop.prs1_busy
invalidate io.replay.bits.uop.ppred
invalidate io.replay.bits.uop.prs3
invalidate io.replay.bits.uop.prs2
invalidate io.replay.bits.uop.prs1
invalidate io.replay.bits.uop.pdst
invalidate io.replay.bits.uop.rxq_idx
invalidate io.replay.bits.uop.stq_idx
invalidate io.replay.bits.uop.ldq_idx
invalidate io.replay.bits.uop.rob_idx
invalidate io.replay.bits.uop.csr_addr
invalidate io.replay.bits.uop.imm_packed
invalidate io.replay.bits.uop.taken
invalidate io.replay.bits.uop.pc_lob
invalidate io.replay.bits.uop.edge_inst
invalidate io.replay.bits.uop.ftq_idx
invalidate io.replay.bits.uop.br_tag
invalidate io.replay.bits.uop.br_mask
invalidate io.replay.bits.uop.is_sfb
invalidate io.replay.bits.uop.is_jal
invalidate io.replay.bits.uop.is_jalr
invalidate io.replay.bits.uop.is_br
invalidate io.replay.bits.uop.iw_p2_poisoned
invalidate io.replay.bits.uop.iw_p1_poisoned
invalidate io.replay.bits.uop.iw_state
invalidate io.replay.bits.uop.ctrl.is_std
invalidate io.replay.bits.uop.ctrl.is_sta
invalidate io.replay.bits.uop.ctrl.is_load
invalidate io.replay.bits.uop.ctrl.csr_cmd
invalidate io.replay.bits.uop.ctrl.fcn_dw
invalidate io.replay.bits.uop.ctrl.op_fcn
invalidate io.replay.bits.uop.ctrl.imm_sel
invalidate io.replay.bits.uop.ctrl.op2_sel
invalidate io.replay.bits.uop.ctrl.op1_sel
invalidate io.replay.bits.uop.ctrl.br_type
invalidate io.replay.bits.uop.fu_code
invalidate io.replay.bits.uop.iq_type
invalidate io.replay.bits.uop.debug_pc
invalidate io.replay.bits.uop.is_rvc
invalidate io.replay.bits.uop.debug_inst
invalidate io.replay.bits.uop.inst
invalidate io.replay.bits.uop.uopc
connect io.wb_req.valid, UInt<1>(0h0)
invalidate io.wb_req.bits.voluntary
invalidate io.wb_req.bits.way_en
invalidate io.wb_req.bits.param
invalidate io.wb_req.bits.source
invalidate io.wb_req.bits.idx
invalidate io.wb_req.bits.tag
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.is_hella
invalidate io.resp.bits.data
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
connect io.commit_val, UInt<1>(0h0)
connect io.commit_addr, req.addr
connect io.commit_coh, coh_on_grant
connect io.meta_read.valid, UInt<1>(0h0)
invalidate io.meta_read.bits.tag
invalidate io.meta_read.bits.way_en
invalidate io.meta_read.bits.idx
connect io.mem_finish.valid, UInt<1>(0h0)
invalidate io.mem_finish.bits.sink
connect io.lb_write.valid, UInt<1>(0h0)
invalidate io.lb_write.bits.data
invalidate io.lb_write.bits.offset
invalidate io.lb_write.bits.id
connect io.lb_read.valid, UInt<1>(0h0)
invalidate io.lb_read.bits.offset
invalidate io.lb_read.bits.id
connect io.mem_grant.ready, UInt<1>(0h0)
node _T_10 = and(io.req_sec_val, io.req_sec_rdy)
when _T_10 :
connect req.uop.mem_cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_11 = eq(state, UInt<5>(0h0))
when _T_11 :
connect io.req_pri_rdy, UInt<1>(0h1)
connect grant_had_data, UInt<1>(0h0)
node _T_12 = and(io.req_pri_val, io.req_pri_rdy)
when _T_12 :
wire state_new_state : UInt
connect state_new_state, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T = asUInt(reset)
node _state_T_1 = eq(_state_T, UInt<1>(0h0))
when _state_T_1 :
node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert
connect req, io.req
node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1)
node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3)
node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20)
node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21)
node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22)
node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24)
node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25)
node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26)
node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28)
node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29)
node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30)
node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32)
node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33)
node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34)
node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36)
node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37)
node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38)
node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40)
node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41)
node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42)
node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44)
node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45)
node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46)
node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48)
node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49)
node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50)
node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52)
node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53)
node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54)
node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56)
node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57)
node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58)
node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6)
node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60)
node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61)
node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62)
wire state_req_needs_wb_meta : { state : UInt<2>}
connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3
connect req_needs_wb, state_req_needs_wb_r_1
when io.req.tag_match :
node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1)
node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3)
node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6)
node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7)
node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8)
node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13)
node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14)
node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15)
node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16)
node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20)
node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21)
node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24)
node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26)
node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29)
node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30)
node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31)
node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36)
node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37)
node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38)
node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39)
node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43)
node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44)
node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46)
node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48)
node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49)
node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state)
node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3))
node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2))
node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1))
node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3))
node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2))
node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3))
node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2))
node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0))
node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1))
node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0))
node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1))
node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0))
node _state_r_T_25 = eq(_state_r_T_24, _state_r_T)
node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_28 = eq(_state_r_T_22, _state_r_T)
node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26)
node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27)
node _state_r_T_31 = eq(_state_r_T_20, _state_r_T)
node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29)
node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30)
node _state_r_T_34 = eq(_state_r_T_18, _state_r_T)
node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32)
node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33)
node _state_r_T_37 = eq(_state_r_T_16, _state_r_T)
node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35)
node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36)
node _state_r_T_40 = eq(_state_r_T_14, _state_r_T)
node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38)
node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39)
node _state_r_T_43 = eq(_state_r_T_12, _state_r_T)
node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41)
node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42)
node _state_r_T_46 = eq(_state_r_T_10, _state_r_T)
node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44)
node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45)
node _state_r_T_49 = eq(_state_r_T_8, _state_r_T)
node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47)
node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48)
node _state_r_T_52 = eq(_state_r_T_6, _state_r_T)
node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50)
node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51)
node _state_r_T_55 = eq(_state_r_T_4, _state_r_T)
node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53)
node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54)
node _state_r_T_58 = eq(_state_r_T_2, _state_r_T)
node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56)
node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57)
wire state_coh_on_hit : { state : UInt<2>}
connect state_coh_on_hit.state, state_r_2
when state_is_hit :
node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_5 = or(_state_T_3, _state_T_4)
node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_7 = or(_state_T_5, _state_T_6)
node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_12 = or(_state_T_8, _state_T_9)
node _state_T_13 = or(_state_T_12, _state_T_10)
node _state_T_14 = or(_state_T_13, _state_T_11)
node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_20 = or(_state_T_15, _state_T_16)
node _state_T_21 = or(_state_T_20, _state_T_17)
node _state_T_22 = or(_state_T_21, _state_T_18)
node _state_T_23 = or(_state_T_22, _state_T_19)
node _state_T_24 = or(_state_T_14, _state_T_23)
node _state_T_25 = or(_state_T_7, _state_T_24)
node _state_T_26 = asUInt(reset)
node _state_T_27 = eq(_state_T_26, UInt<1>(0h0))
when _state_T_27 :
node _state_T_28 = eq(_state_T_25, UInt<1>(0h0))
when _state_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1
assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1
connect new_coh, state_coh_on_hit
connect state_new_state, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state, UInt<5>(0h1)
else :
wire state_new_coh_meta : { state : UInt<2>}
connect state_new_coh_meta.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta
connect state_new_state, UInt<5>(0h1)
connect state, state_new_state
else :
node _T_13 = eq(state, UInt<5>(0h1))
when _T_13 :
connect io.mem_acquire.valid, UInt<1>(0h1)
node _io_mem_acquire_bits_T = cat(req_tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5)
node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7)
node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9)
node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, io.id
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_14 :
connect state, UInt<5>(0h2)
else :
node _T_15 = eq(state, UInt<5>(0h2))
when _T_15 :
node opdata = bits(io.mem_grant.bits.opcode, 0, 0)
when opdata :
connect io.mem_grant.ready, io.lb_write.ready
connect io.lb_write.valid, io.mem_grant.valid
connect io.lb_write.bits.id, io.id
node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3)
connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T
connect io.lb_write.bits.data, io.mem_grant.bits.data
else :
connect io.mem_grant.ready, UInt<1>(0h1)
node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid)
when _T_16 :
node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
connect grant_had_data, grant_had_data_opdata
when refill_done :
node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0))
node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2)
connect grantack.valid, _grantack_valid_T_3
wire grantack_bits_e : { sink : UInt<3>}
connect grantack_bits_e.sink, io.mem_grant.bits.sink
connect grantack.bits, grantack_bits_e
node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc))
connect state, _state_T_29
node _T_17 = eq(grant_had_data, UInt<1>(0h0))
node _T_18 = and(_T_17, req_needs_wb)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
connect commit_line, UInt<1>(0h0)
connect new_coh, coh_on_grant
else :
node _T_23 = eq(state, UInt<5>(0h3))
when _T_23 :
node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0))
node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10))
node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1)
node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2)
node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3)
node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8)
node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9)
node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10)
node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15)
node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16)
node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17)
node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18)
node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22)
node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23)
node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26)
node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28)
node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31)
node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32)
node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33)
node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38)
node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39)
node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40)
node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41)
node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45)
node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46)
node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0))
node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48)
node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node drain_load = and(_drain_load_T_49, _drain_load_T_50)
node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node rp_addr_hi = cat(req_tag, req_idx)
node rp_addr = cat(rp_addr_hi, _rp_addr_T)
node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0))
node data_word = dshr(io.lb_resp, _data_word_T)
node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0)
node hi = cat(req_tag, req_idx)
node _T_25 = cat(hi, _T_24)
wire size : UInt<2>
connect size, rpq.io.deq.bits.uop.mem_size
node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready)
node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1
node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load)
connect io.lb_read.valid, _io_lb_read_valid_T
connect io.lb_read.bits.id, io.id
node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3)
connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T
node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid)
node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T)
node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load)
connect io.resp.valid, _io_resp_valid_T_2
connect io.resp.bits.uop, rpq.io.deq.bits.uop
node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(data_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid)
when _T_26 :
connect commit_line, UInt<1>(0h1)
else :
node _T_27 = eq(commit_line, UInt<1>(0h0))
node _T_28 = and(rpq.io.empty, _T_27)
when _T_28 :
node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_31 = eq(drain_load, UInt<1>(0h0))
node _T_32 = and(rpq.io.deq.valid, _T_31)
node _T_33 = or(rpq.io.empty, _T_32)
when _T_33 :
connect io.commit_val, UInt<1>(0h1)
connect state, UInt<5>(0h4)
else :
node _T_34 = eq(state, UInt<5>(0h4))
when _T_34 :
node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1)
node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6)
node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx)
node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4)
connect io.meta_read.valid, _io_meta_read_valid_T_5
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
connect io.meta_read.bits.way_en, req.way_en
node _T_35 = and(io.meta_read.ready, io.meta_read.valid)
when _T_35 :
connect state, UInt<5>(0h5)
else :
node _T_36 = eq(state, UInt<5>(0h5))
when _T_36 :
connect state, UInt<5>(0h6)
else :
node _T_37 = eq(state, UInt<5>(0h6))
when _T_37 :
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0))
node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb))
node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31)
connect state, _state_T_32
else :
node _T_38 = eq(state, UInt<5>(0h7))
when _T_38 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, coh_on_clear
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_39 = and(io.meta_write.ready, io.meta_write.valid)
when _T_39 :
connect state, UInt<5>(0h9)
else :
node _T_40 = eq(state, UInt<5>(0h9))
when _T_40 :
connect io.wb_req.valid, UInt<1>(0h1)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.source, io.id
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
node _T_41 = and(io.wb_req.ready, io.wb_req.valid)
when _T_41 :
connect state, UInt<5>(0ha)
else :
node _T_42 = eq(state, UInt<5>(0ha))
when _T_42 :
when io.wb_resp :
connect state, UInt<5>(0hb)
else :
node _T_43 = eq(state, UInt<5>(0hb))
when _T_43 :
connect io.lb_read.valid, UInt<1>(0h1)
connect io.lb_read.bits.id, io.id
connect io.lb_read.bits.offset, refill_ctr
node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid)
connect io.refill.valid, _io_refill_valid_T
node _io_refill_bits_addr_T = shl(refill_ctr, 3)
node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T)
connect io.refill.bits.addr, _io_refill_bits_addr_T_1
connect io.refill.bits.way_en, req.way_en
node _io_refill_bits_wmask_T = not(UInt<1>(0h0))
connect io.refill.bits.wmask, _io_refill_bits_wmask_T
connect io.refill.bits.data, io.lb_resp
node _T_44 = and(io.refill.ready, io.refill.valid)
when _T_44 :
node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1))
node _refill_ctr_T_1 = tail(_refill_ctr_T, 1)
connect refill_ctr, _refill_ctr_T_1
node _T_45 = eq(refill_ctr, UInt<3>(0h7))
when _T_45 :
connect state, UInt<5>(0hc)
else :
node _T_46 = eq(state, UInt<5>(0hc))
when _T_46 :
connect io.replay.bits, rpq.io.deq.bits
connect io.replay.valid, rpq.io.deq.valid
connect rpq.io.deq.ready, io.replay.ready
connect io.replay.bits.way_en, req.way_en
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(req_tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
node _T_47 = and(io.replay.ready, io.replay.valid)
node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _T_52 = or(_T_50, _T_51)
node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _T_57 = or(_T_53, _T_54)
node _T_58 = or(_T_57, _T_55)
node _T_59 = or(_T_58, _T_56)
node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _T_65 = or(_T_60, _T_61)
node _T_66 = or(_T_65, _T_62)
node _T_67 = or(_T_66, _T_63)
node _T_68 = or(_T_67, _T_64)
node _T_69 = or(_T_59, _T_68)
node _T_70 = or(_T_52, _T_69)
node _T_71 = and(_T_47, _T_70)
when _T_71 :
node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, new_coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(is_hit, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2
assert(clock, is_hit, UInt<1>(0h1), "") : assert_2
connect new_coh, coh_on_hit
node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0))
node _T_76 = and(rpq.io.empty, _T_75)
when _T_76 :
connect state, UInt<5>(0hd)
else :
node _T_77 = eq(state, UInt<5>(0hd))
when _T_77 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, new_coh
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_78 = and(io.meta_write.ready, io.meta_write.valid)
when _T_78 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_79 = eq(state, UInt<5>(0he))
when _T_79 :
connect io.mem_finish.valid, grantack.valid
connect io.mem_finish.bits, grantack.bits
node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid)
node _T_81 = eq(grantack.valid, UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
when _T_82 :
connect grantack.valid, UInt<1>(0h0)
connect state, UInt<5>(0hf)
else :
node _T_83 = eq(state, UInt<5>(0hf))
when _T_83 :
node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0))
connect state, _state_T_33
else :
node _T_84 = eq(state, UInt<5>(0h11))
when _T_84 :
connect io.req_pri_rdy, UInt<1>(0h1)
node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0))
node _T_86 = and(io.req_sec_val, _T_85)
node _T_87 = or(_T_86, io.clear_prefetch)
when _T_87 :
connect state, UInt<5>(0h0)
else :
node _T_88 = and(io.req_sec_val, io.req_sec_rdy)
when _T_88 :
node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51)
node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53)
node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56)
node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57)
node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58)
node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63)
node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64)
node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65)
node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66)
node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70)
node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71)
node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74)
node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76)
node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79)
node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80)
node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81)
node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86)
node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87)
node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88)
node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89)
node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93)
node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94)
node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96)
node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98)
node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99)
node _r_T_123 = cat(r_c_1, new_coh.state)
node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_125 = cat(_r_T_124, UInt<2>(0h3))
node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_127 = cat(_r_T_126, UInt<2>(0h2))
node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_129 = cat(_r_T_128, UInt<2>(0h1))
node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_131 = cat(_r_T_130, UInt<2>(0h3))
node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_133 = cat(_r_T_132, UInt<2>(0h2))
node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_135 = cat(_r_T_134, UInt<2>(0h3))
node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_137 = cat(_r_T_136, UInt<2>(0h2))
node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_139 = cat(_r_T_138, UInt<2>(0h0))
node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_141 = cat(_r_T_140, UInt<2>(0h1))
node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_143 = cat(_r_T_142, UInt<2>(0h0))
node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_145 = cat(_r_T_144, UInt<2>(0h1))
node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_147 = cat(_r_T_146, UInt<2>(0h0))
node _r_T_148 = eq(_r_T_147, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_151 = eq(_r_T_145, _r_T_123)
node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149)
node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150)
node _r_T_154 = eq(_r_T_143, _r_T_123)
node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152)
node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153)
node _r_T_157 = eq(_r_T_141, _r_T_123)
node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155)
node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156)
node _r_T_160 = eq(_r_T_139, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158)
node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159)
node _r_T_163 = eq(_r_T_137, _r_T_123)
node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161)
node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162)
node _r_T_166 = eq(_r_T_135, _r_T_123)
node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164)
node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165)
node _r_T_169 = eq(_r_T_133, _r_T_123)
node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167)
node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168)
node _r_T_172 = eq(_r_T_131, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170)
node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171)
node _r_T_175 = eq(_r_T_129, _r_T_123)
node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173)
node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174)
node _r_T_178 = eq(_r_T_127, _r_T_123)
node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176)
node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177)
node _r_T_181 = eq(_r_T_125, _r_T_123)
node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179)
node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180)
wire coh_on_hit_1 : { state : UInt<2>}
connect coh_on_hit_1.state, r_2_2
when is_hit_1 :
connect new_coh, coh_on_hit_1
connect state, UInt<5>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
connect state, UInt<5>(0h1)
else :
node _T_89 = and(io.req_pri_val, io.req_pri_rdy)
when _T_89 :
connect grant_had_data, UInt<1>(0h0)
wire state_new_state_1 : UInt
connect state_new_state_1, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T_34 = asUInt(reset)
node _state_T_35 = eq(_state_T_34, UInt<1>(0h0))
when _state_T_35 :
node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2
connect req, io.req
node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65)
node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67)
node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84)
node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85)
node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86)
node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88)
node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89)
node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90)
node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92)
node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93)
node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94)
node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96)
node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97)
node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98)
node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100)
node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101)
node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102)
node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104)
node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105)
node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106)
node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108)
node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109)
node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110)
node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112)
node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113)
node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114)
node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116)
node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117)
node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118)
node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120)
node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121)
node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122)
node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70)
node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124)
node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125)
node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126)
wire state_req_needs_wb_meta_1 : { state : UInt<2>}
connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1
connect req_needs_wb, state_req_needs_wb_r_1_1
when io.req.tag_match :
node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51)
node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53)
node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56)
node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57)
node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58)
node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63)
node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64)
node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65)
node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66)
node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70)
node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71)
node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74)
node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76)
node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79)
node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80)
node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81)
node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86)
node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87)
node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88)
node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89)
node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93)
node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94)
node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96)
node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98)
node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99)
node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state)
node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3))
node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2))
node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1))
node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3))
node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2))
node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3))
node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2))
node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0))
node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1))
node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0))
node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1))
node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0))
node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59)
node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59)
node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85)
node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86)
node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59)
node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88)
node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89)
node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59)
node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91)
node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92)
node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59)
node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94)
node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95)
node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59)
node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97)
node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98)
node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59)
node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100)
node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101)
node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59)
node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103)
node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104)
node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59)
node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106)
node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107)
node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59)
node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109)
node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110)
node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59)
node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112)
node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113)
node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59)
node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115)
node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116)
wire state_coh_on_hit_1 : { state : UInt<2>}
connect state_coh_on_hit_1.state, state_r_2_1
when state_is_hit_1 :
node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_39 = or(_state_T_37, _state_T_38)
node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_41 = or(_state_T_39, _state_T_40)
node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_46 = or(_state_T_42, _state_T_43)
node _state_T_47 = or(_state_T_46, _state_T_44)
node _state_T_48 = or(_state_T_47, _state_T_45)
node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_54 = or(_state_T_49, _state_T_50)
node _state_T_55 = or(_state_T_54, _state_T_51)
node _state_T_56 = or(_state_T_55, _state_T_52)
node _state_T_57 = or(_state_T_56, _state_T_53)
node _state_T_58 = or(_state_T_48, _state_T_57)
node _state_T_59 = or(_state_T_41, _state_T_58)
node _state_T_60 = asUInt(reset)
node _state_T_61 = eq(_state_T_60, UInt<1>(0h0))
when _state_T_61 :
node _state_T_62 = eq(_state_T_59, UInt<1>(0h0))
when _state_T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3
assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3
connect new_coh, state_coh_on_hit_1
connect state_new_state_1, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state_1, UInt<5>(0h1)
else :
wire state_new_coh_meta_1 : { state : UInt<2>}
connect state_new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta_1
connect state_new_state_1, UInt<5>(0h1)
connect state, state_new_state_1 | module BoomMSHR_6( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_is_br, // @[mshrs.scala:39:14]
input io_req_uop_is_jalr, // @[mshrs.scala:39:14]
input io_req_uop_is_jal, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input io_req_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input io_req_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input io_req_uop_fp_single, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [33:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [1:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [3:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [1:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [23:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [33:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
input io_lb_read_ready, // @[mshrs.scala:39:14]
output io_lb_read_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14]
input [63:0] io_lb_resp, // @[mshrs.scala:39:14]
input io_lb_write_ready, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19]
wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7]
wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7]
wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:194:11]
wire _state_T_26 = reset; // @[mshrs.scala:201:15]
wire _state_T_34 = reset; // @[mshrs.scala:194:11]
wire _state_T_60 = reset; // @[mshrs.scala:201:15]
wire [2:0] io_id = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_id = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_id = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] io_mem_acquire_bits_source = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_source = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] io_mem_acquire_bits_a_source = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [3:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [23:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26]
wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_read_valid_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20]
reg req_uop_is_br; // @[mshrs.scala:109:20]
reg req_uop_is_jalr; // @[mshrs.scala:109:20]
reg req_uop_is_jal; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20]
reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg req_uop_bypassable; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg req_uop_ldst_val; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg req_uop_fp_single; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [33:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [1:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34]
wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [2:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37]
wire [4:0] state_new_state; // @[mshrs.scala:191:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28]
wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28]
assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28]
wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22]
assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22]
wire [27:0] hi; // @[mshrs.scala:266:10]
assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10]
wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31]
assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31]
wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}]
wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61]
wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45]
wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}]
wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48]
wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52]
wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T; // @[Decoupled.scala:51:35]
assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_refill_valid_T; // @[Decoupled.scala:51:35]
assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}]
wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}]
assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}]
wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22]
wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41]
assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47]
assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59]
wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}]
wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32]
wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22]
wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39]
wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47]
assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70]
assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}]
assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47]
assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20]
wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17]
wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38]
wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47]
wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:191:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_113 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h70))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h71))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h72))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h73))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<7>(0h7c))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 2)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<7>(0h7b))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0)
node _source_ok_T_37 = shr(io.in.a.bits.source, 5)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0hd))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0)
node _source_ok_T_43 = shr(io.in.a.bits.source, 5)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<4>(0hc))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0)
node _source_ok_T_49 = shr(io.in.a.bits.source, 5)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<4>(0hb))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0)
node _source_ok_T_55 = shr(io.in.a.bits.source, 5)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<4>(0ha))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0)
node _source_ok_T_61 = shr(io.in.a.bits.source, 5)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<4>(0h9))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0)
node _source_ok_T_67 = shr(io.in.a.bits.source, 5)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<4>(0h8))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_73 = shr(io.in.a.bits.source, 2)
node _source_ok_T_74 = eq(_source_ok_T_73, UInt<7>(0h7a))
node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_T_77 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_79 = shr(io.in.a.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<7>(0h79))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0)
node _source_ok_T_85 = shr(io.in.a.bits.source, 5)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<3>(0h7))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0)
node _source_ok_T_91 = shr(io.in.a.bits.source, 5)
node _source_ok_T_92 = eq(_source_ok_T_91, UInt<3>(0h6))
node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93)
node _source_ok_T_95 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f))
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0)
node _source_ok_T_97 = shr(io.in.a.bits.source, 5)
node _source_ok_T_98 = eq(_source_ok_T_97, UInt<3>(0h5))
node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_16)
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f))
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0)
node _source_ok_T_103 = shr(io.in.a.bits.source, 5)
node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4))
node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_17)
node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105)
node _source_ok_T_107 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f))
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0)
node _source_ok_T_109 = shr(io.in.a.bits.source, 5)
node _source_ok_T_110 = eq(_source_ok_T_109, UInt<2>(0h3))
node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_18)
node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111)
node _source_ok_T_113 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f))
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0)
node _source_ok_T_115 = shr(io.in.a.bits.source, 5)
node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2))
node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_19)
node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117)
node _source_ok_T_119 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f))
node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119)
node _source_ok_uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0)
node _source_ok_T_121 = shr(io.in.a.bits.source, 5)
node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h1))
node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_20)
node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123)
node _source_ok_T_125 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f))
node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125)
node _source_ok_uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0)
node _source_ok_T_127 = shr(io.in.a.bits.source, 5)
node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h0))
node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_21)
node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129)
node _source_ok_T_131 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f))
node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131)
node _source_ok_T_133 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _source_ok_T_134 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _source_ok_T_135 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _source_ok_T_136 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE : UInt<1>[27]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_42
connect _source_ok_WIRE[8], _source_ok_T_48
connect _source_ok_WIRE[9], _source_ok_T_54
connect _source_ok_WIRE[10], _source_ok_T_60
connect _source_ok_WIRE[11], _source_ok_T_66
connect _source_ok_WIRE[12], _source_ok_T_72
connect _source_ok_WIRE[13], _source_ok_T_78
connect _source_ok_WIRE[14], _source_ok_T_84
connect _source_ok_WIRE[15], _source_ok_T_90
connect _source_ok_WIRE[16], _source_ok_T_96
connect _source_ok_WIRE[17], _source_ok_T_102
connect _source_ok_WIRE[18], _source_ok_T_108
connect _source_ok_WIRE[19], _source_ok_T_114
connect _source_ok_WIRE[20], _source_ok_T_120
connect _source_ok_WIRE[21], _source_ok_T_126
connect _source_ok_WIRE[22], _source_ok_T_132
connect _source_ok_WIRE[23], _source_ok_T_133
connect _source_ok_WIRE[24], _source_ok_T_134
connect _source_ok_WIRE[25], _source_ok_T_135
connect _source_ok_WIRE[26], _source_ok_T_136
node _source_ok_T_137 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE[2])
node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE[3])
node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE[4])
node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE[5])
node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE[6])
node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE[7])
node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE[8])
node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE[9])
node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE[10])
node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE[11])
node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE[12])
node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE[13])
node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE[14])
node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE[15])
node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE[16])
node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE[17])
node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE[18])
node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE[19])
node _source_ok_T_156 = or(_source_ok_T_155, _source_ok_WIRE[20])
node _source_ok_T_157 = or(_source_ok_T_156, _source_ok_WIRE[21])
node _source_ok_T_158 = or(_source_ok_T_157, _source_ok_WIRE[22])
node _source_ok_T_159 = or(_source_ok_T_158, _source_ok_WIRE[23])
node _source_ok_T_160 = or(_source_ok_T_159, _source_ok_WIRE[24])
node _source_ok_T_161 = or(_source_ok_T_160, _source_ok_WIRE[25])
node source_ok = or(_source_ok_T_161, _source_ok_WIRE[26])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<7>(0h70))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<7>(0h71))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<7>(0h72))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<7>(0h73))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<7>(0h7c))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_77 = shr(io.in.a.bits.source, 2)
node _T_78 = eq(_T_77, UInt<7>(0h7b))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_90 = shr(io.in.a.bits.source, 5)
node _T_91 = eq(_T_90, UInt<4>(0hd))
node _T_92 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_93 = and(_T_91, _T_92)
node _T_94 = leq(uncommonBits_6, UInt<5>(0h1f))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_98 = cvt(_T_97)
node _T_99 = and(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = asSInt(_T_99)
node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0)))
node _T_102 = or(_T_96, _T_101)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_103 = shr(io.in.a.bits.source, 5)
node _T_104 = eq(_T_103, UInt<4>(0hc))
node _T_105 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_106 = and(_T_104, _T_105)
node _T_107 = leq(uncommonBits_7, UInt<5>(0h1f))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(_T_108, UInt<1>(0h0))
node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = or(_T_109, _T_114)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_116 = shr(io.in.a.bits.source, 5)
node _T_117 = eq(_T_116, UInt<4>(0hb))
node _T_118 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_119 = and(_T_117, _T_118)
node _T_120 = leq(uncommonBits_8, UInt<5>(0h1f))
node _T_121 = and(_T_119, _T_120)
node _T_122 = eq(_T_121, UInt<1>(0h0))
node _T_123 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_124 = cvt(_T_123)
node _T_125 = and(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = asSInt(_T_125)
node _T_127 = eq(_T_126, asSInt(UInt<1>(0h0)))
node _T_128 = or(_T_122, _T_127)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0)
node _T_129 = shr(io.in.a.bits.source, 5)
node _T_130 = eq(_T_129, UInt<4>(0ha))
node _T_131 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_132 = and(_T_130, _T_131)
node _T_133 = leq(uncommonBits_9, UInt<5>(0h1f))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(_T_134, UInt<1>(0h0))
node _T_136 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = or(_T_135, _T_140)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0)
node _T_142 = shr(io.in.a.bits.source, 5)
node _T_143 = eq(_T_142, UInt<4>(0h9))
node _T_144 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_145 = and(_T_143, _T_144)
node _T_146 = leq(uncommonBits_10, UInt<5>(0h1f))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = or(_T_148, _T_153)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0)
node _T_155 = shr(io.in.a.bits.source, 5)
node _T_156 = eq(_T_155, UInt<4>(0h8))
node _T_157 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_158 = and(_T_156, _T_157)
node _T_159 = leq(uncommonBits_11, UInt<5>(0h1f))
node _T_160 = and(_T_158, _T_159)
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_168 = shr(io.in.a.bits.source, 2)
node _T_169 = eq(_T_168, UInt<7>(0h7a))
node _T_170 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_171 = and(_T_169, _T_170)
node _T_172 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_173 = and(_T_171, _T_172)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_176 = cvt(_T_175)
node _T_177 = and(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = asSInt(_T_177)
node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0)))
node _T_180 = or(_T_174, _T_179)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<7>(0h79))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(_T_186, UInt<1>(0h0))
node _T_188 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_189 = cvt(_T_188)
node _T_190 = and(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = asSInt(_T_190)
node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0)))
node _T_193 = or(_T_187, _T_192)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0)
node _T_194 = shr(io.in.a.bits.source, 5)
node _T_195 = eq(_T_194, UInt<3>(0h7))
node _T_196 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_197 = and(_T_195, _T_196)
node _T_198 = leq(uncommonBits_14, UInt<5>(0h1f))
node _T_199 = and(_T_197, _T_198)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = or(_T_200, _T_205)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0)
node _T_207 = shr(io.in.a.bits.source, 5)
node _T_208 = eq(_T_207, UInt<3>(0h6))
node _T_209 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_210 = and(_T_208, _T_209)
node _T_211 = leq(uncommonBits_15, UInt<5>(0h1f))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(_T_212, UInt<1>(0h0))
node _T_214 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_215 = cvt(_T_214)
node _T_216 = and(_T_215, asSInt(UInt<1>(0h0)))
node _T_217 = asSInt(_T_216)
node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0)))
node _T_219 = or(_T_213, _T_218)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0)
node _T_220 = shr(io.in.a.bits.source, 5)
node _T_221 = eq(_T_220, UInt<3>(0h5))
node _T_222 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_223 = and(_T_221, _T_222)
node _T_224 = leq(uncommonBits_16, UInt<5>(0h1f))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(_T_225, UInt<1>(0h0))
node _T_227 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_228 = cvt(_T_227)
node _T_229 = and(_T_228, asSInt(UInt<1>(0h0)))
node _T_230 = asSInt(_T_229)
node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0)))
node _T_232 = or(_T_226, _T_231)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0)
node _T_233 = shr(io.in.a.bits.source, 5)
node _T_234 = eq(_T_233, UInt<3>(0h4))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_17, UInt<5>(0h1f))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_241 = cvt(_T_240)
node _T_242 = and(_T_241, asSInt(UInt<1>(0h0)))
node _T_243 = asSInt(_T_242)
node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = or(_T_239, _T_244)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0)
node _T_246 = shr(io.in.a.bits.source, 5)
node _T_247 = eq(_T_246, UInt<2>(0h3))
node _T_248 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_249 = and(_T_247, _T_248)
node _T_250 = leq(uncommonBits_18, UInt<5>(0h1f))
node _T_251 = and(_T_249, _T_250)
node _T_252 = eq(_T_251, UInt<1>(0h0))
node _T_253 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_254 = cvt(_T_253)
node _T_255 = and(_T_254, asSInt(UInt<1>(0h0)))
node _T_256 = asSInt(_T_255)
node _T_257 = eq(_T_256, asSInt(UInt<1>(0h0)))
node _T_258 = or(_T_252, _T_257)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0)
node _T_259 = shr(io.in.a.bits.source, 5)
node _T_260 = eq(_T_259, UInt<2>(0h2))
node _T_261 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_262 = and(_T_260, _T_261)
node _T_263 = leq(uncommonBits_19, UInt<5>(0h1f))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(_T_264, UInt<1>(0h0))
node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_267 = cvt(_T_266)
node _T_268 = and(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = asSInt(_T_268)
node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0)))
node _T_271 = or(_T_265, _T_270)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0)
node _T_272 = shr(io.in.a.bits.source, 5)
node _T_273 = eq(_T_272, UInt<1>(0h1))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_20, UInt<5>(0h1f))
node _T_277 = and(_T_275, _T_276)
node _T_278 = eq(_T_277, UInt<1>(0h0))
node _T_279 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = or(_T_278, _T_283)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0)
node _T_285 = shr(io.in.a.bits.source, 5)
node _T_286 = eq(_T_285, UInt<1>(0h0))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_21, UInt<5>(0h1f))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(_T_290, UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = or(_T_291, _T_296)
node _T_298 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_299 = eq(_T_298, UInt<1>(0h0))
node _T_300 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = or(_T_299, _T_304)
node _T_306 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_307 = eq(_T_306, UInt<1>(0h0))
node _T_308 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_307, _T_312)
node _T_314 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_317 = cvt(_T_316)
node _T_318 = and(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = asSInt(_T_318)
node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0)))
node _T_321 = or(_T_315, _T_320)
node _T_322 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_323 = eq(_T_322, UInt<1>(0h0))
node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = or(_T_323, _T_328)
node _T_330 = and(_T_11, _T_24)
node _T_331 = and(_T_330, _T_37)
node _T_332 = and(_T_331, _T_50)
node _T_333 = and(_T_332, _T_63)
node _T_334 = and(_T_333, _T_76)
node _T_335 = and(_T_334, _T_89)
node _T_336 = and(_T_335, _T_102)
node _T_337 = and(_T_336, _T_115)
node _T_338 = and(_T_337, _T_128)
node _T_339 = and(_T_338, _T_141)
node _T_340 = and(_T_339, _T_154)
node _T_341 = and(_T_340, _T_167)
node _T_342 = and(_T_341, _T_180)
node _T_343 = and(_T_342, _T_193)
node _T_344 = and(_T_343, _T_206)
node _T_345 = and(_T_344, _T_219)
node _T_346 = and(_T_345, _T_232)
node _T_347 = and(_T_346, _T_245)
node _T_348 = and(_T_347, _T_258)
node _T_349 = and(_T_348, _T_271)
node _T_350 = and(_T_349, _T_284)
node _T_351 = and(_T_350, _T_297)
node _T_352 = and(_T_351, _T_305)
node _T_353 = and(_T_352, _T_313)
node _T_354 = and(_T_353, _T_321)
node _T_355 = and(_T_354, _T_329)
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_355, UInt<1>(0h1), "") : assert_1
node _T_359 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_359 :
node _T_360 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_361 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_362 = and(_T_360, _T_361)
node _T_363 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_364 = shr(io.in.a.bits.source, 2)
node _T_365 = eq(_T_364, UInt<7>(0h70))
node _T_366 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_367 = and(_T_365, _T_366)
node _T_368 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_369 = and(_T_367, _T_368)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_370 = shr(io.in.a.bits.source, 2)
node _T_371 = eq(_T_370, UInt<7>(0h71))
node _T_372 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_373 = and(_T_371, _T_372)
node _T_374 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_375 = and(_T_373, _T_374)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_376 = shr(io.in.a.bits.source, 2)
node _T_377 = eq(_T_376, UInt<7>(0h72))
node _T_378 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_379 = and(_T_377, _T_378)
node _T_380 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_381 = and(_T_379, _T_380)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_382 = shr(io.in.a.bits.source, 2)
node _T_383 = eq(_T_382, UInt<7>(0h73))
node _T_384 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_385 = and(_T_383, _T_384)
node _T_386 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_387 = and(_T_385, _T_386)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_388 = shr(io.in.a.bits.source, 2)
node _T_389 = eq(_T_388, UInt<7>(0h7c))
node _T_390 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_391 = and(_T_389, _T_390)
node _T_392 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_393 = and(_T_391, _T_392)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_394 = shr(io.in.a.bits.source, 2)
node _T_395 = eq(_T_394, UInt<7>(0h7b))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0)
node _T_400 = shr(io.in.a.bits.source, 5)
node _T_401 = eq(_T_400, UInt<4>(0hd))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_28, UInt<5>(0h1f))
node _T_405 = and(_T_403, _T_404)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0)
node _T_406 = shr(io.in.a.bits.source, 5)
node _T_407 = eq(_T_406, UInt<4>(0hc))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_29, UInt<5>(0h1f))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0)
node _T_412 = shr(io.in.a.bits.source, 5)
node _T_413 = eq(_T_412, UInt<4>(0hb))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_30, UInt<5>(0h1f))
node _T_417 = and(_T_415, _T_416)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0)
node _T_418 = shr(io.in.a.bits.source, 5)
node _T_419 = eq(_T_418, UInt<4>(0ha))
node _T_420 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_421 = and(_T_419, _T_420)
node _T_422 = leq(uncommonBits_31, UInt<5>(0h1f))
node _T_423 = and(_T_421, _T_422)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0)
node _T_424 = shr(io.in.a.bits.source, 5)
node _T_425 = eq(_T_424, UInt<4>(0h9))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_32, UInt<5>(0h1f))
node _T_429 = and(_T_427, _T_428)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0)
node _T_430 = shr(io.in.a.bits.source, 5)
node _T_431 = eq(_T_430, UInt<4>(0h8))
node _T_432 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_433 = and(_T_431, _T_432)
node _T_434 = leq(uncommonBits_33, UInt<5>(0h1f))
node _T_435 = and(_T_433, _T_434)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_436 = shr(io.in.a.bits.source, 2)
node _T_437 = eq(_T_436, UInt<7>(0h7a))
node _T_438 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_439 = and(_T_437, _T_438)
node _T_440 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_441 = and(_T_439, _T_440)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_442 = shr(io.in.a.bits.source, 2)
node _T_443 = eq(_T_442, UInt<7>(0h79))
node _T_444 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_445 = and(_T_443, _T_444)
node _T_446 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_447 = and(_T_445, _T_446)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0)
node _T_448 = shr(io.in.a.bits.source, 5)
node _T_449 = eq(_T_448, UInt<3>(0h7))
node _T_450 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_451 = and(_T_449, _T_450)
node _T_452 = leq(uncommonBits_36, UInt<5>(0h1f))
node _T_453 = and(_T_451, _T_452)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0)
node _T_454 = shr(io.in.a.bits.source, 5)
node _T_455 = eq(_T_454, UInt<3>(0h6))
node _T_456 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_457 = and(_T_455, _T_456)
node _T_458 = leq(uncommonBits_37, UInt<5>(0h1f))
node _T_459 = and(_T_457, _T_458)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0)
node _T_460 = shr(io.in.a.bits.source, 5)
node _T_461 = eq(_T_460, UInt<3>(0h5))
node _T_462 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_463 = and(_T_461, _T_462)
node _T_464 = leq(uncommonBits_38, UInt<5>(0h1f))
node _T_465 = and(_T_463, _T_464)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0)
node _T_466 = shr(io.in.a.bits.source, 5)
node _T_467 = eq(_T_466, UInt<3>(0h4))
node _T_468 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_469 = and(_T_467, _T_468)
node _T_470 = leq(uncommonBits_39, UInt<5>(0h1f))
node _T_471 = and(_T_469, _T_470)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0)
node _T_472 = shr(io.in.a.bits.source, 5)
node _T_473 = eq(_T_472, UInt<2>(0h3))
node _T_474 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_475 = and(_T_473, _T_474)
node _T_476 = leq(uncommonBits_40, UInt<5>(0h1f))
node _T_477 = and(_T_475, _T_476)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0)
node _T_478 = shr(io.in.a.bits.source, 5)
node _T_479 = eq(_T_478, UInt<2>(0h2))
node _T_480 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_481 = and(_T_479, _T_480)
node _T_482 = leq(uncommonBits_41, UInt<5>(0h1f))
node _T_483 = and(_T_481, _T_482)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0)
node _T_484 = shr(io.in.a.bits.source, 5)
node _T_485 = eq(_T_484, UInt<1>(0h1))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_42, UInt<5>(0h1f))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0)
node _T_490 = shr(io.in.a.bits.source, 5)
node _T_491 = eq(_T_490, UInt<1>(0h0))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_43, UInt<5>(0h1f))
node _T_495 = and(_T_493, _T_494)
node _T_496 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_497 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_498 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_499 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_500 = or(_T_363, _T_369)
node _T_501 = or(_T_500, _T_375)
node _T_502 = or(_T_501, _T_381)
node _T_503 = or(_T_502, _T_387)
node _T_504 = or(_T_503, _T_393)
node _T_505 = or(_T_504, _T_399)
node _T_506 = or(_T_505, _T_405)
node _T_507 = or(_T_506, _T_411)
node _T_508 = or(_T_507, _T_417)
node _T_509 = or(_T_508, _T_423)
node _T_510 = or(_T_509, _T_429)
node _T_511 = or(_T_510, _T_435)
node _T_512 = or(_T_511, _T_441)
node _T_513 = or(_T_512, _T_447)
node _T_514 = or(_T_513, _T_453)
node _T_515 = or(_T_514, _T_459)
node _T_516 = or(_T_515, _T_465)
node _T_517 = or(_T_516, _T_471)
node _T_518 = or(_T_517, _T_477)
node _T_519 = or(_T_518, _T_483)
node _T_520 = or(_T_519, _T_489)
node _T_521 = or(_T_520, _T_495)
node _T_522 = or(_T_521, _T_496)
node _T_523 = or(_T_522, _T_497)
node _T_524 = or(_T_523, _T_498)
node _T_525 = or(_T_524, _T_499)
node _T_526 = and(_T_362, _T_525)
node _T_527 = or(UInt<1>(0h0), _T_526)
node _T_528 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<13>(0h1000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = and(_T_528, _T_533)
node _T_535 = or(UInt<1>(0h0), _T_534)
node _T_536 = and(_T_527, _T_535)
node _T_537 = asUInt(reset)
node _T_538 = eq(_T_537, UInt<1>(0h0))
when _T_538 :
node _T_539 = eq(_T_536, UInt<1>(0h0))
when _T_539 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_536, UInt<1>(0h1), "") : assert_2
node _T_540 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_541 = shr(io.in.a.bits.source, 2)
node _T_542 = eq(_T_541, UInt<7>(0h70))
node _T_543 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_544 = and(_T_542, _T_543)
node _T_545 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_546 = and(_T_544, _T_545)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_547 = shr(io.in.a.bits.source, 2)
node _T_548 = eq(_T_547, UInt<7>(0h71))
node _T_549 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_550 = and(_T_548, _T_549)
node _T_551 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_552 = and(_T_550, _T_551)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_553 = shr(io.in.a.bits.source, 2)
node _T_554 = eq(_T_553, UInt<7>(0h72))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_558 = and(_T_556, _T_557)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_559 = shr(io.in.a.bits.source, 2)
node _T_560 = eq(_T_559, UInt<7>(0h73))
node _T_561 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_562 = and(_T_560, _T_561)
node _T_563 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_564 = and(_T_562, _T_563)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_565 = shr(io.in.a.bits.source, 2)
node _T_566 = eq(_T_565, UInt<7>(0h7c))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_571 = shr(io.in.a.bits.source, 2)
node _T_572 = eq(_T_571, UInt<7>(0h7b))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_576 = and(_T_574, _T_575)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0)
node _T_577 = shr(io.in.a.bits.source, 5)
node _T_578 = eq(_T_577, UInt<4>(0hd))
node _T_579 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_580 = and(_T_578, _T_579)
node _T_581 = leq(uncommonBits_50, UInt<5>(0h1f))
node _T_582 = and(_T_580, _T_581)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0)
node _T_583 = shr(io.in.a.bits.source, 5)
node _T_584 = eq(_T_583, UInt<4>(0hc))
node _T_585 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_586 = and(_T_584, _T_585)
node _T_587 = leq(uncommonBits_51, UInt<5>(0h1f))
node _T_588 = and(_T_586, _T_587)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0)
node _T_589 = shr(io.in.a.bits.source, 5)
node _T_590 = eq(_T_589, UInt<4>(0hb))
node _T_591 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_592 = and(_T_590, _T_591)
node _T_593 = leq(uncommonBits_52, UInt<5>(0h1f))
node _T_594 = and(_T_592, _T_593)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0)
node _T_595 = shr(io.in.a.bits.source, 5)
node _T_596 = eq(_T_595, UInt<4>(0ha))
node _T_597 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_598 = and(_T_596, _T_597)
node _T_599 = leq(uncommonBits_53, UInt<5>(0h1f))
node _T_600 = and(_T_598, _T_599)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0)
node _T_601 = shr(io.in.a.bits.source, 5)
node _T_602 = eq(_T_601, UInt<4>(0h9))
node _T_603 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_604 = and(_T_602, _T_603)
node _T_605 = leq(uncommonBits_54, UInt<5>(0h1f))
node _T_606 = and(_T_604, _T_605)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0)
node _T_607 = shr(io.in.a.bits.source, 5)
node _T_608 = eq(_T_607, UInt<4>(0h8))
node _T_609 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_610 = and(_T_608, _T_609)
node _T_611 = leq(uncommonBits_55, UInt<5>(0h1f))
node _T_612 = and(_T_610, _T_611)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_613 = shr(io.in.a.bits.source, 2)
node _T_614 = eq(_T_613, UInt<7>(0h7a))
node _T_615 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_616 = and(_T_614, _T_615)
node _T_617 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_618 = and(_T_616, _T_617)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_619 = shr(io.in.a.bits.source, 2)
node _T_620 = eq(_T_619, UInt<7>(0h79))
node _T_621 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_622 = and(_T_620, _T_621)
node _T_623 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_624 = and(_T_622, _T_623)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0)
node _T_625 = shr(io.in.a.bits.source, 5)
node _T_626 = eq(_T_625, UInt<3>(0h7))
node _T_627 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_628 = and(_T_626, _T_627)
node _T_629 = leq(uncommonBits_58, UInt<5>(0h1f))
node _T_630 = and(_T_628, _T_629)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0)
node _T_631 = shr(io.in.a.bits.source, 5)
node _T_632 = eq(_T_631, UInt<3>(0h6))
node _T_633 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_634 = and(_T_632, _T_633)
node _T_635 = leq(uncommonBits_59, UInt<5>(0h1f))
node _T_636 = and(_T_634, _T_635)
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0)
node _T_637 = shr(io.in.a.bits.source, 5)
node _T_638 = eq(_T_637, UInt<3>(0h5))
node _T_639 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_640 = and(_T_638, _T_639)
node _T_641 = leq(uncommonBits_60, UInt<5>(0h1f))
node _T_642 = and(_T_640, _T_641)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0)
node _T_643 = shr(io.in.a.bits.source, 5)
node _T_644 = eq(_T_643, UInt<3>(0h4))
node _T_645 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_646 = and(_T_644, _T_645)
node _T_647 = leq(uncommonBits_61, UInt<5>(0h1f))
node _T_648 = and(_T_646, _T_647)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0)
node _T_649 = shr(io.in.a.bits.source, 5)
node _T_650 = eq(_T_649, UInt<2>(0h3))
node _T_651 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_652 = and(_T_650, _T_651)
node _T_653 = leq(uncommonBits_62, UInt<5>(0h1f))
node _T_654 = and(_T_652, _T_653)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0)
node _T_655 = shr(io.in.a.bits.source, 5)
node _T_656 = eq(_T_655, UInt<2>(0h2))
node _T_657 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_658 = and(_T_656, _T_657)
node _T_659 = leq(uncommonBits_63, UInt<5>(0h1f))
node _T_660 = and(_T_658, _T_659)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0)
node _T_661 = shr(io.in.a.bits.source, 5)
node _T_662 = eq(_T_661, UInt<1>(0h1))
node _T_663 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_664 = and(_T_662, _T_663)
node _T_665 = leq(uncommonBits_64, UInt<5>(0h1f))
node _T_666 = and(_T_664, _T_665)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0)
node _T_667 = shr(io.in.a.bits.source, 5)
node _T_668 = eq(_T_667, UInt<1>(0h0))
node _T_669 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_670 = and(_T_668, _T_669)
node _T_671 = leq(uncommonBits_65, UInt<5>(0h1f))
node _T_672 = and(_T_670, _T_671)
node _T_673 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_674 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_675 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_676 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE : UInt<1>[27]
connect _WIRE[0], _T_540
connect _WIRE[1], _T_546
connect _WIRE[2], _T_552
connect _WIRE[3], _T_558
connect _WIRE[4], _T_564
connect _WIRE[5], _T_570
connect _WIRE[6], _T_576
connect _WIRE[7], _T_582
connect _WIRE[8], _T_588
connect _WIRE[9], _T_594
connect _WIRE[10], _T_600
connect _WIRE[11], _T_606
connect _WIRE[12], _T_612
connect _WIRE[13], _T_618
connect _WIRE[14], _T_624
connect _WIRE[15], _T_630
connect _WIRE[16], _T_636
connect _WIRE[17], _T_642
connect _WIRE[18], _T_648
connect _WIRE[19], _T_654
connect _WIRE[20], _T_660
connect _WIRE[21], _T_666
connect _WIRE[22], _T_672
connect _WIRE[23], _T_673
connect _WIRE[24], _T_674
connect _WIRE[25], _T_675
connect _WIRE[26], _T_676
node _T_677 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_678 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_679 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_680 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_681 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_682 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_683 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_684 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_685 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_686 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_687 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_688 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_689 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_690 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_691 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_692 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_693 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_694 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_695 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_696 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_697 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_698 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_699 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_700 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_701 = mux(_WIRE[23], _T_677, UInt<1>(0h0))
node _T_702 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_703 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = mux(_WIRE[26], UInt<1>(0h0), UInt<1>(0h0))
node _T_705 = or(_T_678, _T_679)
node _T_706 = or(_T_705, _T_680)
node _T_707 = or(_T_706, _T_681)
node _T_708 = or(_T_707, _T_682)
node _T_709 = or(_T_708, _T_683)
node _T_710 = or(_T_709, _T_684)
node _T_711 = or(_T_710, _T_685)
node _T_712 = or(_T_711, _T_686)
node _T_713 = or(_T_712, _T_687)
node _T_714 = or(_T_713, _T_688)
node _T_715 = or(_T_714, _T_689)
node _T_716 = or(_T_715, _T_690)
node _T_717 = or(_T_716, _T_691)
node _T_718 = or(_T_717, _T_692)
node _T_719 = or(_T_718, _T_693)
node _T_720 = or(_T_719, _T_694)
node _T_721 = or(_T_720, _T_695)
node _T_722 = or(_T_721, _T_696)
node _T_723 = or(_T_722, _T_697)
node _T_724 = or(_T_723, _T_698)
node _T_725 = or(_T_724, _T_699)
node _T_726 = or(_T_725, _T_700)
node _T_727 = or(_T_726, _T_701)
node _T_728 = or(_T_727, _T_702)
node _T_729 = or(_T_728, _T_703)
node _T_730 = or(_T_729, _T_704)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_730
node _T_731 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_732 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_733 = and(_T_731, _T_732)
node _T_734 = or(UInt<1>(0h0), _T_733)
node _T_735 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_736 = cvt(_T_735)
node _T_737 = and(_T_736, asSInt(UInt<13>(0h1000)))
node _T_738 = asSInt(_T_737)
node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0)))
node _T_740 = and(_T_734, _T_739)
node _T_741 = or(UInt<1>(0h0), _T_740)
node _T_742 = and(_WIRE_1, _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_742, UInt<1>(0h1), "") : assert_3
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(source_ok, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_749 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(_T_749, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_749, UInt<1>(0h1), "") : assert_5
node _T_753 = asUInt(reset)
node _T_754 = eq(_T_753, UInt<1>(0h0))
when _T_754 :
node _T_755 = eq(is_aligned, UInt<1>(0h0))
when _T_755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_756 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_757 = asUInt(reset)
node _T_758 = eq(_T_757, UInt<1>(0h0))
when _T_758 :
node _T_759 = eq(_T_756, UInt<1>(0h0))
when _T_759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_756, UInt<1>(0h1), "") : assert_7
node _T_760 = not(io.in.a.bits.mask)
node _T_761 = eq(_T_760, UInt<1>(0h0))
node _T_762 = asUInt(reset)
node _T_763 = eq(_T_762, UInt<1>(0h0))
when _T_763 :
node _T_764 = eq(_T_761, UInt<1>(0h0))
when _T_764 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_761, UInt<1>(0h1), "") : assert_8
node _T_765 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(_T_765, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_765, UInt<1>(0h1), "") : assert_9
node _T_769 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_769 :
node _T_770 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_771 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_772 = and(_T_770, _T_771)
node _T_773 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_774 = shr(io.in.a.bits.source, 2)
node _T_775 = eq(_T_774, UInt<7>(0h70))
node _T_776 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_777 = and(_T_775, _T_776)
node _T_778 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_779 = and(_T_777, _T_778)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0)
node _T_780 = shr(io.in.a.bits.source, 2)
node _T_781 = eq(_T_780, UInt<7>(0h71))
node _T_782 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_783 = and(_T_781, _T_782)
node _T_784 = leq(uncommonBits_67, UInt<2>(0h3))
node _T_785 = and(_T_783, _T_784)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0)
node _T_786 = shr(io.in.a.bits.source, 2)
node _T_787 = eq(_T_786, UInt<7>(0h72))
node _T_788 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_789 = and(_T_787, _T_788)
node _T_790 = leq(uncommonBits_68, UInt<2>(0h3))
node _T_791 = and(_T_789, _T_790)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0)
node _T_792 = shr(io.in.a.bits.source, 2)
node _T_793 = eq(_T_792, UInt<7>(0h73))
node _T_794 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_795 = and(_T_793, _T_794)
node _T_796 = leq(uncommonBits_69, UInt<2>(0h3))
node _T_797 = and(_T_795, _T_796)
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_798 = shr(io.in.a.bits.source, 2)
node _T_799 = eq(_T_798, UInt<7>(0h7c))
node _T_800 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_801 = and(_T_799, _T_800)
node _T_802 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_803 = and(_T_801, _T_802)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_804 = shr(io.in.a.bits.source, 2)
node _T_805 = eq(_T_804, UInt<7>(0h7b))
node _T_806 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_807 = and(_T_805, _T_806)
node _T_808 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_809 = and(_T_807, _T_808)
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 4, 0)
node _T_810 = shr(io.in.a.bits.source, 5)
node _T_811 = eq(_T_810, UInt<4>(0hd))
node _T_812 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_813 = and(_T_811, _T_812)
node _T_814 = leq(uncommonBits_72, UInt<5>(0h1f))
node _T_815 = and(_T_813, _T_814)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 4, 0)
node _T_816 = shr(io.in.a.bits.source, 5)
node _T_817 = eq(_T_816, UInt<4>(0hc))
node _T_818 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_819 = and(_T_817, _T_818)
node _T_820 = leq(uncommonBits_73, UInt<5>(0h1f))
node _T_821 = and(_T_819, _T_820)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 4, 0)
node _T_822 = shr(io.in.a.bits.source, 5)
node _T_823 = eq(_T_822, UInt<4>(0hb))
node _T_824 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_825 = and(_T_823, _T_824)
node _T_826 = leq(uncommonBits_74, UInt<5>(0h1f))
node _T_827 = and(_T_825, _T_826)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 4, 0)
node _T_828 = shr(io.in.a.bits.source, 5)
node _T_829 = eq(_T_828, UInt<4>(0ha))
node _T_830 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_831 = and(_T_829, _T_830)
node _T_832 = leq(uncommonBits_75, UInt<5>(0h1f))
node _T_833 = and(_T_831, _T_832)
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0)
node _T_834 = shr(io.in.a.bits.source, 5)
node _T_835 = eq(_T_834, UInt<4>(0h9))
node _T_836 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_837 = and(_T_835, _T_836)
node _T_838 = leq(uncommonBits_76, UInt<5>(0h1f))
node _T_839 = and(_T_837, _T_838)
node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0)
node _T_840 = shr(io.in.a.bits.source, 5)
node _T_841 = eq(_T_840, UInt<4>(0h8))
node _T_842 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_843 = and(_T_841, _T_842)
node _T_844 = leq(uncommonBits_77, UInt<5>(0h1f))
node _T_845 = and(_T_843, _T_844)
node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0)
node _T_846 = shr(io.in.a.bits.source, 2)
node _T_847 = eq(_T_846, UInt<7>(0h7a))
node _T_848 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_849 = and(_T_847, _T_848)
node _T_850 = leq(uncommonBits_78, UInt<2>(0h3))
node _T_851 = and(_T_849, _T_850)
node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 1, 0)
node _T_852 = shr(io.in.a.bits.source, 2)
node _T_853 = eq(_T_852, UInt<7>(0h79))
node _T_854 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_855 = and(_T_853, _T_854)
node _T_856 = leq(uncommonBits_79, UInt<2>(0h3))
node _T_857 = and(_T_855, _T_856)
node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0)
node _T_858 = shr(io.in.a.bits.source, 5)
node _T_859 = eq(_T_858, UInt<3>(0h7))
node _T_860 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_861 = and(_T_859, _T_860)
node _T_862 = leq(uncommonBits_80, UInt<5>(0h1f))
node _T_863 = and(_T_861, _T_862)
node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0)
node _T_864 = shr(io.in.a.bits.source, 5)
node _T_865 = eq(_T_864, UInt<3>(0h6))
node _T_866 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_867 = and(_T_865, _T_866)
node _T_868 = leq(uncommonBits_81, UInt<5>(0h1f))
node _T_869 = and(_T_867, _T_868)
node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0)
node _T_870 = shr(io.in.a.bits.source, 5)
node _T_871 = eq(_T_870, UInt<3>(0h5))
node _T_872 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_873 = and(_T_871, _T_872)
node _T_874 = leq(uncommonBits_82, UInt<5>(0h1f))
node _T_875 = and(_T_873, _T_874)
node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0)
node _T_876 = shr(io.in.a.bits.source, 5)
node _T_877 = eq(_T_876, UInt<3>(0h4))
node _T_878 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_879 = and(_T_877, _T_878)
node _T_880 = leq(uncommonBits_83, UInt<5>(0h1f))
node _T_881 = and(_T_879, _T_880)
node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 4, 0)
node _T_882 = shr(io.in.a.bits.source, 5)
node _T_883 = eq(_T_882, UInt<2>(0h3))
node _T_884 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_885 = and(_T_883, _T_884)
node _T_886 = leq(uncommonBits_84, UInt<5>(0h1f))
node _T_887 = and(_T_885, _T_886)
node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 4, 0)
node _T_888 = shr(io.in.a.bits.source, 5)
node _T_889 = eq(_T_888, UInt<2>(0h2))
node _T_890 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_891 = and(_T_889, _T_890)
node _T_892 = leq(uncommonBits_85, UInt<5>(0h1f))
node _T_893 = and(_T_891, _T_892)
node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 4, 0)
node _T_894 = shr(io.in.a.bits.source, 5)
node _T_895 = eq(_T_894, UInt<1>(0h1))
node _T_896 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_897 = and(_T_895, _T_896)
node _T_898 = leq(uncommonBits_86, UInt<5>(0h1f))
node _T_899 = and(_T_897, _T_898)
node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 4, 0)
node _T_900 = shr(io.in.a.bits.source, 5)
node _T_901 = eq(_T_900, UInt<1>(0h0))
node _T_902 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_903 = and(_T_901, _T_902)
node _T_904 = leq(uncommonBits_87, UInt<5>(0h1f))
node _T_905 = and(_T_903, _T_904)
node _T_906 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_907 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_908 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_909 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_910 = or(_T_773, _T_779)
node _T_911 = or(_T_910, _T_785)
node _T_912 = or(_T_911, _T_791)
node _T_913 = or(_T_912, _T_797)
node _T_914 = or(_T_913, _T_803)
node _T_915 = or(_T_914, _T_809)
node _T_916 = or(_T_915, _T_815)
node _T_917 = or(_T_916, _T_821)
node _T_918 = or(_T_917, _T_827)
node _T_919 = or(_T_918, _T_833)
node _T_920 = or(_T_919, _T_839)
node _T_921 = or(_T_920, _T_845)
node _T_922 = or(_T_921, _T_851)
node _T_923 = or(_T_922, _T_857)
node _T_924 = or(_T_923, _T_863)
node _T_925 = or(_T_924, _T_869)
node _T_926 = or(_T_925, _T_875)
node _T_927 = or(_T_926, _T_881)
node _T_928 = or(_T_927, _T_887)
node _T_929 = or(_T_928, _T_893)
node _T_930 = or(_T_929, _T_899)
node _T_931 = or(_T_930, _T_905)
node _T_932 = or(_T_931, _T_906)
node _T_933 = or(_T_932, _T_907)
node _T_934 = or(_T_933, _T_908)
node _T_935 = or(_T_934, _T_909)
node _T_936 = and(_T_772, _T_935)
node _T_937 = or(UInt<1>(0h0), _T_936)
node _T_938 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_939 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = and(_T_938, _T_943)
node _T_945 = or(UInt<1>(0h0), _T_944)
node _T_946 = and(_T_937, _T_945)
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_946, UInt<1>(0h1), "") : assert_10
node _T_950 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0)
node _T_951 = shr(io.in.a.bits.source, 2)
node _T_952 = eq(_T_951, UInt<7>(0h70))
node _T_953 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_954 = and(_T_952, _T_953)
node _T_955 = leq(uncommonBits_88, UInt<2>(0h3))
node _T_956 = and(_T_954, _T_955)
node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 1, 0)
node _T_957 = shr(io.in.a.bits.source, 2)
node _T_958 = eq(_T_957, UInt<7>(0h71))
node _T_959 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_960 = and(_T_958, _T_959)
node _T_961 = leq(uncommonBits_89, UInt<2>(0h3))
node _T_962 = and(_T_960, _T_961)
node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_90 = bits(_uncommonBits_T_90, 1, 0)
node _T_963 = shr(io.in.a.bits.source, 2)
node _T_964 = eq(_T_963, UInt<7>(0h72))
node _T_965 = leq(UInt<1>(0h0), uncommonBits_90)
node _T_966 = and(_T_964, _T_965)
node _T_967 = leq(uncommonBits_90, UInt<2>(0h3))
node _T_968 = and(_T_966, _T_967)
node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_91 = bits(_uncommonBits_T_91, 1, 0)
node _T_969 = shr(io.in.a.bits.source, 2)
node _T_970 = eq(_T_969, UInt<7>(0h73))
node _T_971 = leq(UInt<1>(0h0), uncommonBits_91)
node _T_972 = and(_T_970, _T_971)
node _T_973 = leq(uncommonBits_91, UInt<2>(0h3))
node _T_974 = and(_T_972, _T_973)
node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_92 = bits(_uncommonBits_T_92, 1, 0)
node _T_975 = shr(io.in.a.bits.source, 2)
node _T_976 = eq(_T_975, UInt<7>(0h7c))
node _T_977 = leq(UInt<1>(0h0), uncommonBits_92)
node _T_978 = and(_T_976, _T_977)
node _T_979 = leq(uncommonBits_92, UInt<2>(0h3))
node _T_980 = and(_T_978, _T_979)
node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_93 = bits(_uncommonBits_T_93, 1, 0)
node _T_981 = shr(io.in.a.bits.source, 2)
node _T_982 = eq(_T_981, UInt<7>(0h7b))
node _T_983 = leq(UInt<1>(0h0), uncommonBits_93)
node _T_984 = and(_T_982, _T_983)
node _T_985 = leq(uncommonBits_93, UInt<2>(0h3))
node _T_986 = and(_T_984, _T_985)
node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0)
node _T_987 = shr(io.in.a.bits.source, 5)
node _T_988 = eq(_T_987, UInt<4>(0hd))
node _T_989 = leq(UInt<1>(0h0), uncommonBits_94)
node _T_990 = and(_T_988, _T_989)
node _T_991 = leq(uncommonBits_94, UInt<5>(0h1f))
node _T_992 = and(_T_990, _T_991)
node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0)
node _T_993 = shr(io.in.a.bits.source, 5)
node _T_994 = eq(_T_993, UInt<4>(0hc))
node _T_995 = leq(UInt<1>(0h0), uncommonBits_95)
node _T_996 = and(_T_994, _T_995)
node _T_997 = leq(uncommonBits_95, UInt<5>(0h1f))
node _T_998 = and(_T_996, _T_997)
node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_96 = bits(_uncommonBits_T_96, 4, 0)
node _T_999 = shr(io.in.a.bits.source, 5)
node _T_1000 = eq(_T_999, UInt<4>(0hb))
node _T_1001 = leq(UInt<1>(0h0), uncommonBits_96)
node _T_1002 = and(_T_1000, _T_1001)
node _T_1003 = leq(uncommonBits_96, UInt<5>(0h1f))
node _T_1004 = and(_T_1002, _T_1003)
node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_97 = bits(_uncommonBits_T_97, 4, 0)
node _T_1005 = shr(io.in.a.bits.source, 5)
node _T_1006 = eq(_T_1005, UInt<4>(0ha))
node _T_1007 = leq(UInt<1>(0h0), uncommonBits_97)
node _T_1008 = and(_T_1006, _T_1007)
node _T_1009 = leq(uncommonBits_97, UInt<5>(0h1f))
node _T_1010 = and(_T_1008, _T_1009)
node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_98 = bits(_uncommonBits_T_98, 4, 0)
node _T_1011 = shr(io.in.a.bits.source, 5)
node _T_1012 = eq(_T_1011, UInt<4>(0h9))
node _T_1013 = leq(UInt<1>(0h0), uncommonBits_98)
node _T_1014 = and(_T_1012, _T_1013)
node _T_1015 = leq(uncommonBits_98, UInt<5>(0h1f))
node _T_1016 = and(_T_1014, _T_1015)
node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_99 = bits(_uncommonBits_T_99, 4, 0)
node _T_1017 = shr(io.in.a.bits.source, 5)
node _T_1018 = eq(_T_1017, UInt<4>(0h8))
node _T_1019 = leq(UInt<1>(0h0), uncommonBits_99)
node _T_1020 = and(_T_1018, _T_1019)
node _T_1021 = leq(uncommonBits_99, UInt<5>(0h1f))
node _T_1022 = and(_T_1020, _T_1021)
node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_100 = bits(_uncommonBits_T_100, 1, 0)
node _T_1023 = shr(io.in.a.bits.source, 2)
node _T_1024 = eq(_T_1023, UInt<7>(0h7a))
node _T_1025 = leq(UInt<1>(0h0), uncommonBits_100)
node _T_1026 = and(_T_1024, _T_1025)
node _T_1027 = leq(uncommonBits_100, UInt<2>(0h3))
node _T_1028 = and(_T_1026, _T_1027)
node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_101 = bits(_uncommonBits_T_101, 1, 0)
node _T_1029 = shr(io.in.a.bits.source, 2)
node _T_1030 = eq(_T_1029, UInt<7>(0h79))
node _T_1031 = leq(UInt<1>(0h0), uncommonBits_101)
node _T_1032 = and(_T_1030, _T_1031)
node _T_1033 = leq(uncommonBits_101, UInt<2>(0h3))
node _T_1034 = and(_T_1032, _T_1033)
node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0)
node _T_1035 = shr(io.in.a.bits.source, 5)
node _T_1036 = eq(_T_1035, UInt<3>(0h7))
node _T_1037 = leq(UInt<1>(0h0), uncommonBits_102)
node _T_1038 = and(_T_1036, _T_1037)
node _T_1039 = leq(uncommonBits_102, UInt<5>(0h1f))
node _T_1040 = and(_T_1038, _T_1039)
node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0)
node _T_1041 = shr(io.in.a.bits.source, 5)
node _T_1042 = eq(_T_1041, UInt<3>(0h6))
node _T_1043 = leq(UInt<1>(0h0), uncommonBits_103)
node _T_1044 = and(_T_1042, _T_1043)
node _T_1045 = leq(uncommonBits_103, UInt<5>(0h1f))
node _T_1046 = and(_T_1044, _T_1045)
node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0)
node _T_1047 = shr(io.in.a.bits.source, 5)
node _T_1048 = eq(_T_1047, UInt<3>(0h5))
node _T_1049 = leq(UInt<1>(0h0), uncommonBits_104)
node _T_1050 = and(_T_1048, _T_1049)
node _T_1051 = leq(uncommonBits_104, UInt<5>(0h1f))
node _T_1052 = and(_T_1050, _T_1051)
node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0)
node _T_1053 = shr(io.in.a.bits.source, 5)
node _T_1054 = eq(_T_1053, UInt<3>(0h4))
node _T_1055 = leq(UInt<1>(0h0), uncommonBits_105)
node _T_1056 = and(_T_1054, _T_1055)
node _T_1057 = leq(uncommonBits_105, UInt<5>(0h1f))
node _T_1058 = and(_T_1056, _T_1057)
node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0)
node _T_1059 = shr(io.in.a.bits.source, 5)
node _T_1060 = eq(_T_1059, UInt<2>(0h3))
node _T_1061 = leq(UInt<1>(0h0), uncommonBits_106)
node _T_1062 = and(_T_1060, _T_1061)
node _T_1063 = leq(uncommonBits_106, UInt<5>(0h1f))
node _T_1064 = and(_T_1062, _T_1063)
node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0)
node _T_1065 = shr(io.in.a.bits.source, 5)
node _T_1066 = eq(_T_1065, UInt<2>(0h2))
node _T_1067 = leq(UInt<1>(0h0), uncommonBits_107)
node _T_1068 = and(_T_1066, _T_1067)
node _T_1069 = leq(uncommonBits_107, UInt<5>(0h1f))
node _T_1070 = and(_T_1068, _T_1069)
node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_108 = bits(_uncommonBits_T_108, 4, 0)
node _T_1071 = shr(io.in.a.bits.source, 5)
node _T_1072 = eq(_T_1071, UInt<1>(0h1))
node _T_1073 = leq(UInt<1>(0h0), uncommonBits_108)
node _T_1074 = and(_T_1072, _T_1073)
node _T_1075 = leq(uncommonBits_108, UInt<5>(0h1f))
node _T_1076 = and(_T_1074, _T_1075)
node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_109 = bits(_uncommonBits_T_109, 4, 0)
node _T_1077 = shr(io.in.a.bits.source, 5)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
node _T_1079 = leq(UInt<1>(0h0), uncommonBits_109)
node _T_1080 = and(_T_1078, _T_1079)
node _T_1081 = leq(uncommonBits_109, UInt<5>(0h1f))
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_1084 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_1085 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_1086 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE_2 : UInt<1>[27]
connect _WIRE_2[0], _T_950
connect _WIRE_2[1], _T_956
connect _WIRE_2[2], _T_962
connect _WIRE_2[3], _T_968
connect _WIRE_2[4], _T_974
connect _WIRE_2[5], _T_980
connect _WIRE_2[6], _T_986
connect _WIRE_2[7], _T_992
connect _WIRE_2[8], _T_998
connect _WIRE_2[9], _T_1004
connect _WIRE_2[10], _T_1010
connect _WIRE_2[11], _T_1016
connect _WIRE_2[12], _T_1022
connect _WIRE_2[13], _T_1028
connect _WIRE_2[14], _T_1034
connect _WIRE_2[15], _T_1040
connect _WIRE_2[16], _T_1046
connect _WIRE_2[17], _T_1052
connect _WIRE_2[18], _T_1058
connect _WIRE_2[19], _T_1064
connect _WIRE_2[20], _T_1070
connect _WIRE_2[21], _T_1076
connect _WIRE_2[22], _T_1082
connect _WIRE_2[23], _T_1083
connect _WIRE_2[24], _T_1084
connect _WIRE_2[25], _T_1085
connect _WIRE_2[26], _T_1086
node _T_1087 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_1088 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1089 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1090 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1091 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1092 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1093 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1094 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1095 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1096 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_1097 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_1098 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_1099 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_1100 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_1101 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_1102 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_1103 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_1104 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_1105 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_1106 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_1107 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_1108 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0))
node _T_1109 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_1110 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_1111 = mux(_WIRE_2[23], _T_1087, UInt<1>(0h0))
node _T_1112 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_1113 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_1114 = mux(_WIRE_2[26], UInt<1>(0h0), UInt<1>(0h0))
node _T_1115 = or(_T_1088, _T_1089)
node _T_1116 = or(_T_1115, _T_1090)
node _T_1117 = or(_T_1116, _T_1091)
node _T_1118 = or(_T_1117, _T_1092)
node _T_1119 = or(_T_1118, _T_1093)
node _T_1120 = or(_T_1119, _T_1094)
node _T_1121 = or(_T_1120, _T_1095)
node _T_1122 = or(_T_1121, _T_1096)
node _T_1123 = or(_T_1122, _T_1097)
node _T_1124 = or(_T_1123, _T_1098)
node _T_1125 = or(_T_1124, _T_1099)
node _T_1126 = or(_T_1125, _T_1100)
node _T_1127 = or(_T_1126, _T_1101)
node _T_1128 = or(_T_1127, _T_1102)
node _T_1129 = or(_T_1128, _T_1103)
node _T_1130 = or(_T_1129, _T_1104)
node _T_1131 = or(_T_1130, _T_1105)
node _T_1132 = or(_T_1131, _T_1106)
node _T_1133 = or(_T_1132, _T_1107)
node _T_1134 = or(_T_1133, _T_1108)
node _T_1135 = or(_T_1134, _T_1109)
node _T_1136 = or(_T_1135, _T_1110)
node _T_1137 = or(_T_1136, _T_1111)
node _T_1138 = or(_T_1137, _T_1112)
node _T_1139 = or(_T_1138, _T_1113)
node _T_1140 = or(_T_1139, _T_1114)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_1140
node _T_1141 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1142 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1143 = and(_T_1141, _T_1142)
node _T_1144 = or(UInt<1>(0h0), _T_1143)
node _T_1145 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_1146 = cvt(_T_1145)
node _T_1147 = and(_T_1146, asSInt(UInt<13>(0h1000)))
node _T_1148 = asSInt(_T_1147)
node _T_1149 = eq(_T_1148, asSInt(UInt<1>(0h0)))
node _T_1150 = and(_T_1144, _T_1149)
node _T_1151 = or(UInt<1>(0h0), _T_1150)
node _T_1152 = and(_WIRE_3, _T_1151)
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_11
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(source_ok, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_1159 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_13
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(is_aligned, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_1166 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_15
node _T_1170 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_16
node _T_1174 = not(io.in.a.bits.mask)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_17
node _T_1179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1180 = asUInt(reset)
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
when _T_1181 :
node _T_1182 = eq(_T_1179, UInt<1>(0h0))
when _T_1182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_1179, UInt<1>(0h1), "") : assert_18
node _T_1183 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_1183 :
node _T_1184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1186 = and(_T_1184, _T_1185)
node _T_1187 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0)
node _T_1188 = shr(io.in.a.bits.source, 2)
node _T_1189 = eq(_T_1188, UInt<7>(0h70))
node _T_1190 = leq(UInt<1>(0h0), uncommonBits_110)
node _T_1191 = and(_T_1189, _T_1190)
node _T_1192 = leq(uncommonBits_110, UInt<2>(0h3))
node _T_1193 = and(_T_1191, _T_1192)
node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0)
node _T_1194 = shr(io.in.a.bits.source, 2)
node _T_1195 = eq(_T_1194, UInt<7>(0h71))
node _T_1196 = leq(UInt<1>(0h0), uncommonBits_111)
node _T_1197 = and(_T_1195, _T_1196)
node _T_1198 = leq(uncommonBits_111, UInt<2>(0h3))
node _T_1199 = and(_T_1197, _T_1198)
node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_112 = bits(_uncommonBits_T_112, 1, 0)
node _T_1200 = shr(io.in.a.bits.source, 2)
node _T_1201 = eq(_T_1200, UInt<7>(0h72))
node _T_1202 = leq(UInt<1>(0h0), uncommonBits_112)
node _T_1203 = and(_T_1201, _T_1202)
node _T_1204 = leq(uncommonBits_112, UInt<2>(0h3))
node _T_1205 = and(_T_1203, _T_1204)
node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_113 = bits(_uncommonBits_T_113, 1, 0)
node _T_1206 = shr(io.in.a.bits.source, 2)
node _T_1207 = eq(_T_1206, UInt<7>(0h73))
node _T_1208 = leq(UInt<1>(0h0), uncommonBits_113)
node _T_1209 = and(_T_1207, _T_1208)
node _T_1210 = leq(uncommonBits_113, UInt<2>(0h3))
node _T_1211 = and(_T_1209, _T_1210)
node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_114 = bits(_uncommonBits_T_114, 1, 0)
node _T_1212 = shr(io.in.a.bits.source, 2)
node _T_1213 = eq(_T_1212, UInt<7>(0h7c))
node _T_1214 = leq(UInt<1>(0h0), uncommonBits_114)
node _T_1215 = and(_T_1213, _T_1214)
node _T_1216 = leq(uncommonBits_114, UInt<2>(0h3))
node _T_1217 = and(_T_1215, _T_1216)
node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_115 = bits(_uncommonBits_T_115, 1, 0)
node _T_1218 = shr(io.in.a.bits.source, 2)
node _T_1219 = eq(_T_1218, UInt<7>(0h7b))
node _T_1220 = leq(UInt<1>(0h0), uncommonBits_115)
node _T_1221 = and(_T_1219, _T_1220)
node _T_1222 = leq(uncommonBits_115, UInt<2>(0h3))
node _T_1223 = and(_T_1221, _T_1222)
node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0)
node _T_1224 = shr(io.in.a.bits.source, 5)
node _T_1225 = eq(_T_1224, UInt<4>(0hd))
node _T_1226 = leq(UInt<1>(0h0), uncommonBits_116)
node _T_1227 = and(_T_1225, _T_1226)
node _T_1228 = leq(uncommonBits_116, UInt<5>(0h1f))
node _T_1229 = and(_T_1227, _T_1228)
node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0)
node _T_1230 = shr(io.in.a.bits.source, 5)
node _T_1231 = eq(_T_1230, UInt<4>(0hc))
node _T_1232 = leq(UInt<1>(0h0), uncommonBits_117)
node _T_1233 = and(_T_1231, _T_1232)
node _T_1234 = leq(uncommonBits_117, UInt<5>(0h1f))
node _T_1235 = and(_T_1233, _T_1234)
node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0)
node _T_1236 = shr(io.in.a.bits.source, 5)
node _T_1237 = eq(_T_1236, UInt<4>(0hb))
node _T_1238 = leq(UInt<1>(0h0), uncommonBits_118)
node _T_1239 = and(_T_1237, _T_1238)
node _T_1240 = leq(uncommonBits_118, UInt<5>(0h1f))
node _T_1241 = and(_T_1239, _T_1240)
node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0)
node _T_1242 = shr(io.in.a.bits.source, 5)
node _T_1243 = eq(_T_1242, UInt<4>(0ha))
node _T_1244 = leq(UInt<1>(0h0), uncommonBits_119)
node _T_1245 = and(_T_1243, _T_1244)
node _T_1246 = leq(uncommonBits_119, UInt<5>(0h1f))
node _T_1247 = and(_T_1245, _T_1246)
node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_120 = bits(_uncommonBits_T_120, 4, 0)
node _T_1248 = shr(io.in.a.bits.source, 5)
node _T_1249 = eq(_T_1248, UInt<4>(0h9))
node _T_1250 = leq(UInt<1>(0h0), uncommonBits_120)
node _T_1251 = and(_T_1249, _T_1250)
node _T_1252 = leq(uncommonBits_120, UInt<5>(0h1f))
node _T_1253 = and(_T_1251, _T_1252)
node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_121 = bits(_uncommonBits_T_121, 4, 0)
node _T_1254 = shr(io.in.a.bits.source, 5)
node _T_1255 = eq(_T_1254, UInt<4>(0h8))
node _T_1256 = leq(UInt<1>(0h0), uncommonBits_121)
node _T_1257 = and(_T_1255, _T_1256)
node _T_1258 = leq(uncommonBits_121, UInt<5>(0h1f))
node _T_1259 = and(_T_1257, _T_1258)
node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0)
node _T_1260 = shr(io.in.a.bits.source, 2)
node _T_1261 = eq(_T_1260, UInt<7>(0h7a))
node _T_1262 = leq(UInt<1>(0h0), uncommonBits_122)
node _T_1263 = and(_T_1261, _T_1262)
node _T_1264 = leq(uncommonBits_122, UInt<2>(0h3))
node _T_1265 = and(_T_1263, _T_1264)
node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0)
node _T_1266 = shr(io.in.a.bits.source, 2)
node _T_1267 = eq(_T_1266, UInt<7>(0h79))
node _T_1268 = leq(UInt<1>(0h0), uncommonBits_123)
node _T_1269 = and(_T_1267, _T_1268)
node _T_1270 = leq(uncommonBits_123, UInt<2>(0h3))
node _T_1271 = and(_T_1269, _T_1270)
node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0)
node _T_1272 = shr(io.in.a.bits.source, 5)
node _T_1273 = eq(_T_1272, UInt<3>(0h7))
node _T_1274 = leq(UInt<1>(0h0), uncommonBits_124)
node _T_1275 = and(_T_1273, _T_1274)
node _T_1276 = leq(uncommonBits_124, UInt<5>(0h1f))
node _T_1277 = and(_T_1275, _T_1276)
node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0)
node _T_1278 = shr(io.in.a.bits.source, 5)
node _T_1279 = eq(_T_1278, UInt<3>(0h6))
node _T_1280 = leq(UInt<1>(0h0), uncommonBits_125)
node _T_1281 = and(_T_1279, _T_1280)
node _T_1282 = leq(uncommonBits_125, UInt<5>(0h1f))
node _T_1283 = and(_T_1281, _T_1282)
node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0)
node _T_1284 = shr(io.in.a.bits.source, 5)
node _T_1285 = eq(_T_1284, UInt<3>(0h5))
node _T_1286 = leq(UInt<1>(0h0), uncommonBits_126)
node _T_1287 = and(_T_1285, _T_1286)
node _T_1288 = leq(uncommonBits_126, UInt<5>(0h1f))
node _T_1289 = and(_T_1287, _T_1288)
node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0)
node _T_1290 = shr(io.in.a.bits.source, 5)
node _T_1291 = eq(_T_1290, UInt<3>(0h4))
node _T_1292 = leq(UInt<1>(0h0), uncommonBits_127)
node _T_1293 = and(_T_1291, _T_1292)
node _T_1294 = leq(uncommonBits_127, UInt<5>(0h1f))
node _T_1295 = and(_T_1293, _T_1294)
node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0)
node _T_1296 = shr(io.in.a.bits.source, 5)
node _T_1297 = eq(_T_1296, UInt<2>(0h3))
node _T_1298 = leq(UInt<1>(0h0), uncommonBits_128)
node _T_1299 = and(_T_1297, _T_1298)
node _T_1300 = leq(uncommonBits_128, UInt<5>(0h1f))
node _T_1301 = and(_T_1299, _T_1300)
node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0)
node _T_1302 = shr(io.in.a.bits.source, 5)
node _T_1303 = eq(_T_1302, UInt<2>(0h2))
node _T_1304 = leq(UInt<1>(0h0), uncommonBits_129)
node _T_1305 = and(_T_1303, _T_1304)
node _T_1306 = leq(uncommonBits_129, UInt<5>(0h1f))
node _T_1307 = and(_T_1305, _T_1306)
node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0)
node _T_1308 = shr(io.in.a.bits.source, 5)
node _T_1309 = eq(_T_1308, UInt<1>(0h1))
node _T_1310 = leq(UInt<1>(0h0), uncommonBits_130)
node _T_1311 = and(_T_1309, _T_1310)
node _T_1312 = leq(uncommonBits_130, UInt<5>(0h1f))
node _T_1313 = and(_T_1311, _T_1312)
node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0)
node _T_1314 = shr(io.in.a.bits.source, 5)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
node _T_1316 = leq(UInt<1>(0h0), uncommonBits_131)
node _T_1317 = and(_T_1315, _T_1316)
node _T_1318 = leq(uncommonBits_131, UInt<5>(0h1f))
node _T_1319 = and(_T_1317, _T_1318)
node _T_1320 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_1321 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_1322 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_1323 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1324 = or(_T_1187, _T_1193)
node _T_1325 = or(_T_1324, _T_1199)
node _T_1326 = or(_T_1325, _T_1205)
node _T_1327 = or(_T_1326, _T_1211)
node _T_1328 = or(_T_1327, _T_1217)
node _T_1329 = or(_T_1328, _T_1223)
node _T_1330 = or(_T_1329, _T_1229)
node _T_1331 = or(_T_1330, _T_1235)
node _T_1332 = or(_T_1331, _T_1241)
node _T_1333 = or(_T_1332, _T_1247)
node _T_1334 = or(_T_1333, _T_1253)
node _T_1335 = or(_T_1334, _T_1259)
node _T_1336 = or(_T_1335, _T_1265)
node _T_1337 = or(_T_1336, _T_1271)
node _T_1338 = or(_T_1337, _T_1277)
node _T_1339 = or(_T_1338, _T_1283)
node _T_1340 = or(_T_1339, _T_1289)
node _T_1341 = or(_T_1340, _T_1295)
node _T_1342 = or(_T_1341, _T_1301)
node _T_1343 = or(_T_1342, _T_1307)
node _T_1344 = or(_T_1343, _T_1313)
node _T_1345 = or(_T_1344, _T_1319)
node _T_1346 = or(_T_1345, _T_1320)
node _T_1347 = or(_T_1346, _T_1321)
node _T_1348 = or(_T_1347, _T_1322)
node _T_1349 = or(_T_1348, _T_1323)
node _T_1350 = and(_T_1186, _T_1349)
node _T_1351 = or(UInt<1>(0h0), _T_1350)
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_19
node _T_1355 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1356 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1357 = and(_T_1355, _T_1356)
node _T_1358 = or(UInt<1>(0h0), _T_1357)
node _T_1359 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_1360 = cvt(_T_1359)
node _T_1361 = and(_T_1360, asSInt(UInt<13>(0h1000)))
node _T_1362 = asSInt(_T_1361)
node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0)))
node _T_1364 = and(_T_1358, _T_1363)
node _T_1365 = or(UInt<1>(0h0), _T_1364)
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_20
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(source_ok, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(is_aligned, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_1375 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_23
node _T_1379 = eq(io.in.a.bits.mask, mask)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_24
node _T_1383 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_25
node _T_1387 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1389 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1390 = and(_T_1388, _T_1389)
node _T_1391 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_132 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_132 = bits(_uncommonBits_T_132, 1, 0)
node _T_1392 = shr(io.in.a.bits.source, 2)
node _T_1393 = eq(_T_1392, UInt<7>(0h70))
node _T_1394 = leq(UInt<1>(0h0), uncommonBits_132)
node _T_1395 = and(_T_1393, _T_1394)
node _T_1396 = leq(uncommonBits_132, UInt<2>(0h3))
node _T_1397 = and(_T_1395, _T_1396)
node _uncommonBits_T_133 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_133 = bits(_uncommonBits_T_133, 1, 0)
node _T_1398 = shr(io.in.a.bits.source, 2)
node _T_1399 = eq(_T_1398, UInt<7>(0h71))
node _T_1400 = leq(UInt<1>(0h0), uncommonBits_133)
node _T_1401 = and(_T_1399, _T_1400)
node _T_1402 = leq(uncommonBits_133, UInt<2>(0h3))
node _T_1403 = and(_T_1401, _T_1402)
node _uncommonBits_T_134 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_134 = bits(_uncommonBits_T_134, 1, 0)
node _T_1404 = shr(io.in.a.bits.source, 2)
node _T_1405 = eq(_T_1404, UInt<7>(0h72))
node _T_1406 = leq(UInt<1>(0h0), uncommonBits_134)
node _T_1407 = and(_T_1405, _T_1406)
node _T_1408 = leq(uncommonBits_134, UInt<2>(0h3))
node _T_1409 = and(_T_1407, _T_1408)
node _uncommonBits_T_135 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_135 = bits(_uncommonBits_T_135, 1, 0)
node _T_1410 = shr(io.in.a.bits.source, 2)
node _T_1411 = eq(_T_1410, UInt<7>(0h73))
node _T_1412 = leq(UInt<1>(0h0), uncommonBits_135)
node _T_1413 = and(_T_1411, _T_1412)
node _T_1414 = leq(uncommonBits_135, UInt<2>(0h3))
node _T_1415 = and(_T_1413, _T_1414)
node _uncommonBits_T_136 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_136 = bits(_uncommonBits_T_136, 1, 0)
node _T_1416 = shr(io.in.a.bits.source, 2)
node _T_1417 = eq(_T_1416, UInt<7>(0h7c))
node _T_1418 = leq(UInt<1>(0h0), uncommonBits_136)
node _T_1419 = and(_T_1417, _T_1418)
node _T_1420 = leq(uncommonBits_136, UInt<2>(0h3))
node _T_1421 = and(_T_1419, _T_1420)
node _uncommonBits_T_137 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_137 = bits(_uncommonBits_T_137, 1, 0)
node _T_1422 = shr(io.in.a.bits.source, 2)
node _T_1423 = eq(_T_1422, UInt<7>(0h7b))
node _T_1424 = leq(UInt<1>(0h0), uncommonBits_137)
node _T_1425 = and(_T_1423, _T_1424)
node _T_1426 = leq(uncommonBits_137, UInt<2>(0h3))
node _T_1427 = and(_T_1425, _T_1426)
node _uncommonBits_T_138 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_138 = bits(_uncommonBits_T_138, 4, 0)
node _T_1428 = shr(io.in.a.bits.source, 5)
node _T_1429 = eq(_T_1428, UInt<4>(0hd))
node _T_1430 = leq(UInt<1>(0h0), uncommonBits_138)
node _T_1431 = and(_T_1429, _T_1430)
node _T_1432 = leq(uncommonBits_138, UInt<5>(0h1f))
node _T_1433 = and(_T_1431, _T_1432)
node _uncommonBits_T_139 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_139 = bits(_uncommonBits_T_139, 4, 0)
node _T_1434 = shr(io.in.a.bits.source, 5)
node _T_1435 = eq(_T_1434, UInt<4>(0hc))
node _T_1436 = leq(UInt<1>(0h0), uncommonBits_139)
node _T_1437 = and(_T_1435, _T_1436)
node _T_1438 = leq(uncommonBits_139, UInt<5>(0h1f))
node _T_1439 = and(_T_1437, _T_1438)
node _uncommonBits_T_140 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_140 = bits(_uncommonBits_T_140, 4, 0)
node _T_1440 = shr(io.in.a.bits.source, 5)
node _T_1441 = eq(_T_1440, UInt<4>(0hb))
node _T_1442 = leq(UInt<1>(0h0), uncommonBits_140)
node _T_1443 = and(_T_1441, _T_1442)
node _T_1444 = leq(uncommonBits_140, UInt<5>(0h1f))
node _T_1445 = and(_T_1443, _T_1444)
node _uncommonBits_T_141 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_141 = bits(_uncommonBits_T_141, 4, 0)
node _T_1446 = shr(io.in.a.bits.source, 5)
node _T_1447 = eq(_T_1446, UInt<4>(0ha))
node _T_1448 = leq(UInt<1>(0h0), uncommonBits_141)
node _T_1449 = and(_T_1447, _T_1448)
node _T_1450 = leq(uncommonBits_141, UInt<5>(0h1f))
node _T_1451 = and(_T_1449, _T_1450)
node _uncommonBits_T_142 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_142 = bits(_uncommonBits_T_142, 4, 0)
node _T_1452 = shr(io.in.a.bits.source, 5)
node _T_1453 = eq(_T_1452, UInt<4>(0h9))
node _T_1454 = leq(UInt<1>(0h0), uncommonBits_142)
node _T_1455 = and(_T_1453, _T_1454)
node _T_1456 = leq(uncommonBits_142, UInt<5>(0h1f))
node _T_1457 = and(_T_1455, _T_1456)
node _uncommonBits_T_143 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_143 = bits(_uncommonBits_T_143, 4, 0)
node _T_1458 = shr(io.in.a.bits.source, 5)
node _T_1459 = eq(_T_1458, UInt<4>(0h8))
node _T_1460 = leq(UInt<1>(0h0), uncommonBits_143)
node _T_1461 = and(_T_1459, _T_1460)
node _T_1462 = leq(uncommonBits_143, UInt<5>(0h1f))
node _T_1463 = and(_T_1461, _T_1462)
node _uncommonBits_T_144 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_144 = bits(_uncommonBits_T_144, 1, 0)
node _T_1464 = shr(io.in.a.bits.source, 2)
node _T_1465 = eq(_T_1464, UInt<7>(0h7a))
node _T_1466 = leq(UInt<1>(0h0), uncommonBits_144)
node _T_1467 = and(_T_1465, _T_1466)
node _T_1468 = leq(uncommonBits_144, UInt<2>(0h3))
node _T_1469 = and(_T_1467, _T_1468)
node _uncommonBits_T_145 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_145 = bits(_uncommonBits_T_145, 1, 0)
node _T_1470 = shr(io.in.a.bits.source, 2)
node _T_1471 = eq(_T_1470, UInt<7>(0h79))
node _T_1472 = leq(UInt<1>(0h0), uncommonBits_145)
node _T_1473 = and(_T_1471, _T_1472)
node _T_1474 = leq(uncommonBits_145, UInt<2>(0h3))
node _T_1475 = and(_T_1473, _T_1474)
node _uncommonBits_T_146 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_146 = bits(_uncommonBits_T_146, 4, 0)
node _T_1476 = shr(io.in.a.bits.source, 5)
node _T_1477 = eq(_T_1476, UInt<3>(0h7))
node _T_1478 = leq(UInt<1>(0h0), uncommonBits_146)
node _T_1479 = and(_T_1477, _T_1478)
node _T_1480 = leq(uncommonBits_146, UInt<5>(0h1f))
node _T_1481 = and(_T_1479, _T_1480)
node _uncommonBits_T_147 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_147 = bits(_uncommonBits_T_147, 4, 0)
node _T_1482 = shr(io.in.a.bits.source, 5)
node _T_1483 = eq(_T_1482, UInt<3>(0h6))
node _T_1484 = leq(UInt<1>(0h0), uncommonBits_147)
node _T_1485 = and(_T_1483, _T_1484)
node _T_1486 = leq(uncommonBits_147, UInt<5>(0h1f))
node _T_1487 = and(_T_1485, _T_1486)
node _uncommonBits_T_148 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_148 = bits(_uncommonBits_T_148, 4, 0)
node _T_1488 = shr(io.in.a.bits.source, 5)
node _T_1489 = eq(_T_1488, UInt<3>(0h5))
node _T_1490 = leq(UInt<1>(0h0), uncommonBits_148)
node _T_1491 = and(_T_1489, _T_1490)
node _T_1492 = leq(uncommonBits_148, UInt<5>(0h1f))
node _T_1493 = and(_T_1491, _T_1492)
node _uncommonBits_T_149 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_149 = bits(_uncommonBits_T_149, 4, 0)
node _T_1494 = shr(io.in.a.bits.source, 5)
node _T_1495 = eq(_T_1494, UInt<3>(0h4))
node _T_1496 = leq(UInt<1>(0h0), uncommonBits_149)
node _T_1497 = and(_T_1495, _T_1496)
node _T_1498 = leq(uncommonBits_149, UInt<5>(0h1f))
node _T_1499 = and(_T_1497, _T_1498)
node _uncommonBits_T_150 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_150 = bits(_uncommonBits_T_150, 4, 0)
node _T_1500 = shr(io.in.a.bits.source, 5)
node _T_1501 = eq(_T_1500, UInt<2>(0h3))
node _T_1502 = leq(UInt<1>(0h0), uncommonBits_150)
node _T_1503 = and(_T_1501, _T_1502)
node _T_1504 = leq(uncommonBits_150, UInt<5>(0h1f))
node _T_1505 = and(_T_1503, _T_1504)
node _uncommonBits_T_151 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_151 = bits(_uncommonBits_T_151, 4, 0)
node _T_1506 = shr(io.in.a.bits.source, 5)
node _T_1507 = eq(_T_1506, UInt<2>(0h2))
node _T_1508 = leq(UInt<1>(0h0), uncommonBits_151)
node _T_1509 = and(_T_1507, _T_1508)
node _T_1510 = leq(uncommonBits_151, UInt<5>(0h1f))
node _T_1511 = and(_T_1509, _T_1510)
node _uncommonBits_T_152 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_152 = bits(_uncommonBits_T_152, 4, 0)
node _T_1512 = shr(io.in.a.bits.source, 5)
node _T_1513 = eq(_T_1512, UInt<1>(0h1))
node _T_1514 = leq(UInt<1>(0h0), uncommonBits_152)
node _T_1515 = and(_T_1513, _T_1514)
node _T_1516 = leq(uncommonBits_152, UInt<5>(0h1f))
node _T_1517 = and(_T_1515, _T_1516)
node _uncommonBits_T_153 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_153 = bits(_uncommonBits_T_153, 4, 0)
node _T_1518 = shr(io.in.a.bits.source, 5)
node _T_1519 = eq(_T_1518, UInt<1>(0h0))
node _T_1520 = leq(UInt<1>(0h0), uncommonBits_153)
node _T_1521 = and(_T_1519, _T_1520)
node _T_1522 = leq(uncommonBits_153, UInt<5>(0h1f))
node _T_1523 = and(_T_1521, _T_1522)
node _T_1524 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_1525 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_1526 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_1527 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1528 = or(_T_1391, _T_1397)
node _T_1529 = or(_T_1528, _T_1403)
node _T_1530 = or(_T_1529, _T_1409)
node _T_1531 = or(_T_1530, _T_1415)
node _T_1532 = or(_T_1531, _T_1421)
node _T_1533 = or(_T_1532, _T_1427)
node _T_1534 = or(_T_1533, _T_1433)
node _T_1535 = or(_T_1534, _T_1439)
node _T_1536 = or(_T_1535, _T_1445)
node _T_1537 = or(_T_1536, _T_1451)
node _T_1538 = or(_T_1537, _T_1457)
node _T_1539 = or(_T_1538, _T_1463)
node _T_1540 = or(_T_1539, _T_1469)
node _T_1541 = or(_T_1540, _T_1475)
node _T_1542 = or(_T_1541, _T_1481)
node _T_1543 = or(_T_1542, _T_1487)
node _T_1544 = or(_T_1543, _T_1493)
node _T_1545 = or(_T_1544, _T_1499)
node _T_1546 = or(_T_1545, _T_1505)
node _T_1547 = or(_T_1546, _T_1511)
node _T_1548 = or(_T_1547, _T_1517)
node _T_1549 = or(_T_1548, _T_1523)
node _T_1550 = or(_T_1549, _T_1524)
node _T_1551 = or(_T_1550, _T_1525)
node _T_1552 = or(_T_1551, _T_1526)
node _T_1553 = or(_T_1552, _T_1527)
node _T_1554 = and(_T_1390, _T_1553)
node _T_1555 = or(UInt<1>(0h0), _T_1554)
node _T_1556 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1557 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1558 = and(_T_1556, _T_1557)
node _T_1559 = or(UInt<1>(0h0), _T_1558)
node _T_1560 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_1561 = cvt(_T_1560)
node _T_1562 = and(_T_1561, asSInt(UInt<13>(0h1000)))
node _T_1563 = asSInt(_T_1562)
node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0)))
node _T_1565 = and(_T_1559, _T_1564)
node _T_1566 = or(UInt<1>(0h0), _T_1565)
node _T_1567 = and(_T_1555, _T_1566)
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(_T_1567, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1567, UInt<1>(0h1), "") : assert_26
node _T_1571 = asUInt(reset)
node _T_1572 = eq(_T_1571, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = eq(source_ok, UInt<1>(0h0))
when _T_1573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1574 = asUInt(reset)
node _T_1575 = eq(_T_1574, UInt<1>(0h0))
when _T_1575 :
node _T_1576 = eq(is_aligned, UInt<1>(0h0))
when _T_1576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1577 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1578 = asUInt(reset)
node _T_1579 = eq(_T_1578, UInt<1>(0h0))
when _T_1579 :
node _T_1580 = eq(_T_1577, UInt<1>(0h0))
when _T_1580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1577, UInt<1>(0h1), "") : assert_29
node _T_1581 = eq(io.in.a.bits.mask, mask)
node _T_1582 = asUInt(reset)
node _T_1583 = eq(_T_1582, UInt<1>(0h0))
when _T_1583 :
node _T_1584 = eq(_T_1581, UInt<1>(0h0))
when _T_1584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1581, UInt<1>(0h1), "") : assert_30
node _T_1585 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1585 :
node _T_1586 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1587 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1588 = and(_T_1586, _T_1587)
node _T_1589 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_154 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_154 = bits(_uncommonBits_T_154, 1, 0)
node _T_1590 = shr(io.in.a.bits.source, 2)
node _T_1591 = eq(_T_1590, UInt<7>(0h70))
node _T_1592 = leq(UInt<1>(0h0), uncommonBits_154)
node _T_1593 = and(_T_1591, _T_1592)
node _T_1594 = leq(uncommonBits_154, UInt<2>(0h3))
node _T_1595 = and(_T_1593, _T_1594)
node _uncommonBits_T_155 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_155 = bits(_uncommonBits_T_155, 1, 0)
node _T_1596 = shr(io.in.a.bits.source, 2)
node _T_1597 = eq(_T_1596, UInt<7>(0h71))
node _T_1598 = leq(UInt<1>(0h0), uncommonBits_155)
node _T_1599 = and(_T_1597, _T_1598)
node _T_1600 = leq(uncommonBits_155, UInt<2>(0h3))
node _T_1601 = and(_T_1599, _T_1600)
node _uncommonBits_T_156 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_156 = bits(_uncommonBits_T_156, 1, 0)
node _T_1602 = shr(io.in.a.bits.source, 2)
node _T_1603 = eq(_T_1602, UInt<7>(0h72))
node _T_1604 = leq(UInt<1>(0h0), uncommonBits_156)
node _T_1605 = and(_T_1603, _T_1604)
node _T_1606 = leq(uncommonBits_156, UInt<2>(0h3))
node _T_1607 = and(_T_1605, _T_1606)
node _uncommonBits_T_157 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_157 = bits(_uncommonBits_T_157, 1, 0)
node _T_1608 = shr(io.in.a.bits.source, 2)
node _T_1609 = eq(_T_1608, UInt<7>(0h73))
node _T_1610 = leq(UInt<1>(0h0), uncommonBits_157)
node _T_1611 = and(_T_1609, _T_1610)
node _T_1612 = leq(uncommonBits_157, UInt<2>(0h3))
node _T_1613 = and(_T_1611, _T_1612)
node _uncommonBits_T_158 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_158 = bits(_uncommonBits_T_158, 1, 0)
node _T_1614 = shr(io.in.a.bits.source, 2)
node _T_1615 = eq(_T_1614, UInt<7>(0h7c))
node _T_1616 = leq(UInt<1>(0h0), uncommonBits_158)
node _T_1617 = and(_T_1615, _T_1616)
node _T_1618 = leq(uncommonBits_158, UInt<2>(0h3))
node _T_1619 = and(_T_1617, _T_1618)
node _uncommonBits_T_159 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_159 = bits(_uncommonBits_T_159, 1, 0)
node _T_1620 = shr(io.in.a.bits.source, 2)
node _T_1621 = eq(_T_1620, UInt<7>(0h7b))
node _T_1622 = leq(UInt<1>(0h0), uncommonBits_159)
node _T_1623 = and(_T_1621, _T_1622)
node _T_1624 = leq(uncommonBits_159, UInt<2>(0h3))
node _T_1625 = and(_T_1623, _T_1624)
node _uncommonBits_T_160 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_160 = bits(_uncommonBits_T_160, 4, 0)
node _T_1626 = shr(io.in.a.bits.source, 5)
node _T_1627 = eq(_T_1626, UInt<4>(0hd))
node _T_1628 = leq(UInt<1>(0h0), uncommonBits_160)
node _T_1629 = and(_T_1627, _T_1628)
node _T_1630 = leq(uncommonBits_160, UInt<5>(0h1f))
node _T_1631 = and(_T_1629, _T_1630)
node _uncommonBits_T_161 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_161 = bits(_uncommonBits_T_161, 4, 0)
node _T_1632 = shr(io.in.a.bits.source, 5)
node _T_1633 = eq(_T_1632, UInt<4>(0hc))
node _T_1634 = leq(UInt<1>(0h0), uncommonBits_161)
node _T_1635 = and(_T_1633, _T_1634)
node _T_1636 = leq(uncommonBits_161, UInt<5>(0h1f))
node _T_1637 = and(_T_1635, _T_1636)
node _uncommonBits_T_162 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_162 = bits(_uncommonBits_T_162, 4, 0)
node _T_1638 = shr(io.in.a.bits.source, 5)
node _T_1639 = eq(_T_1638, UInt<4>(0hb))
node _T_1640 = leq(UInt<1>(0h0), uncommonBits_162)
node _T_1641 = and(_T_1639, _T_1640)
node _T_1642 = leq(uncommonBits_162, UInt<5>(0h1f))
node _T_1643 = and(_T_1641, _T_1642)
node _uncommonBits_T_163 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_163 = bits(_uncommonBits_T_163, 4, 0)
node _T_1644 = shr(io.in.a.bits.source, 5)
node _T_1645 = eq(_T_1644, UInt<4>(0ha))
node _T_1646 = leq(UInt<1>(0h0), uncommonBits_163)
node _T_1647 = and(_T_1645, _T_1646)
node _T_1648 = leq(uncommonBits_163, UInt<5>(0h1f))
node _T_1649 = and(_T_1647, _T_1648)
node _uncommonBits_T_164 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_164 = bits(_uncommonBits_T_164, 4, 0)
node _T_1650 = shr(io.in.a.bits.source, 5)
node _T_1651 = eq(_T_1650, UInt<4>(0h9))
node _T_1652 = leq(UInt<1>(0h0), uncommonBits_164)
node _T_1653 = and(_T_1651, _T_1652)
node _T_1654 = leq(uncommonBits_164, UInt<5>(0h1f))
node _T_1655 = and(_T_1653, _T_1654)
node _uncommonBits_T_165 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_165 = bits(_uncommonBits_T_165, 4, 0)
node _T_1656 = shr(io.in.a.bits.source, 5)
node _T_1657 = eq(_T_1656, UInt<4>(0h8))
node _T_1658 = leq(UInt<1>(0h0), uncommonBits_165)
node _T_1659 = and(_T_1657, _T_1658)
node _T_1660 = leq(uncommonBits_165, UInt<5>(0h1f))
node _T_1661 = and(_T_1659, _T_1660)
node _uncommonBits_T_166 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_166 = bits(_uncommonBits_T_166, 1, 0)
node _T_1662 = shr(io.in.a.bits.source, 2)
node _T_1663 = eq(_T_1662, UInt<7>(0h7a))
node _T_1664 = leq(UInt<1>(0h0), uncommonBits_166)
node _T_1665 = and(_T_1663, _T_1664)
node _T_1666 = leq(uncommonBits_166, UInt<2>(0h3))
node _T_1667 = and(_T_1665, _T_1666)
node _uncommonBits_T_167 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_167 = bits(_uncommonBits_T_167, 1, 0)
node _T_1668 = shr(io.in.a.bits.source, 2)
node _T_1669 = eq(_T_1668, UInt<7>(0h79))
node _T_1670 = leq(UInt<1>(0h0), uncommonBits_167)
node _T_1671 = and(_T_1669, _T_1670)
node _T_1672 = leq(uncommonBits_167, UInt<2>(0h3))
node _T_1673 = and(_T_1671, _T_1672)
node _uncommonBits_T_168 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_168 = bits(_uncommonBits_T_168, 4, 0)
node _T_1674 = shr(io.in.a.bits.source, 5)
node _T_1675 = eq(_T_1674, UInt<3>(0h7))
node _T_1676 = leq(UInt<1>(0h0), uncommonBits_168)
node _T_1677 = and(_T_1675, _T_1676)
node _T_1678 = leq(uncommonBits_168, UInt<5>(0h1f))
node _T_1679 = and(_T_1677, _T_1678)
node _uncommonBits_T_169 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_169 = bits(_uncommonBits_T_169, 4, 0)
node _T_1680 = shr(io.in.a.bits.source, 5)
node _T_1681 = eq(_T_1680, UInt<3>(0h6))
node _T_1682 = leq(UInt<1>(0h0), uncommonBits_169)
node _T_1683 = and(_T_1681, _T_1682)
node _T_1684 = leq(uncommonBits_169, UInt<5>(0h1f))
node _T_1685 = and(_T_1683, _T_1684)
node _uncommonBits_T_170 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_170 = bits(_uncommonBits_T_170, 4, 0)
node _T_1686 = shr(io.in.a.bits.source, 5)
node _T_1687 = eq(_T_1686, UInt<3>(0h5))
node _T_1688 = leq(UInt<1>(0h0), uncommonBits_170)
node _T_1689 = and(_T_1687, _T_1688)
node _T_1690 = leq(uncommonBits_170, UInt<5>(0h1f))
node _T_1691 = and(_T_1689, _T_1690)
node _uncommonBits_T_171 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_171 = bits(_uncommonBits_T_171, 4, 0)
node _T_1692 = shr(io.in.a.bits.source, 5)
node _T_1693 = eq(_T_1692, UInt<3>(0h4))
node _T_1694 = leq(UInt<1>(0h0), uncommonBits_171)
node _T_1695 = and(_T_1693, _T_1694)
node _T_1696 = leq(uncommonBits_171, UInt<5>(0h1f))
node _T_1697 = and(_T_1695, _T_1696)
node _uncommonBits_T_172 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_172 = bits(_uncommonBits_T_172, 4, 0)
node _T_1698 = shr(io.in.a.bits.source, 5)
node _T_1699 = eq(_T_1698, UInt<2>(0h3))
node _T_1700 = leq(UInt<1>(0h0), uncommonBits_172)
node _T_1701 = and(_T_1699, _T_1700)
node _T_1702 = leq(uncommonBits_172, UInt<5>(0h1f))
node _T_1703 = and(_T_1701, _T_1702)
node _uncommonBits_T_173 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_173 = bits(_uncommonBits_T_173, 4, 0)
node _T_1704 = shr(io.in.a.bits.source, 5)
node _T_1705 = eq(_T_1704, UInt<2>(0h2))
node _T_1706 = leq(UInt<1>(0h0), uncommonBits_173)
node _T_1707 = and(_T_1705, _T_1706)
node _T_1708 = leq(uncommonBits_173, UInt<5>(0h1f))
node _T_1709 = and(_T_1707, _T_1708)
node _uncommonBits_T_174 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_174 = bits(_uncommonBits_T_174, 4, 0)
node _T_1710 = shr(io.in.a.bits.source, 5)
node _T_1711 = eq(_T_1710, UInt<1>(0h1))
node _T_1712 = leq(UInt<1>(0h0), uncommonBits_174)
node _T_1713 = and(_T_1711, _T_1712)
node _T_1714 = leq(uncommonBits_174, UInt<5>(0h1f))
node _T_1715 = and(_T_1713, _T_1714)
node _uncommonBits_T_175 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_175 = bits(_uncommonBits_T_175, 4, 0)
node _T_1716 = shr(io.in.a.bits.source, 5)
node _T_1717 = eq(_T_1716, UInt<1>(0h0))
node _T_1718 = leq(UInt<1>(0h0), uncommonBits_175)
node _T_1719 = and(_T_1717, _T_1718)
node _T_1720 = leq(uncommonBits_175, UInt<5>(0h1f))
node _T_1721 = and(_T_1719, _T_1720)
node _T_1722 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_1723 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_1724 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_1725 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1726 = or(_T_1589, _T_1595)
node _T_1727 = or(_T_1726, _T_1601)
node _T_1728 = or(_T_1727, _T_1607)
node _T_1729 = or(_T_1728, _T_1613)
node _T_1730 = or(_T_1729, _T_1619)
node _T_1731 = or(_T_1730, _T_1625)
node _T_1732 = or(_T_1731, _T_1631)
node _T_1733 = or(_T_1732, _T_1637)
node _T_1734 = or(_T_1733, _T_1643)
node _T_1735 = or(_T_1734, _T_1649)
node _T_1736 = or(_T_1735, _T_1655)
node _T_1737 = or(_T_1736, _T_1661)
node _T_1738 = or(_T_1737, _T_1667)
node _T_1739 = or(_T_1738, _T_1673)
node _T_1740 = or(_T_1739, _T_1679)
node _T_1741 = or(_T_1740, _T_1685)
node _T_1742 = or(_T_1741, _T_1691)
node _T_1743 = or(_T_1742, _T_1697)
node _T_1744 = or(_T_1743, _T_1703)
node _T_1745 = or(_T_1744, _T_1709)
node _T_1746 = or(_T_1745, _T_1715)
node _T_1747 = or(_T_1746, _T_1721)
node _T_1748 = or(_T_1747, _T_1722)
node _T_1749 = or(_T_1748, _T_1723)
node _T_1750 = or(_T_1749, _T_1724)
node _T_1751 = or(_T_1750, _T_1725)
node _T_1752 = and(_T_1588, _T_1751)
node _T_1753 = or(UInt<1>(0h0), _T_1752)
node _T_1754 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1755 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1756 = and(_T_1754, _T_1755)
node _T_1757 = or(UInt<1>(0h0), _T_1756)
node _T_1758 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_1759 = cvt(_T_1758)
node _T_1760 = and(_T_1759, asSInt(UInt<13>(0h1000)))
node _T_1761 = asSInt(_T_1760)
node _T_1762 = eq(_T_1761, asSInt(UInt<1>(0h0)))
node _T_1763 = and(_T_1757, _T_1762)
node _T_1764 = or(UInt<1>(0h0), _T_1763)
node _T_1765 = and(_T_1753, _T_1764)
node _T_1766 = asUInt(reset)
node _T_1767 = eq(_T_1766, UInt<1>(0h0))
when _T_1767 :
node _T_1768 = eq(_T_1765, UInt<1>(0h0))
when _T_1768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1765, UInt<1>(0h1), "") : assert_31
node _T_1769 = asUInt(reset)
node _T_1770 = eq(_T_1769, UInt<1>(0h0))
when _T_1770 :
node _T_1771 = eq(source_ok, UInt<1>(0h0))
when _T_1771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1772 = asUInt(reset)
node _T_1773 = eq(_T_1772, UInt<1>(0h0))
when _T_1773 :
node _T_1774 = eq(is_aligned, UInt<1>(0h0))
when _T_1774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1775 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1776 = asUInt(reset)
node _T_1777 = eq(_T_1776, UInt<1>(0h0))
when _T_1777 :
node _T_1778 = eq(_T_1775, UInt<1>(0h0))
when _T_1778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1775, UInt<1>(0h1), "") : assert_34
node _T_1779 = not(mask)
node _T_1780 = and(io.in.a.bits.mask, _T_1779)
node _T_1781 = eq(_T_1780, UInt<1>(0h0))
node _T_1782 = asUInt(reset)
node _T_1783 = eq(_T_1782, UInt<1>(0h0))
when _T_1783 :
node _T_1784 = eq(_T_1781, UInt<1>(0h0))
when _T_1784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1781, UInt<1>(0h1), "") : assert_35
node _T_1785 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1785 :
node _T_1786 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1787 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1788 = and(_T_1786, _T_1787)
node _T_1789 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_176 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_176 = bits(_uncommonBits_T_176, 1, 0)
node _T_1790 = shr(io.in.a.bits.source, 2)
node _T_1791 = eq(_T_1790, UInt<7>(0h70))
node _T_1792 = leq(UInt<1>(0h0), uncommonBits_176)
node _T_1793 = and(_T_1791, _T_1792)
node _T_1794 = leq(uncommonBits_176, UInt<2>(0h3))
node _T_1795 = and(_T_1793, _T_1794)
node _uncommonBits_T_177 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_177 = bits(_uncommonBits_T_177, 1, 0)
node _T_1796 = shr(io.in.a.bits.source, 2)
node _T_1797 = eq(_T_1796, UInt<7>(0h71))
node _T_1798 = leq(UInt<1>(0h0), uncommonBits_177)
node _T_1799 = and(_T_1797, _T_1798)
node _T_1800 = leq(uncommonBits_177, UInt<2>(0h3))
node _T_1801 = and(_T_1799, _T_1800)
node _uncommonBits_T_178 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_178 = bits(_uncommonBits_T_178, 1, 0)
node _T_1802 = shr(io.in.a.bits.source, 2)
node _T_1803 = eq(_T_1802, UInt<7>(0h72))
node _T_1804 = leq(UInt<1>(0h0), uncommonBits_178)
node _T_1805 = and(_T_1803, _T_1804)
node _T_1806 = leq(uncommonBits_178, UInt<2>(0h3))
node _T_1807 = and(_T_1805, _T_1806)
node _uncommonBits_T_179 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_179 = bits(_uncommonBits_T_179, 1, 0)
node _T_1808 = shr(io.in.a.bits.source, 2)
node _T_1809 = eq(_T_1808, UInt<7>(0h73))
node _T_1810 = leq(UInt<1>(0h0), uncommonBits_179)
node _T_1811 = and(_T_1809, _T_1810)
node _T_1812 = leq(uncommonBits_179, UInt<2>(0h3))
node _T_1813 = and(_T_1811, _T_1812)
node _uncommonBits_T_180 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_180 = bits(_uncommonBits_T_180, 1, 0)
node _T_1814 = shr(io.in.a.bits.source, 2)
node _T_1815 = eq(_T_1814, UInt<7>(0h7c))
node _T_1816 = leq(UInt<1>(0h0), uncommonBits_180)
node _T_1817 = and(_T_1815, _T_1816)
node _T_1818 = leq(uncommonBits_180, UInt<2>(0h3))
node _T_1819 = and(_T_1817, _T_1818)
node _uncommonBits_T_181 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_181 = bits(_uncommonBits_T_181, 1, 0)
node _T_1820 = shr(io.in.a.bits.source, 2)
node _T_1821 = eq(_T_1820, UInt<7>(0h7b))
node _T_1822 = leq(UInt<1>(0h0), uncommonBits_181)
node _T_1823 = and(_T_1821, _T_1822)
node _T_1824 = leq(uncommonBits_181, UInt<2>(0h3))
node _T_1825 = and(_T_1823, _T_1824)
node _uncommonBits_T_182 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_182 = bits(_uncommonBits_T_182, 4, 0)
node _T_1826 = shr(io.in.a.bits.source, 5)
node _T_1827 = eq(_T_1826, UInt<4>(0hd))
node _T_1828 = leq(UInt<1>(0h0), uncommonBits_182)
node _T_1829 = and(_T_1827, _T_1828)
node _T_1830 = leq(uncommonBits_182, UInt<5>(0h1f))
node _T_1831 = and(_T_1829, _T_1830)
node _uncommonBits_T_183 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_183 = bits(_uncommonBits_T_183, 4, 0)
node _T_1832 = shr(io.in.a.bits.source, 5)
node _T_1833 = eq(_T_1832, UInt<4>(0hc))
node _T_1834 = leq(UInt<1>(0h0), uncommonBits_183)
node _T_1835 = and(_T_1833, _T_1834)
node _T_1836 = leq(uncommonBits_183, UInt<5>(0h1f))
node _T_1837 = and(_T_1835, _T_1836)
node _uncommonBits_T_184 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_184 = bits(_uncommonBits_T_184, 4, 0)
node _T_1838 = shr(io.in.a.bits.source, 5)
node _T_1839 = eq(_T_1838, UInt<4>(0hb))
node _T_1840 = leq(UInt<1>(0h0), uncommonBits_184)
node _T_1841 = and(_T_1839, _T_1840)
node _T_1842 = leq(uncommonBits_184, UInt<5>(0h1f))
node _T_1843 = and(_T_1841, _T_1842)
node _uncommonBits_T_185 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_185 = bits(_uncommonBits_T_185, 4, 0)
node _T_1844 = shr(io.in.a.bits.source, 5)
node _T_1845 = eq(_T_1844, UInt<4>(0ha))
node _T_1846 = leq(UInt<1>(0h0), uncommonBits_185)
node _T_1847 = and(_T_1845, _T_1846)
node _T_1848 = leq(uncommonBits_185, UInt<5>(0h1f))
node _T_1849 = and(_T_1847, _T_1848)
node _uncommonBits_T_186 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_186 = bits(_uncommonBits_T_186, 4, 0)
node _T_1850 = shr(io.in.a.bits.source, 5)
node _T_1851 = eq(_T_1850, UInt<4>(0h9))
node _T_1852 = leq(UInt<1>(0h0), uncommonBits_186)
node _T_1853 = and(_T_1851, _T_1852)
node _T_1854 = leq(uncommonBits_186, UInt<5>(0h1f))
node _T_1855 = and(_T_1853, _T_1854)
node _uncommonBits_T_187 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_187 = bits(_uncommonBits_T_187, 4, 0)
node _T_1856 = shr(io.in.a.bits.source, 5)
node _T_1857 = eq(_T_1856, UInt<4>(0h8))
node _T_1858 = leq(UInt<1>(0h0), uncommonBits_187)
node _T_1859 = and(_T_1857, _T_1858)
node _T_1860 = leq(uncommonBits_187, UInt<5>(0h1f))
node _T_1861 = and(_T_1859, _T_1860)
node _uncommonBits_T_188 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_188 = bits(_uncommonBits_T_188, 1, 0)
node _T_1862 = shr(io.in.a.bits.source, 2)
node _T_1863 = eq(_T_1862, UInt<7>(0h7a))
node _T_1864 = leq(UInt<1>(0h0), uncommonBits_188)
node _T_1865 = and(_T_1863, _T_1864)
node _T_1866 = leq(uncommonBits_188, UInt<2>(0h3))
node _T_1867 = and(_T_1865, _T_1866)
node _uncommonBits_T_189 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_189 = bits(_uncommonBits_T_189, 1, 0)
node _T_1868 = shr(io.in.a.bits.source, 2)
node _T_1869 = eq(_T_1868, UInt<7>(0h79))
node _T_1870 = leq(UInt<1>(0h0), uncommonBits_189)
node _T_1871 = and(_T_1869, _T_1870)
node _T_1872 = leq(uncommonBits_189, UInt<2>(0h3))
node _T_1873 = and(_T_1871, _T_1872)
node _uncommonBits_T_190 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_190 = bits(_uncommonBits_T_190, 4, 0)
node _T_1874 = shr(io.in.a.bits.source, 5)
node _T_1875 = eq(_T_1874, UInt<3>(0h7))
node _T_1876 = leq(UInt<1>(0h0), uncommonBits_190)
node _T_1877 = and(_T_1875, _T_1876)
node _T_1878 = leq(uncommonBits_190, UInt<5>(0h1f))
node _T_1879 = and(_T_1877, _T_1878)
node _uncommonBits_T_191 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_191 = bits(_uncommonBits_T_191, 4, 0)
node _T_1880 = shr(io.in.a.bits.source, 5)
node _T_1881 = eq(_T_1880, UInt<3>(0h6))
node _T_1882 = leq(UInt<1>(0h0), uncommonBits_191)
node _T_1883 = and(_T_1881, _T_1882)
node _T_1884 = leq(uncommonBits_191, UInt<5>(0h1f))
node _T_1885 = and(_T_1883, _T_1884)
node _uncommonBits_T_192 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_192 = bits(_uncommonBits_T_192, 4, 0)
node _T_1886 = shr(io.in.a.bits.source, 5)
node _T_1887 = eq(_T_1886, UInt<3>(0h5))
node _T_1888 = leq(UInt<1>(0h0), uncommonBits_192)
node _T_1889 = and(_T_1887, _T_1888)
node _T_1890 = leq(uncommonBits_192, UInt<5>(0h1f))
node _T_1891 = and(_T_1889, _T_1890)
node _uncommonBits_T_193 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_193 = bits(_uncommonBits_T_193, 4, 0)
node _T_1892 = shr(io.in.a.bits.source, 5)
node _T_1893 = eq(_T_1892, UInt<3>(0h4))
node _T_1894 = leq(UInt<1>(0h0), uncommonBits_193)
node _T_1895 = and(_T_1893, _T_1894)
node _T_1896 = leq(uncommonBits_193, UInt<5>(0h1f))
node _T_1897 = and(_T_1895, _T_1896)
node _uncommonBits_T_194 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_194 = bits(_uncommonBits_T_194, 4, 0)
node _T_1898 = shr(io.in.a.bits.source, 5)
node _T_1899 = eq(_T_1898, UInt<2>(0h3))
node _T_1900 = leq(UInt<1>(0h0), uncommonBits_194)
node _T_1901 = and(_T_1899, _T_1900)
node _T_1902 = leq(uncommonBits_194, UInt<5>(0h1f))
node _T_1903 = and(_T_1901, _T_1902)
node _uncommonBits_T_195 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_195 = bits(_uncommonBits_T_195, 4, 0)
node _T_1904 = shr(io.in.a.bits.source, 5)
node _T_1905 = eq(_T_1904, UInt<2>(0h2))
node _T_1906 = leq(UInt<1>(0h0), uncommonBits_195)
node _T_1907 = and(_T_1905, _T_1906)
node _T_1908 = leq(uncommonBits_195, UInt<5>(0h1f))
node _T_1909 = and(_T_1907, _T_1908)
node _uncommonBits_T_196 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_196 = bits(_uncommonBits_T_196, 4, 0)
node _T_1910 = shr(io.in.a.bits.source, 5)
node _T_1911 = eq(_T_1910, UInt<1>(0h1))
node _T_1912 = leq(UInt<1>(0h0), uncommonBits_196)
node _T_1913 = and(_T_1911, _T_1912)
node _T_1914 = leq(uncommonBits_196, UInt<5>(0h1f))
node _T_1915 = and(_T_1913, _T_1914)
node _uncommonBits_T_197 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_197 = bits(_uncommonBits_T_197, 4, 0)
node _T_1916 = shr(io.in.a.bits.source, 5)
node _T_1917 = eq(_T_1916, UInt<1>(0h0))
node _T_1918 = leq(UInt<1>(0h0), uncommonBits_197)
node _T_1919 = and(_T_1917, _T_1918)
node _T_1920 = leq(uncommonBits_197, UInt<5>(0h1f))
node _T_1921 = and(_T_1919, _T_1920)
node _T_1922 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_1923 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_1924 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_1925 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1926 = or(_T_1789, _T_1795)
node _T_1927 = or(_T_1926, _T_1801)
node _T_1928 = or(_T_1927, _T_1807)
node _T_1929 = or(_T_1928, _T_1813)
node _T_1930 = or(_T_1929, _T_1819)
node _T_1931 = or(_T_1930, _T_1825)
node _T_1932 = or(_T_1931, _T_1831)
node _T_1933 = or(_T_1932, _T_1837)
node _T_1934 = or(_T_1933, _T_1843)
node _T_1935 = or(_T_1934, _T_1849)
node _T_1936 = or(_T_1935, _T_1855)
node _T_1937 = or(_T_1936, _T_1861)
node _T_1938 = or(_T_1937, _T_1867)
node _T_1939 = or(_T_1938, _T_1873)
node _T_1940 = or(_T_1939, _T_1879)
node _T_1941 = or(_T_1940, _T_1885)
node _T_1942 = or(_T_1941, _T_1891)
node _T_1943 = or(_T_1942, _T_1897)
node _T_1944 = or(_T_1943, _T_1903)
node _T_1945 = or(_T_1944, _T_1909)
node _T_1946 = or(_T_1945, _T_1915)
node _T_1947 = or(_T_1946, _T_1921)
node _T_1948 = or(_T_1947, _T_1922)
node _T_1949 = or(_T_1948, _T_1923)
node _T_1950 = or(_T_1949, _T_1924)
node _T_1951 = or(_T_1950, _T_1925)
node _T_1952 = and(_T_1788, _T_1951)
node _T_1953 = or(UInt<1>(0h0), _T_1952)
node _T_1954 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1955 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_1956 = cvt(_T_1955)
node _T_1957 = and(_T_1956, asSInt(UInt<13>(0h1000)))
node _T_1958 = asSInt(_T_1957)
node _T_1959 = eq(_T_1958, asSInt(UInt<1>(0h0)))
node _T_1960 = and(_T_1954, _T_1959)
node _T_1961 = or(UInt<1>(0h0), _T_1960)
node _T_1962 = and(_T_1953, _T_1961)
node _T_1963 = asUInt(reset)
node _T_1964 = eq(_T_1963, UInt<1>(0h0))
when _T_1964 :
node _T_1965 = eq(_T_1962, UInt<1>(0h0))
when _T_1965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1962, UInt<1>(0h1), "") : assert_36
node _T_1966 = asUInt(reset)
node _T_1967 = eq(_T_1966, UInt<1>(0h0))
when _T_1967 :
node _T_1968 = eq(source_ok, UInt<1>(0h0))
when _T_1968 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1969 = asUInt(reset)
node _T_1970 = eq(_T_1969, UInt<1>(0h0))
when _T_1970 :
node _T_1971 = eq(is_aligned, UInt<1>(0h0))
when _T_1971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1972 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1973 = asUInt(reset)
node _T_1974 = eq(_T_1973, UInt<1>(0h0))
when _T_1974 :
node _T_1975 = eq(_T_1972, UInt<1>(0h0))
when _T_1975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1972, UInt<1>(0h1), "") : assert_39
node _T_1976 = eq(io.in.a.bits.mask, mask)
node _T_1977 = asUInt(reset)
node _T_1978 = eq(_T_1977, UInt<1>(0h0))
when _T_1978 :
node _T_1979 = eq(_T_1976, UInt<1>(0h0))
when _T_1979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1976, UInt<1>(0h1), "") : assert_40
node _T_1980 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1980 :
node _T_1981 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1982 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1983 = and(_T_1981, _T_1982)
node _T_1984 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_198 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_198 = bits(_uncommonBits_T_198, 1, 0)
node _T_1985 = shr(io.in.a.bits.source, 2)
node _T_1986 = eq(_T_1985, UInt<7>(0h70))
node _T_1987 = leq(UInt<1>(0h0), uncommonBits_198)
node _T_1988 = and(_T_1986, _T_1987)
node _T_1989 = leq(uncommonBits_198, UInt<2>(0h3))
node _T_1990 = and(_T_1988, _T_1989)
node _uncommonBits_T_199 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_199 = bits(_uncommonBits_T_199, 1, 0)
node _T_1991 = shr(io.in.a.bits.source, 2)
node _T_1992 = eq(_T_1991, UInt<7>(0h71))
node _T_1993 = leq(UInt<1>(0h0), uncommonBits_199)
node _T_1994 = and(_T_1992, _T_1993)
node _T_1995 = leq(uncommonBits_199, UInt<2>(0h3))
node _T_1996 = and(_T_1994, _T_1995)
node _uncommonBits_T_200 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_200 = bits(_uncommonBits_T_200, 1, 0)
node _T_1997 = shr(io.in.a.bits.source, 2)
node _T_1998 = eq(_T_1997, UInt<7>(0h72))
node _T_1999 = leq(UInt<1>(0h0), uncommonBits_200)
node _T_2000 = and(_T_1998, _T_1999)
node _T_2001 = leq(uncommonBits_200, UInt<2>(0h3))
node _T_2002 = and(_T_2000, _T_2001)
node _uncommonBits_T_201 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_201 = bits(_uncommonBits_T_201, 1, 0)
node _T_2003 = shr(io.in.a.bits.source, 2)
node _T_2004 = eq(_T_2003, UInt<7>(0h73))
node _T_2005 = leq(UInt<1>(0h0), uncommonBits_201)
node _T_2006 = and(_T_2004, _T_2005)
node _T_2007 = leq(uncommonBits_201, UInt<2>(0h3))
node _T_2008 = and(_T_2006, _T_2007)
node _uncommonBits_T_202 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_202 = bits(_uncommonBits_T_202, 1, 0)
node _T_2009 = shr(io.in.a.bits.source, 2)
node _T_2010 = eq(_T_2009, UInt<7>(0h7c))
node _T_2011 = leq(UInt<1>(0h0), uncommonBits_202)
node _T_2012 = and(_T_2010, _T_2011)
node _T_2013 = leq(uncommonBits_202, UInt<2>(0h3))
node _T_2014 = and(_T_2012, _T_2013)
node _uncommonBits_T_203 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_203 = bits(_uncommonBits_T_203, 1, 0)
node _T_2015 = shr(io.in.a.bits.source, 2)
node _T_2016 = eq(_T_2015, UInt<7>(0h7b))
node _T_2017 = leq(UInt<1>(0h0), uncommonBits_203)
node _T_2018 = and(_T_2016, _T_2017)
node _T_2019 = leq(uncommonBits_203, UInt<2>(0h3))
node _T_2020 = and(_T_2018, _T_2019)
node _uncommonBits_T_204 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_204 = bits(_uncommonBits_T_204, 4, 0)
node _T_2021 = shr(io.in.a.bits.source, 5)
node _T_2022 = eq(_T_2021, UInt<4>(0hd))
node _T_2023 = leq(UInt<1>(0h0), uncommonBits_204)
node _T_2024 = and(_T_2022, _T_2023)
node _T_2025 = leq(uncommonBits_204, UInt<5>(0h1f))
node _T_2026 = and(_T_2024, _T_2025)
node _uncommonBits_T_205 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_205 = bits(_uncommonBits_T_205, 4, 0)
node _T_2027 = shr(io.in.a.bits.source, 5)
node _T_2028 = eq(_T_2027, UInt<4>(0hc))
node _T_2029 = leq(UInt<1>(0h0), uncommonBits_205)
node _T_2030 = and(_T_2028, _T_2029)
node _T_2031 = leq(uncommonBits_205, UInt<5>(0h1f))
node _T_2032 = and(_T_2030, _T_2031)
node _uncommonBits_T_206 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_206 = bits(_uncommonBits_T_206, 4, 0)
node _T_2033 = shr(io.in.a.bits.source, 5)
node _T_2034 = eq(_T_2033, UInt<4>(0hb))
node _T_2035 = leq(UInt<1>(0h0), uncommonBits_206)
node _T_2036 = and(_T_2034, _T_2035)
node _T_2037 = leq(uncommonBits_206, UInt<5>(0h1f))
node _T_2038 = and(_T_2036, _T_2037)
node _uncommonBits_T_207 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_207 = bits(_uncommonBits_T_207, 4, 0)
node _T_2039 = shr(io.in.a.bits.source, 5)
node _T_2040 = eq(_T_2039, UInt<4>(0ha))
node _T_2041 = leq(UInt<1>(0h0), uncommonBits_207)
node _T_2042 = and(_T_2040, _T_2041)
node _T_2043 = leq(uncommonBits_207, UInt<5>(0h1f))
node _T_2044 = and(_T_2042, _T_2043)
node _uncommonBits_T_208 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_208 = bits(_uncommonBits_T_208, 4, 0)
node _T_2045 = shr(io.in.a.bits.source, 5)
node _T_2046 = eq(_T_2045, UInt<4>(0h9))
node _T_2047 = leq(UInt<1>(0h0), uncommonBits_208)
node _T_2048 = and(_T_2046, _T_2047)
node _T_2049 = leq(uncommonBits_208, UInt<5>(0h1f))
node _T_2050 = and(_T_2048, _T_2049)
node _uncommonBits_T_209 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_209 = bits(_uncommonBits_T_209, 4, 0)
node _T_2051 = shr(io.in.a.bits.source, 5)
node _T_2052 = eq(_T_2051, UInt<4>(0h8))
node _T_2053 = leq(UInt<1>(0h0), uncommonBits_209)
node _T_2054 = and(_T_2052, _T_2053)
node _T_2055 = leq(uncommonBits_209, UInt<5>(0h1f))
node _T_2056 = and(_T_2054, _T_2055)
node _uncommonBits_T_210 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_210 = bits(_uncommonBits_T_210, 1, 0)
node _T_2057 = shr(io.in.a.bits.source, 2)
node _T_2058 = eq(_T_2057, UInt<7>(0h7a))
node _T_2059 = leq(UInt<1>(0h0), uncommonBits_210)
node _T_2060 = and(_T_2058, _T_2059)
node _T_2061 = leq(uncommonBits_210, UInt<2>(0h3))
node _T_2062 = and(_T_2060, _T_2061)
node _uncommonBits_T_211 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_211 = bits(_uncommonBits_T_211, 1, 0)
node _T_2063 = shr(io.in.a.bits.source, 2)
node _T_2064 = eq(_T_2063, UInt<7>(0h79))
node _T_2065 = leq(UInt<1>(0h0), uncommonBits_211)
node _T_2066 = and(_T_2064, _T_2065)
node _T_2067 = leq(uncommonBits_211, UInt<2>(0h3))
node _T_2068 = and(_T_2066, _T_2067)
node _uncommonBits_T_212 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_212 = bits(_uncommonBits_T_212, 4, 0)
node _T_2069 = shr(io.in.a.bits.source, 5)
node _T_2070 = eq(_T_2069, UInt<3>(0h7))
node _T_2071 = leq(UInt<1>(0h0), uncommonBits_212)
node _T_2072 = and(_T_2070, _T_2071)
node _T_2073 = leq(uncommonBits_212, UInt<5>(0h1f))
node _T_2074 = and(_T_2072, _T_2073)
node _uncommonBits_T_213 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_213 = bits(_uncommonBits_T_213, 4, 0)
node _T_2075 = shr(io.in.a.bits.source, 5)
node _T_2076 = eq(_T_2075, UInt<3>(0h6))
node _T_2077 = leq(UInt<1>(0h0), uncommonBits_213)
node _T_2078 = and(_T_2076, _T_2077)
node _T_2079 = leq(uncommonBits_213, UInt<5>(0h1f))
node _T_2080 = and(_T_2078, _T_2079)
node _uncommonBits_T_214 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_214 = bits(_uncommonBits_T_214, 4, 0)
node _T_2081 = shr(io.in.a.bits.source, 5)
node _T_2082 = eq(_T_2081, UInt<3>(0h5))
node _T_2083 = leq(UInt<1>(0h0), uncommonBits_214)
node _T_2084 = and(_T_2082, _T_2083)
node _T_2085 = leq(uncommonBits_214, UInt<5>(0h1f))
node _T_2086 = and(_T_2084, _T_2085)
node _uncommonBits_T_215 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_215 = bits(_uncommonBits_T_215, 4, 0)
node _T_2087 = shr(io.in.a.bits.source, 5)
node _T_2088 = eq(_T_2087, UInt<3>(0h4))
node _T_2089 = leq(UInt<1>(0h0), uncommonBits_215)
node _T_2090 = and(_T_2088, _T_2089)
node _T_2091 = leq(uncommonBits_215, UInt<5>(0h1f))
node _T_2092 = and(_T_2090, _T_2091)
node _uncommonBits_T_216 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_216 = bits(_uncommonBits_T_216, 4, 0)
node _T_2093 = shr(io.in.a.bits.source, 5)
node _T_2094 = eq(_T_2093, UInt<2>(0h3))
node _T_2095 = leq(UInt<1>(0h0), uncommonBits_216)
node _T_2096 = and(_T_2094, _T_2095)
node _T_2097 = leq(uncommonBits_216, UInt<5>(0h1f))
node _T_2098 = and(_T_2096, _T_2097)
node _uncommonBits_T_217 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_217 = bits(_uncommonBits_T_217, 4, 0)
node _T_2099 = shr(io.in.a.bits.source, 5)
node _T_2100 = eq(_T_2099, UInt<2>(0h2))
node _T_2101 = leq(UInt<1>(0h0), uncommonBits_217)
node _T_2102 = and(_T_2100, _T_2101)
node _T_2103 = leq(uncommonBits_217, UInt<5>(0h1f))
node _T_2104 = and(_T_2102, _T_2103)
node _uncommonBits_T_218 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_218 = bits(_uncommonBits_T_218, 4, 0)
node _T_2105 = shr(io.in.a.bits.source, 5)
node _T_2106 = eq(_T_2105, UInt<1>(0h1))
node _T_2107 = leq(UInt<1>(0h0), uncommonBits_218)
node _T_2108 = and(_T_2106, _T_2107)
node _T_2109 = leq(uncommonBits_218, UInt<5>(0h1f))
node _T_2110 = and(_T_2108, _T_2109)
node _uncommonBits_T_219 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_219 = bits(_uncommonBits_T_219, 4, 0)
node _T_2111 = shr(io.in.a.bits.source, 5)
node _T_2112 = eq(_T_2111, UInt<1>(0h0))
node _T_2113 = leq(UInt<1>(0h0), uncommonBits_219)
node _T_2114 = and(_T_2112, _T_2113)
node _T_2115 = leq(uncommonBits_219, UInt<5>(0h1f))
node _T_2116 = and(_T_2114, _T_2115)
node _T_2117 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_2118 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_2119 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_2120 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_2121 = or(_T_1984, _T_1990)
node _T_2122 = or(_T_2121, _T_1996)
node _T_2123 = or(_T_2122, _T_2002)
node _T_2124 = or(_T_2123, _T_2008)
node _T_2125 = or(_T_2124, _T_2014)
node _T_2126 = or(_T_2125, _T_2020)
node _T_2127 = or(_T_2126, _T_2026)
node _T_2128 = or(_T_2127, _T_2032)
node _T_2129 = or(_T_2128, _T_2038)
node _T_2130 = or(_T_2129, _T_2044)
node _T_2131 = or(_T_2130, _T_2050)
node _T_2132 = or(_T_2131, _T_2056)
node _T_2133 = or(_T_2132, _T_2062)
node _T_2134 = or(_T_2133, _T_2068)
node _T_2135 = or(_T_2134, _T_2074)
node _T_2136 = or(_T_2135, _T_2080)
node _T_2137 = or(_T_2136, _T_2086)
node _T_2138 = or(_T_2137, _T_2092)
node _T_2139 = or(_T_2138, _T_2098)
node _T_2140 = or(_T_2139, _T_2104)
node _T_2141 = or(_T_2140, _T_2110)
node _T_2142 = or(_T_2141, _T_2116)
node _T_2143 = or(_T_2142, _T_2117)
node _T_2144 = or(_T_2143, _T_2118)
node _T_2145 = or(_T_2144, _T_2119)
node _T_2146 = or(_T_2145, _T_2120)
node _T_2147 = and(_T_1983, _T_2146)
node _T_2148 = or(UInt<1>(0h0), _T_2147)
node _T_2149 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2150 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_2151 = cvt(_T_2150)
node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000)))
node _T_2153 = asSInt(_T_2152)
node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0)))
node _T_2155 = and(_T_2149, _T_2154)
node _T_2156 = or(UInt<1>(0h0), _T_2155)
node _T_2157 = and(_T_2148, _T_2156)
node _T_2158 = asUInt(reset)
node _T_2159 = eq(_T_2158, UInt<1>(0h0))
when _T_2159 :
node _T_2160 = eq(_T_2157, UInt<1>(0h0))
when _T_2160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_2157, UInt<1>(0h1), "") : assert_41
node _T_2161 = asUInt(reset)
node _T_2162 = eq(_T_2161, UInt<1>(0h0))
when _T_2162 :
node _T_2163 = eq(source_ok, UInt<1>(0h0))
when _T_2163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_2164 = asUInt(reset)
node _T_2165 = eq(_T_2164, UInt<1>(0h0))
when _T_2165 :
node _T_2166 = eq(is_aligned, UInt<1>(0h0))
when _T_2166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_2167 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_2168 = asUInt(reset)
node _T_2169 = eq(_T_2168, UInt<1>(0h0))
when _T_2169 :
node _T_2170 = eq(_T_2167, UInt<1>(0h0))
when _T_2170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_2167, UInt<1>(0h1), "") : assert_44
node _T_2171 = eq(io.in.a.bits.mask, mask)
node _T_2172 = asUInt(reset)
node _T_2173 = eq(_T_2172, UInt<1>(0h0))
when _T_2173 :
node _T_2174 = eq(_T_2171, UInt<1>(0h0))
when _T_2174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_2171, UInt<1>(0h1), "") : assert_45
node _T_2175 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_2175 :
node _T_2176 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_2177 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_2178 = and(_T_2176, _T_2177)
node _T_2179 = eq(io.in.a.bits.source, UInt<9>(0h1d0))
node _uncommonBits_T_220 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_220 = bits(_uncommonBits_T_220, 1, 0)
node _T_2180 = shr(io.in.a.bits.source, 2)
node _T_2181 = eq(_T_2180, UInt<7>(0h70))
node _T_2182 = leq(UInt<1>(0h0), uncommonBits_220)
node _T_2183 = and(_T_2181, _T_2182)
node _T_2184 = leq(uncommonBits_220, UInt<2>(0h3))
node _T_2185 = and(_T_2183, _T_2184)
node _uncommonBits_T_221 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_221 = bits(_uncommonBits_T_221, 1, 0)
node _T_2186 = shr(io.in.a.bits.source, 2)
node _T_2187 = eq(_T_2186, UInt<7>(0h71))
node _T_2188 = leq(UInt<1>(0h0), uncommonBits_221)
node _T_2189 = and(_T_2187, _T_2188)
node _T_2190 = leq(uncommonBits_221, UInt<2>(0h3))
node _T_2191 = and(_T_2189, _T_2190)
node _uncommonBits_T_222 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_222 = bits(_uncommonBits_T_222, 1, 0)
node _T_2192 = shr(io.in.a.bits.source, 2)
node _T_2193 = eq(_T_2192, UInt<7>(0h72))
node _T_2194 = leq(UInt<1>(0h0), uncommonBits_222)
node _T_2195 = and(_T_2193, _T_2194)
node _T_2196 = leq(uncommonBits_222, UInt<2>(0h3))
node _T_2197 = and(_T_2195, _T_2196)
node _uncommonBits_T_223 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_223 = bits(_uncommonBits_T_223, 1, 0)
node _T_2198 = shr(io.in.a.bits.source, 2)
node _T_2199 = eq(_T_2198, UInt<7>(0h73))
node _T_2200 = leq(UInt<1>(0h0), uncommonBits_223)
node _T_2201 = and(_T_2199, _T_2200)
node _T_2202 = leq(uncommonBits_223, UInt<2>(0h3))
node _T_2203 = and(_T_2201, _T_2202)
node _uncommonBits_T_224 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_224 = bits(_uncommonBits_T_224, 1, 0)
node _T_2204 = shr(io.in.a.bits.source, 2)
node _T_2205 = eq(_T_2204, UInt<7>(0h7c))
node _T_2206 = leq(UInt<1>(0h0), uncommonBits_224)
node _T_2207 = and(_T_2205, _T_2206)
node _T_2208 = leq(uncommonBits_224, UInt<2>(0h3))
node _T_2209 = and(_T_2207, _T_2208)
node _uncommonBits_T_225 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_225 = bits(_uncommonBits_T_225, 1, 0)
node _T_2210 = shr(io.in.a.bits.source, 2)
node _T_2211 = eq(_T_2210, UInt<7>(0h7b))
node _T_2212 = leq(UInt<1>(0h0), uncommonBits_225)
node _T_2213 = and(_T_2211, _T_2212)
node _T_2214 = leq(uncommonBits_225, UInt<2>(0h3))
node _T_2215 = and(_T_2213, _T_2214)
node _uncommonBits_T_226 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_226 = bits(_uncommonBits_T_226, 4, 0)
node _T_2216 = shr(io.in.a.bits.source, 5)
node _T_2217 = eq(_T_2216, UInt<4>(0hd))
node _T_2218 = leq(UInt<1>(0h0), uncommonBits_226)
node _T_2219 = and(_T_2217, _T_2218)
node _T_2220 = leq(uncommonBits_226, UInt<5>(0h1f))
node _T_2221 = and(_T_2219, _T_2220)
node _uncommonBits_T_227 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_227 = bits(_uncommonBits_T_227, 4, 0)
node _T_2222 = shr(io.in.a.bits.source, 5)
node _T_2223 = eq(_T_2222, UInt<4>(0hc))
node _T_2224 = leq(UInt<1>(0h0), uncommonBits_227)
node _T_2225 = and(_T_2223, _T_2224)
node _T_2226 = leq(uncommonBits_227, UInt<5>(0h1f))
node _T_2227 = and(_T_2225, _T_2226)
node _uncommonBits_T_228 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_228 = bits(_uncommonBits_T_228, 4, 0)
node _T_2228 = shr(io.in.a.bits.source, 5)
node _T_2229 = eq(_T_2228, UInt<4>(0hb))
node _T_2230 = leq(UInt<1>(0h0), uncommonBits_228)
node _T_2231 = and(_T_2229, _T_2230)
node _T_2232 = leq(uncommonBits_228, UInt<5>(0h1f))
node _T_2233 = and(_T_2231, _T_2232)
node _uncommonBits_T_229 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_229 = bits(_uncommonBits_T_229, 4, 0)
node _T_2234 = shr(io.in.a.bits.source, 5)
node _T_2235 = eq(_T_2234, UInt<4>(0ha))
node _T_2236 = leq(UInt<1>(0h0), uncommonBits_229)
node _T_2237 = and(_T_2235, _T_2236)
node _T_2238 = leq(uncommonBits_229, UInt<5>(0h1f))
node _T_2239 = and(_T_2237, _T_2238)
node _uncommonBits_T_230 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_230 = bits(_uncommonBits_T_230, 4, 0)
node _T_2240 = shr(io.in.a.bits.source, 5)
node _T_2241 = eq(_T_2240, UInt<4>(0h9))
node _T_2242 = leq(UInt<1>(0h0), uncommonBits_230)
node _T_2243 = and(_T_2241, _T_2242)
node _T_2244 = leq(uncommonBits_230, UInt<5>(0h1f))
node _T_2245 = and(_T_2243, _T_2244)
node _uncommonBits_T_231 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_231 = bits(_uncommonBits_T_231, 4, 0)
node _T_2246 = shr(io.in.a.bits.source, 5)
node _T_2247 = eq(_T_2246, UInt<4>(0h8))
node _T_2248 = leq(UInt<1>(0h0), uncommonBits_231)
node _T_2249 = and(_T_2247, _T_2248)
node _T_2250 = leq(uncommonBits_231, UInt<5>(0h1f))
node _T_2251 = and(_T_2249, _T_2250)
node _uncommonBits_T_232 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_232 = bits(_uncommonBits_T_232, 1, 0)
node _T_2252 = shr(io.in.a.bits.source, 2)
node _T_2253 = eq(_T_2252, UInt<7>(0h7a))
node _T_2254 = leq(UInt<1>(0h0), uncommonBits_232)
node _T_2255 = and(_T_2253, _T_2254)
node _T_2256 = leq(uncommonBits_232, UInt<2>(0h3))
node _T_2257 = and(_T_2255, _T_2256)
node _uncommonBits_T_233 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_233 = bits(_uncommonBits_T_233, 1, 0)
node _T_2258 = shr(io.in.a.bits.source, 2)
node _T_2259 = eq(_T_2258, UInt<7>(0h79))
node _T_2260 = leq(UInt<1>(0h0), uncommonBits_233)
node _T_2261 = and(_T_2259, _T_2260)
node _T_2262 = leq(uncommonBits_233, UInt<2>(0h3))
node _T_2263 = and(_T_2261, _T_2262)
node _uncommonBits_T_234 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_234 = bits(_uncommonBits_T_234, 4, 0)
node _T_2264 = shr(io.in.a.bits.source, 5)
node _T_2265 = eq(_T_2264, UInt<3>(0h7))
node _T_2266 = leq(UInt<1>(0h0), uncommonBits_234)
node _T_2267 = and(_T_2265, _T_2266)
node _T_2268 = leq(uncommonBits_234, UInt<5>(0h1f))
node _T_2269 = and(_T_2267, _T_2268)
node _uncommonBits_T_235 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_235 = bits(_uncommonBits_T_235, 4, 0)
node _T_2270 = shr(io.in.a.bits.source, 5)
node _T_2271 = eq(_T_2270, UInt<3>(0h6))
node _T_2272 = leq(UInt<1>(0h0), uncommonBits_235)
node _T_2273 = and(_T_2271, _T_2272)
node _T_2274 = leq(uncommonBits_235, UInt<5>(0h1f))
node _T_2275 = and(_T_2273, _T_2274)
node _uncommonBits_T_236 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_236 = bits(_uncommonBits_T_236, 4, 0)
node _T_2276 = shr(io.in.a.bits.source, 5)
node _T_2277 = eq(_T_2276, UInt<3>(0h5))
node _T_2278 = leq(UInt<1>(0h0), uncommonBits_236)
node _T_2279 = and(_T_2277, _T_2278)
node _T_2280 = leq(uncommonBits_236, UInt<5>(0h1f))
node _T_2281 = and(_T_2279, _T_2280)
node _uncommonBits_T_237 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_237 = bits(_uncommonBits_T_237, 4, 0)
node _T_2282 = shr(io.in.a.bits.source, 5)
node _T_2283 = eq(_T_2282, UInt<3>(0h4))
node _T_2284 = leq(UInt<1>(0h0), uncommonBits_237)
node _T_2285 = and(_T_2283, _T_2284)
node _T_2286 = leq(uncommonBits_237, UInt<5>(0h1f))
node _T_2287 = and(_T_2285, _T_2286)
node _uncommonBits_T_238 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_238 = bits(_uncommonBits_T_238, 4, 0)
node _T_2288 = shr(io.in.a.bits.source, 5)
node _T_2289 = eq(_T_2288, UInt<2>(0h3))
node _T_2290 = leq(UInt<1>(0h0), uncommonBits_238)
node _T_2291 = and(_T_2289, _T_2290)
node _T_2292 = leq(uncommonBits_238, UInt<5>(0h1f))
node _T_2293 = and(_T_2291, _T_2292)
node _uncommonBits_T_239 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_239 = bits(_uncommonBits_T_239, 4, 0)
node _T_2294 = shr(io.in.a.bits.source, 5)
node _T_2295 = eq(_T_2294, UInt<2>(0h2))
node _T_2296 = leq(UInt<1>(0h0), uncommonBits_239)
node _T_2297 = and(_T_2295, _T_2296)
node _T_2298 = leq(uncommonBits_239, UInt<5>(0h1f))
node _T_2299 = and(_T_2297, _T_2298)
node _uncommonBits_T_240 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_240 = bits(_uncommonBits_T_240, 4, 0)
node _T_2300 = shr(io.in.a.bits.source, 5)
node _T_2301 = eq(_T_2300, UInt<1>(0h1))
node _T_2302 = leq(UInt<1>(0h0), uncommonBits_240)
node _T_2303 = and(_T_2301, _T_2302)
node _T_2304 = leq(uncommonBits_240, UInt<5>(0h1f))
node _T_2305 = and(_T_2303, _T_2304)
node _uncommonBits_T_241 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_241 = bits(_uncommonBits_T_241, 4, 0)
node _T_2306 = shr(io.in.a.bits.source, 5)
node _T_2307 = eq(_T_2306, UInt<1>(0h0))
node _T_2308 = leq(UInt<1>(0h0), uncommonBits_241)
node _T_2309 = and(_T_2307, _T_2308)
node _T_2310 = leq(uncommonBits_241, UInt<5>(0h1f))
node _T_2311 = and(_T_2309, _T_2310)
node _T_2312 = eq(io.in.a.bits.source, UInt<9>(0h1e0))
node _T_2313 = eq(io.in.a.bits.source, UInt<9>(0h1e1))
node _T_2314 = eq(io.in.a.bits.source, UInt<9>(0h1e2))
node _T_2315 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_2316 = or(_T_2179, _T_2185)
node _T_2317 = or(_T_2316, _T_2191)
node _T_2318 = or(_T_2317, _T_2197)
node _T_2319 = or(_T_2318, _T_2203)
node _T_2320 = or(_T_2319, _T_2209)
node _T_2321 = or(_T_2320, _T_2215)
node _T_2322 = or(_T_2321, _T_2221)
node _T_2323 = or(_T_2322, _T_2227)
node _T_2324 = or(_T_2323, _T_2233)
node _T_2325 = or(_T_2324, _T_2239)
node _T_2326 = or(_T_2325, _T_2245)
node _T_2327 = or(_T_2326, _T_2251)
node _T_2328 = or(_T_2327, _T_2257)
node _T_2329 = or(_T_2328, _T_2263)
node _T_2330 = or(_T_2329, _T_2269)
node _T_2331 = or(_T_2330, _T_2275)
node _T_2332 = or(_T_2331, _T_2281)
node _T_2333 = or(_T_2332, _T_2287)
node _T_2334 = or(_T_2333, _T_2293)
node _T_2335 = or(_T_2334, _T_2299)
node _T_2336 = or(_T_2335, _T_2305)
node _T_2337 = or(_T_2336, _T_2311)
node _T_2338 = or(_T_2337, _T_2312)
node _T_2339 = or(_T_2338, _T_2313)
node _T_2340 = or(_T_2339, _T_2314)
node _T_2341 = or(_T_2340, _T_2315)
node _T_2342 = and(_T_2178, _T_2341)
node _T_2343 = or(UInt<1>(0h0), _T_2342)
node _T_2344 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2345 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_2346 = cvt(_T_2345)
node _T_2347 = and(_T_2346, asSInt(UInt<13>(0h1000)))
node _T_2348 = asSInt(_T_2347)
node _T_2349 = eq(_T_2348, asSInt(UInt<1>(0h0)))
node _T_2350 = and(_T_2344, _T_2349)
node _T_2351 = or(UInt<1>(0h0), _T_2350)
node _T_2352 = and(_T_2343, _T_2351)
node _T_2353 = asUInt(reset)
node _T_2354 = eq(_T_2353, UInt<1>(0h0))
when _T_2354 :
node _T_2355 = eq(_T_2352, UInt<1>(0h0))
when _T_2355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_2352, UInt<1>(0h1), "") : assert_46
node _T_2356 = asUInt(reset)
node _T_2357 = eq(_T_2356, UInt<1>(0h0))
when _T_2357 :
node _T_2358 = eq(source_ok, UInt<1>(0h0))
when _T_2358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_2359 = asUInt(reset)
node _T_2360 = eq(_T_2359, UInt<1>(0h0))
when _T_2360 :
node _T_2361 = eq(is_aligned, UInt<1>(0h0))
when _T_2361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_2362 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_2363 = asUInt(reset)
node _T_2364 = eq(_T_2363, UInt<1>(0h0))
when _T_2364 :
node _T_2365 = eq(_T_2362, UInt<1>(0h0))
when _T_2365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_2362, UInt<1>(0h1), "") : assert_49
node _T_2366 = eq(io.in.a.bits.mask, mask)
node _T_2367 = asUInt(reset)
node _T_2368 = eq(_T_2367, UInt<1>(0h0))
when _T_2368 :
node _T_2369 = eq(_T_2366, UInt<1>(0h0))
when _T_2369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_2366, UInt<1>(0h1), "") : assert_50
node _T_2370 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_2371 = asUInt(reset)
node _T_2372 = eq(_T_2371, UInt<1>(0h0))
when _T_2372 :
node _T_2373 = eq(_T_2370, UInt<1>(0h0))
when _T_2373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_2370, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_2374 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2375 = asUInt(reset)
node _T_2376 = eq(_T_2375, UInt<1>(0h0))
when _T_2376 :
node _T_2377 = eq(_T_2374, UInt<1>(0h0))
when _T_2377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_2374, UInt<1>(0h1), "") : assert_52
node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<9>(0h1d0))
node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 1, 0)
node _source_ok_T_163 = shr(io.in.d.bits.source, 2)
node _source_ok_T_164 = eq(_source_ok_T_163, UInt<7>(0h70))
node _source_ok_T_165 = leq(UInt<1>(0h0), source_ok_uncommonBits_22)
node _source_ok_T_166 = and(_source_ok_T_164, _source_ok_T_165)
node _source_ok_T_167 = leq(source_ok_uncommonBits_22, UInt<2>(0h3))
node _source_ok_T_168 = and(_source_ok_T_166, _source_ok_T_167)
node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 1, 0)
node _source_ok_T_169 = shr(io.in.d.bits.source, 2)
node _source_ok_T_170 = eq(_source_ok_T_169, UInt<7>(0h71))
node _source_ok_T_171 = leq(UInt<1>(0h0), source_ok_uncommonBits_23)
node _source_ok_T_172 = and(_source_ok_T_170, _source_ok_T_171)
node _source_ok_T_173 = leq(source_ok_uncommonBits_23, UInt<2>(0h3))
node _source_ok_T_174 = and(_source_ok_T_172, _source_ok_T_173)
node _source_ok_uncommonBits_T_24 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_24 = bits(_source_ok_uncommonBits_T_24, 1, 0)
node _source_ok_T_175 = shr(io.in.d.bits.source, 2)
node _source_ok_T_176 = eq(_source_ok_T_175, UInt<7>(0h72))
node _source_ok_T_177 = leq(UInt<1>(0h0), source_ok_uncommonBits_24)
node _source_ok_T_178 = and(_source_ok_T_176, _source_ok_T_177)
node _source_ok_T_179 = leq(source_ok_uncommonBits_24, UInt<2>(0h3))
node _source_ok_T_180 = and(_source_ok_T_178, _source_ok_T_179)
node _source_ok_uncommonBits_T_25 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_25 = bits(_source_ok_uncommonBits_T_25, 1, 0)
node _source_ok_T_181 = shr(io.in.d.bits.source, 2)
node _source_ok_T_182 = eq(_source_ok_T_181, UInt<7>(0h73))
node _source_ok_T_183 = leq(UInt<1>(0h0), source_ok_uncommonBits_25)
node _source_ok_T_184 = and(_source_ok_T_182, _source_ok_T_183)
node _source_ok_T_185 = leq(source_ok_uncommonBits_25, UInt<2>(0h3))
node _source_ok_T_186 = and(_source_ok_T_184, _source_ok_T_185)
node _source_ok_uncommonBits_T_26 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_26 = bits(_source_ok_uncommonBits_T_26, 1, 0)
node _source_ok_T_187 = shr(io.in.d.bits.source, 2)
node _source_ok_T_188 = eq(_source_ok_T_187, UInt<7>(0h7c))
node _source_ok_T_189 = leq(UInt<1>(0h0), source_ok_uncommonBits_26)
node _source_ok_T_190 = and(_source_ok_T_188, _source_ok_T_189)
node _source_ok_T_191 = leq(source_ok_uncommonBits_26, UInt<2>(0h3))
node _source_ok_T_192 = and(_source_ok_T_190, _source_ok_T_191)
node _source_ok_uncommonBits_T_27 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_27 = bits(_source_ok_uncommonBits_T_27, 1, 0)
node _source_ok_T_193 = shr(io.in.d.bits.source, 2)
node _source_ok_T_194 = eq(_source_ok_T_193, UInt<7>(0h7b))
node _source_ok_T_195 = leq(UInt<1>(0h0), source_ok_uncommonBits_27)
node _source_ok_T_196 = and(_source_ok_T_194, _source_ok_T_195)
node _source_ok_T_197 = leq(source_ok_uncommonBits_27, UInt<2>(0h3))
node _source_ok_T_198 = and(_source_ok_T_196, _source_ok_T_197)
node _source_ok_uncommonBits_T_28 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_28 = bits(_source_ok_uncommonBits_T_28, 4, 0)
node _source_ok_T_199 = shr(io.in.d.bits.source, 5)
node _source_ok_T_200 = eq(_source_ok_T_199, UInt<4>(0hd))
node _source_ok_T_201 = leq(UInt<1>(0h0), source_ok_uncommonBits_28)
node _source_ok_T_202 = and(_source_ok_T_200, _source_ok_T_201)
node _source_ok_T_203 = leq(source_ok_uncommonBits_28, UInt<5>(0h1f))
node _source_ok_T_204 = and(_source_ok_T_202, _source_ok_T_203)
node _source_ok_uncommonBits_T_29 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_29 = bits(_source_ok_uncommonBits_T_29, 4, 0)
node _source_ok_T_205 = shr(io.in.d.bits.source, 5)
node _source_ok_T_206 = eq(_source_ok_T_205, UInt<4>(0hc))
node _source_ok_T_207 = leq(UInt<1>(0h0), source_ok_uncommonBits_29)
node _source_ok_T_208 = and(_source_ok_T_206, _source_ok_T_207)
node _source_ok_T_209 = leq(source_ok_uncommonBits_29, UInt<5>(0h1f))
node _source_ok_T_210 = and(_source_ok_T_208, _source_ok_T_209)
node _source_ok_uncommonBits_T_30 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_30 = bits(_source_ok_uncommonBits_T_30, 4, 0)
node _source_ok_T_211 = shr(io.in.d.bits.source, 5)
node _source_ok_T_212 = eq(_source_ok_T_211, UInt<4>(0hb))
node _source_ok_T_213 = leq(UInt<1>(0h0), source_ok_uncommonBits_30)
node _source_ok_T_214 = and(_source_ok_T_212, _source_ok_T_213)
node _source_ok_T_215 = leq(source_ok_uncommonBits_30, UInt<5>(0h1f))
node _source_ok_T_216 = and(_source_ok_T_214, _source_ok_T_215)
node _source_ok_uncommonBits_T_31 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_31 = bits(_source_ok_uncommonBits_T_31, 4, 0)
node _source_ok_T_217 = shr(io.in.d.bits.source, 5)
node _source_ok_T_218 = eq(_source_ok_T_217, UInt<4>(0ha))
node _source_ok_T_219 = leq(UInt<1>(0h0), source_ok_uncommonBits_31)
node _source_ok_T_220 = and(_source_ok_T_218, _source_ok_T_219)
node _source_ok_T_221 = leq(source_ok_uncommonBits_31, UInt<5>(0h1f))
node _source_ok_T_222 = and(_source_ok_T_220, _source_ok_T_221)
node _source_ok_uncommonBits_T_32 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_32 = bits(_source_ok_uncommonBits_T_32, 4, 0)
node _source_ok_T_223 = shr(io.in.d.bits.source, 5)
node _source_ok_T_224 = eq(_source_ok_T_223, UInt<4>(0h9))
node _source_ok_T_225 = leq(UInt<1>(0h0), source_ok_uncommonBits_32)
node _source_ok_T_226 = and(_source_ok_T_224, _source_ok_T_225)
node _source_ok_T_227 = leq(source_ok_uncommonBits_32, UInt<5>(0h1f))
node _source_ok_T_228 = and(_source_ok_T_226, _source_ok_T_227)
node _source_ok_uncommonBits_T_33 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_33 = bits(_source_ok_uncommonBits_T_33, 4, 0)
node _source_ok_T_229 = shr(io.in.d.bits.source, 5)
node _source_ok_T_230 = eq(_source_ok_T_229, UInt<4>(0h8))
node _source_ok_T_231 = leq(UInt<1>(0h0), source_ok_uncommonBits_33)
node _source_ok_T_232 = and(_source_ok_T_230, _source_ok_T_231)
node _source_ok_T_233 = leq(source_ok_uncommonBits_33, UInt<5>(0h1f))
node _source_ok_T_234 = and(_source_ok_T_232, _source_ok_T_233)
node _source_ok_uncommonBits_T_34 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_34 = bits(_source_ok_uncommonBits_T_34, 1, 0)
node _source_ok_T_235 = shr(io.in.d.bits.source, 2)
node _source_ok_T_236 = eq(_source_ok_T_235, UInt<7>(0h7a))
node _source_ok_T_237 = leq(UInt<1>(0h0), source_ok_uncommonBits_34)
node _source_ok_T_238 = and(_source_ok_T_236, _source_ok_T_237)
node _source_ok_T_239 = leq(source_ok_uncommonBits_34, UInt<2>(0h3))
node _source_ok_T_240 = and(_source_ok_T_238, _source_ok_T_239)
node _source_ok_uncommonBits_T_35 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_35 = bits(_source_ok_uncommonBits_T_35, 1, 0)
node _source_ok_T_241 = shr(io.in.d.bits.source, 2)
node _source_ok_T_242 = eq(_source_ok_T_241, UInt<7>(0h79))
node _source_ok_T_243 = leq(UInt<1>(0h0), source_ok_uncommonBits_35)
node _source_ok_T_244 = and(_source_ok_T_242, _source_ok_T_243)
node _source_ok_T_245 = leq(source_ok_uncommonBits_35, UInt<2>(0h3))
node _source_ok_T_246 = and(_source_ok_T_244, _source_ok_T_245)
node _source_ok_uncommonBits_T_36 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_36 = bits(_source_ok_uncommonBits_T_36, 4, 0)
node _source_ok_T_247 = shr(io.in.d.bits.source, 5)
node _source_ok_T_248 = eq(_source_ok_T_247, UInt<3>(0h7))
node _source_ok_T_249 = leq(UInt<1>(0h0), source_ok_uncommonBits_36)
node _source_ok_T_250 = and(_source_ok_T_248, _source_ok_T_249)
node _source_ok_T_251 = leq(source_ok_uncommonBits_36, UInt<5>(0h1f))
node _source_ok_T_252 = and(_source_ok_T_250, _source_ok_T_251)
node _source_ok_uncommonBits_T_37 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_37 = bits(_source_ok_uncommonBits_T_37, 4, 0)
node _source_ok_T_253 = shr(io.in.d.bits.source, 5)
node _source_ok_T_254 = eq(_source_ok_T_253, UInt<3>(0h6))
node _source_ok_T_255 = leq(UInt<1>(0h0), source_ok_uncommonBits_37)
node _source_ok_T_256 = and(_source_ok_T_254, _source_ok_T_255)
node _source_ok_T_257 = leq(source_ok_uncommonBits_37, UInt<5>(0h1f))
node _source_ok_T_258 = and(_source_ok_T_256, _source_ok_T_257)
node _source_ok_uncommonBits_T_38 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_38 = bits(_source_ok_uncommonBits_T_38, 4, 0)
node _source_ok_T_259 = shr(io.in.d.bits.source, 5)
node _source_ok_T_260 = eq(_source_ok_T_259, UInt<3>(0h5))
node _source_ok_T_261 = leq(UInt<1>(0h0), source_ok_uncommonBits_38)
node _source_ok_T_262 = and(_source_ok_T_260, _source_ok_T_261)
node _source_ok_T_263 = leq(source_ok_uncommonBits_38, UInt<5>(0h1f))
node _source_ok_T_264 = and(_source_ok_T_262, _source_ok_T_263)
node _source_ok_uncommonBits_T_39 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_39 = bits(_source_ok_uncommonBits_T_39, 4, 0)
node _source_ok_T_265 = shr(io.in.d.bits.source, 5)
node _source_ok_T_266 = eq(_source_ok_T_265, UInt<3>(0h4))
node _source_ok_T_267 = leq(UInt<1>(0h0), source_ok_uncommonBits_39)
node _source_ok_T_268 = and(_source_ok_T_266, _source_ok_T_267)
node _source_ok_T_269 = leq(source_ok_uncommonBits_39, UInt<5>(0h1f))
node _source_ok_T_270 = and(_source_ok_T_268, _source_ok_T_269)
node _source_ok_uncommonBits_T_40 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_40 = bits(_source_ok_uncommonBits_T_40, 4, 0)
node _source_ok_T_271 = shr(io.in.d.bits.source, 5)
node _source_ok_T_272 = eq(_source_ok_T_271, UInt<2>(0h3))
node _source_ok_T_273 = leq(UInt<1>(0h0), source_ok_uncommonBits_40)
node _source_ok_T_274 = and(_source_ok_T_272, _source_ok_T_273)
node _source_ok_T_275 = leq(source_ok_uncommonBits_40, UInt<5>(0h1f))
node _source_ok_T_276 = and(_source_ok_T_274, _source_ok_T_275)
node _source_ok_uncommonBits_T_41 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_41 = bits(_source_ok_uncommonBits_T_41, 4, 0)
node _source_ok_T_277 = shr(io.in.d.bits.source, 5)
node _source_ok_T_278 = eq(_source_ok_T_277, UInt<2>(0h2))
node _source_ok_T_279 = leq(UInt<1>(0h0), source_ok_uncommonBits_41)
node _source_ok_T_280 = and(_source_ok_T_278, _source_ok_T_279)
node _source_ok_T_281 = leq(source_ok_uncommonBits_41, UInt<5>(0h1f))
node _source_ok_T_282 = and(_source_ok_T_280, _source_ok_T_281)
node _source_ok_uncommonBits_T_42 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_42 = bits(_source_ok_uncommonBits_T_42, 4, 0)
node _source_ok_T_283 = shr(io.in.d.bits.source, 5)
node _source_ok_T_284 = eq(_source_ok_T_283, UInt<1>(0h1))
node _source_ok_T_285 = leq(UInt<1>(0h0), source_ok_uncommonBits_42)
node _source_ok_T_286 = and(_source_ok_T_284, _source_ok_T_285)
node _source_ok_T_287 = leq(source_ok_uncommonBits_42, UInt<5>(0h1f))
node _source_ok_T_288 = and(_source_ok_T_286, _source_ok_T_287)
node _source_ok_uncommonBits_T_43 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_43 = bits(_source_ok_uncommonBits_T_43, 4, 0)
node _source_ok_T_289 = shr(io.in.d.bits.source, 5)
node _source_ok_T_290 = eq(_source_ok_T_289, UInt<1>(0h0))
node _source_ok_T_291 = leq(UInt<1>(0h0), source_ok_uncommonBits_43)
node _source_ok_T_292 = and(_source_ok_T_290, _source_ok_T_291)
node _source_ok_T_293 = leq(source_ok_uncommonBits_43, UInt<5>(0h1f))
node _source_ok_T_294 = and(_source_ok_T_292, _source_ok_T_293)
node _source_ok_T_295 = eq(io.in.d.bits.source, UInt<9>(0h1e0))
node _source_ok_T_296 = eq(io.in.d.bits.source, UInt<9>(0h1e1))
node _source_ok_T_297 = eq(io.in.d.bits.source, UInt<9>(0h1e2))
node _source_ok_T_298 = eq(io.in.d.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE_1 : UInt<1>[27]
connect _source_ok_WIRE_1[0], _source_ok_T_162
connect _source_ok_WIRE_1[1], _source_ok_T_168
connect _source_ok_WIRE_1[2], _source_ok_T_174
connect _source_ok_WIRE_1[3], _source_ok_T_180
connect _source_ok_WIRE_1[4], _source_ok_T_186
connect _source_ok_WIRE_1[5], _source_ok_T_192
connect _source_ok_WIRE_1[6], _source_ok_T_198
connect _source_ok_WIRE_1[7], _source_ok_T_204
connect _source_ok_WIRE_1[8], _source_ok_T_210
connect _source_ok_WIRE_1[9], _source_ok_T_216
connect _source_ok_WIRE_1[10], _source_ok_T_222
connect _source_ok_WIRE_1[11], _source_ok_T_228
connect _source_ok_WIRE_1[12], _source_ok_T_234
connect _source_ok_WIRE_1[13], _source_ok_T_240
connect _source_ok_WIRE_1[14], _source_ok_T_246
connect _source_ok_WIRE_1[15], _source_ok_T_252
connect _source_ok_WIRE_1[16], _source_ok_T_258
connect _source_ok_WIRE_1[17], _source_ok_T_264
connect _source_ok_WIRE_1[18], _source_ok_T_270
connect _source_ok_WIRE_1[19], _source_ok_T_276
connect _source_ok_WIRE_1[20], _source_ok_T_282
connect _source_ok_WIRE_1[21], _source_ok_T_288
connect _source_ok_WIRE_1[22], _source_ok_T_294
connect _source_ok_WIRE_1[23], _source_ok_T_295
connect _source_ok_WIRE_1[24], _source_ok_T_296
connect _source_ok_WIRE_1[25], _source_ok_T_297
connect _source_ok_WIRE_1[26], _source_ok_T_298
node _source_ok_T_299 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_300 = or(_source_ok_T_299, _source_ok_WIRE_1[2])
node _source_ok_T_301 = or(_source_ok_T_300, _source_ok_WIRE_1[3])
node _source_ok_T_302 = or(_source_ok_T_301, _source_ok_WIRE_1[4])
node _source_ok_T_303 = or(_source_ok_T_302, _source_ok_WIRE_1[5])
node _source_ok_T_304 = or(_source_ok_T_303, _source_ok_WIRE_1[6])
node _source_ok_T_305 = or(_source_ok_T_304, _source_ok_WIRE_1[7])
node _source_ok_T_306 = or(_source_ok_T_305, _source_ok_WIRE_1[8])
node _source_ok_T_307 = or(_source_ok_T_306, _source_ok_WIRE_1[9])
node _source_ok_T_308 = or(_source_ok_T_307, _source_ok_WIRE_1[10])
node _source_ok_T_309 = or(_source_ok_T_308, _source_ok_WIRE_1[11])
node _source_ok_T_310 = or(_source_ok_T_309, _source_ok_WIRE_1[12])
node _source_ok_T_311 = or(_source_ok_T_310, _source_ok_WIRE_1[13])
node _source_ok_T_312 = or(_source_ok_T_311, _source_ok_WIRE_1[14])
node _source_ok_T_313 = or(_source_ok_T_312, _source_ok_WIRE_1[15])
node _source_ok_T_314 = or(_source_ok_T_313, _source_ok_WIRE_1[16])
node _source_ok_T_315 = or(_source_ok_T_314, _source_ok_WIRE_1[17])
node _source_ok_T_316 = or(_source_ok_T_315, _source_ok_WIRE_1[18])
node _source_ok_T_317 = or(_source_ok_T_316, _source_ok_WIRE_1[19])
node _source_ok_T_318 = or(_source_ok_T_317, _source_ok_WIRE_1[20])
node _source_ok_T_319 = or(_source_ok_T_318, _source_ok_WIRE_1[21])
node _source_ok_T_320 = or(_source_ok_T_319, _source_ok_WIRE_1[22])
node _source_ok_T_321 = or(_source_ok_T_320, _source_ok_WIRE_1[23])
node _source_ok_T_322 = or(_source_ok_T_321, _source_ok_WIRE_1[24])
node _source_ok_T_323 = or(_source_ok_T_322, _source_ok_WIRE_1[25])
node source_ok_1 = or(_source_ok_T_323, _source_ok_WIRE_1[26])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_2378 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_2378 :
node _T_2379 = asUInt(reset)
node _T_2380 = eq(_T_2379, UInt<1>(0h0))
when _T_2380 :
node _T_2381 = eq(source_ok_1, UInt<1>(0h0))
when _T_2381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_2382 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2383 = asUInt(reset)
node _T_2384 = eq(_T_2383, UInt<1>(0h0))
when _T_2384 :
node _T_2385 = eq(_T_2382, UInt<1>(0h0))
when _T_2385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_2382, UInt<1>(0h1), "") : assert_54
node _T_2386 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2387 = asUInt(reset)
node _T_2388 = eq(_T_2387, UInt<1>(0h0))
when _T_2388 :
node _T_2389 = eq(_T_2386, UInt<1>(0h0))
when _T_2389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_2386, UInt<1>(0h1), "") : assert_55
node _T_2390 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2391 = asUInt(reset)
node _T_2392 = eq(_T_2391, UInt<1>(0h0))
when _T_2392 :
node _T_2393 = eq(_T_2390, UInt<1>(0h0))
when _T_2393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_2390, UInt<1>(0h1), "") : assert_56
node _T_2394 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2395 = asUInt(reset)
node _T_2396 = eq(_T_2395, UInt<1>(0h0))
when _T_2396 :
node _T_2397 = eq(_T_2394, UInt<1>(0h0))
when _T_2397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_2394, UInt<1>(0h1), "") : assert_57
node _T_2398 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_2398 :
node _T_2399 = asUInt(reset)
node _T_2400 = eq(_T_2399, UInt<1>(0h0))
when _T_2400 :
node _T_2401 = eq(source_ok_1, UInt<1>(0h0))
when _T_2401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_2402 = asUInt(reset)
node _T_2403 = eq(_T_2402, UInt<1>(0h0))
when _T_2403 :
node _T_2404 = eq(sink_ok, UInt<1>(0h0))
when _T_2404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_2405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_60
node _T_2409 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_61
node _T_2413 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2414 = asUInt(reset)
node _T_2415 = eq(_T_2414, UInt<1>(0h0))
when _T_2415 :
node _T_2416 = eq(_T_2413, UInt<1>(0h0))
when _T_2416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_2413, UInt<1>(0h1), "") : assert_62
node _T_2417 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2418 = asUInt(reset)
node _T_2419 = eq(_T_2418, UInt<1>(0h0))
when _T_2419 :
node _T_2420 = eq(_T_2417, UInt<1>(0h0))
when _T_2420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_2417, UInt<1>(0h1), "") : assert_63
node _T_2421 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2422 = or(UInt<1>(0h0), _T_2421)
node _T_2423 = asUInt(reset)
node _T_2424 = eq(_T_2423, UInt<1>(0h0))
when _T_2424 :
node _T_2425 = eq(_T_2422, UInt<1>(0h0))
when _T_2425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_2422, UInt<1>(0h1), "") : assert_64
node _T_2426 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_2426 :
node _T_2427 = asUInt(reset)
node _T_2428 = eq(_T_2427, UInt<1>(0h0))
when _T_2428 :
node _T_2429 = eq(source_ok_1, UInt<1>(0h0))
when _T_2429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_2430 = asUInt(reset)
node _T_2431 = eq(_T_2430, UInt<1>(0h0))
when _T_2431 :
node _T_2432 = eq(sink_ok, UInt<1>(0h0))
when _T_2432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_2433 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2434 = asUInt(reset)
node _T_2435 = eq(_T_2434, UInt<1>(0h0))
when _T_2435 :
node _T_2436 = eq(_T_2433, UInt<1>(0h0))
when _T_2436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_2433, UInt<1>(0h1), "") : assert_67
node _T_2437 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2438 = asUInt(reset)
node _T_2439 = eq(_T_2438, UInt<1>(0h0))
when _T_2439 :
node _T_2440 = eq(_T_2437, UInt<1>(0h0))
when _T_2440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_2437, UInt<1>(0h1), "") : assert_68
node _T_2441 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2442 = asUInt(reset)
node _T_2443 = eq(_T_2442, UInt<1>(0h0))
when _T_2443 :
node _T_2444 = eq(_T_2441, UInt<1>(0h0))
when _T_2444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_2441, UInt<1>(0h1), "") : assert_69
node _T_2445 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2446 = or(_T_2445, io.in.d.bits.corrupt)
node _T_2447 = asUInt(reset)
node _T_2448 = eq(_T_2447, UInt<1>(0h0))
when _T_2448 :
node _T_2449 = eq(_T_2446, UInt<1>(0h0))
when _T_2449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_2446, UInt<1>(0h1), "") : assert_70
node _T_2450 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2451 = or(UInt<1>(0h0), _T_2450)
node _T_2452 = asUInt(reset)
node _T_2453 = eq(_T_2452, UInt<1>(0h0))
when _T_2453 :
node _T_2454 = eq(_T_2451, UInt<1>(0h0))
when _T_2454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_2451, UInt<1>(0h1), "") : assert_71
node _T_2455 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_2455 :
node _T_2456 = asUInt(reset)
node _T_2457 = eq(_T_2456, UInt<1>(0h0))
when _T_2457 :
node _T_2458 = eq(source_ok_1, UInt<1>(0h0))
when _T_2458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_2459 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2460 = asUInt(reset)
node _T_2461 = eq(_T_2460, UInt<1>(0h0))
when _T_2461 :
node _T_2462 = eq(_T_2459, UInt<1>(0h0))
when _T_2462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_2459, UInt<1>(0h1), "") : assert_73
node _T_2463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2464 = asUInt(reset)
node _T_2465 = eq(_T_2464, UInt<1>(0h0))
when _T_2465 :
node _T_2466 = eq(_T_2463, UInt<1>(0h0))
when _T_2466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_2463, UInt<1>(0h1), "") : assert_74
node _T_2467 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2468 = or(UInt<1>(0h0), _T_2467)
node _T_2469 = asUInt(reset)
node _T_2470 = eq(_T_2469, UInt<1>(0h0))
when _T_2470 :
node _T_2471 = eq(_T_2468, UInt<1>(0h0))
when _T_2471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_2468, UInt<1>(0h1), "") : assert_75
node _T_2472 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_2472 :
node _T_2473 = asUInt(reset)
node _T_2474 = eq(_T_2473, UInt<1>(0h0))
when _T_2474 :
node _T_2475 = eq(source_ok_1, UInt<1>(0h0))
when _T_2475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_2476 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2477 = asUInt(reset)
node _T_2478 = eq(_T_2477, UInt<1>(0h0))
when _T_2478 :
node _T_2479 = eq(_T_2476, UInt<1>(0h0))
when _T_2479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_2476, UInt<1>(0h1), "") : assert_77
node _T_2480 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2481 = or(_T_2480, io.in.d.bits.corrupt)
node _T_2482 = asUInt(reset)
node _T_2483 = eq(_T_2482, UInt<1>(0h0))
when _T_2483 :
node _T_2484 = eq(_T_2481, UInt<1>(0h0))
when _T_2484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_2481, UInt<1>(0h1), "") : assert_78
node _T_2485 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2486 = or(UInt<1>(0h0), _T_2485)
node _T_2487 = asUInt(reset)
node _T_2488 = eq(_T_2487, UInt<1>(0h0))
when _T_2488 :
node _T_2489 = eq(_T_2486, UInt<1>(0h0))
when _T_2489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_2486, UInt<1>(0h1), "") : assert_79
node _T_2490 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_2490 :
node _T_2491 = asUInt(reset)
node _T_2492 = eq(_T_2491, UInt<1>(0h0))
when _T_2492 :
node _T_2493 = eq(source_ok_1, UInt<1>(0h0))
when _T_2493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_2494 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2495 = asUInt(reset)
node _T_2496 = eq(_T_2495, UInt<1>(0h0))
when _T_2496 :
node _T_2497 = eq(_T_2494, UInt<1>(0h0))
when _T_2497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_2494, UInt<1>(0h1), "") : assert_81
node _T_2498 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2499 = asUInt(reset)
node _T_2500 = eq(_T_2499, UInt<1>(0h0))
when _T_2500 :
node _T_2501 = eq(_T_2498, UInt<1>(0h0))
when _T_2501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_2498, UInt<1>(0h1), "") : assert_82
node _T_2502 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2503 = or(UInt<1>(0h0), _T_2502)
node _T_2504 = asUInt(reset)
node _T_2505 = eq(_T_2504, UInt<1>(0h0))
when _T_2505 :
node _T_2506 = eq(_T_2503, UInt<1>(0h0))
when _T_2506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_2503, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<10>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_2507 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_2508 = asUInt(reset)
node _T_2509 = eq(_T_2508, UInt<1>(0h0))
when _T_2509 :
node _T_2510 = eq(_T_2507, UInt<1>(0h0))
when _T_2510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_2507, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<10>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_2511 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_2512 = asUInt(reset)
node _T_2513 = eq(_T_2512, UInt<1>(0h0))
when _T_2513 :
node _T_2514 = eq(_T_2511, UInt<1>(0h0))
when _T_2514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_2511, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_2515 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_2516 = asUInt(reset)
node _T_2517 = eq(_T_2516, UInt<1>(0h0))
when _T_2517 :
node _T_2518 = eq(_T_2515, UInt<1>(0h0))
when _T_2518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_2515, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2519 = eq(a_first, UInt<1>(0h0))
node _T_2520 = and(io.in.a.valid, _T_2519)
when _T_2520 :
node _T_2521 = eq(io.in.a.bits.opcode, opcode)
node _T_2522 = asUInt(reset)
node _T_2523 = eq(_T_2522, UInt<1>(0h0))
when _T_2523 :
node _T_2524 = eq(_T_2521, UInt<1>(0h0))
when _T_2524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_2521, UInt<1>(0h1), "") : assert_87
node _T_2525 = eq(io.in.a.bits.param, param)
node _T_2526 = asUInt(reset)
node _T_2527 = eq(_T_2526, UInt<1>(0h0))
when _T_2527 :
node _T_2528 = eq(_T_2525, UInt<1>(0h0))
when _T_2528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_2525, UInt<1>(0h1), "") : assert_88
node _T_2529 = eq(io.in.a.bits.size, size)
node _T_2530 = asUInt(reset)
node _T_2531 = eq(_T_2530, UInt<1>(0h0))
when _T_2531 :
node _T_2532 = eq(_T_2529, UInt<1>(0h0))
when _T_2532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_2529, UInt<1>(0h1), "") : assert_89
node _T_2533 = eq(io.in.a.bits.source, source)
node _T_2534 = asUInt(reset)
node _T_2535 = eq(_T_2534, UInt<1>(0h0))
when _T_2535 :
node _T_2536 = eq(_T_2533, UInt<1>(0h0))
when _T_2536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_2533, UInt<1>(0h1), "") : assert_90
node _T_2537 = eq(io.in.a.bits.address, address)
node _T_2538 = asUInt(reset)
node _T_2539 = eq(_T_2538, UInt<1>(0h0))
when _T_2539 :
node _T_2540 = eq(_T_2537, UInt<1>(0h0))
when _T_2540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_2537, UInt<1>(0h1), "") : assert_91
node _T_2541 = and(io.in.a.ready, io.in.a.valid)
node _T_2542 = and(_T_2541, a_first)
when _T_2542 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2543 = eq(d_first, UInt<1>(0h0))
node _T_2544 = and(io.in.d.valid, _T_2543)
when _T_2544 :
node _T_2545 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2546 = asUInt(reset)
node _T_2547 = eq(_T_2546, UInt<1>(0h0))
when _T_2547 :
node _T_2548 = eq(_T_2545, UInt<1>(0h0))
when _T_2548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_2545, UInt<1>(0h1), "") : assert_92
node _T_2549 = eq(io.in.d.bits.param, param_1)
node _T_2550 = asUInt(reset)
node _T_2551 = eq(_T_2550, UInt<1>(0h0))
when _T_2551 :
node _T_2552 = eq(_T_2549, UInt<1>(0h0))
when _T_2552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_2549, UInt<1>(0h1), "") : assert_93
node _T_2553 = eq(io.in.d.bits.size, size_1)
node _T_2554 = asUInt(reset)
node _T_2555 = eq(_T_2554, UInt<1>(0h0))
when _T_2555 :
node _T_2556 = eq(_T_2553, UInt<1>(0h0))
when _T_2556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_2553, UInt<1>(0h1), "") : assert_94
node _T_2557 = eq(io.in.d.bits.source, source_1)
node _T_2558 = asUInt(reset)
node _T_2559 = eq(_T_2558, UInt<1>(0h0))
when _T_2559 :
node _T_2560 = eq(_T_2557, UInt<1>(0h0))
when _T_2560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_2557, UInt<1>(0h1), "") : assert_95
node _T_2561 = eq(io.in.d.bits.sink, sink)
node _T_2562 = asUInt(reset)
node _T_2563 = eq(_T_2562, UInt<1>(0h0))
when _T_2563 :
node _T_2564 = eq(_T_2561, UInt<1>(0h0))
when _T_2564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_2561, UInt<1>(0h1), "") : assert_96
node _T_2565 = eq(io.in.d.bits.denied, denied)
node _T_2566 = asUInt(reset)
node _T_2567 = eq(_T_2566, UInt<1>(0h0))
when _T_2567 :
node _T_2568 = eq(_T_2565, UInt<1>(0h0))
when _T_2568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_2565, UInt<1>(0h1), "") : assert_97
node _T_2569 = and(io.in.d.ready, io.in.d.valid)
node _T_2570 = and(_T_2569, d_first)
when _T_2570 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes : UInt<2052>, clock, reset, UInt<2052>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<513>
connect a_set, UInt<513>(0h0)
wire a_set_wo_ready : UInt<513>
connect a_set_wo_ready, UInt<513>(0h0)
wire a_opcodes_set : UInt<2052>
connect a_opcodes_set, UInt<2052>(0h0)
wire a_sizes_set : UInt<2052>
connect a_sizes_set, UInt<2052>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_2571 = and(io.in.a.valid, a_first_1)
node _T_2572 = and(_T_2571, UInt<1>(0h1))
when _T_2572 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2573 = and(io.in.a.ready, io.in.a.valid)
node _T_2574 = and(_T_2573, a_first_1)
node _T_2575 = and(_T_2574, UInt<1>(0h1))
when _T_2575 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2576 = dshr(inflight, io.in.a.bits.source)
node _T_2577 = bits(_T_2576, 0, 0)
node _T_2578 = eq(_T_2577, UInt<1>(0h0))
node _T_2579 = asUInt(reset)
node _T_2580 = eq(_T_2579, UInt<1>(0h0))
when _T_2580 :
node _T_2581 = eq(_T_2578, UInt<1>(0h0))
when _T_2581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_2578, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<513>
connect d_clr, UInt<513>(0h0)
wire d_clr_wo_ready : UInt<513>
connect d_clr_wo_ready, UInt<513>(0h0)
wire d_opcodes_clr : UInt<2052>
connect d_opcodes_clr, UInt<2052>(0h0)
wire d_sizes_clr : UInt<2052>
connect d_sizes_clr, UInt<2052>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2582 = and(io.in.d.valid, d_first_1)
node _T_2583 = and(_T_2582, UInt<1>(0h1))
node _T_2584 = eq(d_release_ack, UInt<1>(0h0))
node _T_2585 = and(_T_2583, _T_2584)
when _T_2585 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2586 = and(io.in.d.ready, io.in.d.valid)
node _T_2587 = and(_T_2586, d_first_1)
node _T_2588 = and(_T_2587, UInt<1>(0h1))
node _T_2589 = eq(d_release_ack, UInt<1>(0h0))
node _T_2590 = and(_T_2588, _T_2589)
when _T_2590 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2591 = and(io.in.d.valid, d_first_1)
node _T_2592 = and(_T_2591, UInt<1>(0h1))
node _T_2593 = eq(d_release_ack, UInt<1>(0h0))
node _T_2594 = and(_T_2592, _T_2593)
when _T_2594 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2595 = dshr(inflight, io.in.d.bits.source)
node _T_2596 = bits(_T_2595, 0, 0)
node _T_2597 = or(_T_2596, same_cycle_resp)
node _T_2598 = asUInt(reset)
node _T_2599 = eq(_T_2598, UInt<1>(0h0))
when _T_2599 :
node _T_2600 = eq(_T_2597, UInt<1>(0h0))
when _T_2600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_2597, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_2601 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2602 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2603 = or(_T_2601, _T_2602)
node _T_2604 = asUInt(reset)
node _T_2605 = eq(_T_2604, UInt<1>(0h0))
when _T_2605 :
node _T_2606 = eq(_T_2603, UInt<1>(0h0))
when _T_2606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_2603, UInt<1>(0h1), "") : assert_100
node _T_2607 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2608 = asUInt(reset)
node _T_2609 = eq(_T_2608, UInt<1>(0h0))
when _T_2609 :
node _T_2610 = eq(_T_2607, UInt<1>(0h0))
when _T_2610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_2607, UInt<1>(0h1), "") : assert_101
else :
node _T_2611 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2612 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2613 = or(_T_2611, _T_2612)
node _T_2614 = asUInt(reset)
node _T_2615 = eq(_T_2614, UInt<1>(0h0))
when _T_2615 :
node _T_2616 = eq(_T_2613, UInt<1>(0h0))
when _T_2616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_2613, UInt<1>(0h1), "") : assert_102
node _T_2617 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2618 = asUInt(reset)
node _T_2619 = eq(_T_2618, UInt<1>(0h0))
when _T_2619 :
node _T_2620 = eq(_T_2617, UInt<1>(0h0))
when _T_2620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_2617, UInt<1>(0h1), "") : assert_103
node _T_2621 = and(io.in.d.valid, d_first_1)
node _T_2622 = and(_T_2621, a_first_1)
node _T_2623 = and(_T_2622, io.in.a.valid)
node _T_2624 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2625 = and(_T_2623, _T_2624)
node _T_2626 = eq(d_release_ack, UInt<1>(0h0))
node _T_2627 = and(_T_2625, _T_2626)
when _T_2627 :
node _T_2628 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2629 = or(_T_2628, io.in.a.ready)
node _T_2630 = asUInt(reset)
node _T_2631 = eq(_T_2630, UInt<1>(0h0))
when _T_2631 :
node _T_2632 = eq(_T_2629, UInt<1>(0h0))
when _T_2632 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_2629, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_229
node _T_2633 = orr(inflight)
node _T_2634 = eq(_T_2633, UInt<1>(0h0))
node _T_2635 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2636 = or(_T_2634, _T_2635)
node _T_2637 = lt(watchdog, plusarg_reader.out)
node _T_2638 = or(_T_2636, _T_2637)
node _T_2639 = asUInt(reset)
node _T_2640 = eq(_T_2639, UInt<1>(0h0))
when _T_2640 :
node _T_2641 = eq(_T_2638, UInt<1>(0h0))
when _T_2641 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_2638, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2642 = and(io.in.a.ready, io.in.a.valid)
node _T_2643 = and(io.in.d.ready, io.in.d.valid)
node _T_2644 = or(_T_2642, _T_2643)
when _T_2644 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<10>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<513>
connect c_set, UInt<513>(0h0)
wire c_set_wo_ready : UInt<513>
connect c_set_wo_ready, UInt<513>(0h0)
wire c_opcodes_set : UInt<2052>
connect c_opcodes_set, UInt<2052>(0h0)
wire c_sizes_set : UInt<2052>
connect c_sizes_set, UInt<2052>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<10>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_2645 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<10>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_2646 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_2647 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_2648 = and(_T_2646, _T_2647)
node _T_2649 = and(_T_2645, _T_2648)
when _T_2649 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<10>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_2650 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_2651 = and(_T_2650, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<10>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_2652 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_2653 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_2654 = and(_T_2652, _T_2653)
node _T_2655 = and(_T_2651, _T_2654)
when _T_2655 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<10>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_2656 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_2657 = bits(_T_2656, 0, 0)
node _T_2658 = eq(_T_2657, UInt<1>(0h0))
node _T_2659 = asUInt(reset)
node _T_2660 = eq(_T_2659, UInt<1>(0h0))
when _T_2660 :
node _T_2661 = eq(_T_2658, UInt<1>(0h0))
when _T_2661 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_2658, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<513>
connect d_clr_1, UInt<513>(0h0)
wire d_clr_wo_ready_1 : UInt<513>
connect d_clr_wo_ready_1, UInt<513>(0h0)
wire d_opcodes_clr_1 : UInt<2052>
connect d_opcodes_clr_1, UInt<2052>(0h0)
wire d_sizes_clr_1 : UInt<2052>
connect d_sizes_clr_1, UInt<2052>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2662 = and(io.in.d.valid, d_first_2)
node _T_2663 = and(_T_2662, UInt<1>(0h1))
node _T_2664 = and(_T_2663, d_release_ack_1)
when _T_2664 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2665 = and(io.in.d.ready, io.in.d.valid)
node _T_2666 = and(_T_2665, d_first_2)
node _T_2667 = and(_T_2666, UInt<1>(0h1))
node _T_2668 = and(_T_2667, d_release_ack_1)
when _T_2668 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2669 = and(io.in.d.valid, d_first_2)
node _T_2670 = and(_T_2669, UInt<1>(0h1))
node _T_2671 = and(_T_2670, d_release_ack_1)
when _T_2671 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2672 = dshr(inflight_1, io.in.d.bits.source)
node _T_2673 = bits(_T_2672, 0, 0)
node _T_2674 = or(_T_2673, same_cycle_resp_1)
node _T_2675 = asUInt(reset)
node _T_2676 = eq(_T_2675, UInt<1>(0h0))
when _T_2676 :
node _T_2677 = eq(_T_2674, UInt<1>(0h0))
when _T_2677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_2674, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<10>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_2678 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_2679 = asUInt(reset)
node _T_2680 = eq(_T_2679, UInt<1>(0h0))
when _T_2680 :
node _T_2681 = eq(_T_2678, UInt<1>(0h0))
when _T_2681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_2678, UInt<1>(0h1), "") : assert_108
else :
node _T_2682 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2683 = asUInt(reset)
node _T_2684 = eq(_T_2683, UInt<1>(0h0))
when _T_2684 :
node _T_2685 = eq(_T_2682, UInt<1>(0h0))
when _T_2685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_2682, UInt<1>(0h1), "") : assert_109
node _T_2686 = and(io.in.d.valid, d_first_2)
node _T_2687 = and(_T_2686, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<10>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_2688 = and(_T_2687, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<10>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_2689 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_2690 = and(_T_2688, _T_2689)
node _T_2691 = and(_T_2690, d_release_ack_1)
node _T_2692 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2693 = and(_T_2691, _T_2692)
when _T_2693 :
node _T_2694 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<10>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_2695 = or(_T_2694, _WIRE_27.ready)
node _T_2696 = asUInt(reset)
node _T_2697 = eq(_T_2696, UInt<1>(0h0))
when _T_2697 :
node _T_2698 = eq(_T_2695, UInt<1>(0h0))
when _T_2698 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_2695, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_230
node _T_2699 = orr(inflight_1)
node _T_2700 = eq(_T_2699, UInt<1>(0h0))
node _T_2701 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2702 = or(_T_2700, _T_2701)
node _T_2703 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2704 = or(_T_2702, _T_2703)
node _T_2705 = asUInt(reset)
node _T_2706 = eq(_T_2705, UInt<1>(0h0))
when _T_2706 :
node _T_2707 = eq(_T_2704, UInt<1>(0h0))
when _T_2707 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_2704, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<10>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_2708 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_2709 = and(io.in.d.ready, io.in.d.valid)
node _T_2710 = or(_T_2708, _T_2709)
when _T_2710 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_113( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [9:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [9:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_165 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_167 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_171 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_173 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_177 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_179 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_183 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_185 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_189 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_191 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_195 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_197 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_201 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_203 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_207 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_209 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_213 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_215 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_219 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_221 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_225 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_227 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_231 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_233 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_237 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_239 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_243 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_245 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_249 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_251 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_255 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_257 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_261 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_263 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_267 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_269 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_273 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_275 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_279 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_281 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_285 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_287 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_291 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_293 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_first_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_first_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_first_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_first_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_set_wo_ready_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_set_wo_ready_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_opcodes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_opcodes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_sizes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_sizes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_opcodes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_opcodes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_sizes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_sizes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_probe_ack_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_probe_ack_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_probe_ack_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_probe_ack_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _same_cycle_resp_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _same_cycle_resp_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _same_cycle_resp_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _same_cycle_resp_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _same_cycle_resp_WIRE_4_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _same_cycle_resp_WIRE_5_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [8194:0] _c_opcodes_set_T_1 = 8195'h0; // @[Monitor.scala:767:54]
wire [8194:0] _c_sizes_set_T_1 = 8195'h0; // @[Monitor.scala:768:52]
wire [12:0] _c_opcodes_set_T = 13'h0; // @[Monitor.scala:767:79]
wire [12:0] _c_sizes_set_T = 13'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [1023:0] _c_set_wo_ready_T = 1024'h1; // @[OneHot.scala:58:35]
wire [1023:0] _c_set_T = 1024'h1; // @[OneHot.scala:58:35]
wire [2051:0] c_opcodes_set = 2052'h0; // @[Monitor.scala:740:34]
wire [2051:0] c_sizes_set = 2052'h0; // @[Monitor.scala:741:34]
wire [512:0] c_set = 513'h0; // @[Monitor.scala:738:34]
wire [512:0] c_set_wo_ready = 513'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [9:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_77 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_78 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_79 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_80 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_81 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_82 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_83 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_84 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_85 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_86 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_87 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_88 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_89 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_90 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_91 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_92 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_93 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_94 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_95 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_96 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_97 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_98 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_99 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_100 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_101 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_102 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_103 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_104 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_105 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_106 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_107 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_108 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_109 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_110 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_111 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_112 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_113 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_114 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_115 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_116 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_117 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_118 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_119 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_120 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_121 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_122 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_123 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_124 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_125 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_126 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_127 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_128 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_129 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_130 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_131 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_132 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_133 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_134 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_135 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_136 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_137 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_138 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_139 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_140 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_141 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_142 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_143 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_144 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_145 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_146 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_147 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_148 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_149 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_150 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_151 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_152 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_153 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_154 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_155 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_156 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_157 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_158 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_159 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_160 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_161 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_162 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_163 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_164 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_165 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_166 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_167 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_168 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_169 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_170 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_171 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_172 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_173 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_174 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_175 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_176 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_177 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_178 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_179 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_180 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_181 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_182 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_183 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_184 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_185 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_186 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_187 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_188 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_189 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_190 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_191 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_192 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_193 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_194 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_195 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_196 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_197 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_198 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_199 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_200 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_201 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_202 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_203 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_204 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_205 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_206 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_207 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_208 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_209 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_210 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_211 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_212 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_213 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_214 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_215 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_216 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_217 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_218 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_219 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_220 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_221 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_222 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_223 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_224 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_225 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_226 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_227 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_228 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_229 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_230 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_231 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_232 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_233 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_234 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_235 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_236 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_237 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_238 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_239 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_240 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_241 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_22 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_23 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_24 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_25 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_26 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_27 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_28 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_29 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_30 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_31 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_32 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_33 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_34 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_35 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_36 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_37 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_38 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_39 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_40 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_41 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_42 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_43 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [7:0] _source_ok_T_1 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_7 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_13 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_19 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_25 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_31 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_73 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_79 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 8'h70; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 8'h71; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 8'h72; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 8'h73; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 8'h7C; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 8'h7B; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_61 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_67 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_85 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_91 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_97 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_103 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_109 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_115 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_121 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_127 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'hD; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'hC; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_8 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_9 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_10 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_62 = _source_ok_T_61 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_11 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_12 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 8'h7A; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_13 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_80 = _source_ok_T_79 == 8'h79; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_14 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 5'h7; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_15 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_92 = _source_ok_T_91 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_16 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_98 = _source_ok_T_97 == 5'h5; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_17 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_18 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_110 = _source_ok_T_109 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_19 = _source_ok_T_114; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_116 = _source_ok_T_115 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_20 = _source_ok_T_120; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_122 = _source_ok_T_121 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_21 = _source_ok_T_126; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_21 = _source_ok_uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_128 = _source_ok_T_127 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_22 = _source_ok_T_132; // @[Parameters.scala:1138:31]
wire _source_ok_T_133 = io_in_a_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_23 = _source_ok_T_133; // @[Parameters.scala:1138:31]
wire _source_ok_T_134 = io_in_a_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_24 = _source_ok_T_134; // @[Parameters.scala:1138:31]
wire _source_ok_T_135 = io_in_a_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_25 = _source_ok_T_135; // @[Parameters.scala:1138:31]
wire _source_ok_T_136 = io_in_a_bits_source_0 == 10'h200; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_26 = _source_ok_T_136; // @[Parameters.scala:1138:31]
wire _source_ok_T_137 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_156 = _source_ok_T_155 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_157 = _source_ok_T_156 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_158 = _source_ok_T_157 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_159 = _source_ok_T_158 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_160 = _source_ok_T_159 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_161 = _source_ok_T_160 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_161 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_72 = _uncommonBits_T_72[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_73 = _uncommonBits_T_73[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_74 = _uncommonBits_T_74[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_75 = _uncommonBits_T_75[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_76 = _uncommonBits_T_76[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_77 = _uncommonBits_T_77[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_80 = _uncommonBits_T_80[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_81 = _uncommonBits_T_81[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_84 = _uncommonBits_T_84[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_85 = _uncommonBits_T_85[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_86 = _uncommonBits_T_86[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_87 = _uncommonBits_T_87[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_96 = _uncommonBits_T_96[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_97 = _uncommonBits_T_97[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_98 = _uncommonBits_T_98[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_99 = _uncommonBits_T_99[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_102 = _uncommonBits_T_102[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_103 = _uncommonBits_T_103[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_104 = _uncommonBits_T_104[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_105 = _uncommonBits_T_105[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_108 = _uncommonBits_T_108[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_109 = _uncommonBits_T_109[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_110 = _uncommonBits_T_110[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_111 = _uncommonBits_T_111[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_116 = _uncommonBits_T_116[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_117 = _uncommonBits_T_117[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_118 = _uncommonBits_T_118[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_119 = _uncommonBits_T_119[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_120 = _uncommonBits_T_120[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_121 = _uncommonBits_T_121[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_123 = _uncommonBits_T_123[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_124 = _uncommonBits_T_124[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_125 = _uncommonBits_T_125[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_126 = _uncommonBits_T_126[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_127 = _uncommonBits_T_127[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_128 = _uncommonBits_T_128[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_129 = _uncommonBits_T_129[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_130 = _uncommonBits_T_130[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_131 = _uncommonBits_T_131[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_132 = _uncommonBits_T_132[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_133 = _uncommonBits_T_133[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_134 = _uncommonBits_T_134[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_135 = _uncommonBits_T_135[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_136 = _uncommonBits_T_136[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_137 = _uncommonBits_T_137[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_138 = _uncommonBits_T_138[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_139 = _uncommonBits_T_139[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_140 = _uncommonBits_T_140[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_141 = _uncommonBits_T_141[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_142 = _uncommonBits_T_142[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_143 = _uncommonBits_T_143[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_144 = _uncommonBits_T_144[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_145 = _uncommonBits_T_145[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_146 = _uncommonBits_T_146[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_147 = _uncommonBits_T_147[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_148 = _uncommonBits_T_148[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_149 = _uncommonBits_T_149[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_150 = _uncommonBits_T_150[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_151 = _uncommonBits_T_151[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_152 = _uncommonBits_T_152[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_153 = _uncommonBits_T_153[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_154 = _uncommonBits_T_154[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_155 = _uncommonBits_T_155[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_156 = _uncommonBits_T_156[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_157 = _uncommonBits_T_157[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_158 = _uncommonBits_T_158[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_159 = _uncommonBits_T_159[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_160 = _uncommonBits_T_160[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_161 = _uncommonBits_T_161[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_162 = _uncommonBits_T_162[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_163 = _uncommonBits_T_163[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_164 = _uncommonBits_T_164[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_165 = _uncommonBits_T_165[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_166 = _uncommonBits_T_166[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_167 = _uncommonBits_T_167[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_168 = _uncommonBits_T_168[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_169 = _uncommonBits_T_169[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_170 = _uncommonBits_T_170[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_171 = _uncommonBits_T_171[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_172 = _uncommonBits_T_172[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_173 = _uncommonBits_T_173[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_174 = _uncommonBits_T_174[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_175 = _uncommonBits_T_175[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_176 = _uncommonBits_T_176[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_177 = _uncommonBits_T_177[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_178 = _uncommonBits_T_178[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_179 = _uncommonBits_T_179[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_180 = _uncommonBits_T_180[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_181 = _uncommonBits_T_181[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_182 = _uncommonBits_T_182[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_183 = _uncommonBits_T_183[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_184 = _uncommonBits_T_184[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_185 = _uncommonBits_T_185[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_186 = _uncommonBits_T_186[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_187 = _uncommonBits_T_187[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_188 = _uncommonBits_T_188[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_189 = _uncommonBits_T_189[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_190 = _uncommonBits_T_190[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_191 = _uncommonBits_T_191[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_192 = _uncommonBits_T_192[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_193 = _uncommonBits_T_193[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_194 = _uncommonBits_T_194[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_195 = _uncommonBits_T_195[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_196 = _uncommonBits_T_196[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_197 = _uncommonBits_T_197[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_198 = _uncommonBits_T_198[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_199 = _uncommonBits_T_199[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_200 = _uncommonBits_T_200[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_201 = _uncommonBits_T_201[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_202 = _uncommonBits_T_202[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_203 = _uncommonBits_T_203[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_204 = _uncommonBits_T_204[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_205 = _uncommonBits_T_205[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_206 = _uncommonBits_T_206[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_207 = _uncommonBits_T_207[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_208 = _uncommonBits_T_208[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_209 = _uncommonBits_T_209[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_210 = _uncommonBits_T_210[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_211 = _uncommonBits_T_211[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_212 = _uncommonBits_T_212[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_213 = _uncommonBits_T_213[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_214 = _uncommonBits_T_214[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_215 = _uncommonBits_T_215[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_216 = _uncommonBits_T_216[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_217 = _uncommonBits_T_217[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_218 = _uncommonBits_T_218[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_219 = _uncommonBits_T_219[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_220 = _uncommonBits_T_220[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_221 = _uncommonBits_T_221[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_222 = _uncommonBits_T_222[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_223 = _uncommonBits_T_223[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_224 = _uncommonBits_T_224[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_225 = _uncommonBits_T_225[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_226 = _uncommonBits_T_226[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_227 = _uncommonBits_T_227[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_228 = _uncommonBits_T_228[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_229 = _uncommonBits_T_229[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_230 = _uncommonBits_T_230[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_231 = _uncommonBits_T_231[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_232 = _uncommonBits_T_232[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_233 = _uncommonBits_T_233[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_234 = _uncommonBits_T_234[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_235 = _uncommonBits_T_235[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_236 = _uncommonBits_T_236[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_237 = _uncommonBits_T_237[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_238 = _uncommonBits_T_238[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_239 = _uncommonBits_T_239[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_240 = _uncommonBits_T_240[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_241 = _uncommonBits_T_241[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_162 = io_in_d_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_162; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_22 = _source_ok_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [7:0] _source_ok_T_163 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_169 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_175 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_181 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_187 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_193 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_235 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_241 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_164 = _source_ok_T_163 == 8'h70; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_166 = _source_ok_T_164; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_168 = _source_ok_T_166; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_168; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_23 = _source_ok_uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_170 = _source_ok_T_169 == 8'h71; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_172 = _source_ok_T_170; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_174 = _source_ok_T_172; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_174; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_24 = _source_ok_uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_176 = _source_ok_T_175 == 8'h72; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_178 = _source_ok_T_176; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_180 = _source_ok_T_178; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_180; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_25 = _source_ok_uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_182 = _source_ok_T_181 == 8'h73; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_184 = _source_ok_T_182; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_186 = _source_ok_T_184; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_186; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_26 = _source_ok_uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_188 = _source_ok_T_187 == 8'h7C; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_190 = _source_ok_T_188; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_192 = _source_ok_T_190; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_192; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_27 = _source_ok_uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_194 = _source_ok_T_193 == 8'h7B; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_196 = _source_ok_T_194; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_198 = _source_ok_T_196; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_198; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_28 = _source_ok_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_199 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_205 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_211 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_217 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_223 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_229 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_247 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_253 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_259 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_265 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_271 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_277 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_283 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_289 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_200 = _source_ok_T_199 == 5'hD; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_202 = _source_ok_T_200; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_204 = _source_ok_T_202; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_204; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_29 = _source_ok_uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_206 = _source_ok_T_205 == 5'hC; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_208 = _source_ok_T_206; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_210 = _source_ok_T_208; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_8 = _source_ok_T_210; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_30 = _source_ok_uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_212 = _source_ok_T_211 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_214 = _source_ok_T_212; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_216 = _source_ok_T_214; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_9 = _source_ok_T_216; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_31 = _source_ok_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_218 = _source_ok_T_217 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_220 = _source_ok_T_218; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_222 = _source_ok_T_220; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_10 = _source_ok_T_222; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_32 = _source_ok_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_224 = _source_ok_T_223 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_226 = _source_ok_T_224; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_228 = _source_ok_T_226; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_11 = _source_ok_T_228; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_33 = _source_ok_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_230 = _source_ok_T_229 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_232 = _source_ok_T_230; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_234 = _source_ok_T_232; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_12 = _source_ok_T_234; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_34 = _source_ok_uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_236 = _source_ok_T_235 == 8'h7A; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_238 = _source_ok_T_236; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_240 = _source_ok_T_238; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_13 = _source_ok_T_240; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_35 = _source_ok_uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_242 = _source_ok_T_241 == 8'h79; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_244 = _source_ok_T_242; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_246 = _source_ok_T_244; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_14 = _source_ok_T_246; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_36 = _source_ok_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_248 = _source_ok_T_247 == 5'h7; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_250 = _source_ok_T_248; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_252 = _source_ok_T_250; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_15 = _source_ok_T_252; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_37 = _source_ok_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_254 = _source_ok_T_253 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_256 = _source_ok_T_254; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_258 = _source_ok_T_256; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_16 = _source_ok_T_258; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_38 = _source_ok_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_260 = _source_ok_T_259 == 5'h5; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_262 = _source_ok_T_260; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_264 = _source_ok_T_262; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_17 = _source_ok_T_264; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_39 = _source_ok_uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_266 = _source_ok_T_265 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_268 = _source_ok_T_266; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_270 = _source_ok_T_268; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_18 = _source_ok_T_270; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_40 = _source_ok_uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_272 = _source_ok_T_271 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_274 = _source_ok_T_272; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_276 = _source_ok_T_274; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_19 = _source_ok_T_276; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_41 = _source_ok_uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_278 = _source_ok_T_277 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_280 = _source_ok_T_278; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_282 = _source_ok_T_280; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_20 = _source_ok_T_282; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_42 = _source_ok_uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_284 = _source_ok_T_283 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_286 = _source_ok_T_284; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_288 = _source_ok_T_286; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_21 = _source_ok_T_288; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_43 = _source_ok_uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_290 = _source_ok_T_289 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_292 = _source_ok_T_290; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_294 = _source_ok_T_292; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_22 = _source_ok_T_294; // @[Parameters.scala:1138:31]
wire _source_ok_T_295 = io_in_d_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_23 = _source_ok_T_295; // @[Parameters.scala:1138:31]
wire _source_ok_T_296 = io_in_d_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_24 = _source_ok_T_296; // @[Parameters.scala:1138:31]
wire _source_ok_T_297 = io_in_d_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_25 = _source_ok_T_297; // @[Parameters.scala:1138:31]
wire _source_ok_T_298 = io_in_d_bits_source_0 == 10'h200; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_26 = _source_ok_T_298; // @[Parameters.scala:1138:31]
wire _source_ok_T_299 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_300 = _source_ok_T_299 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_301 = _source_ok_T_300 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_302 = _source_ok_T_301 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_303 = _source_ok_T_302 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_304 = _source_ok_T_303 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_305 = _source_ok_T_304 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_306 = _source_ok_T_305 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_307 = _source_ok_T_306 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_308 = _source_ok_T_307 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_309 = _source_ok_T_308 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_310 = _source_ok_T_309 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_311 = _source_ok_T_310 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_312 = _source_ok_T_311 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_313 = _source_ok_T_312 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_314 = _source_ok_T_313 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_315 = _source_ok_T_314 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_316 = _source_ok_T_315 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_317 = _source_ok_T_316 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_318 = _source_ok_T_317 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_319 = _source_ok_T_318 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_320 = _source_ok_T_319 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_321 = _source_ok_T_320 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_322 = _source_ok_T_321 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_323 = _source_ok_T_322 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_323 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46]
wire _T_2642 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2642; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2642; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [9:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_2710 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2710; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2710; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2710; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [9:0] source_1; // @[Monitor.scala:541:22]
reg [512:0] inflight; // @[Monitor.scala:614:27]
reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [512:0] a_set; // @[Monitor.scala:626:34]
wire [512:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [2051:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [2051:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [12:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [12:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [12:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [12:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [12:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [12:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [12:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [12:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [12:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [2051:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [2051:0] _a_opcode_lookup_T_6 = {2048'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [2051:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [2051:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [2051:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [2051:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2051:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1023:0] _GEN_2 = 1024'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [1023:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [1023:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire _T_2575 = _T_2642 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2575 ? _a_set_T[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2575 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2575 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [12:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [12:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [12:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [8194:0] _a_opcodes_set_T_1 = {8191'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2575 ? _a_opcodes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8194:0] _a_sizes_set_T_1 = {8191'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2575 ? _a_sizes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [512:0] d_clr; // @[Monitor.scala:664:34]
wire [512:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [2051:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [2051:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_2621 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1023:0] _GEN_5 = 1024'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [1023:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1023:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1023:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [1023:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2621 & ~d_release_ack ? _d_clr_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire _T_2590 = _T_2710 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2590 ? _d_clr_T[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire [8206:0] _d_opcodes_clr_T_5 = 8207'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2590 ? _d_opcodes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [8206:0] _d_sizes_clr_T_5 = 8207'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2590 ? _d_sizes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [512:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [512:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [512:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [2051:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [2051:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [2051:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [2051:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [2051:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [2051:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [512:0] inflight_1; // @[Monitor.scala:726:35]
wire [512:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [2051:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [2051:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [2051:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [2051:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [2051:0] _c_opcode_lookup_T_6 = {2048'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [2051:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [2051:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [2051:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [2051:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2051:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [512:0] d_clr_1; // @[Monitor.scala:774:34]
wire [512:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [2051:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [2051:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2686 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2686 & d_release_ack_1 ? _d_clr_wo_ready_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire _T_2668 = _T_2710 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2668 ? _d_clr_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire [8206:0] _d_opcodes_clr_T_11 = 8207'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2668 ? _d_opcodes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [8206:0] _d_sizes_clr_T_11 = 8207'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2668 ? _d_sizes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 10'h0; // @[Monitor.scala:36:7, :795:113]
wire [512:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [512:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [2051:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [2051:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [2051:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [2051:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<3>(0h7))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<3>(0h6))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 4, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 5)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<3>(0h5))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<5>(0h13))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 4, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 5)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<3>(0h4))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<5>(0h13))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0)
node _source_ok_T_24 = shr(io.in.a.bits.source, 5)
node _source_ok_T_25 = eq(_source_ok_T_24, UInt<2>(0h3))
node _source_ok_T_26 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_27 = and(_source_ok_T_25, _source_ok_T_26)
node _source_ok_T_28 = leq(source_ok_uncommonBits_4, UInt<5>(0h13))
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0)
node _source_ok_T_30 = shr(io.in.a.bits.source, 5)
node _source_ok_T_31 = eq(_source_ok_T_30, UInt<2>(0h2))
node _source_ok_T_32 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32)
node _source_ok_T_34 = leq(source_ok_uncommonBits_5, UInt<5>(0h13))
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0)
node _source_ok_T_36 = shr(io.in.a.bits.source, 5)
node _source_ok_T_37 = eq(_source_ok_T_36, UInt<1>(0h1))
node _source_ok_T_38 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38)
node _source_ok_T_40 = leq(source_ok_uncommonBits_6, UInt<5>(0h13))
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0)
node _source_ok_T_42 = shr(io.in.a.bits.source, 5)
node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0))
node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_T_46 = leq(source_ok_uncommonBits_7, UInt<5>(0h13))
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
wire _source_ok_WIRE : UInt<1>[8]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
connect _source_ok_WIRE[4], _source_ok_T_29
connect _source_ok_WIRE[5], _source_ok_T_35
connect _source_ok_WIRE[6], _source_ok_T_41
connect _source_ok_WIRE[7], _source_ok_T_47
node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6])
node source_ok = or(_source_ok_T_53, _source_ok_WIRE[7])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<3>(0h7))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<10>(0h1c0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_17 = shr(io.in.a.bits.source, 5)
node _T_18 = eq(_T_17, UInt<3>(0h6))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<10>(0h1c0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_30 = shr(io.in.a.bits.source, 5)
node _T_31 = eq(_T_30, UInt<3>(0h5))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<10>(0h1c0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_43 = shr(io.in.a.bits.source, 5)
node _T_44 = eq(_T_43, UInt<3>(0h4))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<8>(0hc0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<10>(0h1c0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_56 = shr(io.in.a.bits.source, 5)
node _T_57 = eq(_T_56, UInt<2>(0h3))
node _T_58 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_59 = and(_T_57, _T_58)
node _T_60 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(_T_61, UInt<1>(0h0))
node _T_63 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<10>(0h1c0)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = or(_T_62, _T_67)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_69 = shr(io.in.a.bits.source, 5)
node _T_70 = eq(_T_69, UInt<2>(0h2))
node _T_71 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_72 = and(_T_70, _T_71)
node _T_73 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = xor(io.in.a.bits.address, UInt<9>(0h140))
node _T_77 = cvt(_T_76)
node _T_78 = and(_T_77, asSInt(UInt<10>(0h1c0)))
node _T_79 = asSInt(_T_78)
node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0)))
node _T_81 = or(_T_75, _T_80)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_82 = shr(io.in.a.bits.source, 5)
node _T_83 = eq(_T_82, UInt<1>(0h1))
node _T_84 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_85 = and(_T_83, _T_84)
node _T_86 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(_T_87, UInt<1>(0h0))
node _T_89 = xor(io.in.a.bits.address, UInt<9>(0h180))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<10>(0h1c0)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = or(_T_88, _T_93)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_95 = shr(io.in.a.bits.source, 5)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_98 = and(_T_96, _T_97)
node _T_99 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_100 = and(_T_98, _T_99)
node _T_101 = eq(_T_100, UInt<1>(0h0))
node _T_102 = xor(io.in.a.bits.address, UInt<9>(0h1c0))
node _T_103 = cvt(_T_102)
node _T_104 = and(_T_103, asSInt(UInt<10>(0h1c0)))
node _T_105 = asSInt(_T_104)
node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0)))
node _T_107 = or(_T_101, _T_106)
node _T_108 = and(_T_16, _T_29)
node _T_109 = and(_T_108, _T_42)
node _T_110 = and(_T_109, _T_55)
node _T_111 = and(_T_110, _T_68)
node _T_112 = and(_T_111, _T_81)
node _T_113 = and(_T_112, _T_94)
node _T_114 = and(_T_113, _T_107)
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_114, UInt<1>(0h1), "") : assert_1
node _T_118 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_118 :
node _T_119 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_120 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_121 = and(_T_119, _T_120)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_122 = shr(io.in.a.bits.source, 5)
node _T_123 = eq(_T_122, UInt<3>(0h7))
node _T_124 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_125 = and(_T_123, _T_124)
node _T_126 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_127 = and(_T_125, _T_126)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0)
node _T_128 = shr(io.in.a.bits.source, 5)
node _T_129 = eq(_T_128, UInt<3>(0h6))
node _T_130 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_131 = and(_T_129, _T_130)
node _T_132 = leq(uncommonBits_9, UInt<5>(0h13))
node _T_133 = and(_T_131, _T_132)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0)
node _T_134 = shr(io.in.a.bits.source, 5)
node _T_135 = eq(_T_134, UInt<3>(0h5))
node _T_136 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_137 = and(_T_135, _T_136)
node _T_138 = leq(uncommonBits_10, UInt<5>(0h13))
node _T_139 = and(_T_137, _T_138)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0)
node _T_140 = shr(io.in.a.bits.source, 5)
node _T_141 = eq(_T_140, UInt<3>(0h4))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_11, UInt<5>(0h13))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 4, 0)
node _T_146 = shr(io.in.a.bits.source, 5)
node _T_147 = eq(_T_146, UInt<2>(0h3))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_12, UInt<5>(0h13))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 4, 0)
node _T_152 = shr(io.in.a.bits.source, 5)
node _T_153 = eq(_T_152, UInt<2>(0h2))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_13, UInt<5>(0h13))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0)
node _T_158 = shr(io.in.a.bits.source, 5)
node _T_159 = eq(_T_158, UInt<1>(0h1))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_14, UInt<5>(0h13))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0)
node _T_164 = shr(io.in.a.bits.source, 5)
node _T_165 = eq(_T_164, UInt<1>(0h0))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_15, UInt<5>(0h13))
node _T_169 = and(_T_167, _T_168)
node _T_170 = or(_T_127, _T_133)
node _T_171 = or(_T_170, _T_139)
node _T_172 = or(_T_171, _T_145)
node _T_173 = or(_T_172, _T_151)
node _T_174 = or(_T_173, _T_157)
node _T_175 = or(_T_174, _T_163)
node _T_176 = or(_T_175, _T_169)
node _T_177 = and(_T_121, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_180 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_181 = cvt(_T_180)
node _T_182 = and(_T_181, asSInt(UInt<29>(0h100000c0)))
node _T_183 = asSInt(_T_182)
node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0)))
node _T_185 = and(_T_179, _T_184)
node _T_186 = or(UInt<1>(0h0), _T_185)
node _T_187 = and(_T_178, _T_186)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_187, UInt<1>(0h1), "") : assert_2
node _T_191 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_192 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_193 = and(_T_191, _T_192)
node _T_194 = or(UInt<1>(0h0), _T_193)
node _T_195 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_196 = cvt(_T_195)
node _T_197 = and(_T_196, asSInt(UInt<29>(0h100000c0)))
node _T_198 = asSInt(_T_197)
node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0)))
node _T_200 = and(_T_194, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = and(UInt<1>(0h0), _T_201)
node _T_203 = asUInt(reset)
node _T_204 = eq(_T_203, UInt<1>(0h0))
when _T_204 :
node _T_205 = eq(_T_202, UInt<1>(0h0))
when _T_205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_202, UInt<1>(0h1), "") : assert_3
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(source_ok, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(_T_209, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_209, UInt<1>(0h1), "") : assert_5
node _T_213 = asUInt(reset)
node _T_214 = eq(_T_213, UInt<1>(0h0))
when _T_214 :
node _T_215 = eq(is_aligned, UInt<1>(0h0))
when _T_215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_216, UInt<1>(0h1), "") : assert_7
node _T_220 = not(io.in.a.bits.mask)
node _T_221 = eq(_T_220, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_221, UInt<1>(0h1), "") : assert_8
node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_225, UInt<1>(0h1), "") : assert_9
node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_229 :
node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_232 = and(_T_230, _T_231)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0)
node _T_233 = shr(io.in.a.bits.source, 5)
node _T_234 = eq(_T_233, UInt<3>(0h7))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_16, UInt<5>(0h13))
node _T_238 = and(_T_236, _T_237)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0)
node _T_239 = shr(io.in.a.bits.source, 5)
node _T_240 = eq(_T_239, UInt<3>(0h6))
node _T_241 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_242 = and(_T_240, _T_241)
node _T_243 = leq(uncommonBits_17, UInt<5>(0h13))
node _T_244 = and(_T_242, _T_243)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0)
node _T_245 = shr(io.in.a.bits.source, 5)
node _T_246 = eq(_T_245, UInt<3>(0h5))
node _T_247 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_248 = and(_T_246, _T_247)
node _T_249 = leq(uncommonBits_18, UInt<5>(0h13))
node _T_250 = and(_T_248, _T_249)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0)
node _T_251 = shr(io.in.a.bits.source, 5)
node _T_252 = eq(_T_251, UInt<3>(0h4))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_19, UInt<5>(0h13))
node _T_256 = and(_T_254, _T_255)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0)
node _T_257 = shr(io.in.a.bits.source, 5)
node _T_258 = eq(_T_257, UInt<2>(0h3))
node _T_259 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_260 = and(_T_258, _T_259)
node _T_261 = leq(uncommonBits_20, UInt<5>(0h13))
node _T_262 = and(_T_260, _T_261)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0)
node _T_263 = shr(io.in.a.bits.source, 5)
node _T_264 = eq(_T_263, UInt<2>(0h2))
node _T_265 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_266 = and(_T_264, _T_265)
node _T_267 = leq(uncommonBits_21, UInt<5>(0h13))
node _T_268 = and(_T_266, _T_267)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0)
node _T_269 = shr(io.in.a.bits.source, 5)
node _T_270 = eq(_T_269, UInt<1>(0h1))
node _T_271 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_272 = and(_T_270, _T_271)
node _T_273 = leq(uncommonBits_22, UInt<5>(0h13))
node _T_274 = and(_T_272, _T_273)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0)
node _T_275 = shr(io.in.a.bits.source, 5)
node _T_276 = eq(_T_275, UInt<1>(0h0))
node _T_277 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_278 = and(_T_276, _T_277)
node _T_279 = leq(uncommonBits_23, UInt<5>(0h13))
node _T_280 = and(_T_278, _T_279)
node _T_281 = or(_T_238, _T_244)
node _T_282 = or(_T_281, _T_250)
node _T_283 = or(_T_282, _T_256)
node _T_284 = or(_T_283, _T_262)
node _T_285 = or(_T_284, _T_268)
node _T_286 = or(_T_285, _T_274)
node _T_287 = or(_T_286, _T_280)
node _T_288 = and(_T_232, _T_287)
node _T_289 = or(UInt<1>(0h0), _T_288)
node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_291 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_292 = cvt(_T_291)
node _T_293 = and(_T_292, asSInt(UInt<29>(0h100000c0)))
node _T_294 = asSInt(_T_293)
node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0)))
node _T_296 = and(_T_290, _T_295)
node _T_297 = or(UInt<1>(0h0), _T_296)
node _T_298 = and(_T_289, _T_297)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_298, UInt<1>(0h1), "") : assert_10
node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_304 = and(_T_302, _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_307 = cvt(_T_306)
node _T_308 = and(_T_307, asSInt(UInt<29>(0h100000c0)))
node _T_309 = asSInt(_T_308)
node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = and(_T_305, _T_310)
node _T_312 = or(UInt<1>(0h0), _T_311)
node _T_313 = and(UInt<1>(0h0), _T_312)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_313, UInt<1>(0h1), "") : assert_11
node _T_317 = asUInt(reset)
node _T_318 = eq(_T_317, UInt<1>(0h0))
when _T_318 :
node _T_319 = eq(source_ok, UInt<1>(0h0))
when _T_319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_320 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(_T_320, UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_320, UInt<1>(0h1), "") : assert_13
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(is_aligned, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_327 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_327, UInt<1>(0h1), "") : assert_15
node _T_331 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_331, UInt<1>(0h1), "") : assert_16
node _T_335 = not(io.in.a.bits.mask)
node _T_336 = eq(_T_335, UInt<1>(0h0))
node _T_337 = asUInt(reset)
node _T_338 = eq(_T_337, UInt<1>(0h0))
when _T_338 :
node _T_339 = eq(_T_336, UInt<1>(0h0))
when _T_339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_336, UInt<1>(0h1), "") : assert_17
node _T_340 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_T_340, UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_340, UInt<1>(0h1), "") : assert_18
node _T_344 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_344 :
node _T_345 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_346 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_347 = and(_T_345, _T_346)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 4, 0)
node _T_348 = shr(io.in.a.bits.source, 5)
node _T_349 = eq(_T_348, UInt<3>(0h7))
node _T_350 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_351 = and(_T_349, _T_350)
node _T_352 = leq(uncommonBits_24, UInt<5>(0h13))
node _T_353 = and(_T_351, _T_352)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 4, 0)
node _T_354 = shr(io.in.a.bits.source, 5)
node _T_355 = eq(_T_354, UInt<3>(0h6))
node _T_356 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_357 = and(_T_355, _T_356)
node _T_358 = leq(uncommonBits_25, UInt<5>(0h13))
node _T_359 = and(_T_357, _T_358)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 4, 0)
node _T_360 = shr(io.in.a.bits.source, 5)
node _T_361 = eq(_T_360, UInt<3>(0h5))
node _T_362 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_363 = and(_T_361, _T_362)
node _T_364 = leq(uncommonBits_26, UInt<5>(0h13))
node _T_365 = and(_T_363, _T_364)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 4, 0)
node _T_366 = shr(io.in.a.bits.source, 5)
node _T_367 = eq(_T_366, UInt<3>(0h4))
node _T_368 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_369 = and(_T_367, _T_368)
node _T_370 = leq(uncommonBits_27, UInt<5>(0h13))
node _T_371 = and(_T_369, _T_370)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0)
node _T_372 = shr(io.in.a.bits.source, 5)
node _T_373 = eq(_T_372, UInt<2>(0h3))
node _T_374 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_375 = and(_T_373, _T_374)
node _T_376 = leq(uncommonBits_28, UInt<5>(0h13))
node _T_377 = and(_T_375, _T_376)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0)
node _T_378 = shr(io.in.a.bits.source, 5)
node _T_379 = eq(_T_378, UInt<2>(0h2))
node _T_380 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_381 = and(_T_379, _T_380)
node _T_382 = leq(uncommonBits_29, UInt<5>(0h13))
node _T_383 = and(_T_381, _T_382)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0)
node _T_384 = shr(io.in.a.bits.source, 5)
node _T_385 = eq(_T_384, UInt<1>(0h1))
node _T_386 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_387 = and(_T_385, _T_386)
node _T_388 = leq(uncommonBits_30, UInt<5>(0h13))
node _T_389 = and(_T_387, _T_388)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0)
node _T_390 = shr(io.in.a.bits.source, 5)
node _T_391 = eq(_T_390, UInt<1>(0h0))
node _T_392 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_393 = and(_T_391, _T_392)
node _T_394 = leq(uncommonBits_31, UInt<5>(0h13))
node _T_395 = and(_T_393, _T_394)
node _T_396 = or(_T_353, _T_359)
node _T_397 = or(_T_396, _T_365)
node _T_398 = or(_T_397, _T_371)
node _T_399 = or(_T_398, _T_377)
node _T_400 = or(_T_399, _T_383)
node _T_401 = or(_T_400, _T_389)
node _T_402 = or(_T_401, _T_395)
node _T_403 = and(_T_347, _T_402)
node _T_404 = or(UInt<1>(0h0), _T_403)
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_404, UInt<1>(0h1), "") : assert_19
node _T_408 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_409 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_410 = and(_T_408, _T_409)
node _T_411 = or(UInt<1>(0h0), _T_410)
node _T_412 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_413 = cvt(_T_412)
node _T_414 = and(_T_413, asSInt(UInt<29>(0h100000c0)))
node _T_415 = asSInt(_T_414)
node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0)))
node _T_417 = and(_T_411, _T_416)
node _T_418 = or(UInt<1>(0h0), _T_417)
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_418, UInt<1>(0h1), "") : assert_20
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(source_ok, UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(is_aligned, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_428 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_428, UInt<1>(0h1), "") : assert_23
node _T_432 = eq(io.in.a.bits.mask, mask)
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_432, UInt<1>(0h1), "") : assert_24
node _T_436 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_436, UInt<1>(0h1), "") : assert_25
node _T_440 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_440 :
node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_443 = and(_T_441, _T_442)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0)
node _T_444 = shr(io.in.a.bits.source, 5)
node _T_445 = eq(_T_444, UInt<3>(0h7))
node _T_446 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_447 = and(_T_445, _T_446)
node _T_448 = leq(uncommonBits_32, UInt<5>(0h13))
node _T_449 = and(_T_447, _T_448)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0)
node _T_450 = shr(io.in.a.bits.source, 5)
node _T_451 = eq(_T_450, UInt<3>(0h6))
node _T_452 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_453 = and(_T_451, _T_452)
node _T_454 = leq(uncommonBits_33, UInt<5>(0h13))
node _T_455 = and(_T_453, _T_454)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0)
node _T_456 = shr(io.in.a.bits.source, 5)
node _T_457 = eq(_T_456, UInt<3>(0h5))
node _T_458 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_459 = and(_T_457, _T_458)
node _T_460 = leq(uncommonBits_34, UInt<5>(0h13))
node _T_461 = and(_T_459, _T_460)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0)
node _T_462 = shr(io.in.a.bits.source, 5)
node _T_463 = eq(_T_462, UInt<3>(0h4))
node _T_464 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_465 = and(_T_463, _T_464)
node _T_466 = leq(uncommonBits_35, UInt<5>(0h13))
node _T_467 = and(_T_465, _T_466)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0)
node _T_468 = shr(io.in.a.bits.source, 5)
node _T_469 = eq(_T_468, UInt<2>(0h3))
node _T_470 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_471 = and(_T_469, _T_470)
node _T_472 = leq(uncommonBits_36, UInt<5>(0h13))
node _T_473 = and(_T_471, _T_472)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0)
node _T_474 = shr(io.in.a.bits.source, 5)
node _T_475 = eq(_T_474, UInt<2>(0h2))
node _T_476 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_477 = and(_T_475, _T_476)
node _T_478 = leq(uncommonBits_37, UInt<5>(0h13))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0)
node _T_480 = shr(io.in.a.bits.source, 5)
node _T_481 = eq(_T_480, UInt<1>(0h1))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_38, UInt<5>(0h13))
node _T_485 = and(_T_483, _T_484)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0)
node _T_486 = shr(io.in.a.bits.source, 5)
node _T_487 = eq(_T_486, UInt<1>(0h0))
node _T_488 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_489 = and(_T_487, _T_488)
node _T_490 = leq(uncommonBits_39, UInt<5>(0h13))
node _T_491 = and(_T_489, _T_490)
node _T_492 = or(_T_449, _T_455)
node _T_493 = or(_T_492, _T_461)
node _T_494 = or(_T_493, _T_467)
node _T_495 = or(_T_494, _T_473)
node _T_496 = or(_T_495, _T_479)
node _T_497 = or(_T_496, _T_485)
node _T_498 = or(_T_497, _T_491)
node _T_499 = and(_T_443, _T_498)
node _T_500 = or(UInt<1>(0h0), _T_499)
node _T_501 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_502 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_503 = and(_T_501, _T_502)
node _T_504 = or(UInt<1>(0h0), _T_503)
node _T_505 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_506 = cvt(_T_505)
node _T_507 = and(_T_506, asSInt(UInt<29>(0h100000c0)))
node _T_508 = asSInt(_T_507)
node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0)))
node _T_510 = and(_T_504, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_510)
node _T_512 = and(_T_500, _T_511)
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(_T_512, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_512, UInt<1>(0h1), "") : assert_26
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(source_ok, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(is_aligned, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_522, UInt<1>(0h1), "") : assert_29
node _T_526 = eq(io.in.a.bits.mask, mask)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_526, UInt<1>(0h1), "") : assert_30
node _T_530 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_530 :
node _T_531 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_532 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_533 = and(_T_531, _T_532)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0)
node _T_534 = shr(io.in.a.bits.source, 5)
node _T_535 = eq(_T_534, UInt<3>(0h7))
node _T_536 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_537 = and(_T_535, _T_536)
node _T_538 = leq(uncommonBits_40, UInt<5>(0h13))
node _T_539 = and(_T_537, _T_538)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0)
node _T_540 = shr(io.in.a.bits.source, 5)
node _T_541 = eq(_T_540, UInt<3>(0h6))
node _T_542 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_543 = and(_T_541, _T_542)
node _T_544 = leq(uncommonBits_41, UInt<5>(0h13))
node _T_545 = and(_T_543, _T_544)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0)
node _T_546 = shr(io.in.a.bits.source, 5)
node _T_547 = eq(_T_546, UInt<3>(0h5))
node _T_548 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_549 = and(_T_547, _T_548)
node _T_550 = leq(uncommonBits_42, UInt<5>(0h13))
node _T_551 = and(_T_549, _T_550)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0)
node _T_552 = shr(io.in.a.bits.source, 5)
node _T_553 = eq(_T_552, UInt<3>(0h4))
node _T_554 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_555 = and(_T_553, _T_554)
node _T_556 = leq(uncommonBits_43, UInt<5>(0h13))
node _T_557 = and(_T_555, _T_556)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0)
node _T_558 = shr(io.in.a.bits.source, 5)
node _T_559 = eq(_T_558, UInt<2>(0h3))
node _T_560 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_561 = and(_T_559, _T_560)
node _T_562 = leq(uncommonBits_44, UInt<5>(0h13))
node _T_563 = and(_T_561, _T_562)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0)
node _T_564 = shr(io.in.a.bits.source, 5)
node _T_565 = eq(_T_564, UInt<2>(0h2))
node _T_566 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_567 = and(_T_565, _T_566)
node _T_568 = leq(uncommonBits_45, UInt<5>(0h13))
node _T_569 = and(_T_567, _T_568)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0)
node _T_570 = shr(io.in.a.bits.source, 5)
node _T_571 = eq(_T_570, UInt<1>(0h1))
node _T_572 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_573 = and(_T_571, _T_572)
node _T_574 = leq(uncommonBits_46, UInt<5>(0h13))
node _T_575 = and(_T_573, _T_574)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0)
node _T_576 = shr(io.in.a.bits.source, 5)
node _T_577 = eq(_T_576, UInt<1>(0h0))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_47, UInt<5>(0h13))
node _T_581 = and(_T_579, _T_580)
node _T_582 = or(_T_539, _T_545)
node _T_583 = or(_T_582, _T_551)
node _T_584 = or(_T_583, _T_557)
node _T_585 = or(_T_584, _T_563)
node _T_586 = or(_T_585, _T_569)
node _T_587 = or(_T_586, _T_575)
node _T_588 = or(_T_587, _T_581)
node _T_589 = and(_T_533, _T_588)
node _T_590 = or(UInt<1>(0h0), _T_589)
node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_592 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_593 = and(_T_591, _T_592)
node _T_594 = or(UInt<1>(0h0), _T_593)
node _T_595 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_596 = cvt(_T_595)
node _T_597 = and(_T_596, asSInt(UInt<29>(0h100000c0)))
node _T_598 = asSInt(_T_597)
node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0)))
node _T_600 = and(_T_594, _T_599)
node _T_601 = or(UInt<1>(0h0), _T_600)
node _T_602 = and(_T_590, _T_601)
node _T_603 = asUInt(reset)
node _T_604 = eq(_T_603, UInt<1>(0h0))
when _T_604 :
node _T_605 = eq(_T_602, UInt<1>(0h0))
when _T_605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_602, UInt<1>(0h1), "") : assert_31
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(source_ok, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(is_aligned, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_612 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_612, UInt<1>(0h1), "") : assert_34
node _T_616 = not(mask)
node _T_617 = and(io.in.a.bits.mask, _T_616)
node _T_618 = eq(_T_617, UInt<1>(0h0))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_618, UInt<1>(0h1), "") : assert_35
node _T_622 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_622 :
node _T_623 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_624 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_625 = and(_T_623, _T_624)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 4, 0)
node _T_626 = shr(io.in.a.bits.source, 5)
node _T_627 = eq(_T_626, UInt<3>(0h7))
node _T_628 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_629 = and(_T_627, _T_628)
node _T_630 = leq(uncommonBits_48, UInt<5>(0h13))
node _T_631 = and(_T_629, _T_630)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 4, 0)
node _T_632 = shr(io.in.a.bits.source, 5)
node _T_633 = eq(_T_632, UInt<3>(0h6))
node _T_634 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_635 = and(_T_633, _T_634)
node _T_636 = leq(uncommonBits_49, UInt<5>(0h13))
node _T_637 = and(_T_635, _T_636)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0)
node _T_638 = shr(io.in.a.bits.source, 5)
node _T_639 = eq(_T_638, UInt<3>(0h5))
node _T_640 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_641 = and(_T_639, _T_640)
node _T_642 = leq(uncommonBits_50, UInt<5>(0h13))
node _T_643 = and(_T_641, _T_642)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0)
node _T_644 = shr(io.in.a.bits.source, 5)
node _T_645 = eq(_T_644, UInt<3>(0h4))
node _T_646 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_647 = and(_T_645, _T_646)
node _T_648 = leq(uncommonBits_51, UInt<5>(0h13))
node _T_649 = and(_T_647, _T_648)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0)
node _T_650 = shr(io.in.a.bits.source, 5)
node _T_651 = eq(_T_650, UInt<2>(0h3))
node _T_652 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_653 = and(_T_651, _T_652)
node _T_654 = leq(uncommonBits_52, UInt<5>(0h13))
node _T_655 = and(_T_653, _T_654)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0)
node _T_656 = shr(io.in.a.bits.source, 5)
node _T_657 = eq(_T_656, UInt<2>(0h2))
node _T_658 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_659 = and(_T_657, _T_658)
node _T_660 = leq(uncommonBits_53, UInt<5>(0h13))
node _T_661 = and(_T_659, _T_660)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0)
node _T_662 = shr(io.in.a.bits.source, 5)
node _T_663 = eq(_T_662, UInt<1>(0h1))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_54, UInt<5>(0h13))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0)
node _T_668 = shr(io.in.a.bits.source, 5)
node _T_669 = eq(_T_668, UInt<1>(0h0))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_55, UInt<5>(0h13))
node _T_673 = and(_T_671, _T_672)
node _T_674 = or(_T_631, _T_637)
node _T_675 = or(_T_674, _T_643)
node _T_676 = or(_T_675, _T_649)
node _T_677 = or(_T_676, _T_655)
node _T_678 = or(_T_677, _T_661)
node _T_679 = or(_T_678, _T_667)
node _T_680 = or(_T_679, _T_673)
node _T_681 = and(_T_625, _T_680)
node _T_682 = or(UInt<1>(0h0), _T_681)
node _T_683 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_684 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_685 = cvt(_T_684)
node _T_686 = and(_T_685, asSInt(UInt<29>(0h100000c0)))
node _T_687 = asSInt(_T_686)
node _T_688 = eq(_T_687, asSInt(UInt<1>(0h0)))
node _T_689 = and(_T_683, _T_688)
node _T_690 = or(UInt<1>(0h0), _T_689)
node _T_691 = and(_T_682, _T_690)
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(_T_691, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_691, UInt<1>(0h1), "") : assert_36
node _T_695 = asUInt(reset)
node _T_696 = eq(_T_695, UInt<1>(0h0))
when _T_696 :
node _T_697 = eq(source_ok, UInt<1>(0h0))
when _T_697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(is_aligned, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_701 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_701, UInt<1>(0h1), "") : assert_39
node _T_705 = eq(io.in.a.bits.mask, mask)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_705, UInt<1>(0h1), "") : assert_40
node _T_709 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_709 :
node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_711 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_712 = and(_T_710, _T_711)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0)
node _T_713 = shr(io.in.a.bits.source, 5)
node _T_714 = eq(_T_713, UInt<3>(0h7))
node _T_715 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_716 = and(_T_714, _T_715)
node _T_717 = leq(uncommonBits_56, UInt<5>(0h13))
node _T_718 = and(_T_716, _T_717)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0)
node _T_719 = shr(io.in.a.bits.source, 5)
node _T_720 = eq(_T_719, UInt<3>(0h6))
node _T_721 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_722 = and(_T_720, _T_721)
node _T_723 = leq(uncommonBits_57, UInt<5>(0h13))
node _T_724 = and(_T_722, _T_723)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0)
node _T_725 = shr(io.in.a.bits.source, 5)
node _T_726 = eq(_T_725, UInt<3>(0h5))
node _T_727 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_728 = and(_T_726, _T_727)
node _T_729 = leq(uncommonBits_58, UInt<5>(0h13))
node _T_730 = and(_T_728, _T_729)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0)
node _T_731 = shr(io.in.a.bits.source, 5)
node _T_732 = eq(_T_731, UInt<3>(0h4))
node _T_733 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_734 = and(_T_732, _T_733)
node _T_735 = leq(uncommonBits_59, UInt<5>(0h13))
node _T_736 = and(_T_734, _T_735)
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0)
node _T_737 = shr(io.in.a.bits.source, 5)
node _T_738 = eq(_T_737, UInt<2>(0h3))
node _T_739 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_740 = and(_T_738, _T_739)
node _T_741 = leq(uncommonBits_60, UInt<5>(0h13))
node _T_742 = and(_T_740, _T_741)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0)
node _T_743 = shr(io.in.a.bits.source, 5)
node _T_744 = eq(_T_743, UInt<2>(0h2))
node _T_745 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_746 = and(_T_744, _T_745)
node _T_747 = leq(uncommonBits_61, UInt<5>(0h13))
node _T_748 = and(_T_746, _T_747)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0)
node _T_749 = shr(io.in.a.bits.source, 5)
node _T_750 = eq(_T_749, UInt<1>(0h1))
node _T_751 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_752 = and(_T_750, _T_751)
node _T_753 = leq(uncommonBits_62, UInt<5>(0h13))
node _T_754 = and(_T_752, _T_753)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0)
node _T_755 = shr(io.in.a.bits.source, 5)
node _T_756 = eq(_T_755, UInt<1>(0h0))
node _T_757 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_758 = and(_T_756, _T_757)
node _T_759 = leq(uncommonBits_63, UInt<5>(0h13))
node _T_760 = and(_T_758, _T_759)
node _T_761 = or(_T_718, _T_724)
node _T_762 = or(_T_761, _T_730)
node _T_763 = or(_T_762, _T_736)
node _T_764 = or(_T_763, _T_742)
node _T_765 = or(_T_764, _T_748)
node _T_766 = or(_T_765, _T_754)
node _T_767 = or(_T_766, _T_760)
node _T_768 = and(_T_712, _T_767)
node _T_769 = or(UInt<1>(0h0), _T_768)
node _T_770 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_771 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_772 = cvt(_T_771)
node _T_773 = and(_T_772, asSInt(UInt<29>(0h100000c0)))
node _T_774 = asSInt(_T_773)
node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0)))
node _T_776 = and(_T_770, _T_775)
node _T_777 = or(UInt<1>(0h0), _T_776)
node _T_778 = and(_T_769, _T_777)
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_778, UInt<1>(0h1), "") : assert_41
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(source_ok, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_785 = asUInt(reset)
node _T_786 = eq(_T_785, UInt<1>(0h0))
when _T_786 :
node _T_787 = eq(is_aligned, UInt<1>(0h0))
when _T_787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_788 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(_T_788, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_788, UInt<1>(0h1), "") : assert_44
node _T_792 = eq(io.in.a.bits.mask, mask)
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(_T_792, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_792, UInt<1>(0h1), "") : assert_45
node _T_796 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_796 :
node _T_797 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_798 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_799 = and(_T_797, _T_798)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0)
node _T_800 = shr(io.in.a.bits.source, 5)
node _T_801 = eq(_T_800, UInt<3>(0h7))
node _T_802 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_803 = and(_T_801, _T_802)
node _T_804 = leq(uncommonBits_64, UInt<5>(0h13))
node _T_805 = and(_T_803, _T_804)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0)
node _T_806 = shr(io.in.a.bits.source, 5)
node _T_807 = eq(_T_806, UInt<3>(0h6))
node _T_808 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_809 = and(_T_807, _T_808)
node _T_810 = leq(uncommonBits_65, UInt<5>(0h13))
node _T_811 = and(_T_809, _T_810)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0)
node _T_812 = shr(io.in.a.bits.source, 5)
node _T_813 = eq(_T_812, UInt<3>(0h5))
node _T_814 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_815 = and(_T_813, _T_814)
node _T_816 = leq(uncommonBits_66, UInt<5>(0h13))
node _T_817 = and(_T_815, _T_816)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0)
node _T_818 = shr(io.in.a.bits.source, 5)
node _T_819 = eq(_T_818, UInt<3>(0h4))
node _T_820 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_821 = and(_T_819, _T_820)
node _T_822 = leq(uncommonBits_67, UInt<5>(0h13))
node _T_823 = and(_T_821, _T_822)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0)
node _T_824 = shr(io.in.a.bits.source, 5)
node _T_825 = eq(_T_824, UInt<2>(0h3))
node _T_826 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_827 = and(_T_825, _T_826)
node _T_828 = leq(uncommonBits_68, UInt<5>(0h13))
node _T_829 = and(_T_827, _T_828)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0)
node _T_830 = shr(io.in.a.bits.source, 5)
node _T_831 = eq(_T_830, UInt<2>(0h2))
node _T_832 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_833 = and(_T_831, _T_832)
node _T_834 = leq(uncommonBits_69, UInt<5>(0h13))
node _T_835 = and(_T_833, _T_834)
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0)
node _T_836 = shr(io.in.a.bits.source, 5)
node _T_837 = eq(_T_836, UInt<1>(0h1))
node _T_838 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_839 = and(_T_837, _T_838)
node _T_840 = leq(uncommonBits_70, UInt<5>(0h13))
node _T_841 = and(_T_839, _T_840)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0)
node _T_842 = shr(io.in.a.bits.source, 5)
node _T_843 = eq(_T_842, UInt<1>(0h0))
node _T_844 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_845 = and(_T_843, _T_844)
node _T_846 = leq(uncommonBits_71, UInt<5>(0h13))
node _T_847 = and(_T_845, _T_846)
node _T_848 = or(_T_805, _T_811)
node _T_849 = or(_T_848, _T_817)
node _T_850 = or(_T_849, _T_823)
node _T_851 = or(_T_850, _T_829)
node _T_852 = or(_T_851, _T_835)
node _T_853 = or(_T_852, _T_841)
node _T_854 = or(_T_853, _T_847)
node _T_855 = and(_T_799, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_858 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_859 = cvt(_T_858)
node _T_860 = and(_T_859, asSInt(UInt<29>(0h100000c0)))
node _T_861 = asSInt(_T_860)
node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0)))
node _T_863 = and(_T_857, _T_862)
node _T_864 = or(UInt<1>(0h0), _T_863)
node _T_865 = and(_T_856, _T_864)
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_865, UInt<1>(0h1), "") : assert_46
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(source_ok, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_872 = asUInt(reset)
node _T_873 = eq(_T_872, UInt<1>(0h0))
when _T_873 :
node _T_874 = eq(is_aligned, UInt<1>(0h0))
when _T_874 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_875 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_876 = asUInt(reset)
node _T_877 = eq(_T_876, UInt<1>(0h0))
when _T_877 :
node _T_878 = eq(_T_875, UInt<1>(0h0))
when _T_878 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_875, UInt<1>(0h1), "") : assert_49
node _T_879 = eq(io.in.a.bits.mask, mask)
node _T_880 = asUInt(reset)
node _T_881 = eq(_T_880, UInt<1>(0h0))
when _T_881 :
node _T_882 = eq(_T_879, UInt<1>(0h0))
when _T_882 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_879, UInt<1>(0h1), "") : assert_50
node _T_883 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_884 = asUInt(reset)
node _T_885 = eq(_T_884, UInt<1>(0h0))
when _T_885 :
node _T_886 = eq(_T_883, UInt<1>(0h0))
when _T_886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_883, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_887 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(_T_887, UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_887, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0)
node _source_ok_T_54 = shr(io.in.d.bits.source, 5)
node _source_ok_T_55 = eq(_source_ok_T_54, UInt<3>(0h7))
node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_T_58 = leq(source_ok_uncommonBits_8, UInt<5>(0h13))
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0)
node _source_ok_T_60 = shr(io.in.d.bits.source, 5)
node _source_ok_T_61 = eq(_source_ok_T_60, UInt<3>(0h6))
node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_T_64 = leq(source_ok_uncommonBits_9, UInt<5>(0h13))
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0)
node _source_ok_T_66 = shr(io.in.d.bits.source, 5)
node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h5))
node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_T_70 = leq(source_ok_uncommonBits_10, UInt<5>(0h13))
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0)
node _source_ok_T_72 = shr(io.in.d.bits.source, 5)
node _source_ok_T_73 = eq(_source_ok_T_72, UInt<3>(0h4))
node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_T_76 = leq(source_ok_uncommonBits_11, UInt<5>(0h13))
node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76)
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 4, 0)
node _source_ok_T_78 = shr(io.in.d.bits.source, 5)
node _source_ok_T_79 = eq(_source_ok_T_78, UInt<2>(0h3))
node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80)
node _source_ok_T_82 = leq(source_ok_uncommonBits_12, UInt<5>(0h13))
node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 4, 0)
node _source_ok_T_84 = shr(io.in.d.bits.source, 5)
node _source_ok_T_85 = eq(_source_ok_T_84, UInt<2>(0h2))
node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86)
node _source_ok_T_88 = leq(source_ok_uncommonBits_13, UInt<5>(0h13))
node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88)
node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0)
node _source_ok_T_90 = shr(io.in.d.bits.source, 5)
node _source_ok_T_91 = eq(_source_ok_T_90, UInt<1>(0h1))
node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92)
node _source_ok_T_94 = leq(source_ok_uncommonBits_14, UInt<5>(0h13))
node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94)
node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0)
node _source_ok_T_96 = shr(io.in.d.bits.source, 5)
node _source_ok_T_97 = eq(_source_ok_T_96, UInt<1>(0h0))
node _source_ok_T_98 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_99 = and(_source_ok_T_97, _source_ok_T_98)
node _source_ok_T_100 = leq(source_ok_uncommonBits_15, UInt<5>(0h13))
node _source_ok_T_101 = and(_source_ok_T_99, _source_ok_T_100)
wire _source_ok_WIRE_1 : UInt<1>[8]
connect _source_ok_WIRE_1[0], _source_ok_T_59
connect _source_ok_WIRE_1[1], _source_ok_T_65
connect _source_ok_WIRE_1[2], _source_ok_T_71
connect _source_ok_WIRE_1[3], _source_ok_T_77
connect _source_ok_WIRE_1[4], _source_ok_T_83
connect _source_ok_WIRE_1[5], _source_ok_T_89
connect _source_ok_WIRE_1[6], _source_ok_T_95
connect _source_ok_WIRE_1[7], _source_ok_T_101
node _source_ok_T_102 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[2])
node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[3])
node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[4])
node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[5])
node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[6])
node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[7])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_891 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_891 :
node _T_892 = asUInt(reset)
node _T_893 = eq(_T_892, UInt<1>(0h0))
when _T_893 :
node _T_894 = eq(source_ok_1, UInt<1>(0h0))
when _T_894 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_895 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_896 = asUInt(reset)
node _T_897 = eq(_T_896, UInt<1>(0h0))
when _T_897 :
node _T_898 = eq(_T_895, UInt<1>(0h0))
when _T_898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_895, UInt<1>(0h1), "") : assert_54
node _T_899 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(_T_899, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_899, UInt<1>(0h1), "") : assert_55
node _T_903 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_903, UInt<1>(0h1), "") : assert_56
node _T_907 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_907, UInt<1>(0h1), "") : assert_57
node _T_911 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_911 :
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(source_ok_1, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(sink_ok, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_918 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_918, UInt<1>(0h1), "") : assert_60
node _T_922 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(_T_922, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_922, UInt<1>(0h1), "") : assert_61
node _T_926 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_927 = asUInt(reset)
node _T_928 = eq(_T_927, UInt<1>(0h0))
when _T_928 :
node _T_929 = eq(_T_926, UInt<1>(0h0))
when _T_929 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_926, UInt<1>(0h1), "") : assert_62
node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_930, UInt<1>(0h1), "") : assert_63
node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_935 = or(UInt<1>(0h1), _T_934)
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_935, UInt<1>(0h1), "") : assert_64
node _T_939 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_939 :
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(source_ok_1, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(sink_ok, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_946 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_946, UInt<1>(0h1), "") : assert_67
node _T_950 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_951 = asUInt(reset)
node _T_952 = eq(_T_951, UInt<1>(0h0))
when _T_952 :
node _T_953 = eq(_T_950, UInt<1>(0h0))
when _T_953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_950, UInt<1>(0h1), "") : assert_68
node _T_954 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_955 = asUInt(reset)
node _T_956 = eq(_T_955, UInt<1>(0h0))
when _T_956 :
node _T_957 = eq(_T_954, UInt<1>(0h0))
when _T_957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_954, UInt<1>(0h1), "") : assert_69
node _T_958 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_959 = or(_T_958, io.in.d.bits.corrupt)
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_959, UInt<1>(0h1), "") : assert_70
node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_964 = or(UInt<1>(0h1), _T_963)
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_964, UInt<1>(0h1), "") : assert_71
node _T_968 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_968 :
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(source_ok_1, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_972 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_972, UInt<1>(0h1), "") : assert_73
node _T_976 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_976, UInt<1>(0h1), "") : assert_74
node _T_980 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_981 = or(UInt<1>(0h1), _T_980)
node _T_982 = asUInt(reset)
node _T_983 = eq(_T_982, UInt<1>(0h0))
when _T_983 :
node _T_984 = eq(_T_981, UInt<1>(0h0))
when _T_984 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_981, UInt<1>(0h1), "") : assert_75
node _T_985 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_985 :
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(source_ok_1, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_989 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_T_989, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_989, UInt<1>(0h1), "") : assert_77
node _T_993 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_994 = or(_T_993, io.in.d.bits.corrupt)
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_994, UInt<1>(0h1), "") : assert_78
node _T_998 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_999 = or(UInt<1>(0h1), _T_998)
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_999, UInt<1>(0h1), "") : assert_79
node _T_1003 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1003 :
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(source_ok_1, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1007 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_81
node _T_1011 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(_T_1011, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1011, UInt<1>(0h1), "") : assert_82
node _T_1015 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1016 = or(UInt<1>(0h1), _T_1015)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1020 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1024 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(_T_1024, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1024, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1028 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1032 = eq(a_first, UInt<1>(0h0))
node _T_1033 = and(io.in.a.valid, _T_1032)
when _T_1033 :
node _T_1034 = eq(io.in.a.bits.opcode, opcode)
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_T_1034, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1034, UInt<1>(0h1), "") : assert_87
node _T_1038 = eq(io.in.a.bits.param, param)
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_88
node _T_1042 = eq(io.in.a.bits.size, size)
node _T_1043 = asUInt(reset)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
when _T_1044 :
node _T_1045 = eq(_T_1042, UInt<1>(0h0))
when _T_1045 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1042, UInt<1>(0h1), "") : assert_89
node _T_1046 = eq(io.in.a.bits.source, source)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_90
node _T_1050 = eq(io.in.a.bits.address, address)
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_91
node _T_1054 = and(io.in.a.ready, io.in.a.valid)
node _T_1055 = and(_T_1054, a_first)
when _T_1055 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1056 = eq(d_first, UInt<1>(0h0))
node _T_1057 = and(io.in.d.valid, _T_1056)
when _T_1057 :
node _T_1058 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_92
node _T_1062 = eq(io.in.d.bits.param, param_1)
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_93
node _T_1066 = eq(io.in.d.bits.size, size_1)
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_94
node _T_1070 = eq(io.in.d.bits.source, source_1)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_95
node _T_1074 = eq(io.in.d.bits.sink, sink)
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_96
node _T_1078 = eq(io.in.d.bits.denied, denied)
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_97
node _T_1082 = and(io.in.d.ready, io.in.d.valid)
node _T_1083 = and(_T_1082, d_first)
when _T_1083 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<244>, clock, reset, UInt<244>(0h0)
regreset inflight_opcodes : UInt<976>, clock, reset, UInt<976>(0h0)
regreset inflight_sizes : UInt<976>, clock, reset, UInt<976>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<244>
connect a_set, UInt<244>(0h0)
wire a_set_wo_ready : UInt<244>
connect a_set_wo_ready, UInt<244>(0h0)
wire a_opcodes_set : UInt<976>
connect a_opcodes_set, UInt<976>(0h0)
wire a_sizes_set : UInt<976>
connect a_sizes_set, UInt<976>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1084 = and(io.in.a.valid, a_first_1)
node _T_1085 = and(_T_1084, UInt<1>(0h1))
when _T_1085 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1086 = and(io.in.a.ready, io.in.a.valid)
node _T_1087 = and(_T_1086, a_first_1)
node _T_1088 = and(_T_1087, UInt<1>(0h1))
when _T_1088 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1089 = dshr(inflight, io.in.a.bits.source)
node _T_1090 = bits(_T_1089, 0, 0)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
node _T_1092 = asUInt(reset)
node _T_1093 = eq(_T_1092, UInt<1>(0h0))
when _T_1093 :
node _T_1094 = eq(_T_1091, UInt<1>(0h0))
when _T_1094 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1091, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<244>
connect d_clr, UInt<244>(0h0)
wire d_clr_wo_ready : UInt<244>
connect d_clr_wo_ready, UInt<244>(0h0)
wire d_opcodes_clr : UInt<976>
connect d_opcodes_clr, UInt<976>(0h0)
wire d_sizes_clr : UInt<976>
connect d_sizes_clr, UInt<976>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1095 = and(io.in.d.valid, d_first_1)
node _T_1096 = and(_T_1095, UInt<1>(0h1))
node _T_1097 = eq(d_release_ack, UInt<1>(0h0))
node _T_1098 = and(_T_1096, _T_1097)
when _T_1098 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1099 = and(io.in.d.ready, io.in.d.valid)
node _T_1100 = and(_T_1099, d_first_1)
node _T_1101 = and(_T_1100, UInt<1>(0h1))
node _T_1102 = eq(d_release_ack, UInt<1>(0h0))
node _T_1103 = and(_T_1101, _T_1102)
when _T_1103 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1104 = and(io.in.d.valid, d_first_1)
node _T_1105 = and(_T_1104, UInt<1>(0h1))
node _T_1106 = eq(d_release_ack, UInt<1>(0h0))
node _T_1107 = and(_T_1105, _T_1106)
when _T_1107 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1108 = dshr(inflight, io.in.d.bits.source)
node _T_1109 = bits(_T_1108, 0, 0)
node _T_1110 = or(_T_1109, same_cycle_resp)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1114 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1115 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1116 = or(_T_1114, _T_1115)
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_100
node _T_1120 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_101
else :
node _T_1124 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1125 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1126 = or(_T_1124, _T_1125)
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_102
node _T_1130 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_103
node _T_1134 = and(io.in.d.valid, d_first_1)
node _T_1135 = and(_T_1134, a_first_1)
node _T_1136 = and(_T_1135, io.in.a.valid)
node _T_1137 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1138 = and(_T_1136, _T_1137)
node _T_1139 = eq(d_release_ack, UInt<1>(0h0))
node _T_1140 = and(_T_1138, _T_1139)
when _T_1140 :
node _T_1141 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1142 = or(_T_1141, io.in.a.ready)
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_104
node _T_1146 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1147 = orr(a_set_wo_ready)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
node _T_1149 = or(_T_1146, _T_1148)
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_82
node _T_1153 = orr(inflight)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
node _T_1155 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1156 = or(_T_1154, _T_1155)
node _T_1157 = lt(watchdog, plusarg_reader.out)
node _T_1158 = or(_T_1156, _T_1157)
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(_T_1158, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1158, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1162 = and(io.in.a.ready, io.in.a.valid)
node _T_1163 = and(io.in.d.ready, io.in.d.valid)
node _T_1164 = or(_T_1162, _T_1163)
when _T_1164 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<244>, clock, reset, UInt<244>(0h0)
regreset inflight_opcodes_1 : UInt<976>, clock, reset, UInt<976>(0h0)
regreset inflight_sizes_1 : UInt<976>, clock, reset, UInt<976>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<244>
connect c_set, UInt<244>(0h0)
wire c_set_wo_ready : UInt<244>
connect c_set_wo_ready, UInt<244>(0h0)
wire c_opcodes_set : UInt<976>
connect c_opcodes_set, UInt<976>(0h0)
wire c_sizes_set : UInt<976>
connect c_sizes_set, UInt<976>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1165 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1166 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1167 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = and(_T_1165, _T_1168)
when _T_1169 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1170 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1171 = and(_T_1170, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1172 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1173 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1174 = and(_T_1172, _T_1173)
node _T_1175 = and(_T_1171, _T_1174)
when _T_1175 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1176 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1177 = bits(_T_1176, 0, 0)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<244>
connect d_clr_1, UInt<244>(0h0)
wire d_clr_wo_ready_1 : UInt<244>
connect d_clr_wo_ready_1, UInt<244>(0h0)
wire d_opcodes_clr_1 : UInt<976>
connect d_opcodes_clr_1, UInt<976>(0h0)
wire d_sizes_clr_1 : UInt<976>
connect d_sizes_clr_1, UInt<976>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1182 = and(io.in.d.valid, d_first_2)
node _T_1183 = and(_T_1182, UInt<1>(0h1))
node _T_1184 = and(_T_1183, d_release_ack_1)
when _T_1184 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1185 = and(io.in.d.ready, io.in.d.valid)
node _T_1186 = and(_T_1185, d_first_2)
node _T_1187 = and(_T_1186, UInt<1>(0h1))
node _T_1188 = and(_T_1187, d_release_ack_1)
when _T_1188 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1189 = and(io.in.d.valid, d_first_2)
node _T_1190 = and(_T_1189, UInt<1>(0h1))
node _T_1191 = and(_T_1190, d_release_ack_1)
when _T_1191 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1192 = dshr(inflight_1, io.in.d.bits.source)
node _T_1193 = bits(_T_1192, 0, 0)
node _T_1194 = or(_T_1193, same_cycle_resp_1)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1198 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_109
else :
node _T_1202 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_110
node _T_1206 = and(io.in.d.valid, d_first_2)
node _T_1207 = and(_T_1206, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1208 = and(_T_1207, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1209 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1210 = and(_T_1208, _T_1209)
node _T_1211 = and(_T_1210, d_release_ack_1)
node _T_1212 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1213 = and(_T_1211, _T_1212)
when _T_1213 :
node _T_1214 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1215 = or(_T_1214, _WIRE_23.ready)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_111
node _T_1219 = orr(c_set_wo_ready)
when _T_1219 :
node _T_1220 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_83
node _T_1224 = orr(inflight_1)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
node _T_1226 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1227 = or(_T_1225, _T_1226)
node _T_1228 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1229 = or(_T_1227, _T_1228)
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(_T_1229, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1229, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1233 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1234 = and(io.in.d.ready, io.in.d.valid)
node _T_1235 = or(_T_1233, _T_1234)
when _T_1235 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_84 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_85 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_41( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_26 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_32 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_38 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_98 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [975:0] c_opcodes_set = 976'h0; // @[Monitor.scala:740:34]
wire [975:0] c_sizes_set = 976'h0; // @[Monitor.scala:741:34]
wire [243:0] c_set = 244'h0; // @[Monitor.scala:738:34]
wire [243:0] c_set_wo_ready = 244'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_14 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_15 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_6 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_12 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_18 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_24 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_30 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_36 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_42 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = &_source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6 == 3'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_9 & _source_ok_T_10; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_13 = _source_ok_T_12 == 3'h5; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_16 = source_ok_uncommonBits_2 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_17 = _source_ok_T_15 & _source_ok_T_16; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = _source_ok_T_18 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_22 = source_ok_uncommonBits_3 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_25 = _source_ok_T_24 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_27 = _source_ok_T_25; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_28 = source_ok_uncommonBits_4 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_29 = _source_ok_T_27 & _source_ok_T_28; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_4 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_31 = _source_ok_T_30 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_33 = _source_ok_T_31; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_34 = source_ok_uncommonBits_5 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_35 = _source_ok_T_33 & _source_ok_T_34; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_35; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_37 = _source_ok_T_36 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_39 = _source_ok_T_37; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = source_ok_uncommonBits_6 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_41 = _source_ok_T_39 & _source_ok_T_40; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_6 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_43 = _source_ok_T_42 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = source_ok_uncommonBits_7 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_47 = _source_ok_T_45 & _source_ok_T_46; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_7 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_12 = _uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_13 = _uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_24 = _uncommonBits_T_24[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_25 = _uncommonBits_T_25[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_26 = _uncommonBits_T_26[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_27 = _uncommonBits_T_27[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_44 = _uncommonBits_T_44[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_45 = _uncommonBits_T_45[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_48 = _uncommonBits_T_48[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_49 = _uncommonBits_T_49[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_56 = _uncommonBits_T_56[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_57 = _uncommonBits_T_57[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_66 = _uncommonBits_T_66[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_67 = _uncommonBits_T_67[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_68 = _uncommonBits_T_68[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_69 = _uncommonBits_T_69[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_70 = _uncommonBits_T_70[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_71 = _uncommonBits_T_71[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_54 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_60 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_66 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_72 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_78 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_84 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_90 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_96 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_55 = &_source_ok_T_54; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = source_ok_uncommonBits_8 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_59 = _source_ok_T_57 & _source_ok_T_58; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 3'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = source_ok_uncommonBits_9 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_65 = _source_ok_T_63 & _source_ok_T_64; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_1 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_67 = _source_ok_T_66 == 3'h5; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_10 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_2 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_73 = _source_ok_T_72 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = source_ok_uncommonBits_11 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_77 = _source_ok_T_75 & _source_ok_T_76; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_3 = _source_ok_T_77; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_79 = _source_ok_T_78 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = source_ok_uncommonBits_12 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_83 = _source_ok_T_81 & _source_ok_T_82; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_4 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_85 = _source_ok_T_84 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = source_ok_uncommonBits_13 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_89 = _source_ok_T_87 & _source_ok_T_88; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_91 = _source_ok_T_90 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_94 = source_ok_uncommonBits_14 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_6 = _source_ok_T_95; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_97 = _source_ok_T_96 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_99 = _source_ok_T_97; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_100 = source_ok_uncommonBits_15 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_101 = _source_ok_T_99 & _source_ok_T_100; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_7 = _source_ok_T_101; // @[Parameters.scala:1138:31]
wire _source_ok_T_102 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_107 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1162 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1162; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1162; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1235 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1235; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1235; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1235; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg denied; // @[Monitor.scala:543:22]
reg [243:0] inflight; // @[Monitor.scala:614:27]
reg [975:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [975:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [243:0] a_set; // @[Monitor.scala:626:34]
wire [243:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [975:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [975:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [975:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [975:0] _a_opcode_lookup_T_6 = {972'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [975:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [975:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [975:0] _a_size_lookup_T_6 = {972'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [975:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[975:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire _T_1088 = _T_1162 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1088 ? _a_set_T[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1088 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1088 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1088 ? _a_opcodes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1088 ? _a_sizes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [243:0] d_clr; // @[Monitor.scala:664:34]
wire [243:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [975:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [975:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1134 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1134 & ~d_release_ack ? _d_clr_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire _T_1103 = _T_1235 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1103 ? _d_clr_T[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1103 ? _d_opcodes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1103 ? _d_sizes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [243:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [243:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [243:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [975:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [975:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [975:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [975:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [975:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [975:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [243:0] inflight_1; // @[Monitor.scala:726:35]
wire [243:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [975:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [975:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [975:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [975:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [975:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [975:0] _c_opcode_lookup_T_6 = {972'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [975:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [975:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [975:0] _c_size_lookup_T_6 = {972'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [975:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[975:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [243:0] d_clr_1; // @[Monitor.scala:774:34]
wire [243:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [975:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [975:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1206 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1206 & d_release_ack_1 ? _d_clr_wo_ready_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire _T_1188 = _T_1235 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1188 ? _d_clr_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1188 ? _d_opcodes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1188 ? _d_sizes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [243:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [243:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [975:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [975:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [975:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [975:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_164 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_288
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_164( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_288 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncAsyncCrossingSink_n1x1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]}
wire nodeIn : { sync : UInt<1>[1]}
invalidate nodeIn.sync[0]
wire nodeOut : UInt<1>[1]
invalidate nodeOut[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst chain of SynchronizerShiftReg_w1_d3
connect chain.clock, clock
connect chain.reset, reset
connect chain.io.d, nodeIn.sync[0]
wire _WIRE : UInt<1>[1]
wire _WIRE_1 : UInt<1>
connect _WIRE_1, chain.io.q
node _T = bits(_WIRE_1, 0, 0)
connect _WIRE[0], _T
connect nodeOut, _WIRE | module IntSyncAsyncCrossingSink_n1x1( // @[Crossing.scala:74:9]
input clock, // @[Crossing.scala:74:9]
input reset, // @[Crossing.scala:74:9]
output auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0 = 1'h0; // @[ShiftReg.scala:45:23]
wire nodeIn_sync_0 = 1'h0; // @[ShiftReg.scala:45:23]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:74:9]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:74:9]
SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (nodeOut_0)
); // @[ShiftReg.scala:45:23]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:74:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_3 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 55, 55)
wire common_expOut : UInt<12>
wire common_fractOut : UInt<52>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 11, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 11, 11)
node roundMask_lsbs = bits(_roundMask_T_1, 10, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 10, 10)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 9, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 9, 9)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 8, 0)
node roundMask_msb_3 = bits(roundMask_lsbs_2, 8, 8)
node roundMask_lsbs_3 = bits(roundMask_lsbs_2, 7, 0)
node roundMask_msb_4 = bits(roundMask_lsbs_3, 7, 7)
node roundMask_lsbs_4 = bits(roundMask_lsbs_3, 6, 0)
node roundMask_msb_5 = bits(roundMask_lsbs_4, 6, 6)
node roundMask_lsbs_5 = bits(roundMask_lsbs_4, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_5)
node _roundMask_T_2 = bits(roundMask_shift, 63, 13)
node _roundMask_T_3 = bits(_roundMask_T_2, 31, 0)
node _roundMask_T_4 = shl(UInt<16>(0hffff), 16)
node _roundMask_T_5 = xor(UInt<32>(0hffffffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 16)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 15, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 16)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 23, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 8)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 8)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 23, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 8)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 27, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 4)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 4)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 27, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 4)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 29, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 2)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 2)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 29, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 2)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_35, 30, 0)
node _roundMask_T_44 = shl(_roundMask_T_43, 1)
node _roundMask_T_45 = xor(_roundMask_T_35, _roundMask_T_44)
node _roundMask_T_46 = shr(_roundMask_T_42, 1)
node _roundMask_T_47 = and(_roundMask_T_46, _roundMask_T_45)
node _roundMask_T_48 = bits(_roundMask_T_42, 30, 0)
node _roundMask_T_49 = shl(_roundMask_T_48, 1)
node _roundMask_T_50 = not(_roundMask_T_45)
node _roundMask_T_51 = and(_roundMask_T_49, _roundMask_T_50)
node _roundMask_T_52 = or(_roundMask_T_47, _roundMask_T_51)
node _roundMask_T_53 = bits(_roundMask_T_2, 50, 32)
node _roundMask_T_54 = bits(_roundMask_T_53, 15, 0)
node _roundMask_T_55 = shl(UInt<8>(0hff), 8)
node _roundMask_T_56 = xor(UInt<16>(0hffff), _roundMask_T_55)
node _roundMask_T_57 = shr(_roundMask_T_54, 8)
node _roundMask_T_58 = and(_roundMask_T_57, _roundMask_T_56)
node _roundMask_T_59 = bits(_roundMask_T_54, 7, 0)
node _roundMask_T_60 = shl(_roundMask_T_59, 8)
node _roundMask_T_61 = not(_roundMask_T_56)
node _roundMask_T_62 = and(_roundMask_T_60, _roundMask_T_61)
node _roundMask_T_63 = or(_roundMask_T_58, _roundMask_T_62)
node _roundMask_T_64 = bits(_roundMask_T_56, 11, 0)
node _roundMask_T_65 = shl(_roundMask_T_64, 4)
node _roundMask_T_66 = xor(_roundMask_T_56, _roundMask_T_65)
node _roundMask_T_67 = shr(_roundMask_T_63, 4)
node _roundMask_T_68 = and(_roundMask_T_67, _roundMask_T_66)
node _roundMask_T_69 = bits(_roundMask_T_63, 11, 0)
node _roundMask_T_70 = shl(_roundMask_T_69, 4)
node _roundMask_T_71 = not(_roundMask_T_66)
node _roundMask_T_72 = and(_roundMask_T_70, _roundMask_T_71)
node _roundMask_T_73 = or(_roundMask_T_68, _roundMask_T_72)
node _roundMask_T_74 = bits(_roundMask_T_66, 13, 0)
node _roundMask_T_75 = shl(_roundMask_T_74, 2)
node _roundMask_T_76 = xor(_roundMask_T_66, _roundMask_T_75)
node _roundMask_T_77 = shr(_roundMask_T_73, 2)
node _roundMask_T_78 = and(_roundMask_T_77, _roundMask_T_76)
node _roundMask_T_79 = bits(_roundMask_T_73, 13, 0)
node _roundMask_T_80 = shl(_roundMask_T_79, 2)
node _roundMask_T_81 = not(_roundMask_T_76)
node _roundMask_T_82 = and(_roundMask_T_80, _roundMask_T_81)
node _roundMask_T_83 = or(_roundMask_T_78, _roundMask_T_82)
node _roundMask_T_84 = bits(_roundMask_T_76, 14, 0)
node _roundMask_T_85 = shl(_roundMask_T_84, 1)
node _roundMask_T_86 = xor(_roundMask_T_76, _roundMask_T_85)
node _roundMask_T_87 = shr(_roundMask_T_83, 1)
node _roundMask_T_88 = and(_roundMask_T_87, _roundMask_T_86)
node _roundMask_T_89 = bits(_roundMask_T_83, 14, 0)
node _roundMask_T_90 = shl(_roundMask_T_89, 1)
node _roundMask_T_91 = not(_roundMask_T_86)
node _roundMask_T_92 = and(_roundMask_T_90, _roundMask_T_91)
node _roundMask_T_93 = or(_roundMask_T_88, _roundMask_T_92)
node _roundMask_T_94 = bits(_roundMask_T_53, 18, 16)
node _roundMask_T_95 = bits(_roundMask_T_94, 1, 0)
node _roundMask_T_96 = bits(_roundMask_T_95, 0, 0)
node _roundMask_T_97 = bits(_roundMask_T_95, 1, 1)
node _roundMask_T_98 = cat(_roundMask_T_96, _roundMask_T_97)
node _roundMask_T_99 = bits(_roundMask_T_94, 2, 2)
node _roundMask_T_100 = cat(_roundMask_T_98, _roundMask_T_99)
node _roundMask_T_101 = cat(_roundMask_T_93, _roundMask_T_100)
node _roundMask_T_102 = cat(_roundMask_T_52, _roundMask_T_101)
node _roundMask_T_103 = not(_roundMask_T_102)
node _roundMask_T_104 = mux(roundMask_msb_5, UInt<1>(0h0), _roundMask_T_103)
node _roundMask_T_105 = not(_roundMask_T_104)
node _roundMask_T_106 = not(_roundMask_T_105)
node _roundMask_T_107 = mux(roundMask_msb_4, UInt<1>(0h0), _roundMask_T_106)
node _roundMask_T_108 = not(_roundMask_T_107)
node _roundMask_T_109 = not(_roundMask_T_108)
node _roundMask_T_110 = mux(roundMask_msb_3, UInt<1>(0h0), _roundMask_T_109)
node _roundMask_T_111 = not(_roundMask_T_110)
node _roundMask_T_112 = not(_roundMask_T_111)
node _roundMask_T_113 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_112)
node _roundMask_T_114 = not(_roundMask_T_113)
node _roundMask_T_115 = cat(_roundMask_T_114, UInt<3>(0h7))
node roundMask_msb_6 = bits(roundMask_lsbs_1, 9, 9)
node roundMask_lsbs_6 = bits(roundMask_lsbs_1, 8, 0)
node roundMask_msb_7 = bits(roundMask_lsbs_6, 8, 8)
node roundMask_lsbs_7 = bits(roundMask_lsbs_6, 7, 0)
node roundMask_msb_8 = bits(roundMask_lsbs_7, 7, 7)
node roundMask_lsbs_8 = bits(roundMask_lsbs_7, 6, 0)
node roundMask_msb_9 = bits(roundMask_lsbs_8, 6, 6)
node roundMask_lsbs_9 = bits(roundMask_lsbs_8, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_9)
node _roundMask_T_116 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_117 = bits(_roundMask_T_116, 1, 0)
node _roundMask_T_118 = bits(_roundMask_T_117, 0, 0)
node _roundMask_T_119 = bits(_roundMask_T_117, 1, 1)
node _roundMask_T_120 = cat(_roundMask_T_118, _roundMask_T_119)
node _roundMask_T_121 = bits(_roundMask_T_116, 2, 2)
node _roundMask_T_122 = cat(_roundMask_T_120, _roundMask_T_121)
node _roundMask_T_123 = mux(roundMask_msb_9, _roundMask_T_122, UInt<1>(0h0))
node _roundMask_T_124 = mux(roundMask_msb_8, _roundMask_T_123, UInt<1>(0h0))
node _roundMask_T_125 = mux(roundMask_msb_7, _roundMask_T_124, UInt<1>(0h0))
node _roundMask_T_126 = mux(roundMask_msb_6, _roundMask_T_125, UInt<1>(0h0))
node _roundMask_T_127 = mux(roundMask_msb_1, _roundMask_T_115, _roundMask_T_126)
node _roundMask_T_128 = mux(roundMask_msb, _roundMask_T_127, UInt<1>(0h0))
node _roundMask_T_129 = or(_roundMask_T_128, doShiftSigDown1)
node roundMask = cat(_roundMask_T_129, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 53)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 11, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 52, 1)
node _common_fractOut_T_1 = bits(roundedSig, 51, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 10)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<11>(0h3ce)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 54, 54)
node _roundCarry_T_1 = bits(roundedSig, 53, 53)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 11)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<12>(0h3ce))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_3( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20]
wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[55]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25]
wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26]
wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56]
wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22]
wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_52 = _roundMask_T_47 | _roundMask_T_51; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_63 = _roundMask_T_58 | _roundMask_T_62; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_73 = _roundMask_T_68 | _roundMask_T_72; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_83 = _roundMask_T_78 | _roundMask_T_82; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_93 = _roundMask_T_88 | _roundMask_T_92; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20]
wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20]
wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20]
wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}]
wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20]
wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20]
wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [53:0] _roundMask_T_129 = {_roundMask_T_128[53:1], _roundMask_T_128[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [55:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [11:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [11:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [51:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_3 :
input clock : Clock
input reset : Reset
output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<4>(0hf))
when _T :
connect doing_reset, UInt<1>(0h0)
reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock
node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))
node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)
wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect f2_entry, entries[_f2_entry_T_1]
node _T_1 = eq(io.update_idx, io.f2_req_idx)
node _T_2 = and(io.update_repair, _T_1)
when _T_2 :
connect f2_entry.s_cnt, io.update_meta.s_cnt
else :
node _T_3 = eq(io.update_idx, io.f2_req_idx)
node _T_4 = and(io.update_mispredict, _T_3)
when _T_4 :
connect f2_entry.s_cnt, UInt<1>(0h0)
reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f3_entry, f2_entry
reg f3_scnt_REG : UInt, clock
connect f3_scnt_REG, io.f2_req_idx
node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG)
node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T)
node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt)
node _f3_tag_T = bits(io.f2_req_idx, 13, 4)
reg f3_tag : UInt, clock
connect f3_tag, _f3_tag_T
connect io.f3_pred, io.f3_pred_in
connect io.f3_meta.s_cnt, f3_scnt
node _T_5 = eq(f3_entry.tag, f3_tag)
when _T_5 :
node _T_6 = eq(f3_scnt, f3_entry.p_cnt)
node _T_7 = eq(f3_entry.conf, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0))
connect io.f3_pred, _io_f3_pred_T
reg f4_fire : UInt<1>, clock
connect f4_fire, io.f3_req_fire
reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f4_entry, f3_entry
reg f4_tag : UInt, clock
connect f4_tag, f3_tag
reg f4_scnt : UInt, clock
connect f4_scnt, f3_scnt
reg f4_idx_REG : UInt, clock
connect f4_idx_REG, io.f2_req_idx
reg f4_idx : UInt, clock
connect f4_idx, f4_idx_REG
when f4_fire :
node _T_9 = eq(f4_entry.tag, f4_tag)
when _T_9 :
node _T_10 = eq(f4_scnt, f4_entry.p_cnt)
node _T_11 = eq(f4_entry.conf, UInt<3>(0h7))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
node _T_13 = or(f4_idx, UInt<4>(0h0))
node _T_14 = bits(_T_13, 3, 0)
connect entries[_T_14].age, UInt<3>(0h7)
node _T_15 = or(f4_idx, UInt<4>(0h0))
node _T_16 = bits(_T_15, 3, 0)
connect entries[_T_16].s_cnt, UInt<1>(0h0)
else :
node _T_17 = or(f4_idx, UInt<4>(0h0))
node _T_18 = bits(_T_17, 3, 0)
node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1))
node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1)
connect entries[_T_18].s_cnt, _entries_s_cnt_T_1
node _T_19 = or(f4_idx, UInt<4>(0h0))
node _T_20 = bits(_T_19, 3, 0)
node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7))
node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1))
node _entries_age_T_2 = tail(_entries_age_T_1, 1)
node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2)
connect entries[_T_20].age, _entries_age_T_3
node _entry_T = or(io.update_idx, UInt<4>(0h0))
node _entry_T_1 = bits(_entry_T, 3, 0)
node tag = bits(io.update_idx, 13, 4)
node tag_match = eq(entries[_entry_T_1].tag, tag)
node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt)
wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect wentry, entries[_entry_T_1]
node _T_21 = eq(doing_reset, UInt<1>(0h0))
node _T_22 = and(io.update_mispredict, _T_21)
when _T_22 :
node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_24 = and(_T_23, tag_match)
when _T_24 :
connect wentry.s_cnt, UInt<1>(0h0)
node _wentry_conf_T = sub(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_1 = tail(_wentry_conf_T, 1)
connect wentry.conf, _wentry_conf_T_1
else :
node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_26 = eq(tag_match, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
skip
else :
node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_29 = and(_T_28, tag_match)
node _T_30 = and(_T_29, ctr_match)
when _T_30 :
node _wentry_conf_T_2 = add(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_3 = tail(_wentry_conf_T_2, 1)
connect wentry.conf, _wentry_conf_T_3
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_32 = and(_T_31, tag_match)
node _T_33 = eq(ctr_match, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
when _T_34 :
connect wentry.conf, UInt<1>(0h0)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_36 = eq(tag_match, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_41 = eq(tag_match, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
when _T_44 :
node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1))
node _wentry_age_T_1 = tail(_wentry_age_T, 1)
connect wentry.age, _wentry_age_T_1
else :
node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_46 = and(_T_45, tag_match)
node _T_47 = and(_T_46, ctr_match)
when _T_47 :
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_49 = and(_T_48, tag_match)
node _T_50 = eq(ctr_match, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect wentry.p_cnt, io.update_meta.s_cnt
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_53 = eq(tag_match, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
when _T_54 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
node _T_55 = or(io.update_idx, UInt<4>(0h0))
node _T_56 = bits(_T_55, 3, 0)
connect entries[_T_56], wentry
else :
node _T_57 = eq(doing_reset, UInt<1>(0h0))
node _T_58 = and(io.update_repair, _T_57)
when _T_58 :
node _T_59 = eq(io.update_idx, f4_idx)
node _T_60 = and(f4_fire, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = and(tag_match, _T_61)
when _T_62 :
connect wentry.s_cnt, io.update_meta.s_cnt
node _T_63 = or(io.update_idx, UInt<4>(0h0))
node _T_64 = bits(_T_63, 3, 0)
connect entries[_T_64], wentry
when doing_reset :
wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect _entries_WIRE.s_cnt, UInt<10>(0h0)
connect _entries_WIRE.p_cnt, UInt<10>(0h0)
connect _entries_WIRE.age, UInt<3>(0h0)
connect _entries_WIRE.conf, UInt<3>(0h0)
connect _entries_WIRE.tag, UInt<10>(0h0)
connect entries[reset_idx], _entries_WIRE | module LoopBranchPredictorColumn_3( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [36:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [36:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [36:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [36:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [36:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [36:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [36:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [36:0] f4_idx_REG; // @[loop.scala:92:35]
reg [36:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire [3:0] _GEN_4 = {1'h0, _GEN_0[_entry_T_1]}; // @[loop.scala:66:28, :110:31, :119:36]
wire [3:0] _wentry_conf_T = _GEN_4 - 4'h1; // @[loop.scala:119:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:119:36]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T_2 = _GEN_4 + 4'h1; // @[loop.scala:102:80, :119:36, :126:36]
wire [2:0] _wentry_conf_T_3 = _wentry_conf_T_2[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_5 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_6 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_6 | ~(_T_39 | ~(_T_44 | _GEN_5 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? _wentry_conf_T_1 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_3 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:{22,36}, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_7 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_8 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_8 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_7 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_8 | ~(_T_44 | _T_47 | ~_GEN_7)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_6 | _T_39 | ~(_T_44 | ~(_GEN_5 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_9 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_318 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_62
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_318( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_62 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_166 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_181
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_166( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_181 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SourceB :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<11>, set : UInt<10>, clients : UInt<4>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset remain : UInt<4>, clock, reset, UInt<4>(0h0)
wire remain_set : UInt<4>
connect remain_set, UInt<4>(0h0)
wire remain_clr : UInt<4>
connect remain_clr, UInt<4>(0h0)
node _remain_T = or(remain, remain_set)
node _remain_T_1 = not(remain_clr)
node _remain_T_2 = and(_remain_T, _remain_T_1)
connect remain, _remain_T_2
node busy = orr(remain)
node todo = mux(busy, remain, io.req.bits.clients)
node _next_T = shl(todo, 1)
node _next_T_1 = bits(_next_T, 3, 0)
node _next_T_2 = or(todo, _next_T_1)
node _next_T_3 = shl(_next_T_2, 2)
node _next_T_4 = bits(_next_T_3, 3, 0)
node _next_T_5 = or(_next_T_2, _next_T_4)
node _next_T_6 = bits(_next_T_5, 3, 0)
node _next_T_7 = shl(_next_T_6, 1)
node _next_T_8 = not(_next_T_7)
node next = and(_next_T_8, todo)
node _T = bits(remain, 0, 0)
node _T_1 = bits(remain, 1, 1)
node _T_2 = bits(remain, 2, 2)
node _T_3 = bits(remain, 3, 3)
node _T_4 = add(_T, _T_1)
node _T_5 = bits(_T_4, 1, 0)
node _T_6 = add(_T_2, _T_3)
node _T_7 = bits(_T_6, 1, 0)
node _T_8 = add(_T_5, _T_7)
node _T_9 = bits(_T_8, 2, 0)
node _T_10 = gt(_T_9, UInt<1>(0h1))
node _T_11 = eq(io.req.valid, UInt<1>(0h0))
node _T_12 = neq(io.req.bits.clients, UInt<1>(0h0))
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid || io.req.bits.clients =/= 0.U)\n") : printf
assert(clock, _T_13, UInt<1>(0h1), "") : assert
node _io_req_ready_T = eq(busy, UInt<1>(0h0))
connect io.req.ready, _io_req_ready_T
node _T_17 = and(io.req.ready, io.req.valid)
when _T_17 :
connect remain_set, io.req.bits.clients
wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect io.b, b
node _b_valid_T = or(busy, io.req.valid)
connect b.valid, _b_valid_T
node _T_18 = and(b.ready, b.valid)
when _T_18 :
connect remain_clr, next
node _T_19 = eq(b.ready, UInt<1>(0h0))
node _T_20 = and(b.valid, _T_19)
node _tag_T = eq(busy, UInt<1>(0h0))
node _tag_T_1 = and(io.req.ready, io.req.valid)
reg tag_r : UInt<11>, clock
when _tag_T_1 :
connect tag_r, io.req.bits.tag
node tag = mux(_tag_T, io.req.bits.tag, tag_r)
node _set_T = eq(busy, UInt<1>(0h0))
node _set_T_1 = and(io.req.ready, io.req.valid)
reg set_r : UInt<10>, clock
when _set_T_1 :
connect set_r, io.req.bits.set
node set = mux(_set_T, io.req.bits.set, set_r)
node _param_T = eq(busy, UInt<1>(0h0))
node _param_T_1 = and(io.req.ready, io.req.valid)
reg param_r : UInt<3>, clock
when _param_T_1 :
connect param_r, io.req.bits.param
node param = mux(_param_T, io.req.bits.param, param_r)
connect b.bits.opcode, UInt<3>(0h6)
connect b.bits.param, param
connect b.bits.size, UInt<3>(0h6)
node _b_bits_source_T = bits(next, 0, 0)
node _b_bits_source_T_1 = bits(next, 1, 1)
node _b_bits_source_T_2 = bits(next, 2, 2)
node _b_bits_source_T_3 = bits(next, 3, 3)
node _b_bits_source_T_4 = mux(_b_bits_source_T, UInt<6>(0h2c), UInt<1>(0h0))
node _b_bits_source_T_5 = mux(_b_bits_source_T_1, UInt<6>(0h28), UInt<1>(0h0))
node _b_bits_source_T_6 = mux(_b_bits_source_T_2, UInt<6>(0h24), UInt<1>(0h0))
node _b_bits_source_T_7 = mux(_b_bits_source_T_3, UInt<6>(0h20), UInt<1>(0h0))
node _b_bits_source_T_8 = or(_b_bits_source_T_4, _b_bits_source_T_5)
node _b_bits_source_T_9 = or(_b_bits_source_T_8, _b_bits_source_T_6)
node _b_bits_source_T_10 = or(_b_bits_source_T_9, _b_bits_source_T_7)
wire _b_bits_source_WIRE : UInt<6>
connect _b_bits_source_WIRE, _b_bits_source_T_10
connect b.bits.source, _b_bits_source_WIRE
node b_bits_address_base_y = or(tag, UInt<11>(0h0))
node _b_bits_address_base_T = shr(b_bits_address_base_y, 11)
node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0))
node _b_bits_address_base_T_2 = asUInt(reset)
node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0))
when _b_bits_address_base_T_3 :
node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0))
when _b_bits_address_base_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf
assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert
node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 10, 0)
node b_bits_address_base_y_1 = or(set, UInt<10>(0h0))
node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 10)
node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0))
node _b_bits_address_base_T_8 = asUInt(reset)
node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0))
when _b_bits_address_base_T_9 :
node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0))
when _b_bits_address_base_T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1
assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1
node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 9, 0)
node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0))
node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6)
node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0))
node _b_bits_address_base_T_14 = asUInt(reset)
node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0))
when _b_bits_address_base_T_15 :
node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0))
when _b_bits_address_base_T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2
assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2
node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0)
node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11)
node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17)
node _b_bits_address_T = bits(b_bits_address_base, 0, 0)
node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1)
node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2)
node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3)
node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4)
node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5)
node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6)
node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7)
node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8)
node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9)
node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10)
node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11)
node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12)
node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13)
node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14)
node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15)
node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16)
node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17)
node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18)
node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19)
node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20)
node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21)
node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22)
node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23)
node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24)
node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25)
node _b_bits_address_T_26 = bits(b_bits_address_base, 26, 26)
node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T)
node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2)
node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo)
node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4)
node b_bits_address_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo)
node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo)
node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_7, _b_bits_address_T_6)
node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_9, _b_bits_address_T_8)
node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo)
node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_11, _b_bits_address_T_10)
node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_13, _b_bits_address_T_12)
node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo)
node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo)
node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo)
node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_15, _b_bits_address_T_14)
node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_17, _b_bits_address_T_16)
node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo)
node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_19, _b_bits_address_T_18)
node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_21, _b_bits_address_T_20)
node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo)
node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo)
node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_23, _b_bits_address_T_22)
node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_25, _b_bits_address_T_24)
node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo)
node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node b_bits_address_hi_hi_hi_hi = cat(_b_bits_address_T_26, UInt<1>(0h0))
node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo)
node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo)
node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo)
node _b_bits_address_T_27 = cat(b_bits_address_hi, b_bits_address_lo)
connect b.bits.address, _b_bits_address_T_27
node _b_bits_mask_T = not(UInt<8>(0h0))
connect b.bits.mask, _b_bits_mask_T
connect b.bits.data, UInt<1>(0h0)
connect b.bits.corrupt, UInt<1>(0h0) | module SourceB( // @[SourceB.scala:33:7]
input clock, // @[SourceB.scala:33:7]
input reset, // @[SourceB.scala:33:7]
output io_req_ready, // @[SourceB.scala:35:14]
input io_req_valid, // @[SourceB.scala:35:14]
input [2:0] io_req_bits_param, // @[SourceB.scala:35:14]
input [10:0] io_req_bits_tag, // @[SourceB.scala:35:14]
input [9:0] io_req_bits_set, // @[SourceB.scala:35:14]
input [3:0] io_req_bits_clients, // @[SourceB.scala:35:14]
input io_b_ready, // @[SourceB.scala:35:14]
output io_b_valid, // @[SourceB.scala:35:14]
output [1:0] io_b_bits_param, // @[SourceB.scala:35:14]
output [5:0] io_b_bits_source, // @[SourceB.scala:35:14]
output [31:0] io_b_bits_address // @[SourceB.scala:35:14]
);
reg [3:0] remain; // @[SourceB.scala:46:25]
wire [3:0] todo = (|remain) ? remain : io_req_bits_clients; // @[SourceB.scala:46:25, :51:23, :52:19]
wire [2:0] _next_T_2 = todo[2:0] | {todo[1:0], 1'h0}; // @[package.scala:253:{43,53}]
wire [3:0] _GEN = {~(_next_T_2 | {_next_T_2[0], 2'h0}), 1'h1} & todo; // @[package.scala:253:{43,53}] |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_11 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock
inst q of Queue3_EgressFlit_11
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19)
node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22)
node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25)
node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h8), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h4), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0he), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h6), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h0), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_32 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0ha), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_33 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0hc), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_34 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0h10), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_35 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h2), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28)
node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_29)
node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_30)
node _q_io_enq_bits_ingress_id_T_39 = or(_q_io_enq_bits_ingress_id_T_38, _q_io_enq_bits_ingress_id_T_31)
node _q_io_enq_bits_ingress_id_T_40 = or(_q_io_enq_bits_ingress_id_T_39, _q_io_enq_bits_ingress_id_T_32)
node _q_io_enq_bits_ingress_id_T_41 = or(_q_io_enq_bits_ingress_id_T_40, _q_io_enq_bits_ingress_id_T_33)
node _q_io_enq_bits_ingress_id_T_42 = or(_q_io_enq_bits_ingress_id_T_41, _q_io_enq_bits_ingress_id_T_34)
node _q_io_enq_bits_ingress_id_T_43 = or(_q_io_enq_bits_ingress_id_T_42, _q_io_enq_bits_ingress_id_T_35)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_43
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_11( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_25 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_204 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_364
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_204( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_364 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module FpPipeline :
input clock : Clock
input reset : Reset
output io : { flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush_pipeline : UInt<1>, flip fcsr_rm : UInt<3>, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], flip ll_wports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1], flip from_int : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, dgen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}, to_int : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2], wb : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[2], flip debug_tsc_reg : UInt<64>}
inst fp_exe_unit_0 of FPExeUnit
connect fp_exe_unit_0.clock, clock
connect fp_exe_unit_0.reset, reset
inst fp_issue_unit of IssueUnitCollapsing
connect fp_issue_unit.clock, clock
connect fp_issue_unit.reset, reset
inst fregfile of BankedRF
connect fregfile.clock, clock
connect fregfile.reset, reset
wire fp_bypasses : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1]
wire fp_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2]
connect io.wakeups, fp_wakeups
connect fp_issue_unit.io.tsc_reg, io.debug_tsc_reg
connect fp_issue_unit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect fp_issue_unit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect fp_issue_unit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect fp_issue_unit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect fp_issue_unit.io.brupdate.b2.taken, io.brupdate.b2.taken
connect fp_issue_unit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect fp_issue_unit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect fp_issue_unit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect fp_issue_unit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect fp_issue_unit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect fp_issue_unit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect fp_issue_unit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect fp_issue_unit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect fp_issue_unit.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect fp_issue_unit.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect fp_issue_unit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect fp_issue_unit.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect fp_issue_unit.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect fp_issue_unit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect fp_issue_unit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect fp_issue_unit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect fp_issue_unit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect fp_issue_unit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect fp_issue_unit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect fp_issue_unit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect fp_issue_unit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect fp_issue_unit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect fp_issue_unit.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect fp_issue_unit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect fp_issue_unit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect fp_issue_unit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect fp_issue_unit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect fp_issue_unit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect fp_issue_unit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect fp_issue_unit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect fp_issue_unit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect fp_issue_unit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect fp_issue_unit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect fp_issue_unit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect fp_issue_unit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect fp_issue_unit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect fp_issue_unit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect fp_issue_unit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect fp_issue_unit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect fp_issue_unit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect fp_issue_unit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect fp_issue_unit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect fp_issue_unit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect fp_issue_unit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect fp_issue_unit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect fp_issue_unit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect fp_issue_unit.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect fp_issue_unit.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect fp_issue_unit.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect fp_issue_unit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect fp_issue_unit.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect fp_issue_unit.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect fp_issue_unit.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect fp_issue_unit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect fp_issue_unit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect fp_issue_unit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect fp_issue_unit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect fp_issue_unit.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect fp_issue_unit.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect fp_issue_unit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect fp_issue_unit.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect fp_issue_unit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect fp_issue_unit.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect fp_issue_unit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect fp_issue_unit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect fp_issue_unit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect fp_issue_unit.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect fp_issue_unit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect fp_issue_unit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect fp_issue_unit.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect fp_issue_unit.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect fp_issue_unit.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect fp_issue_unit.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect fp_issue_unit.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect fp_issue_unit.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect fp_issue_unit.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect fp_issue_unit.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect fp_issue_unit.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect fp_issue_unit.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect fp_issue_unit.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect fp_issue_unit.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect fp_issue_unit.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect fp_issue_unit.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect fp_issue_unit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect fp_issue_unit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect fp_issue_unit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect fp_issue_unit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect fp_issue_unit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect fp_issue_unit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect fp_issue_unit.io.flush_pipeline, io.flush_pipeline
connect fp_issue_unit.io.squash_grant, fp_exe_unit_0.io_squash_iss
connect fp_issue_unit.io.dis_uops[0], io.dis_uops[0]
connect fp_issue_unit.io.dis_uops[1], io.dis_uops[1]
connect fp_issue_unit.io.dis_uops[2], io.dis_uops[2]
connect fp_issue_unit.io.fu_types[0][0], fp_exe_unit_0.io_ready_fu_types[0]
connect fp_issue_unit.io.fu_types[0][1], fp_exe_unit_0.io_ready_fu_types[1]
connect fp_issue_unit.io.fu_types[0][2], fp_exe_unit_0.io_ready_fu_types[2]
connect fp_issue_unit.io.fu_types[0][3], fp_exe_unit_0.io_ready_fu_types[3]
connect fp_issue_unit.io.fu_types[0][4], fp_exe_unit_0.io_ready_fu_types[4]
connect fp_issue_unit.io.fu_types[0][5], fp_exe_unit_0.io_ready_fu_types[5]
connect fp_issue_unit.io.fu_types[0][6], fp_exe_unit_0.io_ready_fu_types[6]
connect fp_issue_unit.io.fu_types[0][7], fp_exe_unit_0.io_ready_fu_types[7]
connect fp_issue_unit.io.fu_types[0][8], fp_exe_unit_0.io_ready_fu_types[8]
connect fp_issue_unit.io.fu_types[0][9], fp_exe_unit_0.io_ready_fu_types[9]
connect fp_issue_unit.io.wakeup_ports[0].bits.rebusy, fp_wakeups[0].bits.rebusy
connect fp_issue_unit.io.wakeup_ports[0].bits.speculative_mask, fp_wakeups[0].bits.speculative_mask
connect fp_issue_unit.io.wakeup_ports[0].bits.bypassable, fp_wakeups[0].bits.bypassable
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.debug_tsrc, fp_wakeups[0].bits.uop.debug_tsrc
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.debug_fsrc, fp_wakeups[0].bits.uop.debug_fsrc
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.bp_xcpt_if, fp_wakeups[0].bits.uop.bp_xcpt_if
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.bp_debug_if, fp_wakeups[0].bits.uop.bp_debug_if
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.xcpt_ma_if, fp_wakeups[0].bits.uop.xcpt_ma_if
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.xcpt_ae_if, fp_wakeups[0].bits.uop.xcpt_ae_if
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.xcpt_pf_if, fp_wakeups[0].bits.uop.xcpt_pf_if
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_typ, fp_wakeups[0].bits.uop.fp_typ
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_rm, fp_wakeups[0].bits.uop.fp_rm
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_val, fp_wakeups[0].bits.uop.fp_val
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fcn_op, fp_wakeups[0].bits.uop.fcn_op
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fcn_dw, fp_wakeups[0].bits.uop.fcn_dw
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.frs3_en, fp_wakeups[0].bits.uop.frs3_en
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.lrs2_rtype, fp_wakeups[0].bits.uop.lrs2_rtype
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.lrs1_rtype, fp_wakeups[0].bits.uop.lrs1_rtype
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.dst_rtype, fp_wakeups[0].bits.uop.dst_rtype
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.lrs3, fp_wakeups[0].bits.uop.lrs3
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.lrs2, fp_wakeups[0].bits.uop.lrs2
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.lrs1, fp_wakeups[0].bits.uop.lrs1
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.ldst, fp_wakeups[0].bits.uop.ldst
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.ldst_is_rs1, fp_wakeups[0].bits.uop.ldst_is_rs1
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.csr_cmd, fp_wakeups[0].bits.uop.csr_cmd
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.flush_on_commit, fp_wakeups[0].bits.uop.flush_on_commit
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_unique, fp_wakeups[0].bits.uop.is_unique
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.uses_stq, fp_wakeups[0].bits.uop.uses_stq
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.uses_ldq, fp_wakeups[0].bits.uop.uses_ldq
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.mem_signed, fp_wakeups[0].bits.uop.mem_signed
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.mem_size, fp_wakeups[0].bits.uop.mem_size
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.mem_cmd, fp_wakeups[0].bits.uop.mem_cmd
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.exc_cause, fp_wakeups[0].bits.uop.exc_cause
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.exception, fp_wakeups[0].bits.uop.exception
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.stale_pdst, fp_wakeups[0].bits.uop.stale_pdst
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.ppred_busy, fp_wakeups[0].bits.uop.ppred_busy
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.prs3_busy, fp_wakeups[0].bits.uop.prs3_busy
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.prs2_busy, fp_wakeups[0].bits.uop.prs2_busy
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.prs1_busy, fp_wakeups[0].bits.uop.prs1_busy
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.ppred, fp_wakeups[0].bits.uop.ppred
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.prs3, fp_wakeups[0].bits.uop.prs3
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.prs2, fp_wakeups[0].bits.uop.prs2
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.prs1, fp_wakeups[0].bits.uop.prs1
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.pdst, fp_wakeups[0].bits.uop.pdst
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.rxq_idx, fp_wakeups[0].bits.uop.rxq_idx
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.stq_idx, fp_wakeups[0].bits.uop.stq_idx
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.ldq_idx, fp_wakeups[0].bits.uop.ldq_idx
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.rob_idx, fp_wakeups[0].bits.uop.rob_idx
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, fp_wakeups[0].bits.uop.fp_ctrl.vec
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, fp_wakeups[0].bits.uop.fp_ctrl.wflags
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, fp_wakeups[0].bits.uop.fp_ctrl.sqrt
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.div, fp_wakeups[0].bits.uop.fp_ctrl.div
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, fp_wakeups[0].bits.uop.fp_ctrl.fma
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, fp_wakeups[0].bits.uop.fp_ctrl.fastpipe
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, fp_wakeups[0].bits.uop.fp_ctrl.toint
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, fp_wakeups[0].bits.uop.fp_ctrl.fromint
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, fp_wakeups[0].bits.uop.fp_ctrl.typeTagOut
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, fp_wakeups[0].bits.uop.fp_ctrl.typeTagIn
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, fp_wakeups[0].bits.uop.fp_ctrl.swap23
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, fp_wakeups[0].bits.uop.fp_ctrl.swap12
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, fp_wakeups[0].bits.uop.fp_ctrl.ren3
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, fp_wakeups[0].bits.uop.fp_ctrl.ren2
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, fp_wakeups[0].bits.uop.fp_ctrl.ren1
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, fp_wakeups[0].bits.uop.fp_ctrl.wen
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, fp_wakeups[0].bits.uop.fp_ctrl.ldst
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.op2_sel, fp_wakeups[0].bits.uop.op2_sel
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.op1_sel, fp_wakeups[0].bits.uop.op1_sel
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.imm_packed, fp_wakeups[0].bits.uop.imm_packed
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.pimm, fp_wakeups[0].bits.uop.pimm
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.imm_sel, fp_wakeups[0].bits.uop.imm_sel
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.imm_rename, fp_wakeups[0].bits.uop.imm_rename
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.taken, fp_wakeups[0].bits.uop.taken
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.pc_lob, fp_wakeups[0].bits.uop.pc_lob
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.edge_inst, fp_wakeups[0].bits.uop.edge_inst
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.ftq_idx, fp_wakeups[0].bits.uop.ftq_idx
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_mov, fp_wakeups[0].bits.uop.is_mov
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_rocc, fp_wakeups[0].bits.uop.is_rocc
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, fp_wakeups[0].bits.uop.is_sys_pc2epc
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_eret, fp_wakeups[0].bits.uop.is_eret
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_amo, fp_wakeups[0].bits.uop.is_amo
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_sfence, fp_wakeups[0].bits.uop.is_sfence
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_fencei, fp_wakeups[0].bits.uop.is_fencei
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_fence, fp_wakeups[0].bits.uop.is_fence
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_sfb, fp_wakeups[0].bits.uop.is_sfb
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.br_type, fp_wakeups[0].bits.uop.br_type
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.br_tag, fp_wakeups[0].bits.uop.br_tag
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.br_mask, fp_wakeups[0].bits.uop.br_mask
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.dis_col_sel, fp_wakeups[0].bits.uop.dis_col_sel
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, fp_wakeups[0].bits.uop.iw_p3_bypass_hint
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, fp_wakeups[0].bits.uop.iw_p2_bypass_hint
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, fp_wakeups[0].bits.uop.iw_p1_bypass_hint
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, fp_wakeups[0].bits.uop.iw_p2_speculative_child
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, fp_wakeups[0].bits.uop.iw_p1_speculative_child
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, fp_wakeups[0].bits.uop.iw_issued_partial_dgen
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, fp_wakeups[0].bits.uop.iw_issued_partial_agen
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iw_issued, fp_wakeups[0].bits.uop.iw_issued
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[0], fp_wakeups[0].bits.uop.fu_code[0]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[1], fp_wakeups[0].bits.uop.fu_code[1]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[2], fp_wakeups[0].bits.uop.fu_code[2]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[3], fp_wakeups[0].bits.uop.fu_code[3]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[4], fp_wakeups[0].bits.uop.fu_code[4]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[5], fp_wakeups[0].bits.uop.fu_code[5]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[6], fp_wakeups[0].bits.uop.fu_code[6]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[7], fp_wakeups[0].bits.uop.fu_code[7]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[8], fp_wakeups[0].bits.uop.fu_code[8]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.fu_code[9], fp_wakeups[0].bits.uop.fu_code[9]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iq_type[0], fp_wakeups[0].bits.uop.iq_type[0]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iq_type[1], fp_wakeups[0].bits.uop.iq_type[1]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iq_type[2], fp_wakeups[0].bits.uop.iq_type[2]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.iq_type[3], fp_wakeups[0].bits.uop.iq_type[3]
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.debug_pc, fp_wakeups[0].bits.uop.debug_pc
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.is_rvc, fp_wakeups[0].bits.uop.is_rvc
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.debug_inst, fp_wakeups[0].bits.uop.debug_inst
connect fp_issue_unit.io.wakeup_ports[0].bits.uop.inst, fp_wakeups[0].bits.uop.inst
connect fp_issue_unit.io.wakeup_ports[0].valid, fp_wakeups[0].valid
connect fp_issue_unit.io.wakeup_ports[1].bits.rebusy, fp_wakeups[1].bits.rebusy
connect fp_issue_unit.io.wakeup_ports[1].bits.speculative_mask, fp_wakeups[1].bits.speculative_mask
connect fp_issue_unit.io.wakeup_ports[1].bits.bypassable, fp_wakeups[1].bits.bypassable
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.debug_tsrc, fp_wakeups[1].bits.uop.debug_tsrc
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.debug_fsrc, fp_wakeups[1].bits.uop.debug_fsrc
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.bp_xcpt_if, fp_wakeups[1].bits.uop.bp_xcpt_if
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.bp_debug_if, fp_wakeups[1].bits.uop.bp_debug_if
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.xcpt_ma_if, fp_wakeups[1].bits.uop.xcpt_ma_if
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.xcpt_ae_if, fp_wakeups[1].bits.uop.xcpt_ae_if
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.xcpt_pf_if, fp_wakeups[1].bits.uop.xcpt_pf_if
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_typ, fp_wakeups[1].bits.uop.fp_typ
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_rm, fp_wakeups[1].bits.uop.fp_rm
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_val, fp_wakeups[1].bits.uop.fp_val
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fcn_op, fp_wakeups[1].bits.uop.fcn_op
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fcn_dw, fp_wakeups[1].bits.uop.fcn_dw
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.frs3_en, fp_wakeups[1].bits.uop.frs3_en
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.lrs2_rtype, fp_wakeups[1].bits.uop.lrs2_rtype
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.lrs1_rtype, fp_wakeups[1].bits.uop.lrs1_rtype
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.dst_rtype, fp_wakeups[1].bits.uop.dst_rtype
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.lrs3, fp_wakeups[1].bits.uop.lrs3
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.lrs2, fp_wakeups[1].bits.uop.lrs2
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.lrs1, fp_wakeups[1].bits.uop.lrs1
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.ldst, fp_wakeups[1].bits.uop.ldst
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.ldst_is_rs1, fp_wakeups[1].bits.uop.ldst_is_rs1
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.csr_cmd, fp_wakeups[1].bits.uop.csr_cmd
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.flush_on_commit, fp_wakeups[1].bits.uop.flush_on_commit
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_unique, fp_wakeups[1].bits.uop.is_unique
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.uses_stq, fp_wakeups[1].bits.uop.uses_stq
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.uses_ldq, fp_wakeups[1].bits.uop.uses_ldq
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.mem_signed, fp_wakeups[1].bits.uop.mem_signed
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.mem_size, fp_wakeups[1].bits.uop.mem_size
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.mem_cmd, fp_wakeups[1].bits.uop.mem_cmd
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.exc_cause, fp_wakeups[1].bits.uop.exc_cause
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.exception, fp_wakeups[1].bits.uop.exception
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.stale_pdst, fp_wakeups[1].bits.uop.stale_pdst
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.ppred_busy, fp_wakeups[1].bits.uop.ppred_busy
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.prs3_busy, fp_wakeups[1].bits.uop.prs3_busy
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.prs2_busy, fp_wakeups[1].bits.uop.prs2_busy
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.prs1_busy, fp_wakeups[1].bits.uop.prs1_busy
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.ppred, fp_wakeups[1].bits.uop.ppred
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.prs3, fp_wakeups[1].bits.uop.prs3
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.prs2, fp_wakeups[1].bits.uop.prs2
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.prs1, fp_wakeups[1].bits.uop.prs1
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.pdst, fp_wakeups[1].bits.uop.pdst
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.rxq_idx, fp_wakeups[1].bits.uop.rxq_idx
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.stq_idx, fp_wakeups[1].bits.uop.stq_idx
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.ldq_idx, fp_wakeups[1].bits.uop.ldq_idx
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.rob_idx, fp_wakeups[1].bits.uop.rob_idx
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, fp_wakeups[1].bits.uop.fp_ctrl.vec
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, fp_wakeups[1].bits.uop.fp_ctrl.wflags
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, fp_wakeups[1].bits.uop.fp_ctrl.sqrt
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.div, fp_wakeups[1].bits.uop.fp_ctrl.div
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, fp_wakeups[1].bits.uop.fp_ctrl.fma
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, fp_wakeups[1].bits.uop.fp_ctrl.fastpipe
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, fp_wakeups[1].bits.uop.fp_ctrl.toint
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, fp_wakeups[1].bits.uop.fp_ctrl.fromint
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, fp_wakeups[1].bits.uop.fp_ctrl.typeTagOut
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, fp_wakeups[1].bits.uop.fp_ctrl.typeTagIn
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, fp_wakeups[1].bits.uop.fp_ctrl.swap23
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, fp_wakeups[1].bits.uop.fp_ctrl.swap12
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, fp_wakeups[1].bits.uop.fp_ctrl.ren3
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, fp_wakeups[1].bits.uop.fp_ctrl.ren2
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, fp_wakeups[1].bits.uop.fp_ctrl.ren1
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, fp_wakeups[1].bits.uop.fp_ctrl.wen
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, fp_wakeups[1].bits.uop.fp_ctrl.ldst
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.op2_sel, fp_wakeups[1].bits.uop.op2_sel
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.op1_sel, fp_wakeups[1].bits.uop.op1_sel
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.imm_packed, fp_wakeups[1].bits.uop.imm_packed
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.pimm, fp_wakeups[1].bits.uop.pimm
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.imm_sel, fp_wakeups[1].bits.uop.imm_sel
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.imm_rename, fp_wakeups[1].bits.uop.imm_rename
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.taken, fp_wakeups[1].bits.uop.taken
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.pc_lob, fp_wakeups[1].bits.uop.pc_lob
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.edge_inst, fp_wakeups[1].bits.uop.edge_inst
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.ftq_idx, fp_wakeups[1].bits.uop.ftq_idx
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_mov, fp_wakeups[1].bits.uop.is_mov
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_rocc, fp_wakeups[1].bits.uop.is_rocc
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, fp_wakeups[1].bits.uop.is_sys_pc2epc
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_eret, fp_wakeups[1].bits.uop.is_eret
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_amo, fp_wakeups[1].bits.uop.is_amo
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_sfence, fp_wakeups[1].bits.uop.is_sfence
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_fencei, fp_wakeups[1].bits.uop.is_fencei
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_fence, fp_wakeups[1].bits.uop.is_fence
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_sfb, fp_wakeups[1].bits.uop.is_sfb
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.br_type, fp_wakeups[1].bits.uop.br_type
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.br_tag, fp_wakeups[1].bits.uop.br_tag
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.br_mask, fp_wakeups[1].bits.uop.br_mask
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.dis_col_sel, fp_wakeups[1].bits.uop.dis_col_sel
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, fp_wakeups[1].bits.uop.iw_p3_bypass_hint
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, fp_wakeups[1].bits.uop.iw_p2_bypass_hint
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, fp_wakeups[1].bits.uop.iw_p1_bypass_hint
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, fp_wakeups[1].bits.uop.iw_p2_speculative_child
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, fp_wakeups[1].bits.uop.iw_p1_speculative_child
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, fp_wakeups[1].bits.uop.iw_issued_partial_dgen
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, fp_wakeups[1].bits.uop.iw_issued_partial_agen
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iw_issued, fp_wakeups[1].bits.uop.iw_issued
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[0], fp_wakeups[1].bits.uop.fu_code[0]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[1], fp_wakeups[1].bits.uop.fu_code[1]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[2], fp_wakeups[1].bits.uop.fu_code[2]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[3], fp_wakeups[1].bits.uop.fu_code[3]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[4], fp_wakeups[1].bits.uop.fu_code[4]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[5], fp_wakeups[1].bits.uop.fu_code[5]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[6], fp_wakeups[1].bits.uop.fu_code[6]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[7], fp_wakeups[1].bits.uop.fu_code[7]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[8], fp_wakeups[1].bits.uop.fu_code[8]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.fu_code[9], fp_wakeups[1].bits.uop.fu_code[9]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iq_type[0], fp_wakeups[1].bits.uop.iq_type[0]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iq_type[1], fp_wakeups[1].bits.uop.iq_type[1]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iq_type[2], fp_wakeups[1].bits.uop.iq_type[2]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.iq_type[3], fp_wakeups[1].bits.uop.iq_type[3]
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.debug_pc, fp_wakeups[1].bits.uop.debug_pc
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.is_rvc, fp_wakeups[1].bits.uop.is_rvc
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.debug_inst, fp_wakeups[1].bits.uop.debug_inst
connect fp_issue_unit.io.wakeup_ports[1].bits.uop.inst, fp_wakeups[1].bits.uop.inst
connect fp_issue_unit.io.wakeup_ports[1].valid, fp_wakeups[1].valid
connect fp_issue_unit.io.pred_wakeup_port.valid, UInt<1>(0h0)
invalidate fp_issue_unit.io.pred_wakeup_port.bits
connect fp_issue_unit.io.child_rebusys, UInt<1>(0h0)
connect fp_exe_unit_0.io_iss_uop.bits.debug_tsrc, fp_issue_unit.io.iss_uops[0].bits.debug_tsrc
connect fp_exe_unit_0.io_iss_uop.bits.debug_fsrc, fp_issue_unit.io.iss_uops[0].bits.debug_fsrc
connect fp_exe_unit_0.io_iss_uop.bits.bp_xcpt_if, fp_issue_unit.io.iss_uops[0].bits.bp_xcpt_if
connect fp_exe_unit_0.io_iss_uop.bits.bp_debug_if, fp_issue_unit.io.iss_uops[0].bits.bp_debug_if
connect fp_exe_unit_0.io_iss_uop.bits.xcpt_ma_if, fp_issue_unit.io.iss_uops[0].bits.xcpt_ma_if
connect fp_exe_unit_0.io_iss_uop.bits.xcpt_ae_if, fp_issue_unit.io.iss_uops[0].bits.xcpt_ae_if
connect fp_exe_unit_0.io_iss_uop.bits.xcpt_pf_if, fp_issue_unit.io.iss_uops[0].bits.xcpt_pf_if
connect fp_exe_unit_0.io_iss_uop.bits.fp_typ, fp_issue_unit.io.iss_uops[0].bits.fp_typ
connect fp_exe_unit_0.io_iss_uop.bits.fp_rm, fp_issue_unit.io.iss_uops[0].bits.fp_rm
connect fp_exe_unit_0.io_iss_uop.bits.fp_val, fp_issue_unit.io.iss_uops[0].bits.fp_val
connect fp_exe_unit_0.io_iss_uop.bits.fcn_op, fp_issue_unit.io.iss_uops[0].bits.fcn_op
connect fp_exe_unit_0.io_iss_uop.bits.fcn_dw, fp_issue_unit.io.iss_uops[0].bits.fcn_dw
connect fp_exe_unit_0.io_iss_uop.bits.frs3_en, fp_issue_unit.io.iss_uops[0].bits.frs3_en
connect fp_exe_unit_0.io_iss_uop.bits.lrs2_rtype, fp_issue_unit.io.iss_uops[0].bits.lrs2_rtype
connect fp_exe_unit_0.io_iss_uop.bits.lrs1_rtype, fp_issue_unit.io.iss_uops[0].bits.lrs1_rtype
connect fp_exe_unit_0.io_iss_uop.bits.dst_rtype, fp_issue_unit.io.iss_uops[0].bits.dst_rtype
connect fp_exe_unit_0.io_iss_uop.bits.lrs3, fp_issue_unit.io.iss_uops[0].bits.lrs3
connect fp_exe_unit_0.io_iss_uop.bits.lrs2, fp_issue_unit.io.iss_uops[0].bits.lrs2
connect fp_exe_unit_0.io_iss_uop.bits.lrs1, fp_issue_unit.io.iss_uops[0].bits.lrs1
connect fp_exe_unit_0.io_iss_uop.bits.ldst, fp_issue_unit.io.iss_uops[0].bits.ldst
connect fp_exe_unit_0.io_iss_uop.bits.ldst_is_rs1, fp_issue_unit.io.iss_uops[0].bits.ldst_is_rs1
connect fp_exe_unit_0.io_iss_uop.bits.csr_cmd, fp_issue_unit.io.iss_uops[0].bits.csr_cmd
connect fp_exe_unit_0.io_iss_uop.bits.flush_on_commit, fp_issue_unit.io.iss_uops[0].bits.flush_on_commit
connect fp_exe_unit_0.io_iss_uop.bits.is_unique, fp_issue_unit.io.iss_uops[0].bits.is_unique
connect fp_exe_unit_0.io_iss_uop.bits.uses_stq, fp_issue_unit.io.iss_uops[0].bits.uses_stq
connect fp_exe_unit_0.io_iss_uop.bits.uses_ldq, fp_issue_unit.io.iss_uops[0].bits.uses_ldq
connect fp_exe_unit_0.io_iss_uop.bits.mem_signed, fp_issue_unit.io.iss_uops[0].bits.mem_signed
connect fp_exe_unit_0.io_iss_uop.bits.mem_size, fp_issue_unit.io.iss_uops[0].bits.mem_size
connect fp_exe_unit_0.io_iss_uop.bits.mem_cmd, fp_issue_unit.io.iss_uops[0].bits.mem_cmd
connect fp_exe_unit_0.io_iss_uop.bits.exc_cause, fp_issue_unit.io.iss_uops[0].bits.exc_cause
connect fp_exe_unit_0.io_iss_uop.bits.exception, fp_issue_unit.io.iss_uops[0].bits.exception
connect fp_exe_unit_0.io_iss_uop.bits.stale_pdst, fp_issue_unit.io.iss_uops[0].bits.stale_pdst
connect fp_exe_unit_0.io_iss_uop.bits.ppred_busy, fp_issue_unit.io.iss_uops[0].bits.ppred_busy
connect fp_exe_unit_0.io_iss_uop.bits.prs3_busy, fp_issue_unit.io.iss_uops[0].bits.prs3_busy
connect fp_exe_unit_0.io_iss_uop.bits.prs2_busy, fp_issue_unit.io.iss_uops[0].bits.prs2_busy
connect fp_exe_unit_0.io_iss_uop.bits.prs1_busy, fp_issue_unit.io.iss_uops[0].bits.prs1_busy
connect fp_exe_unit_0.io_iss_uop.bits.ppred, fp_issue_unit.io.iss_uops[0].bits.ppred
connect fp_exe_unit_0.io_iss_uop.bits.prs3, fp_issue_unit.io.iss_uops[0].bits.prs3
connect fp_exe_unit_0.io_iss_uop.bits.prs2, fp_issue_unit.io.iss_uops[0].bits.prs2
connect fp_exe_unit_0.io_iss_uop.bits.prs1, fp_issue_unit.io.iss_uops[0].bits.prs1
connect fp_exe_unit_0.io_iss_uop.bits.pdst, fp_issue_unit.io.iss_uops[0].bits.pdst
connect fp_exe_unit_0.io_iss_uop.bits.rxq_idx, fp_issue_unit.io.iss_uops[0].bits.rxq_idx
connect fp_exe_unit_0.io_iss_uop.bits.stq_idx, fp_issue_unit.io.iss_uops[0].bits.stq_idx
connect fp_exe_unit_0.io_iss_uop.bits.ldq_idx, fp_issue_unit.io.iss_uops[0].bits.ldq_idx
connect fp_exe_unit_0.io_iss_uop.bits.rob_idx, fp_issue_unit.io.iss_uops[0].bits.rob_idx
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.vec, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.vec
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.wflags, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.wflags
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.sqrt, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.sqrt
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.div, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.div
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.fma, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.fma
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.fastpipe, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.fastpipe
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.toint, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.toint
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.fromint, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.fromint
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.typeTagOut, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.typeTagOut
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.typeTagIn, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.typeTagIn
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.swap23, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.swap23
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.swap12, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.swap12
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren3, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.ren3
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren2, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.ren2
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren1, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.ren1
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.wen, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.wen
connect fp_exe_unit_0.io_iss_uop.bits.fp_ctrl.ldst, fp_issue_unit.io.iss_uops[0].bits.fp_ctrl.ldst
connect fp_exe_unit_0.io_iss_uop.bits.op2_sel, fp_issue_unit.io.iss_uops[0].bits.op2_sel
connect fp_exe_unit_0.io_iss_uop.bits.op1_sel, fp_issue_unit.io.iss_uops[0].bits.op1_sel
connect fp_exe_unit_0.io_iss_uop.bits.imm_packed, fp_issue_unit.io.iss_uops[0].bits.imm_packed
connect fp_exe_unit_0.io_iss_uop.bits.pimm, fp_issue_unit.io.iss_uops[0].bits.pimm
connect fp_exe_unit_0.io_iss_uop.bits.imm_sel, fp_issue_unit.io.iss_uops[0].bits.imm_sel
connect fp_exe_unit_0.io_iss_uop.bits.imm_rename, fp_issue_unit.io.iss_uops[0].bits.imm_rename
connect fp_exe_unit_0.io_iss_uop.bits.taken, fp_issue_unit.io.iss_uops[0].bits.taken
connect fp_exe_unit_0.io_iss_uop.bits.pc_lob, fp_issue_unit.io.iss_uops[0].bits.pc_lob
connect fp_exe_unit_0.io_iss_uop.bits.edge_inst, fp_issue_unit.io.iss_uops[0].bits.edge_inst
connect fp_exe_unit_0.io_iss_uop.bits.ftq_idx, fp_issue_unit.io.iss_uops[0].bits.ftq_idx
connect fp_exe_unit_0.io_iss_uop.bits.is_mov, fp_issue_unit.io.iss_uops[0].bits.is_mov
connect fp_exe_unit_0.io_iss_uop.bits.is_rocc, fp_issue_unit.io.iss_uops[0].bits.is_rocc
connect fp_exe_unit_0.io_iss_uop.bits.is_sys_pc2epc, fp_issue_unit.io.iss_uops[0].bits.is_sys_pc2epc
connect fp_exe_unit_0.io_iss_uop.bits.is_eret, fp_issue_unit.io.iss_uops[0].bits.is_eret
connect fp_exe_unit_0.io_iss_uop.bits.is_amo, fp_issue_unit.io.iss_uops[0].bits.is_amo
connect fp_exe_unit_0.io_iss_uop.bits.is_sfence, fp_issue_unit.io.iss_uops[0].bits.is_sfence
connect fp_exe_unit_0.io_iss_uop.bits.is_fencei, fp_issue_unit.io.iss_uops[0].bits.is_fencei
connect fp_exe_unit_0.io_iss_uop.bits.is_fence, fp_issue_unit.io.iss_uops[0].bits.is_fence
connect fp_exe_unit_0.io_iss_uop.bits.is_sfb, fp_issue_unit.io.iss_uops[0].bits.is_sfb
connect fp_exe_unit_0.io_iss_uop.bits.br_type, fp_issue_unit.io.iss_uops[0].bits.br_type
connect fp_exe_unit_0.io_iss_uop.bits.br_tag, fp_issue_unit.io.iss_uops[0].bits.br_tag
connect fp_exe_unit_0.io_iss_uop.bits.br_mask, fp_issue_unit.io.iss_uops[0].bits.br_mask
connect fp_exe_unit_0.io_iss_uop.bits.dis_col_sel, fp_issue_unit.io.iss_uops[0].bits.dis_col_sel
connect fp_exe_unit_0.io_iss_uop.bits.iw_p3_bypass_hint, fp_issue_unit.io.iss_uops[0].bits.iw_p3_bypass_hint
connect fp_exe_unit_0.io_iss_uop.bits.iw_p2_bypass_hint, fp_issue_unit.io.iss_uops[0].bits.iw_p2_bypass_hint
connect fp_exe_unit_0.io_iss_uop.bits.iw_p1_bypass_hint, fp_issue_unit.io.iss_uops[0].bits.iw_p1_bypass_hint
connect fp_exe_unit_0.io_iss_uop.bits.iw_p2_speculative_child, fp_issue_unit.io.iss_uops[0].bits.iw_p2_speculative_child
connect fp_exe_unit_0.io_iss_uop.bits.iw_p1_speculative_child, fp_issue_unit.io.iss_uops[0].bits.iw_p1_speculative_child
connect fp_exe_unit_0.io_iss_uop.bits.iw_issued_partial_dgen, fp_issue_unit.io.iss_uops[0].bits.iw_issued_partial_dgen
connect fp_exe_unit_0.io_iss_uop.bits.iw_issued_partial_agen, fp_issue_unit.io.iss_uops[0].bits.iw_issued_partial_agen
connect fp_exe_unit_0.io_iss_uop.bits.iw_issued, fp_issue_unit.io.iss_uops[0].bits.iw_issued
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[0], fp_issue_unit.io.iss_uops[0].bits.fu_code[0]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[1], fp_issue_unit.io.iss_uops[0].bits.fu_code[1]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[2], fp_issue_unit.io.iss_uops[0].bits.fu_code[2]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[3], fp_issue_unit.io.iss_uops[0].bits.fu_code[3]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[4], fp_issue_unit.io.iss_uops[0].bits.fu_code[4]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[5], fp_issue_unit.io.iss_uops[0].bits.fu_code[5]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[6], fp_issue_unit.io.iss_uops[0].bits.fu_code[6]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[7], fp_issue_unit.io.iss_uops[0].bits.fu_code[7]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[8], fp_issue_unit.io.iss_uops[0].bits.fu_code[8]
connect fp_exe_unit_0.io_iss_uop.bits.fu_code[9], fp_issue_unit.io.iss_uops[0].bits.fu_code[9]
connect fp_exe_unit_0.io_iss_uop.bits.iq_type[0], fp_issue_unit.io.iss_uops[0].bits.iq_type[0]
connect fp_exe_unit_0.io_iss_uop.bits.iq_type[1], fp_issue_unit.io.iss_uops[0].bits.iq_type[1]
connect fp_exe_unit_0.io_iss_uop.bits.iq_type[2], fp_issue_unit.io.iss_uops[0].bits.iq_type[2]
connect fp_exe_unit_0.io_iss_uop.bits.iq_type[3], fp_issue_unit.io.iss_uops[0].bits.iq_type[3]
connect fp_exe_unit_0.io_iss_uop.bits.debug_pc, fp_issue_unit.io.iss_uops[0].bits.debug_pc
connect fp_exe_unit_0.io_iss_uop.bits.is_rvc, fp_issue_unit.io.iss_uops[0].bits.is_rvc
connect fp_exe_unit_0.io_iss_uop.bits.debug_inst, fp_issue_unit.io.iss_uops[0].bits.debug_inst
connect fp_exe_unit_0.io_iss_uop.bits.inst, fp_issue_unit.io.iss_uops[0].bits.inst
connect fp_exe_unit_0.io_iss_uop.valid, fp_issue_unit.io.iss_uops[0].valid
connect fregfile.io.arb_read_reqs[0], fp_exe_unit_0.io_arb_frf_reqs[0]
connect fregfile.io.arb_read_reqs[1], fp_exe_unit_0.io_arb_frf_reqs[1]
connect fregfile.io.arb_read_reqs[2], fp_exe_unit_0.io_arb_frf_reqs[2]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.fflags.bits, fp_bypasses[0].bits.fflags.bits
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.fflags.valid, fp_bypasses[0].bits.fflags.valid
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.predicated, fp_bypasses[0].bits.predicated
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.data, fp_bypasses[0].bits.data
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.debug_tsrc, fp_bypasses[0].bits.uop.debug_tsrc
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.debug_fsrc, fp_bypasses[0].bits.uop.debug_fsrc
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.bp_xcpt_if, fp_bypasses[0].bits.uop.bp_xcpt_if
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.bp_debug_if, fp_bypasses[0].bits.uop.bp_debug_if
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.xcpt_ma_if, fp_bypasses[0].bits.uop.xcpt_ma_if
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.xcpt_ae_if, fp_bypasses[0].bits.uop.xcpt_ae_if
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.xcpt_pf_if, fp_bypasses[0].bits.uop.xcpt_pf_if
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_typ, fp_bypasses[0].bits.uop.fp_typ
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_rm, fp_bypasses[0].bits.uop.fp_rm
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_val, fp_bypasses[0].bits.uop.fp_val
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fcn_op, fp_bypasses[0].bits.uop.fcn_op
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fcn_dw, fp_bypasses[0].bits.uop.fcn_dw
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.frs3_en, fp_bypasses[0].bits.uop.frs3_en
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.lrs2_rtype, fp_bypasses[0].bits.uop.lrs2_rtype
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.lrs1_rtype, fp_bypasses[0].bits.uop.lrs1_rtype
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.dst_rtype, fp_bypasses[0].bits.uop.dst_rtype
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.lrs3, fp_bypasses[0].bits.uop.lrs3
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.lrs2, fp_bypasses[0].bits.uop.lrs2
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.lrs1, fp_bypasses[0].bits.uop.lrs1
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.ldst, fp_bypasses[0].bits.uop.ldst
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.ldst_is_rs1, fp_bypasses[0].bits.uop.ldst_is_rs1
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.csr_cmd, fp_bypasses[0].bits.uop.csr_cmd
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.flush_on_commit, fp_bypasses[0].bits.uop.flush_on_commit
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_unique, fp_bypasses[0].bits.uop.is_unique
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.uses_stq, fp_bypasses[0].bits.uop.uses_stq
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.uses_ldq, fp_bypasses[0].bits.uop.uses_ldq
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.mem_signed, fp_bypasses[0].bits.uop.mem_signed
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.mem_size, fp_bypasses[0].bits.uop.mem_size
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.mem_cmd, fp_bypasses[0].bits.uop.mem_cmd
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.exc_cause, fp_bypasses[0].bits.uop.exc_cause
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.exception, fp_bypasses[0].bits.uop.exception
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.stale_pdst, fp_bypasses[0].bits.uop.stale_pdst
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.ppred_busy, fp_bypasses[0].bits.uop.ppred_busy
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.prs3_busy, fp_bypasses[0].bits.uop.prs3_busy
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.prs2_busy, fp_bypasses[0].bits.uop.prs2_busy
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.prs1_busy, fp_bypasses[0].bits.uop.prs1_busy
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.ppred, fp_bypasses[0].bits.uop.ppred
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.prs3, fp_bypasses[0].bits.uop.prs3
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.prs2, fp_bypasses[0].bits.uop.prs2
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.prs1, fp_bypasses[0].bits.uop.prs1
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.pdst, fp_bypasses[0].bits.uop.pdst
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.rxq_idx, fp_bypasses[0].bits.uop.rxq_idx
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.stq_idx, fp_bypasses[0].bits.uop.stq_idx
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.ldq_idx, fp_bypasses[0].bits.uop.ldq_idx
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.rob_idx, fp_bypasses[0].bits.uop.rob_idx
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.vec, fp_bypasses[0].bits.uop.fp_ctrl.vec
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.wflags, fp_bypasses[0].bits.uop.fp_ctrl.wflags
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.sqrt, fp_bypasses[0].bits.uop.fp_ctrl.sqrt
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.div, fp_bypasses[0].bits.uop.fp_ctrl.div
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.fma, fp_bypasses[0].bits.uop.fp_ctrl.fma
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.fastpipe, fp_bypasses[0].bits.uop.fp_ctrl.fastpipe
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.toint, fp_bypasses[0].bits.uop.fp_ctrl.toint
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.fromint, fp_bypasses[0].bits.uop.fp_ctrl.fromint
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.typeTagOut, fp_bypasses[0].bits.uop.fp_ctrl.typeTagOut
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.typeTagIn, fp_bypasses[0].bits.uop.fp_ctrl.typeTagIn
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.swap23, fp_bypasses[0].bits.uop.fp_ctrl.swap23
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.swap12, fp_bypasses[0].bits.uop.fp_ctrl.swap12
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.ren3, fp_bypasses[0].bits.uop.fp_ctrl.ren3
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.ren2, fp_bypasses[0].bits.uop.fp_ctrl.ren2
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.ren1, fp_bypasses[0].bits.uop.fp_ctrl.ren1
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.wen, fp_bypasses[0].bits.uop.fp_ctrl.wen
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fp_ctrl.ldst, fp_bypasses[0].bits.uop.fp_ctrl.ldst
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.op2_sel, fp_bypasses[0].bits.uop.op2_sel
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.op1_sel, fp_bypasses[0].bits.uop.op1_sel
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.imm_packed, fp_bypasses[0].bits.uop.imm_packed
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.pimm, fp_bypasses[0].bits.uop.pimm
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.imm_sel, fp_bypasses[0].bits.uop.imm_sel
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.imm_rename, fp_bypasses[0].bits.uop.imm_rename
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.taken, fp_bypasses[0].bits.uop.taken
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.pc_lob, fp_bypasses[0].bits.uop.pc_lob
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.edge_inst, fp_bypasses[0].bits.uop.edge_inst
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.ftq_idx, fp_bypasses[0].bits.uop.ftq_idx
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_mov, fp_bypasses[0].bits.uop.is_mov
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_rocc, fp_bypasses[0].bits.uop.is_rocc
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_sys_pc2epc, fp_bypasses[0].bits.uop.is_sys_pc2epc
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_eret, fp_bypasses[0].bits.uop.is_eret
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_amo, fp_bypasses[0].bits.uop.is_amo
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_sfence, fp_bypasses[0].bits.uop.is_sfence
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_fencei, fp_bypasses[0].bits.uop.is_fencei
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_fence, fp_bypasses[0].bits.uop.is_fence
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_sfb, fp_bypasses[0].bits.uop.is_sfb
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.br_type, fp_bypasses[0].bits.uop.br_type
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.br_tag, fp_bypasses[0].bits.uop.br_tag
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.br_mask, fp_bypasses[0].bits.uop.br_mask
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.dis_col_sel, fp_bypasses[0].bits.uop.dis_col_sel
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iw_p3_bypass_hint, fp_bypasses[0].bits.uop.iw_p3_bypass_hint
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iw_p2_bypass_hint, fp_bypasses[0].bits.uop.iw_p2_bypass_hint
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iw_p1_bypass_hint, fp_bypasses[0].bits.uop.iw_p1_bypass_hint
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iw_p2_speculative_child, fp_bypasses[0].bits.uop.iw_p2_speculative_child
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iw_p1_speculative_child, fp_bypasses[0].bits.uop.iw_p1_speculative_child
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iw_issued_partial_dgen, fp_bypasses[0].bits.uop.iw_issued_partial_dgen
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iw_issued_partial_agen, fp_bypasses[0].bits.uop.iw_issued_partial_agen
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iw_issued, fp_bypasses[0].bits.uop.iw_issued
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[0], fp_bypasses[0].bits.uop.fu_code[0]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[1], fp_bypasses[0].bits.uop.fu_code[1]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[2], fp_bypasses[0].bits.uop.fu_code[2]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[3], fp_bypasses[0].bits.uop.fu_code[3]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[4], fp_bypasses[0].bits.uop.fu_code[4]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[5], fp_bypasses[0].bits.uop.fu_code[5]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[6], fp_bypasses[0].bits.uop.fu_code[6]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[7], fp_bypasses[0].bits.uop.fu_code[7]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[8], fp_bypasses[0].bits.uop.fu_code[8]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.fu_code[9], fp_bypasses[0].bits.uop.fu_code[9]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iq_type[0], fp_bypasses[0].bits.uop.iq_type[0]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iq_type[1], fp_bypasses[0].bits.uop.iq_type[1]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iq_type[2], fp_bypasses[0].bits.uop.iq_type[2]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.iq_type[3], fp_bypasses[0].bits.uop.iq_type[3]
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.debug_pc, fp_bypasses[0].bits.uop.debug_pc
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.is_rvc, fp_bypasses[0].bits.uop.is_rvc
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.debug_inst, fp_bypasses[0].bits.uop.debug_inst
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].bits.uop.inst, fp_bypasses[0].bits.uop.inst
connect fp_exe_unit_0.io_rrd_frf_bypasses[0].valid, fp_bypasses[0].valid
connect fp_exe_unit_0.io_rrd_frf_resps[0], fregfile.io.rrd_read_resps[0]
connect fp_exe_unit_0.io_rrd_frf_resps[1], fregfile.io.rrd_read_resps[1]
connect fp_exe_unit_0.io_rrd_frf_resps[2], fregfile.io.rrd_read_resps[2]
connect fp_exe_unit_0.io_brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect fp_exe_unit_0.io_brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect fp_exe_unit_0.io_brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect fp_exe_unit_0.io_brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect fp_exe_unit_0.io_brupdate.b2.taken, io.brupdate.b2.taken
connect fp_exe_unit_0.io_brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect fp_exe_unit_0.io_brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect fp_exe_unit_0.io_brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect fp_exe_unit_0.io_brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect fp_exe_unit_0.io_brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect fp_exe_unit_0.io_brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect fp_exe_unit_0.io_brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect fp_exe_unit_0.io_brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect fp_exe_unit_0.io_brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect fp_exe_unit_0.io_brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect fp_exe_unit_0.io_brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect fp_exe_unit_0.io_brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect fp_exe_unit_0.io_brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect fp_exe_unit_0.io_brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect fp_exe_unit_0.io_brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect fp_exe_unit_0.io_brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect fp_exe_unit_0.io_brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect fp_exe_unit_0.io_brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect fp_exe_unit_0.io_brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect fp_exe_unit_0.io_brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect fp_exe_unit_0.io_brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect fp_exe_unit_0.io_brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect fp_exe_unit_0.io_brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect fp_exe_unit_0.io_brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect fp_exe_unit_0.io_brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect fp_exe_unit_0.io_brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect fp_exe_unit_0.io_brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect fp_exe_unit_0.io_brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect fp_exe_unit_0.io_brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect fp_exe_unit_0.io_brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect fp_exe_unit_0.io_brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect fp_exe_unit_0.io_brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect fp_exe_unit_0.io_brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect fp_exe_unit_0.io_brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect fp_exe_unit_0.io_brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect fp_exe_unit_0.io_brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect fp_exe_unit_0.io_brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect fp_exe_unit_0.io_brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect fp_exe_unit_0.io_brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect fp_exe_unit_0.io_brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect fp_exe_unit_0.io_brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect fp_exe_unit_0.io_brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect fp_exe_unit_0.io_brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect fp_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect fp_exe_unit_0.io_brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect fp_exe_unit_0.io_brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect fp_exe_unit_0.io_brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect fp_exe_unit_0.io_brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect fp_exe_unit_0.io_brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect fp_exe_unit_0.io_brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect fp_exe_unit_0.io_brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect fp_exe_unit_0.io_brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect fp_exe_unit_0.io_brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect fp_exe_unit_0.io_brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect fp_exe_unit_0.io_brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect fp_exe_unit_0.io_brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect fp_exe_unit_0.io_brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect fp_exe_unit_0.io_brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect fp_exe_unit_0.io_brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect fp_exe_unit_0.io_brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect fp_exe_unit_0.io_brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect fp_exe_unit_0.io_brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect fp_exe_unit_0.io_brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect fp_exe_unit_0.io_brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect fp_exe_unit_0.io_brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect fp_exe_unit_0.io_brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect fp_exe_unit_0.io_brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect fp_exe_unit_0.io_brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect fp_exe_unit_0.io_brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect fp_exe_unit_0.io_brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect fp_exe_unit_0.io_brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect fp_exe_unit_0.io_brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect fp_exe_unit_0.io_brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect fp_exe_unit_0.io_brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect fp_exe_unit_0.io_brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect fp_exe_unit_0.io_brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect fp_exe_unit_0.io_brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect fp_exe_unit_0.io_brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect fp_exe_unit_0.io_brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect fp_exe_unit_0.io_brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect fp_exe_unit_0.io_brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect fp_exe_unit_0.io_brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect fp_exe_unit_0.io_brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect fp_exe_unit_0.io_brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect fp_exe_unit_0.io_brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect fp_exe_unit_0.io_brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
inst ll_wbarb of Arbiter3_ExeUnitResp
connect ll_wbarb.clock, clock
connect ll_wbarb.reset, reset
node _ll_wbarb_io_in_0_valid_T = and(io.brupdate.b1.mispredict_mask, io.ll_wports[0].bits.uop.br_mask)
node _ll_wbarb_io_in_0_valid_T_1 = neq(_ll_wbarb_io_in_0_valid_T, UInt<1>(0h0))
node _ll_wbarb_io_in_0_valid_T_2 = or(_ll_wbarb_io_in_0_valid_T_1, io.flush_pipeline)
node _ll_wbarb_io_in_0_valid_T_3 = eq(_ll_wbarb_io_in_0_valid_T_2, UInt<1>(0h0))
node _ll_wbarb_io_in_0_valid_T_4 = and(io.ll_wports[0].valid, _ll_wbarb_io_in_0_valid_T_3)
reg ll_wbarb_io_in_0_valid_REG : UInt<1>, clock
connect ll_wbarb_io_in_0_valid_REG, _ll_wbarb_io_in_0_valid_T_4
connect ll_wbarb.io.in[0].valid, ll_wbarb_io_in_0_valid_REG
wire ll_wbarb_io_in_0_bits_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}
connect ll_wbarb_io_in_0_bits_out, io.ll_wports[0].bits
node _ll_wbarb_io_in_0_bits_out_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _ll_wbarb_io_in_0_bits_out_uop_br_mask_T_1 = and(io.ll_wports[0].bits.uop.br_mask, _ll_wbarb_io_in_0_bits_out_uop_br_mask_T)
connect ll_wbarb_io_in_0_bits_out.uop.br_mask, _ll_wbarb_io_in_0_bits_out_uop_br_mask_T_1
reg ll_wbarb_io_in_0_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}, clock
connect ll_wbarb_io_in_0_bits_REG, ll_wbarb_io_in_0_bits_out
connect ll_wbarb.io.in[0].bits.fflags.bits, ll_wbarb_io_in_0_bits_REG.fflags.bits
connect ll_wbarb.io.in[0].bits.fflags.valid, ll_wbarb_io_in_0_bits_REG.fflags.valid
connect ll_wbarb.io.in[0].bits.predicated, ll_wbarb_io_in_0_bits_REG.predicated
connect ll_wbarb.io.in[0].bits.data, ll_wbarb_io_in_0_bits_REG.data
connect ll_wbarb.io.in[0].bits.uop.debug_tsrc, ll_wbarb_io_in_0_bits_REG.uop.debug_tsrc
connect ll_wbarb.io.in[0].bits.uop.debug_fsrc, ll_wbarb_io_in_0_bits_REG.uop.debug_fsrc
connect ll_wbarb.io.in[0].bits.uop.bp_xcpt_if, ll_wbarb_io_in_0_bits_REG.uop.bp_xcpt_if
connect ll_wbarb.io.in[0].bits.uop.bp_debug_if, ll_wbarb_io_in_0_bits_REG.uop.bp_debug_if
connect ll_wbarb.io.in[0].bits.uop.xcpt_ma_if, ll_wbarb_io_in_0_bits_REG.uop.xcpt_ma_if
connect ll_wbarb.io.in[0].bits.uop.xcpt_ae_if, ll_wbarb_io_in_0_bits_REG.uop.xcpt_ae_if
connect ll_wbarb.io.in[0].bits.uop.xcpt_pf_if, ll_wbarb_io_in_0_bits_REG.uop.xcpt_pf_if
connect ll_wbarb.io.in[0].bits.uop.fp_typ, ll_wbarb_io_in_0_bits_REG.uop.fp_typ
connect ll_wbarb.io.in[0].bits.uop.fp_rm, ll_wbarb_io_in_0_bits_REG.uop.fp_rm
connect ll_wbarb.io.in[0].bits.uop.fp_val, ll_wbarb_io_in_0_bits_REG.uop.fp_val
connect ll_wbarb.io.in[0].bits.uop.fcn_op, ll_wbarb_io_in_0_bits_REG.uop.fcn_op
connect ll_wbarb.io.in[0].bits.uop.fcn_dw, ll_wbarb_io_in_0_bits_REG.uop.fcn_dw
connect ll_wbarb.io.in[0].bits.uop.frs3_en, ll_wbarb_io_in_0_bits_REG.uop.frs3_en
connect ll_wbarb.io.in[0].bits.uop.lrs2_rtype, ll_wbarb_io_in_0_bits_REG.uop.lrs2_rtype
connect ll_wbarb.io.in[0].bits.uop.lrs1_rtype, ll_wbarb_io_in_0_bits_REG.uop.lrs1_rtype
connect ll_wbarb.io.in[0].bits.uop.dst_rtype, ll_wbarb_io_in_0_bits_REG.uop.dst_rtype
connect ll_wbarb.io.in[0].bits.uop.lrs3, ll_wbarb_io_in_0_bits_REG.uop.lrs3
connect ll_wbarb.io.in[0].bits.uop.lrs2, ll_wbarb_io_in_0_bits_REG.uop.lrs2
connect ll_wbarb.io.in[0].bits.uop.lrs1, ll_wbarb_io_in_0_bits_REG.uop.lrs1
connect ll_wbarb.io.in[0].bits.uop.ldst, ll_wbarb_io_in_0_bits_REG.uop.ldst
connect ll_wbarb.io.in[0].bits.uop.ldst_is_rs1, ll_wbarb_io_in_0_bits_REG.uop.ldst_is_rs1
connect ll_wbarb.io.in[0].bits.uop.csr_cmd, ll_wbarb_io_in_0_bits_REG.uop.csr_cmd
connect ll_wbarb.io.in[0].bits.uop.flush_on_commit, ll_wbarb_io_in_0_bits_REG.uop.flush_on_commit
connect ll_wbarb.io.in[0].bits.uop.is_unique, ll_wbarb_io_in_0_bits_REG.uop.is_unique
connect ll_wbarb.io.in[0].bits.uop.uses_stq, ll_wbarb_io_in_0_bits_REG.uop.uses_stq
connect ll_wbarb.io.in[0].bits.uop.uses_ldq, ll_wbarb_io_in_0_bits_REG.uop.uses_ldq
connect ll_wbarb.io.in[0].bits.uop.mem_signed, ll_wbarb_io_in_0_bits_REG.uop.mem_signed
connect ll_wbarb.io.in[0].bits.uop.mem_size, ll_wbarb_io_in_0_bits_REG.uop.mem_size
connect ll_wbarb.io.in[0].bits.uop.mem_cmd, ll_wbarb_io_in_0_bits_REG.uop.mem_cmd
connect ll_wbarb.io.in[0].bits.uop.exc_cause, ll_wbarb_io_in_0_bits_REG.uop.exc_cause
connect ll_wbarb.io.in[0].bits.uop.exception, ll_wbarb_io_in_0_bits_REG.uop.exception
connect ll_wbarb.io.in[0].bits.uop.stale_pdst, ll_wbarb_io_in_0_bits_REG.uop.stale_pdst
connect ll_wbarb.io.in[0].bits.uop.ppred_busy, ll_wbarb_io_in_0_bits_REG.uop.ppred_busy
connect ll_wbarb.io.in[0].bits.uop.prs3_busy, ll_wbarb_io_in_0_bits_REG.uop.prs3_busy
connect ll_wbarb.io.in[0].bits.uop.prs2_busy, ll_wbarb_io_in_0_bits_REG.uop.prs2_busy
connect ll_wbarb.io.in[0].bits.uop.prs1_busy, ll_wbarb_io_in_0_bits_REG.uop.prs1_busy
connect ll_wbarb.io.in[0].bits.uop.ppred, ll_wbarb_io_in_0_bits_REG.uop.ppred
connect ll_wbarb.io.in[0].bits.uop.prs3, ll_wbarb_io_in_0_bits_REG.uop.prs3
connect ll_wbarb.io.in[0].bits.uop.prs2, ll_wbarb_io_in_0_bits_REG.uop.prs2
connect ll_wbarb.io.in[0].bits.uop.prs1, ll_wbarb_io_in_0_bits_REG.uop.prs1
connect ll_wbarb.io.in[0].bits.uop.pdst, ll_wbarb_io_in_0_bits_REG.uop.pdst
connect ll_wbarb.io.in[0].bits.uop.rxq_idx, ll_wbarb_io_in_0_bits_REG.uop.rxq_idx
connect ll_wbarb.io.in[0].bits.uop.stq_idx, ll_wbarb_io_in_0_bits_REG.uop.stq_idx
connect ll_wbarb.io.in[0].bits.uop.ldq_idx, ll_wbarb_io_in_0_bits_REG.uop.ldq_idx
connect ll_wbarb.io.in[0].bits.uop.rob_idx, ll_wbarb_io_in_0_bits_REG.uop.rob_idx
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.vec, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.vec
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.wflags, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.wflags
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.sqrt, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.sqrt
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.div, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.div
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.fma, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.fma
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.fastpipe, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.fastpipe
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.toint, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.toint
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.fromint, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.fromint
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.typeTagOut, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.typeTagOut
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.typeTagIn, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.typeTagIn
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.swap23, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.swap23
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.swap12, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.swap12
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.ren3, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.ren3
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.ren2, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.ren2
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.ren1, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.ren1
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.wen, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.wen
connect ll_wbarb.io.in[0].bits.uop.fp_ctrl.ldst, ll_wbarb_io_in_0_bits_REG.uop.fp_ctrl.ldst
connect ll_wbarb.io.in[0].bits.uop.op2_sel, ll_wbarb_io_in_0_bits_REG.uop.op2_sel
connect ll_wbarb.io.in[0].bits.uop.op1_sel, ll_wbarb_io_in_0_bits_REG.uop.op1_sel
connect ll_wbarb.io.in[0].bits.uop.imm_packed, ll_wbarb_io_in_0_bits_REG.uop.imm_packed
connect ll_wbarb.io.in[0].bits.uop.pimm, ll_wbarb_io_in_0_bits_REG.uop.pimm
connect ll_wbarb.io.in[0].bits.uop.imm_sel, ll_wbarb_io_in_0_bits_REG.uop.imm_sel
connect ll_wbarb.io.in[0].bits.uop.imm_rename, ll_wbarb_io_in_0_bits_REG.uop.imm_rename
connect ll_wbarb.io.in[0].bits.uop.taken, ll_wbarb_io_in_0_bits_REG.uop.taken
connect ll_wbarb.io.in[0].bits.uop.pc_lob, ll_wbarb_io_in_0_bits_REG.uop.pc_lob
connect ll_wbarb.io.in[0].bits.uop.edge_inst, ll_wbarb_io_in_0_bits_REG.uop.edge_inst
connect ll_wbarb.io.in[0].bits.uop.ftq_idx, ll_wbarb_io_in_0_bits_REG.uop.ftq_idx
connect ll_wbarb.io.in[0].bits.uop.is_mov, ll_wbarb_io_in_0_bits_REG.uop.is_mov
connect ll_wbarb.io.in[0].bits.uop.is_rocc, ll_wbarb_io_in_0_bits_REG.uop.is_rocc
connect ll_wbarb.io.in[0].bits.uop.is_sys_pc2epc, ll_wbarb_io_in_0_bits_REG.uop.is_sys_pc2epc
connect ll_wbarb.io.in[0].bits.uop.is_eret, ll_wbarb_io_in_0_bits_REG.uop.is_eret
connect ll_wbarb.io.in[0].bits.uop.is_amo, ll_wbarb_io_in_0_bits_REG.uop.is_amo
connect ll_wbarb.io.in[0].bits.uop.is_sfence, ll_wbarb_io_in_0_bits_REG.uop.is_sfence
connect ll_wbarb.io.in[0].bits.uop.is_fencei, ll_wbarb_io_in_0_bits_REG.uop.is_fencei
connect ll_wbarb.io.in[0].bits.uop.is_fence, ll_wbarb_io_in_0_bits_REG.uop.is_fence
connect ll_wbarb.io.in[0].bits.uop.is_sfb, ll_wbarb_io_in_0_bits_REG.uop.is_sfb
connect ll_wbarb.io.in[0].bits.uop.br_type, ll_wbarb_io_in_0_bits_REG.uop.br_type
connect ll_wbarb.io.in[0].bits.uop.br_tag, ll_wbarb_io_in_0_bits_REG.uop.br_tag
connect ll_wbarb.io.in[0].bits.uop.br_mask, ll_wbarb_io_in_0_bits_REG.uop.br_mask
connect ll_wbarb.io.in[0].bits.uop.dis_col_sel, ll_wbarb_io_in_0_bits_REG.uop.dis_col_sel
connect ll_wbarb.io.in[0].bits.uop.iw_p3_bypass_hint, ll_wbarb_io_in_0_bits_REG.uop.iw_p3_bypass_hint
connect ll_wbarb.io.in[0].bits.uop.iw_p2_bypass_hint, ll_wbarb_io_in_0_bits_REG.uop.iw_p2_bypass_hint
connect ll_wbarb.io.in[0].bits.uop.iw_p1_bypass_hint, ll_wbarb_io_in_0_bits_REG.uop.iw_p1_bypass_hint
connect ll_wbarb.io.in[0].bits.uop.iw_p2_speculative_child, ll_wbarb_io_in_0_bits_REG.uop.iw_p2_speculative_child
connect ll_wbarb.io.in[0].bits.uop.iw_p1_speculative_child, ll_wbarb_io_in_0_bits_REG.uop.iw_p1_speculative_child
connect ll_wbarb.io.in[0].bits.uop.iw_issued_partial_dgen, ll_wbarb_io_in_0_bits_REG.uop.iw_issued_partial_dgen
connect ll_wbarb.io.in[0].bits.uop.iw_issued_partial_agen, ll_wbarb_io_in_0_bits_REG.uop.iw_issued_partial_agen
connect ll_wbarb.io.in[0].bits.uop.iw_issued, ll_wbarb_io_in_0_bits_REG.uop.iw_issued
connect ll_wbarb.io.in[0].bits.uop.fu_code[0], ll_wbarb_io_in_0_bits_REG.uop.fu_code[0]
connect ll_wbarb.io.in[0].bits.uop.fu_code[1], ll_wbarb_io_in_0_bits_REG.uop.fu_code[1]
connect ll_wbarb.io.in[0].bits.uop.fu_code[2], ll_wbarb_io_in_0_bits_REG.uop.fu_code[2]
connect ll_wbarb.io.in[0].bits.uop.fu_code[3], ll_wbarb_io_in_0_bits_REG.uop.fu_code[3]
connect ll_wbarb.io.in[0].bits.uop.fu_code[4], ll_wbarb_io_in_0_bits_REG.uop.fu_code[4]
connect ll_wbarb.io.in[0].bits.uop.fu_code[5], ll_wbarb_io_in_0_bits_REG.uop.fu_code[5]
connect ll_wbarb.io.in[0].bits.uop.fu_code[6], ll_wbarb_io_in_0_bits_REG.uop.fu_code[6]
connect ll_wbarb.io.in[0].bits.uop.fu_code[7], ll_wbarb_io_in_0_bits_REG.uop.fu_code[7]
connect ll_wbarb.io.in[0].bits.uop.fu_code[8], ll_wbarb_io_in_0_bits_REG.uop.fu_code[8]
connect ll_wbarb.io.in[0].bits.uop.fu_code[9], ll_wbarb_io_in_0_bits_REG.uop.fu_code[9]
connect ll_wbarb.io.in[0].bits.uop.iq_type[0], ll_wbarb_io_in_0_bits_REG.uop.iq_type[0]
connect ll_wbarb.io.in[0].bits.uop.iq_type[1], ll_wbarb_io_in_0_bits_REG.uop.iq_type[1]
connect ll_wbarb.io.in[0].bits.uop.iq_type[2], ll_wbarb_io_in_0_bits_REG.uop.iq_type[2]
connect ll_wbarb.io.in[0].bits.uop.iq_type[3], ll_wbarb_io_in_0_bits_REG.uop.iq_type[3]
connect ll_wbarb.io.in[0].bits.uop.debug_pc, ll_wbarb_io_in_0_bits_REG.uop.debug_pc
connect ll_wbarb.io.in[0].bits.uop.is_rvc, ll_wbarb_io_in_0_bits_REG.uop.is_rvc
connect ll_wbarb.io.in[0].bits.uop.debug_inst, ll_wbarb_io_in_0_bits_REG.uop.debug_inst
connect ll_wbarb.io.in[0].bits.uop.inst, ll_wbarb_io_in_0_bits_REG.uop.inst
reg ll_wbarb_io_in_0_bits_data_REG : UInt, clock
connect ll_wbarb_io_in_0_bits_data_REG, io.ll_wports[0].bits.data
node _ll_wbarb_io_in_0_bits_data_T = neq(io.ll_wports[0].bits.uop.mem_size, UInt<2>(0h2))
reg ll_wbarb_io_in_0_bits_data_REG_1 : UInt<1>, clock
connect ll_wbarb_io_in_0_bits_data_REG_1, _ll_wbarb_io_in_0_bits_data_T
node _ll_wbarb_io_in_0_bits_data_T_1 = eq(ll_wbarb_io_in_0_bits_data_REG_1, UInt<1>(0h1))
node _ll_wbarb_io_in_0_bits_data_T_2 = mux(_ll_wbarb_io_in_0_bits_data_T_1, UInt<1>(0h0), UInt<64>(0hffffffff00000000))
node _ll_wbarb_io_in_0_bits_data_T_3 = or(_ll_wbarb_io_in_0_bits_data_T_2, ll_wbarb_io_in_0_bits_data_REG)
node ll_wbarb_io_in_0_bits_data_rawIn_sign = bits(_ll_wbarb_io_in_0_bits_data_T_3, 63, 63)
node ll_wbarb_io_in_0_bits_data_rawIn_expIn = bits(_ll_wbarb_io_in_0_bits_data_T_3, 62, 52)
node ll_wbarb_io_in_0_bits_data_rawIn_fractIn = bits(_ll_wbarb_io_in_0_bits_data_T_3, 51, 0)
node ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn = eq(ll_wbarb_io_in_0_bits_data_rawIn_expIn, UInt<1>(0h0))
node ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn = eq(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, UInt<1>(0h0))
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 0, 0)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_1 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 1, 1)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_2 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 2, 2)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_3 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 3, 3)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_4 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 4, 4)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_5 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 5, 5)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_6 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 6, 6)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_7 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 7, 7)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_8 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 8, 8)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_9 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 9, 9)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_10 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 10, 10)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_11 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 11, 11)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_12 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 12, 12)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_13 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 13, 13)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_14 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 14, 14)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_15 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 15, 15)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_16 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 16, 16)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_17 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 17, 17)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_18 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 18, 18)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_19 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 19, 19)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_20 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 20, 20)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_21 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 21, 21)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_22 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 22, 22)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_23 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 23, 23)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_24 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 24, 24)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_25 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 25, 25)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_26 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 26, 26)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_27 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 27, 27)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_28 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 28, 28)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_29 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 29, 29)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_30 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 30, 30)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_31 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 31, 31)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_32 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 32, 32)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_33 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 33, 33)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_34 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 34, 34)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_35 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 35, 35)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_36 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 36, 36)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_37 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 37, 37)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_38 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 38, 38)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_39 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 39, 39)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_40 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 40, 40)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_41 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 41, 41)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_42 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 42, 42)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_43 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 43, 43)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_44 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 44, 44)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_45 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 45, 45)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_46 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 46, 46)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_47 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 47, 47)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_48 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 48, 48)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_49 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 49, 49)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_50 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 50, 50)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_51 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, 51, 51)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_52 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33))
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_53 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_2, UInt<6>(0h31), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_52)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_54 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_3, UInt<6>(0h30), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_53)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_55 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_4, UInt<6>(0h2f), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_54)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_56 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_5, UInt<6>(0h2e), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_55)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_57 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_6, UInt<6>(0h2d), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_56)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_58 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_7, UInt<6>(0h2c), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_57)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_59 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_8, UInt<6>(0h2b), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_58)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_60 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_9, UInt<6>(0h2a), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_59)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_61 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_10, UInt<6>(0h29), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_60)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_62 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_11, UInt<6>(0h28), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_61)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_63 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_12, UInt<6>(0h27), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_62)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_64 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_13, UInt<6>(0h26), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_63)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_65 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_14, UInt<6>(0h25), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_64)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_66 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_15, UInt<6>(0h24), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_65)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_67 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_16, UInt<6>(0h23), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_66)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_68 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_17, UInt<6>(0h22), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_67)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_69 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_18, UInt<6>(0h21), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_68)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_70 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_19, UInt<6>(0h20), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_69)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_71 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_20, UInt<5>(0h1f), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_70)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_72 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_21, UInt<5>(0h1e), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_71)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_73 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_22, UInt<5>(0h1d), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_72)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_74 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_23, UInt<5>(0h1c), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_73)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_75 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_24, UInt<5>(0h1b), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_74)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_76 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_25, UInt<5>(0h1a), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_75)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_77 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_26, UInt<5>(0h19), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_76)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_78 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_27, UInt<5>(0h18), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_77)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_79 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_28, UInt<5>(0h17), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_78)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_80 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_29, UInt<5>(0h16), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_79)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_81 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_30, UInt<5>(0h15), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_80)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_82 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_31, UInt<5>(0h14), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_81)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_83 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_32, UInt<5>(0h13), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_82)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_84 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_33, UInt<5>(0h12), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_83)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_85 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_34, UInt<5>(0h11), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_84)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_86 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_35, UInt<5>(0h10), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_85)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_87 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_36, UInt<4>(0hf), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_86)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_88 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_37, UInt<4>(0he), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_87)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_89 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_38, UInt<4>(0hd), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_88)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_90 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_39, UInt<4>(0hc), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_89)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_91 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_40, UInt<4>(0hb), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_90)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_92 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_41, UInt<4>(0ha), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_91)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_93 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_42, UInt<4>(0h9), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_92)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_94 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_43, UInt<4>(0h8), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_93)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_95 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_44, UInt<3>(0h7), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_94)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_96 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_45, UInt<3>(0h6), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_95)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_97 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_46, UInt<3>(0h5), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_96)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_98 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_47, UInt<3>(0h4), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_97)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_99 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_48, UInt<2>(0h3), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_98)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_100 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_49, UInt<2>(0h2), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_99)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_101 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_50, UInt<1>(0h1), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_100)
node ll_wbarb_io_in_0_bits_data_rawIn_normDist = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_51, UInt<1>(0h0), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_101)
node _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T = dshl(ll_wbarb_io_in_0_bits_data_rawIn_fractIn, ll_wbarb_io_in_0_bits_data_rawIn_normDist)
node _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_1 = bits(_ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T, 50, 0)
node ll_wbarb_io_in_0_bits_data_rawIn_subnormFract = shl(_ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_1, 1)
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T = xor(ll_wbarb_io_in_0_bits_data_rawIn_normDist, UInt<12>(0hfff))
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_1 = mux(ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T, ll_wbarb_io_in_0_bits_data_rawIn_expIn)
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_2 = mux(ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_2)
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_4 = add(_ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_1, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_3)
node ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp = tail(_ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_4, 1)
node ll_wbarb_io_in_0_bits_data_rawIn_isZero = and(ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn, ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn)
node _ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_T = bits(ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp, 11, 10)
node ll_wbarb_io_in_0_bits_data_rawIn_isSpecial = eq(_ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_T, UInt<2>(0h3))
wire ll_wbarb_io_in_0_bits_data_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T = eq(ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn, UInt<1>(0h0))
node _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_1 = and(ll_wbarb_io_in_0_bits_data_rawIn_isSpecial, _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T)
connect ll_wbarb_io_in_0_bits_data_rawIn.isNaN, _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_1
node _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T = and(ll_wbarb_io_in_0_bits_data_rawIn_isSpecial, ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn)
connect ll_wbarb_io_in_0_bits_data_rawIn.isInf, _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T
connect ll_wbarb_io_in_0_bits_data_rawIn.isZero, ll_wbarb_io_in_0_bits_data_rawIn_isZero
connect ll_wbarb_io_in_0_bits_data_rawIn.sign, ll_wbarb_io_in_0_bits_data_rawIn_sign
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T = bits(ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp, 11, 0)
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_1 = cvt(_ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T)
connect ll_wbarb_io_in_0_bits_data_rawIn.sExp, _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_1
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T = eq(ll_wbarb_io_in_0_bits_data_rawIn_isZero, UInt<1>(0h0))
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T)
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_2 = mux(ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn, ll_wbarb_io_in_0_bits_data_rawIn_subnormFract, ll_wbarb_io_in_0_bits_data_rawIn_fractIn)
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_3 = cat(_ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_1, _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_2)
connect ll_wbarb_io_in_0_bits_data_rawIn.sig, _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_3
node _ll_wbarb_io_in_0_bits_data_T_4 = bits(ll_wbarb_io_in_0_bits_data_rawIn.sExp, 11, 9)
node _ll_wbarb_io_in_0_bits_data_T_5 = mux(ll_wbarb_io_in_0_bits_data_rawIn.isZero, UInt<3>(0h0), _ll_wbarb_io_in_0_bits_data_T_4)
node _ll_wbarb_io_in_0_bits_data_T_6 = mux(ll_wbarb_io_in_0_bits_data_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _ll_wbarb_io_in_0_bits_data_T_7 = or(_ll_wbarb_io_in_0_bits_data_T_5, _ll_wbarb_io_in_0_bits_data_T_6)
node _ll_wbarb_io_in_0_bits_data_T_8 = cat(ll_wbarb_io_in_0_bits_data_rawIn.sign, _ll_wbarb_io_in_0_bits_data_T_7)
node _ll_wbarb_io_in_0_bits_data_T_9 = bits(ll_wbarb_io_in_0_bits_data_rawIn.sExp, 8, 0)
node _ll_wbarb_io_in_0_bits_data_T_10 = cat(_ll_wbarb_io_in_0_bits_data_T_8, _ll_wbarb_io_in_0_bits_data_T_9)
node _ll_wbarb_io_in_0_bits_data_T_11 = bits(ll_wbarb_io_in_0_bits_data_rawIn.sig, 51, 0)
node _ll_wbarb_io_in_0_bits_data_T_12 = cat(_ll_wbarb_io_in_0_bits_data_T_10, _ll_wbarb_io_in_0_bits_data_T_11)
node ll_wbarb_io_in_0_bits_data_rawIn_sign_1 = bits(_ll_wbarb_io_in_0_bits_data_T_3, 31, 31)
node ll_wbarb_io_in_0_bits_data_rawIn_expIn_1 = bits(_ll_wbarb_io_in_0_bits_data_T_3, 30, 23)
node ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1 = bits(_ll_wbarb_io_in_0_bits_data_T_3, 22, 0)
node ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1 = eq(ll_wbarb_io_in_0_bits_data_rawIn_expIn_1, UInt<1>(0h0))
node ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn_1 = eq(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, UInt<1>(0h0))
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_102 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 0, 0)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_103 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 1, 1)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_104 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 2, 2)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_105 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 3, 3)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_106 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 4, 4)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_107 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 5, 5)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_108 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 6, 6)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_109 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 7, 7)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_110 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 8, 8)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_111 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 9, 9)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_112 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 10, 10)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_113 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 11, 11)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_114 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 12, 12)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_115 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 13, 13)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_116 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 14, 14)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_117 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 15, 15)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_118 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 16, 16)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_119 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 17, 17)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_120 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 18, 18)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_121 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 19, 19)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_122 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 20, 20)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_123 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 21, 21)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_124 = bits(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, 22, 22)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_125 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16))
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_126 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_104, UInt<5>(0h14), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_125)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_127 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_105, UInt<5>(0h13), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_126)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_128 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_106, UInt<5>(0h12), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_127)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_129 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_107, UInt<5>(0h11), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_128)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_130 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_108, UInt<5>(0h10), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_129)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_131 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_109, UInt<4>(0hf), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_130)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_132 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_110, UInt<4>(0he), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_131)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_133 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_111, UInt<4>(0hd), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_132)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_134 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_112, UInt<4>(0hc), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_133)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_135 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_113, UInt<4>(0hb), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_134)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_136 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_114, UInt<4>(0ha), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_135)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_137 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_115, UInt<4>(0h9), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_136)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_138 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_116, UInt<4>(0h8), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_137)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_139 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_117, UInt<3>(0h7), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_138)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_140 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_118, UInt<3>(0h6), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_139)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_141 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_119, UInt<3>(0h5), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_140)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_142 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_120, UInt<3>(0h4), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_141)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_143 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_121, UInt<2>(0h3), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_142)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_144 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_122, UInt<2>(0h2), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_143)
node _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_145 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_123, UInt<1>(0h1), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_144)
node ll_wbarb_io_in_0_bits_data_rawIn_normDist_1 = mux(_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_124, UInt<1>(0h0), _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_145)
node _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_2 = dshl(ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1, ll_wbarb_io_in_0_bits_data_rawIn_normDist_1)
node _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_3 = bits(_ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_2, 21, 0)
node ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_1 = shl(_ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_3, 1)
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_5 = xor(ll_wbarb_io_in_0_bits_data_rawIn_normDist_1, UInt<9>(0h1ff))
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_6 = mux(ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_5, ll_wbarb_io_in_0_bits_data_rawIn_expIn_1)
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_7 = mux(ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1))
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_7)
node _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_9 = add(_ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_6, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_8)
node ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_1 = tail(_ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_9, 1)
node ll_wbarb_io_in_0_bits_data_rawIn_isZero_1 = and(ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1, ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn_1)
node _ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_T_1 = bits(ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_1, 8, 7)
node ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_1 = eq(_ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire ll_wbarb_io_in_0_bits_data_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_2 = eq(ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn_1, UInt<1>(0h0))
node _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_3 = and(ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_1, _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_2)
connect ll_wbarb_io_in_0_bits_data_rawIn_1.isNaN, _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_3
node _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T_1 = and(ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_1, ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn_1)
connect ll_wbarb_io_in_0_bits_data_rawIn_1.isInf, _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T_1
connect ll_wbarb_io_in_0_bits_data_rawIn_1.isZero, ll_wbarb_io_in_0_bits_data_rawIn_isZero_1
connect ll_wbarb_io_in_0_bits_data_rawIn_1.sign, ll_wbarb_io_in_0_bits_data_rawIn_sign_1
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_2 = bits(ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_1, 8, 0)
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_3 = cvt(_ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_2)
connect ll_wbarb_io_in_0_bits_data_rawIn_1.sExp, _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_3
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_4 = eq(ll_wbarb_io_in_0_bits_data_rawIn_isZero_1, UInt<1>(0h0))
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_4)
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_6 = mux(ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1, ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_1, ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1)
node _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_7 = cat(_ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_5, _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_6)
connect ll_wbarb_io_in_0_bits_data_rawIn_1.sig, _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_7
node _ll_wbarb_io_in_0_bits_data_T_13 = bits(ll_wbarb_io_in_0_bits_data_rawIn_1.sExp, 8, 6)
node _ll_wbarb_io_in_0_bits_data_T_14 = mux(ll_wbarb_io_in_0_bits_data_rawIn_1.isZero, UInt<3>(0h0), _ll_wbarb_io_in_0_bits_data_T_13)
node _ll_wbarb_io_in_0_bits_data_T_15 = mux(ll_wbarb_io_in_0_bits_data_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _ll_wbarb_io_in_0_bits_data_T_16 = or(_ll_wbarb_io_in_0_bits_data_T_14, _ll_wbarb_io_in_0_bits_data_T_15)
node _ll_wbarb_io_in_0_bits_data_T_17 = cat(ll_wbarb_io_in_0_bits_data_rawIn_1.sign, _ll_wbarb_io_in_0_bits_data_T_16)
node _ll_wbarb_io_in_0_bits_data_T_18 = bits(ll_wbarb_io_in_0_bits_data_rawIn_1.sExp, 5, 0)
node _ll_wbarb_io_in_0_bits_data_T_19 = cat(_ll_wbarb_io_in_0_bits_data_T_17, _ll_wbarb_io_in_0_bits_data_T_18)
node _ll_wbarb_io_in_0_bits_data_T_20 = bits(ll_wbarb_io_in_0_bits_data_rawIn_1.sig, 22, 0)
node _ll_wbarb_io_in_0_bits_data_T_21 = cat(_ll_wbarb_io_in_0_bits_data_T_19, _ll_wbarb_io_in_0_bits_data_T_20)
node _ll_wbarb_io_in_0_bits_data_swizzledNaN_T = bits(_ll_wbarb_io_in_0_bits_data_T_12, 64, 61)
node _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_1 = bits(_ll_wbarb_io_in_0_bits_data_T_12, 51, 32)
node _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_2 = andr(_ll_wbarb_io_in_0_bits_data_swizzledNaN_T_1)
node _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_3 = bits(_ll_wbarb_io_in_0_bits_data_T_12, 59, 53)
node _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_4 = bits(_ll_wbarb_io_in_0_bits_data_T_21, 31, 31)
node _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_5 = bits(_ll_wbarb_io_in_0_bits_data_T_12, 51, 32)
node _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_6 = bits(_ll_wbarb_io_in_0_bits_data_T_21, 32, 32)
node _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_7 = bits(_ll_wbarb_io_in_0_bits_data_T_21, 30, 0)
node ll_wbarb_io_in_0_bits_data_swizzledNaN_lo_hi = cat(_ll_wbarb_io_in_0_bits_data_swizzledNaN_T_5, _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_6)
node ll_wbarb_io_in_0_bits_data_swizzledNaN_lo = cat(ll_wbarb_io_in_0_bits_data_swizzledNaN_lo_hi, _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_7)
node ll_wbarb_io_in_0_bits_data_swizzledNaN_hi_lo = cat(_ll_wbarb_io_in_0_bits_data_swizzledNaN_T_3, _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_4)
node ll_wbarb_io_in_0_bits_data_swizzledNaN_hi_hi = cat(_ll_wbarb_io_in_0_bits_data_swizzledNaN_T, _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_2)
node ll_wbarb_io_in_0_bits_data_swizzledNaN_hi = cat(ll_wbarb_io_in_0_bits_data_swizzledNaN_hi_hi, ll_wbarb_io_in_0_bits_data_swizzledNaN_hi_lo)
node ll_wbarb_io_in_0_bits_data_swizzledNaN = cat(ll_wbarb_io_in_0_bits_data_swizzledNaN_hi, ll_wbarb_io_in_0_bits_data_swizzledNaN_lo)
node _ll_wbarb_io_in_0_bits_data_T_22 = bits(_ll_wbarb_io_in_0_bits_data_T_12, 63, 61)
node _ll_wbarb_io_in_0_bits_data_T_23 = andr(_ll_wbarb_io_in_0_bits_data_T_22)
node _ll_wbarb_io_in_0_bits_data_T_24 = mux(_ll_wbarb_io_in_0_bits_data_T_23, ll_wbarb_io_in_0_bits_data_swizzledNaN, _ll_wbarb_io_in_0_bits_data_T_12)
connect ll_wbarb.io.in[0].bits.data, _ll_wbarb_io_in_0_bits_data_T_24
connect ll_wbarb.io.in[1], io.from_int
connect ll_wbarb.io.in[2], fp_exe_unit_0.io_fdiv_resp
node _fregfile_io_write_ports_0_valid_T = eq(ll_wbarb.io.out.bits.uop.dst_rtype, UInt<2>(0h1))
node _fregfile_io_write_ports_0_valid_T_1 = and(ll_wbarb.io.out.valid, _fregfile_io_write_ports_0_valid_T)
connect fregfile.io.write_ports[0].valid, _fregfile_io_write_ports_0_valid_T_1
connect fregfile.io.write_ports[0].bits.addr, ll_wbarb.io.out.bits.uop.pdst
connect fregfile.io.write_ports[0].bits.data, ll_wbarb.io.out.bits.data
node _T = asUInt(reset)
node _T_1 = eq(_T, UInt<1>(0h0))
when _T_1 :
node _T_2 = eq(ll_wbarb.io.in[0].ready, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at fp-pipeline.scala:193 assert (ll_wbarb.io.in(0).ready) // never backpressure the memory unit.\n") : printf
assert(clock, ll_wbarb.io.in[0].ready, UInt<1>(0h1), "") : assert
when io.from_int.valid :
node _T_3 = eq(io.from_int.bits.uop.dst_rtype, UInt<2>(0h1))
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at fp-pipeline.scala:194 when (ifpu_resp.valid) { assert (ifpu_resp.bits.uop.dst_rtype === RT_FLT) }\n") : printf_1
assert(clock, _T_3, UInt<1>(0h1), "") : assert_1
node _fregfile_io_write_ports_1_valid_T = eq(fp_exe_unit_0.io_fpu_resp.bits.uop.dst_rtype, UInt<2>(0h1))
node _fregfile_io_write_ports_1_valid_T_1 = and(fp_exe_unit_0.io_fpu_resp.valid, _fregfile_io_write_ports_1_valid_T)
connect fregfile.io.write_ports[1].valid, _fregfile_io_write_ports_1_valid_T_1
connect fregfile.io.write_ports[1].bits.addr, fp_exe_unit_0.io_fpu_resp.bits.uop.pdst
connect fregfile.io.write_ports[1].bits.data, fp_exe_unit_0.io_fpu_resp.bits.data
node _fp_bypasses_0_valid_T = eq(fp_exe_unit_0.io_fpu_resp.bits.uop.dst_rtype, UInt<2>(0h1))
node _fp_bypasses_0_valid_T_1 = and(fp_exe_unit_0.io_fpu_resp.valid, _fp_bypasses_0_valid_T)
connect fp_bypasses[0].valid, _fp_bypasses_0_valid_T_1
connect fp_bypasses[0].bits, fp_exe_unit_0.io_fpu_resp.bits
connect io.to_int.bits, fp_exe_unit_0.io_fpiu_resp.bits
connect io.to_int.valid, fp_exe_unit_0.io_fpiu_resp.valid
connect fp_exe_unit_0.io_fpiu_resp.ready, io.to_int.ready
connect io.dgen, fp_exe_unit_0.io_dgen
connect fp_wakeups[0], fp_exe_unit_0.io_wakeup
connect io.wb[0], fp_exe_unit_0.io_fpu_resp
connect fp_wakeups[1].valid, ll_wbarb.io.out.valid
connect fp_wakeups[1].bits.uop, ll_wbarb.io.out.bits.uop
connect fp_wakeups[1].bits.speculative_mask, UInt<1>(0h0)
connect fp_wakeups[1].bits.bypassable, UInt<1>(0h0)
connect fp_wakeups[1].bits.rebusy, UInt<1>(0h0)
connect io.wb[1].bits, ll_wbarb.io.out.bits
connect io.wb[1].valid, ll_wbarb.io.out.valid
connect ll_wbarb.io.out.ready, UInt<1>(0h1)
connect fp_exe_unit_0.io_fcsr_rm, io.fcsr_rm
connect fp_exe_unit_0.io_status.uie, io.status.uie
connect fp_exe_unit_0.io_status.sie, io.status.sie
connect fp_exe_unit_0.io_status.hie, io.status.hie
connect fp_exe_unit_0.io_status.mie, io.status.mie
connect fp_exe_unit_0.io_status.upie, io.status.upie
connect fp_exe_unit_0.io_status.spie, io.status.spie
connect fp_exe_unit_0.io_status.ube, io.status.ube
connect fp_exe_unit_0.io_status.mpie, io.status.mpie
connect fp_exe_unit_0.io_status.spp, io.status.spp
connect fp_exe_unit_0.io_status.vs, io.status.vs
connect fp_exe_unit_0.io_status.mpp, io.status.mpp
connect fp_exe_unit_0.io_status.fs, io.status.fs
connect fp_exe_unit_0.io_status.xs, io.status.xs
connect fp_exe_unit_0.io_status.mprv, io.status.mprv
connect fp_exe_unit_0.io_status.sum, io.status.sum
connect fp_exe_unit_0.io_status.mxr, io.status.mxr
connect fp_exe_unit_0.io_status.tvm, io.status.tvm
connect fp_exe_unit_0.io_status.tw, io.status.tw
connect fp_exe_unit_0.io_status.tsr, io.status.tsr
connect fp_exe_unit_0.io_status.zero1, io.status.zero1
connect fp_exe_unit_0.io_status.sd_rv32, io.status.sd_rv32
connect fp_exe_unit_0.io_status.uxl, io.status.uxl
connect fp_exe_unit_0.io_status.sxl, io.status.sxl
connect fp_exe_unit_0.io_status.sbe, io.status.sbe
connect fp_exe_unit_0.io_status.mbe, io.status.mbe
connect fp_exe_unit_0.io_status.gva, io.status.gva
connect fp_exe_unit_0.io_status.mpv, io.status.mpv
connect fp_exe_unit_0.io_status.zero2, io.status.zero2
connect fp_exe_unit_0.io_status.sd, io.status.sd
connect fp_exe_unit_0.io_status.v, io.status.v
connect fp_exe_unit_0.io_status.prv, io.status.prv
connect fp_exe_unit_0.io_status.dv, io.status.dv
connect fp_exe_unit_0.io_status.dprv, io.status.dprv
connect fp_exe_unit_0.io_status.isa, io.status.isa
connect fp_exe_unit_0.io_status.wfi, io.status.wfi
connect fp_exe_unit_0.io_status.cease, io.status.cease
connect fp_exe_unit_0.io_status.debug, io.status.debug
connect fp_exe_unit_0.io_kill, io.flush_pipeline | module FpPipeline( // @[fp-pipeline.scala:27:7]
input clock, // @[fp-pipeline.scala:27:7]
input reset, // @[fp-pipeline.scala:27:7]
input [15:0] io_brupdate_b1_resolve_mask, // @[fp-pipeline.scala:35:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[fp-pipeline.scala:35:14]
input [31:0] io_brupdate_b2_uop_inst, // @[fp-pipeline.scala:35:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_rvc, // @[fp-pipeline.scala:35:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iw_issued, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[fp-pipeline.scala:35:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[fp-pipeline.scala:35:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_sfb, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_fence, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_fencei, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_sfence, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_amo, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_eret, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_rocc, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_mov, // @[fp-pipeline.scala:35:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_edge_inst, // @[fp-pipeline.scala:35:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_taken, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_imm_rename, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[fp-pipeline.scala:35:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[fp-pipeline.scala:35:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[fp-pipeline.scala:35:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[fp-pipeline.scala:35:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[fp-pipeline.scala:35:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[fp-pipeline.scala:35:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_exception, // @[fp-pipeline.scala:35:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[fp-pipeline.scala:35:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_mem_signed, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_uses_stq, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_is_unique, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[fp-pipeline.scala:35:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[fp-pipeline.scala:35:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_frs3_en, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_fp_val, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_mispredict, // @[fp-pipeline.scala:35:14]
input io_brupdate_b2_taken, // @[fp-pipeline.scala:35:14]
input [2:0] io_brupdate_b2_cfi_type, // @[fp-pipeline.scala:35:14]
input [1:0] io_brupdate_b2_pc_sel, // @[fp-pipeline.scala:35:14]
input [39:0] io_brupdate_b2_jalr_target, // @[fp-pipeline.scala:35:14]
input [20:0] io_brupdate_b2_target_offset, // @[fp-pipeline.scala:35:14]
input io_flush_pipeline, // @[fp-pipeline.scala:35:14]
input [2:0] io_fcsr_rm, // @[fp-pipeline.scala:35:14]
input io_status_debug, // @[fp-pipeline.scala:35:14]
input io_status_cease, // @[fp-pipeline.scala:35:14]
input io_status_wfi, // @[fp-pipeline.scala:35:14]
input [1:0] io_status_dprv, // @[fp-pipeline.scala:35:14]
input io_status_dv, // @[fp-pipeline.scala:35:14]
input [1:0] io_status_prv, // @[fp-pipeline.scala:35:14]
input io_status_v, // @[fp-pipeline.scala:35:14]
input io_status_sd, // @[fp-pipeline.scala:35:14]
input io_status_mpv, // @[fp-pipeline.scala:35:14]
input io_status_gva, // @[fp-pipeline.scala:35:14]
input io_status_tsr, // @[fp-pipeline.scala:35:14]
input io_status_tw, // @[fp-pipeline.scala:35:14]
input io_status_tvm, // @[fp-pipeline.scala:35:14]
input io_status_mxr, // @[fp-pipeline.scala:35:14]
input io_status_sum, // @[fp-pipeline.scala:35:14]
input io_status_mprv, // @[fp-pipeline.scala:35:14]
input [1:0] io_status_fs, // @[fp-pipeline.scala:35:14]
input [1:0] io_status_mpp, // @[fp-pipeline.scala:35:14]
input io_status_spp, // @[fp-pipeline.scala:35:14]
input io_status_mpie, // @[fp-pipeline.scala:35:14]
input io_status_spie, // @[fp-pipeline.scala:35:14]
input io_status_mie, // @[fp-pipeline.scala:35:14]
input io_status_sie, // @[fp-pipeline.scala:35:14]
output io_dis_uops_0_ready, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_valid, // @[fp-pipeline.scala:35:14]
input [31:0] io_dis_uops_0_bits_inst, // @[fp-pipeline.scala:35:14]
input [31:0] io_dis_uops_0_bits_debug_inst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_rvc, // @[fp-pipeline.scala:35:14]
input [39:0] io_dis_uops_0_bits_debug_pc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iq_type_0, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iq_type_1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iq_type_2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iq_type_3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_0, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_4, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_5, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_6, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_7, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_8, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fu_code_9, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iw_issued, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_dis_col_sel, // @[fp-pipeline.scala:35:14]
input [15:0] io_dis_uops_0_bits_br_mask, // @[fp-pipeline.scala:35:14]
input [3:0] io_dis_uops_0_bits_br_tag, // @[fp-pipeline.scala:35:14]
input [3:0] io_dis_uops_0_bits_br_type, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_sfb, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_fence, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_fencei, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_sfence, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_amo, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_eret, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_rocc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_mov, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_0_bits_ftq_idx, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_edge_inst, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_0_bits_pc_lob, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_taken, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_imm_rename, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_imm_sel, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_0_bits_pimm, // @[fp-pipeline.scala:35:14]
input [19:0] io_dis_uops_0_bits_imm_packed, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_op1_sel, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_op2_sel, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_0_bits_rob_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_0_bits_ldq_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_0_bits_stq_idx, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_rxq_idx, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_0_bits_pdst, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_0_bits_prs1, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_0_bits_prs2, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_0_bits_prs3, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_0_bits_ppred, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_prs1_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_prs2_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_prs3_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_ppred_busy, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_0_bits_stale_pdst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_exception, // @[fp-pipeline.scala:35:14]
input [63:0] io_dis_uops_0_bits_exc_cause, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_0_bits_mem_cmd, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_mem_size, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_mem_signed, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_uses_ldq, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_uses_stq, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_is_unique, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_flush_on_commit, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_csr_cmd, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_0_bits_ldst, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_0_bits_lrs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_0_bits_lrs2, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_0_bits_lrs3, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_dst_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_frs3_en, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fcn_dw, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_0_bits_fcn_op, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_fp_val, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_fp_rm, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_0_bits_fp_typ, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_bp_debug_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_0_bits_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[fp-pipeline.scala:35:14]
output io_dis_uops_1_ready, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_valid, // @[fp-pipeline.scala:35:14]
input [31:0] io_dis_uops_1_bits_inst, // @[fp-pipeline.scala:35:14]
input [31:0] io_dis_uops_1_bits_debug_inst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_rvc, // @[fp-pipeline.scala:35:14]
input [39:0] io_dis_uops_1_bits_debug_pc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iq_type_0, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iq_type_1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iq_type_2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iq_type_3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_0, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_4, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_5, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_6, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_7, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_8, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fu_code_9, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iw_issued, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_dis_col_sel, // @[fp-pipeline.scala:35:14]
input [15:0] io_dis_uops_1_bits_br_mask, // @[fp-pipeline.scala:35:14]
input [3:0] io_dis_uops_1_bits_br_tag, // @[fp-pipeline.scala:35:14]
input [3:0] io_dis_uops_1_bits_br_type, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_sfb, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_fence, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_fencei, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_sfence, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_amo, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_eret, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_rocc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_mov, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_1_bits_ftq_idx, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_edge_inst, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_1_bits_pc_lob, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_taken, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_imm_rename, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_imm_sel, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_1_bits_pimm, // @[fp-pipeline.scala:35:14]
input [19:0] io_dis_uops_1_bits_imm_packed, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_op1_sel, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_op2_sel, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_1_bits_rob_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_1_bits_ldq_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_1_bits_stq_idx, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_rxq_idx, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_1_bits_pdst, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_1_bits_prs1, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_1_bits_prs2, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_1_bits_prs3, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_1_bits_ppred, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_prs1_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_prs2_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_prs3_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_ppred_busy, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_1_bits_stale_pdst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_exception, // @[fp-pipeline.scala:35:14]
input [63:0] io_dis_uops_1_bits_exc_cause, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_1_bits_mem_cmd, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_mem_size, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_mem_signed, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_uses_ldq, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_uses_stq, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_is_unique, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_flush_on_commit, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_csr_cmd, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_1_bits_ldst, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_1_bits_lrs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_1_bits_lrs2, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_1_bits_lrs3, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_dst_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_frs3_en, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fcn_dw, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_1_bits_fcn_op, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_fp_val, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_fp_rm, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_1_bits_fp_typ, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_bp_debug_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_1_bits_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[fp-pipeline.scala:35:14]
output io_dis_uops_2_ready, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_valid, // @[fp-pipeline.scala:35:14]
input [31:0] io_dis_uops_2_bits_inst, // @[fp-pipeline.scala:35:14]
input [31:0] io_dis_uops_2_bits_debug_inst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_rvc, // @[fp-pipeline.scala:35:14]
input [39:0] io_dis_uops_2_bits_debug_pc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iq_type_0, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iq_type_1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iq_type_2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iq_type_3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_0, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_4, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_5, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_6, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_7, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_8, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fu_code_9, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iw_issued, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_dis_col_sel, // @[fp-pipeline.scala:35:14]
input [15:0] io_dis_uops_2_bits_br_mask, // @[fp-pipeline.scala:35:14]
input [3:0] io_dis_uops_2_bits_br_tag, // @[fp-pipeline.scala:35:14]
input [3:0] io_dis_uops_2_bits_br_type, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_sfb, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_fence, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_fencei, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_sfence, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_amo, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_eret, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_rocc, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_mov, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_2_bits_ftq_idx, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_edge_inst, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_2_bits_pc_lob, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_taken, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_imm_rename, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_imm_sel, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_2_bits_pimm, // @[fp-pipeline.scala:35:14]
input [19:0] io_dis_uops_2_bits_imm_packed, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_op1_sel, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_op2_sel, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_2_bits_rob_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_2_bits_ldq_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_2_bits_stq_idx, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_rxq_idx, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_2_bits_pdst, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_2_bits_prs1, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_2_bits_prs2, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_2_bits_prs3, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_2_bits_ppred, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_prs1_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_prs2_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_prs3_busy, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_ppred_busy, // @[fp-pipeline.scala:35:14]
input [6:0] io_dis_uops_2_bits_stale_pdst, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_exception, // @[fp-pipeline.scala:35:14]
input [63:0] io_dis_uops_2_bits_exc_cause, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_2_bits_mem_cmd, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_mem_size, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_mem_signed, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_uses_ldq, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_uses_stq, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_is_unique, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_flush_on_commit, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_csr_cmd, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_2_bits_ldst, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_2_bits_lrs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_2_bits_lrs2, // @[fp-pipeline.scala:35:14]
input [5:0] io_dis_uops_2_bits_lrs3, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_dst_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_frs3_en, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fcn_dw, // @[fp-pipeline.scala:35:14]
input [4:0] io_dis_uops_2_bits_fcn_op, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_fp_val, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_fp_rm, // @[fp-pipeline.scala:35:14]
input [1:0] io_dis_uops_2_bits_fp_typ, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_bp_debug_if, // @[fp-pipeline.scala:35:14]
input io_dis_uops_2_bits_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_debug_fsrc, // @[fp-pipeline.scala:35:14]
input [2:0] io_dis_uops_2_bits_debug_tsrc, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_valid, // @[fp-pipeline.scala:35:14]
input [31:0] io_ll_wports_0_bits_uop_inst, // @[fp-pipeline.scala:35:14]
input [31:0] io_ll_wports_0_bits_uop_debug_inst, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_rvc, // @[fp-pipeline.scala:35:14]
input [39:0] io_ll_wports_0_bits_uop_debug_pc, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iw_issued, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
input [15:0] io_ll_wports_0_bits_uop_br_mask, // @[fp-pipeline.scala:35:14]
input [3:0] io_ll_wports_0_bits_uop_br_tag, // @[fp-pipeline.scala:35:14]
input [3:0] io_ll_wports_0_bits_uop_br_type, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_sfb, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_fence, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_fencei, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_sfence, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_amo, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_eret, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_rocc, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_mov, // @[fp-pipeline.scala:35:14]
input [4:0] io_ll_wports_0_bits_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_edge_inst, // @[fp-pipeline.scala:35:14]
input [5:0] io_ll_wports_0_bits_uop_pc_lob, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_taken, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_imm_rename, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_imm_sel, // @[fp-pipeline.scala:35:14]
input [4:0] io_ll_wports_0_bits_uop_pimm, // @[fp-pipeline.scala:35:14]
input [19:0] io_ll_wports_0_bits_uop_imm_packed, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_op1_sel, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_op2_sel, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
input [6:0] io_ll_wports_0_bits_uop_rob_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_ll_wports_0_bits_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_ll_wports_0_bits_uop_stq_idx, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
input [6:0] io_ll_wports_0_bits_uop_pdst, // @[fp-pipeline.scala:35:14]
input [6:0] io_ll_wports_0_bits_uop_prs1, // @[fp-pipeline.scala:35:14]
input [6:0] io_ll_wports_0_bits_uop_prs2, // @[fp-pipeline.scala:35:14]
input [6:0] io_ll_wports_0_bits_uop_prs3, // @[fp-pipeline.scala:35:14]
input [4:0] io_ll_wports_0_bits_uop_ppred, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
input [6:0] io_ll_wports_0_bits_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_exception, // @[fp-pipeline.scala:35:14]
input [63:0] io_ll_wports_0_bits_uop_exc_cause, // @[fp-pipeline.scala:35:14]
input [4:0] io_ll_wports_0_bits_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_mem_size, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_mem_signed, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_uses_stq, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_is_unique, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_ll_wports_0_bits_uop_ldst, // @[fp-pipeline.scala:35:14]
input [5:0] io_ll_wports_0_bits_uop_lrs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_ll_wports_0_bits_uop_lrs2, // @[fp-pipeline.scala:35:14]
input [5:0] io_ll_wports_0_bits_uop_lrs3, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_frs3_en, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
input [4:0] io_ll_wports_0_bits_uop_fcn_op, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_fp_val, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_fp_rm, // @[fp-pipeline.scala:35:14]
input [1:0] io_ll_wports_0_bits_uop_fp_typ, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
input io_ll_wports_0_bits_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
input [2:0] io_ll_wports_0_bits_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
input [64:0] io_ll_wports_0_bits_data, // @[fp-pipeline.scala:35:14]
output io_from_int_ready, // @[fp-pipeline.scala:35:14]
input io_from_int_valid, // @[fp-pipeline.scala:35:14]
input [31:0] io_from_int_bits_uop_inst, // @[fp-pipeline.scala:35:14]
input [31:0] io_from_int_bits_uop_debug_inst, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_rvc, // @[fp-pipeline.scala:35:14]
input [39:0] io_from_int_bits_uop_debug_pc, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iw_issued, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
input [15:0] io_from_int_bits_uop_br_mask, // @[fp-pipeline.scala:35:14]
input [3:0] io_from_int_bits_uop_br_tag, // @[fp-pipeline.scala:35:14]
input [3:0] io_from_int_bits_uop_br_type, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_sfb, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_fence, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_fencei, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_sfence, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_amo, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_eret, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_rocc, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_mov, // @[fp-pipeline.scala:35:14]
input [4:0] io_from_int_bits_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_edge_inst, // @[fp-pipeline.scala:35:14]
input [5:0] io_from_int_bits_uop_pc_lob, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_taken, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_imm_rename, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_imm_sel, // @[fp-pipeline.scala:35:14]
input [4:0] io_from_int_bits_uop_pimm, // @[fp-pipeline.scala:35:14]
input [19:0] io_from_int_bits_uop_imm_packed, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_op1_sel, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_op2_sel, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
input [6:0] io_from_int_bits_uop_rob_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_from_int_bits_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
input [4:0] io_from_int_bits_uop_stq_idx, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
input [6:0] io_from_int_bits_uop_pdst, // @[fp-pipeline.scala:35:14]
input [6:0] io_from_int_bits_uop_prs1, // @[fp-pipeline.scala:35:14]
input [6:0] io_from_int_bits_uop_prs2, // @[fp-pipeline.scala:35:14]
input [6:0] io_from_int_bits_uop_prs3, // @[fp-pipeline.scala:35:14]
input [4:0] io_from_int_bits_uop_ppred, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
input [6:0] io_from_int_bits_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_exception, // @[fp-pipeline.scala:35:14]
input [63:0] io_from_int_bits_uop_exc_cause, // @[fp-pipeline.scala:35:14]
input [4:0] io_from_int_bits_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_mem_size, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_mem_signed, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_uses_stq, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_is_unique, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_from_int_bits_uop_ldst, // @[fp-pipeline.scala:35:14]
input [5:0] io_from_int_bits_uop_lrs1, // @[fp-pipeline.scala:35:14]
input [5:0] io_from_int_bits_uop_lrs2, // @[fp-pipeline.scala:35:14]
input [5:0] io_from_int_bits_uop_lrs3, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_frs3_en, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
input [4:0] io_from_int_bits_uop_fcn_op, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_fp_val, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_fp_rm, // @[fp-pipeline.scala:35:14]
input [1:0] io_from_int_bits_uop_fp_typ, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
input [2:0] io_from_int_bits_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
input [64:0] io_from_int_bits_data, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_predicated, // @[fp-pipeline.scala:35:14]
input io_from_int_bits_fflags_valid, // @[fp-pipeline.scala:35:14]
input [4:0] io_from_int_bits_fflags_bits, // @[fp-pipeline.scala:35:14]
output io_dgen_valid, // @[fp-pipeline.scala:35:14]
output [31:0] io_dgen_bits_uop_inst, // @[fp-pipeline.scala:35:14]
output [31:0] io_dgen_bits_uop_debug_inst, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_rvc, // @[fp-pipeline.scala:35:14]
output [39:0] io_dgen_bits_uop_debug_pc, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iw_issued, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
output [15:0] io_dgen_bits_uop_br_mask, // @[fp-pipeline.scala:35:14]
output [3:0] io_dgen_bits_uop_br_tag, // @[fp-pipeline.scala:35:14]
output [3:0] io_dgen_bits_uop_br_type, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_sfb, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_fence, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_fencei, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_sfence, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_amo, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_eret, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_rocc, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_mov, // @[fp-pipeline.scala:35:14]
output [4:0] io_dgen_bits_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_edge_inst, // @[fp-pipeline.scala:35:14]
output [5:0] io_dgen_bits_uop_pc_lob, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_taken, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_imm_rename, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_imm_sel, // @[fp-pipeline.scala:35:14]
output [4:0] io_dgen_bits_uop_pimm, // @[fp-pipeline.scala:35:14]
output [19:0] io_dgen_bits_uop_imm_packed, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_op1_sel, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_op2_sel, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
output [6:0] io_dgen_bits_uop_rob_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_dgen_bits_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_dgen_bits_uop_stq_idx, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
output [6:0] io_dgen_bits_uop_pdst, // @[fp-pipeline.scala:35:14]
output [6:0] io_dgen_bits_uop_prs1, // @[fp-pipeline.scala:35:14]
output [6:0] io_dgen_bits_uop_prs2, // @[fp-pipeline.scala:35:14]
output [6:0] io_dgen_bits_uop_prs3, // @[fp-pipeline.scala:35:14]
output [4:0] io_dgen_bits_uop_ppred, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
output [6:0] io_dgen_bits_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_exception, // @[fp-pipeline.scala:35:14]
output [63:0] io_dgen_bits_uop_exc_cause, // @[fp-pipeline.scala:35:14]
output [4:0] io_dgen_bits_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_mem_size, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_mem_signed, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_uses_stq, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_is_unique, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_dgen_bits_uop_ldst, // @[fp-pipeline.scala:35:14]
output [5:0] io_dgen_bits_uop_lrs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_dgen_bits_uop_lrs2, // @[fp-pipeline.scala:35:14]
output [5:0] io_dgen_bits_uop_lrs3, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_frs3_en, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
output [4:0] io_dgen_bits_uop_fcn_op, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_fp_val, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_fp_rm, // @[fp-pipeline.scala:35:14]
output [1:0] io_dgen_bits_uop_fp_typ, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
output io_dgen_bits_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
output [2:0] io_dgen_bits_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
output [63:0] io_dgen_bits_data, // @[fp-pipeline.scala:35:14]
input io_to_int_ready, // @[fp-pipeline.scala:35:14]
output io_to_int_valid, // @[fp-pipeline.scala:35:14]
output [31:0] io_to_int_bits_uop_inst, // @[fp-pipeline.scala:35:14]
output [31:0] io_to_int_bits_uop_debug_inst, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_rvc, // @[fp-pipeline.scala:35:14]
output [39:0] io_to_int_bits_uop_debug_pc, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iw_issued, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
output [15:0] io_to_int_bits_uop_br_mask, // @[fp-pipeline.scala:35:14]
output [3:0] io_to_int_bits_uop_br_tag, // @[fp-pipeline.scala:35:14]
output [3:0] io_to_int_bits_uop_br_type, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_sfb, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_fence, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_fencei, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_sfence, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_amo, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_eret, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_rocc, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_mov, // @[fp-pipeline.scala:35:14]
output [4:0] io_to_int_bits_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_edge_inst, // @[fp-pipeline.scala:35:14]
output [5:0] io_to_int_bits_uop_pc_lob, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_taken, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_imm_rename, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_imm_sel, // @[fp-pipeline.scala:35:14]
output [4:0] io_to_int_bits_uop_pimm, // @[fp-pipeline.scala:35:14]
output [19:0] io_to_int_bits_uop_imm_packed, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_op1_sel, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_op2_sel, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
output [6:0] io_to_int_bits_uop_rob_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_to_int_bits_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_to_int_bits_uop_stq_idx, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
output [6:0] io_to_int_bits_uop_pdst, // @[fp-pipeline.scala:35:14]
output [6:0] io_to_int_bits_uop_prs1, // @[fp-pipeline.scala:35:14]
output [6:0] io_to_int_bits_uop_prs2, // @[fp-pipeline.scala:35:14]
output [6:0] io_to_int_bits_uop_prs3, // @[fp-pipeline.scala:35:14]
output [4:0] io_to_int_bits_uop_ppred, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
output [6:0] io_to_int_bits_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_exception, // @[fp-pipeline.scala:35:14]
output [63:0] io_to_int_bits_uop_exc_cause, // @[fp-pipeline.scala:35:14]
output [4:0] io_to_int_bits_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_mem_size, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_mem_signed, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_uses_stq, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_is_unique, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_to_int_bits_uop_ldst, // @[fp-pipeline.scala:35:14]
output [5:0] io_to_int_bits_uop_lrs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_to_int_bits_uop_lrs2, // @[fp-pipeline.scala:35:14]
output [5:0] io_to_int_bits_uop_lrs3, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_frs3_en, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
output [4:0] io_to_int_bits_uop_fcn_op, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_fp_val, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_fp_rm, // @[fp-pipeline.scala:35:14]
output [1:0] io_to_int_bits_uop_fp_typ, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
output [2:0] io_to_int_bits_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
output [63:0] io_to_int_bits_data, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_predicated, // @[fp-pipeline.scala:35:14]
output io_to_int_bits_fflags_valid, // @[fp-pipeline.scala:35:14]
output [4:0] io_to_int_bits_fflags_bits, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_valid, // @[fp-pipeline.scala:35:14]
output [31:0] io_wakeups_0_bits_uop_inst, // @[fp-pipeline.scala:35:14]
output [31:0] io_wakeups_0_bits_uop_debug_inst, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_rvc, // @[fp-pipeline.scala:35:14]
output [39:0] io_wakeups_0_bits_uop_debug_pc, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iw_issued, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
output [15:0] io_wakeups_0_bits_uop_br_mask, // @[fp-pipeline.scala:35:14]
output [3:0] io_wakeups_0_bits_uop_br_tag, // @[fp-pipeline.scala:35:14]
output [3:0] io_wakeups_0_bits_uop_br_type, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_sfb, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_fence, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_fencei, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_sfence, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_amo, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_eret, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_rocc, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_mov, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_0_bits_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_edge_inst, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_0_bits_uop_pc_lob, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_taken, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_imm_rename, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_imm_sel, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_0_bits_uop_pimm, // @[fp-pipeline.scala:35:14]
output [19:0] io_wakeups_0_bits_uop_imm_packed, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_op1_sel, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_op2_sel, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_0_bits_uop_rob_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_0_bits_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_0_bits_uop_stq_idx, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_0_bits_uop_pdst, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_0_bits_uop_prs1, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_0_bits_uop_prs2, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_0_bits_uop_prs3, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_0_bits_uop_ppred, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_0_bits_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_exception, // @[fp-pipeline.scala:35:14]
output [63:0] io_wakeups_0_bits_uop_exc_cause, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_mem_size, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_mem_signed, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_uses_stq, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_is_unique, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_0_bits_uop_ldst, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_0_bits_uop_lrs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_0_bits_uop_lrs2, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_0_bits_uop_lrs3, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_frs3_en, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_0_bits_uop_fcn_op, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_fp_val, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_fp_rm, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_0_bits_uop_fp_typ, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
output io_wakeups_0_bits_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_0_bits_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_valid, // @[fp-pipeline.scala:35:14]
output [31:0] io_wakeups_1_bits_uop_inst, // @[fp-pipeline.scala:35:14]
output [31:0] io_wakeups_1_bits_uop_debug_inst, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_rvc, // @[fp-pipeline.scala:35:14]
output [39:0] io_wakeups_1_bits_uop_debug_pc, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iw_issued, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
output [15:0] io_wakeups_1_bits_uop_br_mask, // @[fp-pipeline.scala:35:14]
output [3:0] io_wakeups_1_bits_uop_br_tag, // @[fp-pipeline.scala:35:14]
output [3:0] io_wakeups_1_bits_uop_br_type, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_sfb, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_fence, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_fencei, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_sfence, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_amo, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_eret, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_rocc, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_mov, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_1_bits_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_edge_inst, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_1_bits_uop_pc_lob, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_taken, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_imm_rename, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_imm_sel, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_1_bits_uop_pimm, // @[fp-pipeline.scala:35:14]
output [19:0] io_wakeups_1_bits_uop_imm_packed, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_op1_sel, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_op2_sel, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_1_bits_uop_rob_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_1_bits_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_1_bits_uop_stq_idx, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_1_bits_uop_pdst, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_1_bits_uop_prs1, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_1_bits_uop_prs2, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_1_bits_uop_prs3, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_1_bits_uop_ppred, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
output [6:0] io_wakeups_1_bits_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_exception, // @[fp-pipeline.scala:35:14]
output [63:0] io_wakeups_1_bits_uop_exc_cause, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_mem_size, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_mem_signed, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_uses_stq, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_is_unique, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_1_bits_uop_ldst, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_1_bits_uop_lrs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_1_bits_uop_lrs2, // @[fp-pipeline.scala:35:14]
output [5:0] io_wakeups_1_bits_uop_lrs3, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_frs3_en, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
output [4:0] io_wakeups_1_bits_uop_fcn_op, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_fp_val, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_fp_rm, // @[fp-pipeline.scala:35:14]
output [1:0] io_wakeups_1_bits_uop_fp_typ, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
output io_wakeups_1_bits_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
output [2:0] io_wakeups_1_bits_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
output io_wb_0_valid, // @[fp-pipeline.scala:35:14]
output [31:0] io_wb_0_bits_uop_inst, // @[fp-pipeline.scala:35:14]
output [31:0] io_wb_0_bits_uop_debug_inst, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_rvc, // @[fp-pipeline.scala:35:14]
output [39:0] io_wb_0_bits_uop_debug_pc, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iw_issued, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
output [15:0] io_wb_0_bits_uop_br_mask, // @[fp-pipeline.scala:35:14]
output [3:0] io_wb_0_bits_uop_br_tag, // @[fp-pipeline.scala:35:14]
output [3:0] io_wb_0_bits_uop_br_type, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_sfb, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_fence, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_fencei, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_sfence, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_amo, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_eret, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_rocc, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_mov, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_0_bits_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_edge_inst, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_0_bits_uop_pc_lob, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_taken, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_imm_rename, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_imm_sel, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_0_bits_uop_pimm, // @[fp-pipeline.scala:35:14]
output [19:0] io_wb_0_bits_uop_imm_packed, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_op1_sel, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_op2_sel, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_0_bits_uop_rob_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_0_bits_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_0_bits_uop_stq_idx, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_0_bits_uop_pdst, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_0_bits_uop_prs1, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_0_bits_uop_prs2, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_0_bits_uop_prs3, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_0_bits_uop_ppred, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_0_bits_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_exception, // @[fp-pipeline.scala:35:14]
output [63:0] io_wb_0_bits_uop_exc_cause, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_0_bits_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_mem_size, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_mem_signed, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_uses_stq, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_is_unique, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_0_bits_uop_ldst, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_0_bits_uop_lrs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_0_bits_uop_lrs2, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_0_bits_uop_lrs3, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_frs3_en, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_0_bits_uop_fcn_op, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_fp_val, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_fp_rm, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_0_bits_uop_fp_typ, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_0_bits_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
output [64:0] io_wb_0_bits_data, // @[fp-pipeline.scala:35:14]
output io_wb_0_bits_fflags_valid, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_0_bits_fflags_bits, // @[fp-pipeline.scala:35:14]
output io_wb_1_valid, // @[fp-pipeline.scala:35:14]
output [31:0] io_wb_1_bits_uop_inst, // @[fp-pipeline.scala:35:14]
output [31:0] io_wb_1_bits_uop_debug_inst, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_rvc, // @[fp-pipeline.scala:35:14]
output [39:0] io_wb_1_bits_uop_debug_pc, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iq_type_0, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iq_type_1, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iq_type_2, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iq_type_3, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_0, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_1, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_2, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_3, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_4, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_5, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_6, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_7, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_8, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fu_code_9, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iw_issued, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iw_issued_partial_agen, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iw_issued_partial_dgen, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_iw_p1_speculative_child, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_iw_p2_speculative_child, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iw_p1_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iw_p2_bypass_hint, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_iw_p3_bypass_hint, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_dis_col_sel, // @[fp-pipeline.scala:35:14]
output [15:0] io_wb_1_bits_uop_br_mask, // @[fp-pipeline.scala:35:14]
output [3:0] io_wb_1_bits_uop_br_tag, // @[fp-pipeline.scala:35:14]
output [3:0] io_wb_1_bits_uop_br_type, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_sfb, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_fence, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_fencei, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_sfence, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_amo, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_eret, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_sys_pc2epc, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_rocc, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_mov, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_1_bits_uop_ftq_idx, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_edge_inst, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_1_bits_uop_pc_lob, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_taken, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_imm_rename, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_imm_sel, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_1_bits_uop_pimm, // @[fp-pipeline.scala:35:14]
output [19:0] io_wb_1_bits_uop_imm_packed, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_op1_sel, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_op2_sel, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_ldst, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_wen, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_ren1, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_ren2, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_ren3, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_swap12, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_swap23, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_fp_ctrl_typeTagIn, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_fp_ctrl_typeTagOut, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_fromint, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_toint, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_fastpipe, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_fma, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_div, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_sqrt, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_wflags, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_ctrl_vec, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_1_bits_uop_rob_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_1_bits_uop_ldq_idx, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_1_bits_uop_stq_idx, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_rxq_idx, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_1_bits_uop_pdst, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_1_bits_uop_prs1, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_1_bits_uop_prs2, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_1_bits_uop_prs3, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_1_bits_uop_ppred, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_prs1_busy, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_prs2_busy, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_prs3_busy, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_ppred_busy, // @[fp-pipeline.scala:35:14]
output [6:0] io_wb_1_bits_uop_stale_pdst, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_exception, // @[fp-pipeline.scala:35:14]
output [63:0] io_wb_1_bits_uop_exc_cause, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_1_bits_uop_mem_cmd, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_mem_size, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_mem_signed, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_uses_ldq, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_uses_stq, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_is_unique, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_flush_on_commit, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_csr_cmd, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_ldst_is_rs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_1_bits_uop_ldst, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_1_bits_uop_lrs1, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_1_bits_uop_lrs2, // @[fp-pipeline.scala:35:14]
output [5:0] io_wb_1_bits_uop_lrs3, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_dst_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_lrs1_rtype, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_lrs2_rtype, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_frs3_en, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fcn_dw, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_1_bits_uop_fcn_op, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_fp_val, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_fp_rm, // @[fp-pipeline.scala:35:14]
output [1:0] io_wb_1_bits_uop_fp_typ, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_xcpt_pf_if, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_xcpt_ae_if, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_xcpt_ma_if, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_bp_debug_if, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_uop_bp_xcpt_if, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_debug_fsrc, // @[fp-pipeline.scala:35:14]
output [2:0] io_wb_1_bits_uop_debug_tsrc, // @[fp-pipeline.scala:35:14]
output [64:0] io_wb_1_bits_data, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_predicated, // @[fp-pipeline.scala:35:14]
output io_wb_1_bits_fflags_valid, // @[fp-pipeline.scala:35:14]
output [4:0] io_wb_1_bits_fflags_bits, // @[fp-pipeline.scala:35:14]
input [63:0] io_debug_tsc_reg // @[fp-pipeline.scala:35:14]
);
wire ll_wbarb_io_in_0_bits_data_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire ll_wbarb_io_in_0_bits_data_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire _ll_wbarb_io_in_2_ready; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_valid; // @[fp-pipeline.scala:167:24]
wire [31:0] _ll_wbarb_io_out_bits_uop_inst; // @[fp-pipeline.scala:167:24]
wire [31:0] _ll_wbarb_io_out_bits_uop_debug_inst; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_rvc; // @[fp-pipeline.scala:167:24]
wire [39:0] _ll_wbarb_io_out_bits_uop_debug_pc; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iq_type_0; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iq_type_1; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iq_type_2; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iq_type_3; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_0; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_1; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_2; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_3; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_4; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_5; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_6; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_7; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_8; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fu_code_9; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iw_issued; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_dis_col_sel; // @[fp-pipeline.scala:167:24]
wire [15:0] _ll_wbarb_io_out_bits_uop_br_mask; // @[fp-pipeline.scala:167:24]
wire [3:0] _ll_wbarb_io_out_bits_uop_br_tag; // @[fp-pipeline.scala:167:24]
wire [3:0] _ll_wbarb_io_out_bits_uop_br_type; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_sfb; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_fence; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_fencei; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_sfence; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_amo; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_eret; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_rocc; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_mov; // @[fp-pipeline.scala:167:24]
wire [4:0] _ll_wbarb_io_out_bits_uop_ftq_idx; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_edge_inst; // @[fp-pipeline.scala:167:24]
wire [5:0] _ll_wbarb_io_out_bits_uop_pc_lob; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_taken; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_imm_rename; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_imm_sel; // @[fp-pipeline.scala:167:24]
wire [4:0] _ll_wbarb_io_out_bits_uop_pimm; // @[fp-pipeline.scala:167:24]
wire [19:0] _ll_wbarb_io_out_bits_uop_imm_packed; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_op1_sel; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_op2_sel; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:167:24]
wire [6:0] _ll_wbarb_io_out_bits_uop_rob_idx; // @[fp-pipeline.scala:167:24]
wire [4:0] _ll_wbarb_io_out_bits_uop_ldq_idx; // @[fp-pipeline.scala:167:24]
wire [4:0] _ll_wbarb_io_out_bits_uop_stq_idx; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_rxq_idx; // @[fp-pipeline.scala:167:24]
wire [6:0] _ll_wbarb_io_out_bits_uop_pdst; // @[fp-pipeline.scala:167:24]
wire [6:0] _ll_wbarb_io_out_bits_uop_prs1; // @[fp-pipeline.scala:167:24]
wire [6:0] _ll_wbarb_io_out_bits_uop_prs2; // @[fp-pipeline.scala:167:24]
wire [6:0] _ll_wbarb_io_out_bits_uop_prs3; // @[fp-pipeline.scala:167:24]
wire [4:0] _ll_wbarb_io_out_bits_uop_ppred; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_prs1_busy; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_prs2_busy; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_prs3_busy; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_ppred_busy; // @[fp-pipeline.scala:167:24]
wire [6:0] _ll_wbarb_io_out_bits_uop_stale_pdst; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_exception; // @[fp-pipeline.scala:167:24]
wire [63:0] _ll_wbarb_io_out_bits_uop_exc_cause; // @[fp-pipeline.scala:167:24]
wire [4:0] _ll_wbarb_io_out_bits_uop_mem_cmd; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_mem_size; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_mem_signed; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_uses_ldq; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_uses_stq; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_is_unique; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_flush_on_commit; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_csr_cmd; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:167:24]
wire [5:0] _ll_wbarb_io_out_bits_uop_ldst; // @[fp-pipeline.scala:167:24]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs1; // @[fp-pipeline.scala:167:24]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs2; // @[fp-pipeline.scala:167:24]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs3; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_dst_rtype; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_frs3_en; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fcn_dw; // @[fp-pipeline.scala:167:24]
wire [4:0] _ll_wbarb_io_out_bits_uop_fcn_op; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_fp_val; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_fp_rm; // @[fp-pipeline.scala:167:24]
wire [1:0] _ll_wbarb_io_out_bits_uop_fp_typ; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_bp_debug_if; // @[fp-pipeline.scala:167:24]
wire _ll_wbarb_io_out_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_debug_fsrc; // @[fp-pipeline.scala:167:24]
wire [2:0] _ll_wbarb_io_out_bits_uop_debug_tsrc; // @[fp-pipeline.scala:167:24]
wire [64:0] _ll_wbarb_io_out_bits_data; // @[fp-pipeline.scala:167:24]
wire _fregfile_io_arb_read_reqs_2_ready; // @[fp-pipeline.scala:71:30]
wire [64:0] _fregfile_io_rrd_read_resps_0; // @[fp-pipeline.scala:71:30]
wire [64:0] _fregfile_io_rrd_read_resps_1; // @[fp-pipeline.scala:71:30]
wire [64:0] _fregfile_io_rrd_read_resps_2; // @[fp-pipeline.scala:71:30]
wire _fp_issue_unit_io_iss_uops_0_valid; // @[issue-unit.scala:81:13]
wire [31:0] _fp_issue_unit_io_iss_uops_0_bits_inst; // @[issue-unit.scala:81:13]
wire [31:0] _fp_issue_unit_io_iss_uops_0_bits_debug_inst; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_rvc; // @[issue-unit.scala:81:13]
wire [39:0] _fp_issue_unit_io_iss_uops_0_bits_debug_pc; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_iq_type_0; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_iq_type_1; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_iq_type_2; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_iq_type_3; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_0; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_1; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_2; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_3; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_4; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_5; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_6; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_7; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_8; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fu_code_9; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_iw_issued; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_dis_col_sel; // @[issue-unit.scala:81:13]
wire [15:0] _fp_issue_unit_io_iss_uops_0_bits_br_mask; // @[issue-unit.scala:81:13]
wire [3:0] _fp_issue_unit_io_iss_uops_0_bits_br_tag; // @[issue-unit.scala:81:13]
wire [3:0] _fp_issue_unit_io_iss_uops_0_bits_br_type; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_sfb; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_fence; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_fencei; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_sfence; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_amo; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_eret; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_rocc; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_mov; // @[issue-unit.scala:81:13]
wire [4:0] _fp_issue_unit_io_iss_uops_0_bits_ftq_idx; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_edge_inst; // @[issue-unit.scala:81:13]
wire [5:0] _fp_issue_unit_io_iss_uops_0_bits_pc_lob; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_taken; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_imm_rename; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_imm_sel; // @[issue-unit.scala:81:13]
wire [4:0] _fp_issue_unit_io_iss_uops_0_bits_pimm; // @[issue-unit.scala:81:13]
wire [19:0] _fp_issue_unit_io_iss_uops_0_bits_imm_packed; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_op1_sel; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_op2_sel; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_div; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit.scala:81:13]
wire [6:0] _fp_issue_unit_io_iss_uops_0_bits_rob_idx; // @[issue-unit.scala:81:13]
wire [4:0] _fp_issue_unit_io_iss_uops_0_bits_ldq_idx; // @[issue-unit.scala:81:13]
wire [4:0] _fp_issue_unit_io_iss_uops_0_bits_stq_idx; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_rxq_idx; // @[issue-unit.scala:81:13]
wire [6:0] _fp_issue_unit_io_iss_uops_0_bits_pdst; // @[issue-unit.scala:81:13]
wire [6:0] _fp_issue_unit_io_iss_uops_0_bits_prs1; // @[issue-unit.scala:81:13]
wire [6:0] _fp_issue_unit_io_iss_uops_0_bits_prs2; // @[issue-unit.scala:81:13]
wire [6:0] _fp_issue_unit_io_iss_uops_0_bits_prs3; // @[issue-unit.scala:81:13]
wire [4:0] _fp_issue_unit_io_iss_uops_0_bits_ppred; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_prs1_busy; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_prs2_busy; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_prs3_busy; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_ppred_busy; // @[issue-unit.scala:81:13]
wire [6:0] _fp_issue_unit_io_iss_uops_0_bits_stale_pdst; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_exception; // @[issue-unit.scala:81:13]
wire [63:0] _fp_issue_unit_io_iss_uops_0_bits_exc_cause; // @[issue-unit.scala:81:13]
wire [4:0] _fp_issue_unit_io_iss_uops_0_bits_mem_cmd; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_mem_size; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_mem_signed; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_uses_ldq; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_uses_stq; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_is_unique; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_flush_on_commit; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_csr_cmd; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_ldst_is_rs1; // @[issue-unit.scala:81:13]
wire [5:0] _fp_issue_unit_io_iss_uops_0_bits_ldst; // @[issue-unit.scala:81:13]
wire [5:0] _fp_issue_unit_io_iss_uops_0_bits_lrs1; // @[issue-unit.scala:81:13]
wire [5:0] _fp_issue_unit_io_iss_uops_0_bits_lrs2; // @[issue-unit.scala:81:13]
wire [5:0] _fp_issue_unit_io_iss_uops_0_bits_lrs3; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_dst_rtype; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_lrs1_rtype; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_lrs2_rtype; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_frs3_en; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fcn_dw; // @[issue-unit.scala:81:13]
wire [4:0] _fp_issue_unit_io_iss_uops_0_bits_fcn_op; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_fp_val; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_fp_rm; // @[issue-unit.scala:81:13]
wire [1:0] _fp_issue_unit_io_iss_uops_0_bits_fp_typ; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_xcpt_pf_if; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_xcpt_ae_if; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_xcpt_ma_if; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_bp_debug_if; // @[issue-unit.scala:81:13]
wire _fp_issue_unit_io_iss_uops_0_bits_bp_xcpt_if; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_debug_fsrc; // @[issue-unit.scala:81:13]
wire [2:0] _fp_issue_unit_io_iss_uops_0_bits_debug_tsrc; // @[issue-unit.scala:81:13]
wire _fp_exe_unit_0_io_ready_fu_types_7; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_ready_fu_types_9; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_arb_frf_reqs_0_valid; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_arb_frf_reqs_0_bits; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_arb_frf_reqs_1_valid; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_arb_frf_reqs_1_bits; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_arb_frf_reqs_2_valid; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_arb_frf_reqs_2_bits; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_squash_iss; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_valid; // @[fp-pipeline.scala:59:11]
wire [31:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_inst; // @[fp-pipeline.scala:59:11]
wire [31:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_debug_inst; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_rvc; // @[fp-pipeline.scala:59:11]
wire [39:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_debug_pc; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iq_type_0; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iq_type_1; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iq_type_2; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iq_type_3; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_0; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_1; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_2; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_3; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_4; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_5; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_6; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_7; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_8; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fu_code_9; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iw_issued; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_dis_col_sel; // @[fp-pipeline.scala:59:11]
wire [15:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_br_mask; // @[fp-pipeline.scala:59:11]
wire [3:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_br_tag; // @[fp-pipeline.scala:59:11]
wire [3:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_br_type; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_sfb; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_fence; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_fencei; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_sfence; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_amo; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_eret; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_rocc; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_mov; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_ftq_idx; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_edge_inst; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_pc_lob; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_taken; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_imm_rename; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_imm_sel; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_pimm; // @[fp-pipeline.scala:59:11]
wire [19:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_imm_packed; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_op1_sel; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_op2_sel; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_rob_idx; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_ldq_idx; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_stq_idx; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_rxq_idx; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_pdst; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_prs1; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_prs2; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_prs3; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_ppred; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_prs1_busy; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_prs2_busy; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_prs3_busy; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_ppred_busy; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_stale_pdst; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_exception; // @[fp-pipeline.scala:59:11]
wire [63:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_exc_cause; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_mem_cmd; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_mem_size; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_mem_signed; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_uses_ldq; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_uses_stq; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_is_unique; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_flush_on_commit; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_csr_cmd; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_ldst; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_lrs1; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_lrs2; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_lrs3; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_dst_rtype; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_frs3_en; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fcn_dw; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_fcn_op; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_val; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_rm; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_fp_typ; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_bp_debug_if; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_debug_fsrc; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fpu_resp_bits_uop_debug_tsrc; // @[fp-pipeline.scala:59:11]
wire [64:0] _fp_exe_unit_0_io_fpu_resp_bits_data; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fpu_resp_bits_fflags_valid; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fpu_resp_bits_fflags_bits; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_valid; // @[fp-pipeline.scala:59:11]
wire [31:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_inst; // @[fp-pipeline.scala:59:11]
wire [31:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_debug_inst; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_rvc; // @[fp-pipeline.scala:59:11]
wire [39:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_debug_pc; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iq_type_0; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iq_type_1; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iq_type_2; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iq_type_3; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_0; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_1; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_2; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_3; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_4; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_5; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_6; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_7; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_8; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fu_code_9; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iw_issued; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_dis_col_sel; // @[fp-pipeline.scala:59:11]
wire [15:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_br_mask; // @[fp-pipeline.scala:59:11]
wire [3:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_br_tag; // @[fp-pipeline.scala:59:11]
wire [3:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_br_type; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_sfb; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_fence; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_fencei; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_sfence; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_amo; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_eret; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_rocc; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_mov; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_ftq_idx; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_edge_inst; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_pc_lob; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_taken; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_imm_rename; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_imm_sel; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_pimm; // @[fp-pipeline.scala:59:11]
wire [19:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_imm_packed; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_op1_sel; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_op2_sel; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_rob_idx; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_ldq_idx; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_stq_idx; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_rxq_idx; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_pdst; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_prs1; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_prs2; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_prs3; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_ppred; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_prs1_busy; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_prs2_busy; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_prs3_busy; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_ppred_busy; // @[fp-pipeline.scala:59:11]
wire [6:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_stale_pdst; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_exception; // @[fp-pipeline.scala:59:11]
wire [63:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_exc_cause; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_mem_cmd; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_mem_size; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_mem_signed; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_uses_ldq; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_uses_stq; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_is_unique; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_flush_on_commit; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_csr_cmd; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_ldst; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_lrs1; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_lrs2; // @[fp-pipeline.scala:59:11]
wire [5:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_lrs3; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_dst_rtype; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_frs3_en; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fcn_dw; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_fcn_op; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_val; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_rm; // @[fp-pipeline.scala:59:11]
wire [1:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_fp_typ; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_bp_debug_if; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_debug_fsrc; // @[fp-pipeline.scala:59:11]
wire [2:0] _fp_exe_unit_0_io_fdiv_resp_bits_uop_debug_tsrc; // @[fp-pipeline.scala:59:11]
wire [64:0] _fp_exe_unit_0_io_fdiv_resp_bits_data; // @[fp-pipeline.scala:59:11]
wire _fp_exe_unit_0_io_fdiv_resp_bits_fflags_valid; // @[fp-pipeline.scala:59:11]
wire [4:0] _fp_exe_unit_0_io_fdiv_resp_bits_fflags_bits; // @[fp-pipeline.scala:59:11]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[fp-pipeline.scala:27:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[fp-pipeline.scala:27:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[fp-pipeline.scala:27:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[fp-pipeline.scala:27:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[fp-pipeline.scala:27:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[fp-pipeline.scala:27:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[fp-pipeline.scala:27:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[fp-pipeline.scala:27:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[fp-pipeline.scala:27:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[fp-pipeline.scala:27:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[fp-pipeline.scala:27:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[fp-pipeline.scala:27:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[fp-pipeline.scala:27:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[fp-pipeline.scala:27:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[fp-pipeline.scala:27:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[fp-pipeline.scala:27:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[fp-pipeline.scala:27:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[fp-pipeline.scala:27:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[fp-pipeline.scala:27:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[fp-pipeline.scala:27:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[fp-pipeline.scala:27:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[fp-pipeline.scala:27:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[fp-pipeline.scala:27:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[fp-pipeline.scala:27:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[fp-pipeline.scala:27:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[fp-pipeline.scala:27:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[fp-pipeline.scala:27:7]
wire io_flush_pipeline_0 = io_flush_pipeline; // @[fp-pipeline.scala:27:7]
wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[fp-pipeline.scala:27:7]
wire io_status_debug_0 = io_status_debug; // @[fp-pipeline.scala:27:7]
wire io_status_cease_0 = io_status_cease; // @[fp-pipeline.scala:27:7]
wire io_status_wfi_0 = io_status_wfi; // @[fp-pipeline.scala:27:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[fp-pipeline.scala:27:7]
wire io_status_dv_0 = io_status_dv; // @[fp-pipeline.scala:27:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[fp-pipeline.scala:27:7]
wire io_status_v_0 = io_status_v; // @[fp-pipeline.scala:27:7]
wire io_status_sd_0 = io_status_sd; // @[fp-pipeline.scala:27:7]
wire io_status_mpv_0 = io_status_mpv; // @[fp-pipeline.scala:27:7]
wire io_status_gva_0 = io_status_gva; // @[fp-pipeline.scala:27:7]
wire io_status_tsr_0 = io_status_tsr; // @[fp-pipeline.scala:27:7]
wire io_status_tw_0 = io_status_tw; // @[fp-pipeline.scala:27:7]
wire io_status_tvm_0 = io_status_tvm; // @[fp-pipeline.scala:27:7]
wire io_status_mxr_0 = io_status_mxr; // @[fp-pipeline.scala:27:7]
wire io_status_sum_0 = io_status_sum; // @[fp-pipeline.scala:27:7]
wire io_status_mprv_0 = io_status_mprv; // @[fp-pipeline.scala:27:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[fp-pipeline.scala:27:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[fp-pipeline.scala:27:7]
wire io_status_spp_0 = io_status_spp; // @[fp-pipeline.scala:27:7]
wire io_status_mpie_0 = io_status_mpie; // @[fp-pipeline.scala:27:7]
wire io_status_spie_0 = io_status_spie; // @[fp-pipeline.scala:27:7]
wire io_status_mie_0 = io_status_mie; // @[fp-pipeline.scala:27:7]
wire io_status_sie_0 = io_status_sie; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[fp-pipeline.scala:27:7]
wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[fp-pipeline.scala:27:7]
wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[fp-pipeline.scala:27:7]
wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[fp-pipeline.scala:27:7]
wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[fp-pipeline.scala:27:7]
wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[fp-pipeline.scala:27:7]
wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[fp-pipeline.scala:27:7]
wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[fp-pipeline.scala:27:7]
wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[fp-pipeline.scala:27:7]
wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[fp-pipeline.scala:27:7]
wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[fp-pipeline.scala:27:7]
wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[fp-pipeline.scala:27:7]
wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[fp-pipeline.scala:27:7]
wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[fp-pipeline.scala:27:7]
wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[fp-pipeline.scala:27:7]
wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[fp-pipeline.scala:27:7]
wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[fp-pipeline.scala:27:7]
wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[fp-pipeline.scala:27:7]
wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[fp-pipeline.scala:27:7]
wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iq_type_0_0 = io_dis_uops_2_bits_iq_type_0; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iq_type_1_0 = io_dis_uops_2_bits_iq_type_1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iq_type_2_0 = io_dis_uops_2_bits_iq_type_2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iq_type_3_0 = io_dis_uops_2_bits_iq_type_3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_0_0 = io_dis_uops_2_bits_fu_code_0; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_1_0 = io_dis_uops_2_bits_fu_code_1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_2_0 = io_dis_uops_2_bits_fu_code_2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_3_0 = io_dis_uops_2_bits_fu_code_3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_4_0 = io_dis_uops_2_bits_fu_code_4; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_5_0 = io_dis_uops_2_bits_fu_code_5; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_6_0 = io_dis_uops_2_bits_fu_code_6; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_7_0 = io_dis_uops_2_bits_fu_code_7; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_8_0 = io_dis_uops_2_bits_fu_code_8; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fu_code_9_0 = io_dis_uops_2_bits_fu_code_9; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iw_issued_0 = io_dis_uops_2_bits_iw_issued; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iw_issued_partial_agen_0 = io_dis_uops_2_bits_iw_issued_partial_agen; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iw_issued_partial_dgen_0 = io_dis_uops_2_bits_iw_issued_partial_dgen; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_iw_p1_speculative_child_0 = io_dis_uops_2_bits_iw_p1_speculative_child; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_iw_p2_speculative_child_0 = io_dis_uops_2_bits_iw_p2_speculative_child; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iw_p1_bypass_hint_0 = io_dis_uops_2_bits_iw_p1_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iw_p2_bypass_hint_0 = io_dis_uops_2_bits_iw_p2_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_iw_p3_bypass_hint_0 = io_dis_uops_2_bits_iw_p3_bypass_hint; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_dis_col_sel_0 = io_dis_uops_2_bits_dis_col_sel; // @[fp-pipeline.scala:27:7]
wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[fp-pipeline.scala:27:7]
wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[fp-pipeline.scala:27:7]
wire [3:0] io_dis_uops_2_bits_br_type_0 = io_dis_uops_2_bits_br_type; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_sfence_0 = io_dis_uops_2_bits_is_sfence; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_eret_0 = io_dis_uops_2_bits_is_eret; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_rocc_0 = io_dis_uops_2_bits_is_rocc; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_mov_0 = io_dis_uops_2_bits_is_mov; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_imm_rename_0 = io_dis_uops_2_bits_imm_rename; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_imm_sel_0 = io_dis_uops_2_bits_imm_sel; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_2_bits_pimm_0 = io_dis_uops_2_bits_pimm; // @[fp-pipeline.scala:27:7]
wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_op1_sel_0 = io_dis_uops_2_bits_op1_sel; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_op2_sel_0 = io_dis_uops_2_bits_op2_sel; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_ldst_0 = io_dis_uops_2_bits_fp_ctrl_ldst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_wen_0 = io_dis_uops_2_bits_fp_ctrl_wen; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_ren1_0 = io_dis_uops_2_bits_fp_ctrl_ren1; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_ren2_0 = io_dis_uops_2_bits_fp_ctrl_ren2; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_ren3_0 = io_dis_uops_2_bits_fp_ctrl_ren3; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_swap12_0 = io_dis_uops_2_bits_fp_ctrl_swap12; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_swap23_0 = io_dis_uops_2_bits_fp_ctrl_swap23; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_2_bits_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_2_bits_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_fromint_0 = io_dis_uops_2_bits_fp_ctrl_fromint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_toint_0 = io_dis_uops_2_bits_fp_ctrl_toint; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_fastpipe_0 = io_dis_uops_2_bits_fp_ctrl_fastpipe; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_fma_0 = io_dis_uops_2_bits_fp_ctrl_fma; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_div_0 = io_dis_uops_2_bits_fp_ctrl_div; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_sqrt_0 = io_dis_uops_2_bits_fp_ctrl_sqrt; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_wflags_0 = io_dis_uops_2_bits_fp_ctrl_wflags; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_ctrl_vec_0 = io_dis_uops_2_bits_fp_ctrl_vec; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_2_bits_ppred_0 = io_dis_uops_2_bits_ppred; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_ppred_busy_0 = io_dis_uops_2_bits_ppred_busy; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[fp-pipeline.scala:27:7]
wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_csr_cmd_0 = io_dis_uops_2_bits_csr_cmd; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fcn_dw_0 = io_dis_uops_2_bits_fcn_dw; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dis_uops_2_bits_fcn_op_0 = io_dis_uops_2_bits_fcn_op; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_fp_rm_0 = io_dis_uops_2_bits_fp_rm; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dis_uops_2_bits_fp_typ_0 = io_dis_uops_2_bits_fp_typ; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_valid_0 = io_ll_wports_0_valid; // @[fp-pipeline.scala:27:7]
wire [31:0] io_ll_wports_0_bits_uop_inst_0 = io_ll_wports_0_bits_uop_inst; // @[fp-pipeline.scala:27:7]
wire [31:0] io_ll_wports_0_bits_uop_debug_inst_0 = io_ll_wports_0_bits_uop_debug_inst; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_rvc_0 = io_ll_wports_0_bits_uop_is_rvc; // @[fp-pipeline.scala:27:7]
wire [39:0] io_ll_wports_0_bits_uop_debug_pc_0 = io_ll_wports_0_bits_uop_debug_pc; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iq_type_0_0 = io_ll_wports_0_bits_uop_iq_type_0; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iq_type_1_0 = io_ll_wports_0_bits_uop_iq_type_1; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iq_type_2_0 = io_ll_wports_0_bits_uop_iq_type_2; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iq_type_3_0 = io_ll_wports_0_bits_uop_iq_type_3; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_0_0 = io_ll_wports_0_bits_uop_fu_code_0; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_1_0 = io_ll_wports_0_bits_uop_fu_code_1; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_2_0 = io_ll_wports_0_bits_uop_fu_code_2; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_3_0 = io_ll_wports_0_bits_uop_fu_code_3; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_4_0 = io_ll_wports_0_bits_uop_fu_code_4; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_5_0 = io_ll_wports_0_bits_uop_fu_code_5; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_6_0 = io_ll_wports_0_bits_uop_fu_code_6; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_7_0 = io_ll_wports_0_bits_uop_fu_code_7; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_8_0 = io_ll_wports_0_bits_uop_fu_code_8; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fu_code_9_0 = io_ll_wports_0_bits_uop_fu_code_9; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iw_issued_0 = io_ll_wports_0_bits_uop_iw_issued; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iw_issued_partial_agen_0 = io_ll_wports_0_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iw_issued_partial_dgen_0 = io_ll_wports_0_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_iw_p1_speculative_child_0 = io_ll_wports_0_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_iw_p2_speculative_child_0 = io_ll_wports_0_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iw_p1_bypass_hint_0 = io_ll_wports_0_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iw_p2_bypass_hint_0 = io_ll_wports_0_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_iw_p3_bypass_hint_0 = io_ll_wports_0_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_dis_col_sel_0 = io_ll_wports_0_bits_uop_dis_col_sel; // @[fp-pipeline.scala:27:7]
wire [15:0] io_ll_wports_0_bits_uop_br_mask_0 = io_ll_wports_0_bits_uop_br_mask; // @[fp-pipeline.scala:27:7]
wire [3:0] io_ll_wports_0_bits_uop_br_tag_0 = io_ll_wports_0_bits_uop_br_tag; // @[fp-pipeline.scala:27:7]
wire [3:0] io_ll_wports_0_bits_uop_br_type_0 = io_ll_wports_0_bits_uop_br_type; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_sfb_0 = io_ll_wports_0_bits_uop_is_sfb; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_fence_0 = io_ll_wports_0_bits_uop_is_fence; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_fencei_0 = io_ll_wports_0_bits_uop_is_fencei; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_sfence_0 = io_ll_wports_0_bits_uop_is_sfence; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_amo_0 = io_ll_wports_0_bits_uop_is_amo; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_eret_0 = io_ll_wports_0_bits_uop_is_eret; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_sys_pc2epc_0 = io_ll_wports_0_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_rocc_0 = io_ll_wports_0_bits_uop_is_rocc; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_mov_0 = io_ll_wports_0_bits_uop_is_mov; // @[fp-pipeline.scala:27:7]
wire [4:0] io_ll_wports_0_bits_uop_ftq_idx_0 = io_ll_wports_0_bits_uop_ftq_idx; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_edge_inst_0 = io_ll_wports_0_bits_uop_edge_inst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_ll_wports_0_bits_uop_pc_lob_0 = io_ll_wports_0_bits_uop_pc_lob; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_taken_0 = io_ll_wports_0_bits_uop_taken; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_imm_rename_0 = io_ll_wports_0_bits_uop_imm_rename; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_imm_sel_0 = io_ll_wports_0_bits_uop_imm_sel; // @[fp-pipeline.scala:27:7]
wire [4:0] io_ll_wports_0_bits_uop_pimm_0 = io_ll_wports_0_bits_uop_pimm; // @[fp-pipeline.scala:27:7]
wire [19:0] io_ll_wports_0_bits_uop_imm_packed_0 = io_ll_wports_0_bits_uop_imm_packed; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_op1_sel_0 = io_ll_wports_0_bits_uop_op1_sel; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_op2_sel_0 = io_ll_wports_0_bits_uop_op2_sel; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_ldst_0 = io_ll_wports_0_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_wen_0 = io_ll_wports_0_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_ren1_0 = io_ll_wports_0_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_ren2_0 = io_ll_wports_0_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_ren3_0 = io_ll_wports_0_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_swap12_0 = io_ll_wports_0_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_swap23_0 = io_ll_wports_0_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_ll_wports_0_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_ll_wports_0_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_fromint_0 = io_ll_wports_0_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_toint_0 = io_ll_wports_0_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_fastpipe_0 = io_ll_wports_0_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_fma_0 = io_ll_wports_0_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_div_0 = io_ll_wports_0_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_sqrt_0 = io_ll_wports_0_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_wflags_0 = io_ll_wports_0_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_ctrl_vec_0 = io_ll_wports_0_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:27:7]
wire [6:0] io_ll_wports_0_bits_uop_rob_idx_0 = io_ll_wports_0_bits_uop_rob_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_ll_wports_0_bits_uop_ldq_idx_0 = io_ll_wports_0_bits_uop_ldq_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_ll_wports_0_bits_uop_stq_idx_0 = io_ll_wports_0_bits_uop_stq_idx; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_rxq_idx_0 = io_ll_wports_0_bits_uop_rxq_idx; // @[fp-pipeline.scala:27:7]
wire [6:0] io_ll_wports_0_bits_uop_pdst_0 = io_ll_wports_0_bits_uop_pdst; // @[fp-pipeline.scala:27:7]
wire [6:0] io_ll_wports_0_bits_uop_prs1_0 = io_ll_wports_0_bits_uop_prs1; // @[fp-pipeline.scala:27:7]
wire [6:0] io_ll_wports_0_bits_uop_prs2_0 = io_ll_wports_0_bits_uop_prs2; // @[fp-pipeline.scala:27:7]
wire [6:0] io_ll_wports_0_bits_uop_prs3_0 = io_ll_wports_0_bits_uop_prs3; // @[fp-pipeline.scala:27:7]
wire [4:0] io_ll_wports_0_bits_uop_ppred_0 = io_ll_wports_0_bits_uop_ppred; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_prs1_busy_0 = io_ll_wports_0_bits_uop_prs1_busy; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_prs2_busy_0 = io_ll_wports_0_bits_uop_prs2_busy; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_prs3_busy_0 = io_ll_wports_0_bits_uop_prs3_busy; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_ppred_busy_0 = io_ll_wports_0_bits_uop_ppred_busy; // @[fp-pipeline.scala:27:7]
wire [6:0] io_ll_wports_0_bits_uop_stale_pdst_0 = io_ll_wports_0_bits_uop_stale_pdst; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_exception_0 = io_ll_wports_0_bits_uop_exception; // @[fp-pipeline.scala:27:7]
wire [63:0] io_ll_wports_0_bits_uop_exc_cause_0 = io_ll_wports_0_bits_uop_exc_cause; // @[fp-pipeline.scala:27:7]
wire [4:0] io_ll_wports_0_bits_uop_mem_cmd_0 = io_ll_wports_0_bits_uop_mem_cmd; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_mem_size_0 = io_ll_wports_0_bits_uop_mem_size; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_mem_signed_0 = io_ll_wports_0_bits_uop_mem_signed; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_uses_ldq_0 = io_ll_wports_0_bits_uop_uses_ldq; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_uses_stq_0 = io_ll_wports_0_bits_uop_uses_stq; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_is_unique_0 = io_ll_wports_0_bits_uop_is_unique; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_flush_on_commit_0 = io_ll_wports_0_bits_uop_flush_on_commit; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_csr_cmd_0 = io_ll_wports_0_bits_uop_csr_cmd; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_ldst_is_rs1_0 = io_ll_wports_0_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_ll_wports_0_bits_uop_ldst_0 = io_ll_wports_0_bits_uop_ldst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_ll_wports_0_bits_uop_lrs1_0 = io_ll_wports_0_bits_uop_lrs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_ll_wports_0_bits_uop_lrs2_0 = io_ll_wports_0_bits_uop_lrs2; // @[fp-pipeline.scala:27:7]
wire [5:0] io_ll_wports_0_bits_uop_lrs3_0 = io_ll_wports_0_bits_uop_lrs3; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_dst_rtype_0 = io_ll_wports_0_bits_uop_dst_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_lrs1_rtype_0 = io_ll_wports_0_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_lrs2_rtype_0 = io_ll_wports_0_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_frs3_en_0 = io_ll_wports_0_bits_uop_frs3_en; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fcn_dw_0 = io_ll_wports_0_bits_uop_fcn_dw; // @[fp-pipeline.scala:27:7]
wire [4:0] io_ll_wports_0_bits_uop_fcn_op_0 = io_ll_wports_0_bits_uop_fcn_op; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_fp_val_0 = io_ll_wports_0_bits_uop_fp_val; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_fp_rm_0 = io_ll_wports_0_bits_uop_fp_rm; // @[fp-pipeline.scala:27:7]
wire [1:0] io_ll_wports_0_bits_uop_fp_typ_0 = io_ll_wports_0_bits_uop_fp_typ; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_xcpt_pf_if_0 = io_ll_wports_0_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_xcpt_ae_if_0 = io_ll_wports_0_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_xcpt_ma_if_0 = io_ll_wports_0_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_bp_debug_if_0 = io_ll_wports_0_bits_uop_bp_debug_if; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_uop_bp_xcpt_if_0 = io_ll_wports_0_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_debug_fsrc_0 = io_ll_wports_0_bits_uop_debug_fsrc; // @[fp-pipeline.scala:27:7]
wire [2:0] io_ll_wports_0_bits_uop_debug_tsrc_0 = io_ll_wports_0_bits_uop_debug_tsrc; // @[fp-pipeline.scala:27:7]
wire [64:0] io_ll_wports_0_bits_data_0 = io_ll_wports_0_bits_data; // @[fp-pipeline.scala:27:7]
wire io_from_int_valid_0 = io_from_int_valid; // @[fp-pipeline.scala:27:7]
wire [31:0] io_from_int_bits_uop_inst_0 = io_from_int_bits_uop_inst; // @[fp-pipeline.scala:27:7]
wire [31:0] io_from_int_bits_uop_debug_inst_0 = io_from_int_bits_uop_debug_inst; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_rvc_0 = io_from_int_bits_uop_is_rvc; // @[fp-pipeline.scala:27:7]
wire [39:0] io_from_int_bits_uop_debug_pc_0 = io_from_int_bits_uop_debug_pc; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iq_type_0_0 = io_from_int_bits_uop_iq_type_0; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iq_type_1_0 = io_from_int_bits_uop_iq_type_1; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iq_type_2_0 = io_from_int_bits_uop_iq_type_2; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iq_type_3_0 = io_from_int_bits_uop_iq_type_3; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_0_0 = io_from_int_bits_uop_fu_code_0; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_1_0 = io_from_int_bits_uop_fu_code_1; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_2_0 = io_from_int_bits_uop_fu_code_2; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_3_0 = io_from_int_bits_uop_fu_code_3; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_4_0 = io_from_int_bits_uop_fu_code_4; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_5_0 = io_from_int_bits_uop_fu_code_5; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_6_0 = io_from_int_bits_uop_fu_code_6; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_7_0 = io_from_int_bits_uop_fu_code_7; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_8_0 = io_from_int_bits_uop_fu_code_8; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fu_code_9_0 = io_from_int_bits_uop_fu_code_9; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iw_issued_0 = io_from_int_bits_uop_iw_issued; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iw_issued_partial_agen_0 = io_from_int_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iw_issued_partial_dgen_0 = io_from_int_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_iw_p1_speculative_child_0 = io_from_int_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_iw_p2_speculative_child_0 = io_from_int_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iw_p1_bypass_hint_0 = io_from_int_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iw_p2_bypass_hint_0 = io_from_int_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_iw_p3_bypass_hint_0 = io_from_int_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_dis_col_sel_0 = io_from_int_bits_uop_dis_col_sel; // @[fp-pipeline.scala:27:7]
wire [15:0] io_from_int_bits_uop_br_mask_0 = io_from_int_bits_uop_br_mask; // @[fp-pipeline.scala:27:7]
wire [3:0] io_from_int_bits_uop_br_tag_0 = io_from_int_bits_uop_br_tag; // @[fp-pipeline.scala:27:7]
wire [3:0] io_from_int_bits_uop_br_type_0 = io_from_int_bits_uop_br_type; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_sfb_0 = io_from_int_bits_uop_is_sfb; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_fence_0 = io_from_int_bits_uop_is_fence; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_fencei_0 = io_from_int_bits_uop_is_fencei; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_sfence_0 = io_from_int_bits_uop_is_sfence; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_amo_0 = io_from_int_bits_uop_is_amo; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_eret_0 = io_from_int_bits_uop_is_eret; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_sys_pc2epc_0 = io_from_int_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_rocc_0 = io_from_int_bits_uop_is_rocc; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_mov_0 = io_from_int_bits_uop_is_mov; // @[fp-pipeline.scala:27:7]
wire [4:0] io_from_int_bits_uop_ftq_idx_0 = io_from_int_bits_uop_ftq_idx; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_edge_inst_0 = io_from_int_bits_uop_edge_inst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_from_int_bits_uop_pc_lob_0 = io_from_int_bits_uop_pc_lob; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_taken_0 = io_from_int_bits_uop_taken; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_imm_rename_0 = io_from_int_bits_uop_imm_rename; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_imm_sel_0 = io_from_int_bits_uop_imm_sel; // @[fp-pipeline.scala:27:7]
wire [4:0] io_from_int_bits_uop_pimm_0 = io_from_int_bits_uop_pimm; // @[fp-pipeline.scala:27:7]
wire [19:0] io_from_int_bits_uop_imm_packed_0 = io_from_int_bits_uop_imm_packed; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_op1_sel_0 = io_from_int_bits_uop_op1_sel; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_op2_sel_0 = io_from_int_bits_uop_op2_sel; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_ldst_0 = io_from_int_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_wen_0 = io_from_int_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_ren1_0 = io_from_int_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_ren2_0 = io_from_int_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_ren3_0 = io_from_int_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_swap12_0 = io_from_int_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_swap23_0 = io_from_int_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_fp_ctrl_typeTagIn_0 = io_from_int_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_fp_ctrl_typeTagOut_0 = io_from_int_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_fromint_0 = io_from_int_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_toint_0 = io_from_int_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_fastpipe_0 = io_from_int_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_fma_0 = io_from_int_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_div_0 = io_from_int_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_sqrt_0 = io_from_int_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_wflags_0 = io_from_int_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_ctrl_vec_0 = io_from_int_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:27:7]
wire [6:0] io_from_int_bits_uop_rob_idx_0 = io_from_int_bits_uop_rob_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_from_int_bits_uop_ldq_idx_0 = io_from_int_bits_uop_ldq_idx; // @[fp-pipeline.scala:27:7]
wire [4:0] io_from_int_bits_uop_stq_idx_0 = io_from_int_bits_uop_stq_idx; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_rxq_idx_0 = io_from_int_bits_uop_rxq_idx; // @[fp-pipeline.scala:27:7]
wire [6:0] io_from_int_bits_uop_pdst_0 = io_from_int_bits_uop_pdst; // @[fp-pipeline.scala:27:7]
wire [6:0] io_from_int_bits_uop_prs1_0 = io_from_int_bits_uop_prs1; // @[fp-pipeline.scala:27:7]
wire [6:0] io_from_int_bits_uop_prs2_0 = io_from_int_bits_uop_prs2; // @[fp-pipeline.scala:27:7]
wire [6:0] io_from_int_bits_uop_prs3_0 = io_from_int_bits_uop_prs3; // @[fp-pipeline.scala:27:7]
wire [4:0] io_from_int_bits_uop_ppred_0 = io_from_int_bits_uop_ppred; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_prs1_busy_0 = io_from_int_bits_uop_prs1_busy; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_prs2_busy_0 = io_from_int_bits_uop_prs2_busy; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_prs3_busy_0 = io_from_int_bits_uop_prs3_busy; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_ppred_busy_0 = io_from_int_bits_uop_ppred_busy; // @[fp-pipeline.scala:27:7]
wire [6:0] io_from_int_bits_uop_stale_pdst_0 = io_from_int_bits_uop_stale_pdst; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_exception_0 = io_from_int_bits_uop_exception; // @[fp-pipeline.scala:27:7]
wire [63:0] io_from_int_bits_uop_exc_cause_0 = io_from_int_bits_uop_exc_cause; // @[fp-pipeline.scala:27:7]
wire [4:0] io_from_int_bits_uop_mem_cmd_0 = io_from_int_bits_uop_mem_cmd; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_mem_size_0 = io_from_int_bits_uop_mem_size; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_mem_signed_0 = io_from_int_bits_uop_mem_signed; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_uses_ldq_0 = io_from_int_bits_uop_uses_ldq; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_uses_stq_0 = io_from_int_bits_uop_uses_stq; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_is_unique_0 = io_from_int_bits_uop_is_unique; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_flush_on_commit_0 = io_from_int_bits_uop_flush_on_commit; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_csr_cmd_0 = io_from_int_bits_uop_csr_cmd; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_ldst_is_rs1_0 = io_from_int_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_from_int_bits_uop_ldst_0 = io_from_int_bits_uop_ldst; // @[fp-pipeline.scala:27:7]
wire [5:0] io_from_int_bits_uop_lrs1_0 = io_from_int_bits_uop_lrs1; // @[fp-pipeline.scala:27:7]
wire [5:0] io_from_int_bits_uop_lrs2_0 = io_from_int_bits_uop_lrs2; // @[fp-pipeline.scala:27:7]
wire [5:0] io_from_int_bits_uop_lrs3_0 = io_from_int_bits_uop_lrs3; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_dst_rtype_0 = io_from_int_bits_uop_dst_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_lrs1_rtype_0 = io_from_int_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_lrs2_rtype_0 = io_from_int_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_frs3_en_0 = io_from_int_bits_uop_frs3_en; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fcn_dw_0 = io_from_int_bits_uop_fcn_dw; // @[fp-pipeline.scala:27:7]
wire [4:0] io_from_int_bits_uop_fcn_op_0 = io_from_int_bits_uop_fcn_op; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_fp_val_0 = io_from_int_bits_uop_fp_val; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_fp_rm_0 = io_from_int_bits_uop_fp_rm; // @[fp-pipeline.scala:27:7]
wire [1:0] io_from_int_bits_uop_fp_typ_0 = io_from_int_bits_uop_fp_typ; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_xcpt_pf_if_0 = io_from_int_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_xcpt_ae_if_0 = io_from_int_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_xcpt_ma_if_0 = io_from_int_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_bp_debug_if_0 = io_from_int_bits_uop_bp_debug_if; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_uop_bp_xcpt_if_0 = io_from_int_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_debug_fsrc_0 = io_from_int_bits_uop_debug_fsrc; // @[fp-pipeline.scala:27:7]
wire [2:0] io_from_int_bits_uop_debug_tsrc_0 = io_from_int_bits_uop_debug_tsrc; // @[fp-pipeline.scala:27:7]
wire [64:0] io_from_int_bits_data_0 = io_from_int_bits_data; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_predicated_0 = io_from_int_bits_predicated; // @[fp-pipeline.scala:27:7]
wire io_from_int_bits_fflags_valid_0 = io_from_int_bits_fflags_valid; // @[fp-pipeline.scala:27:7]
wire [4:0] io_from_int_bits_fflags_bits_0 = io_from_int_bits_fflags_bits; // @[fp-pipeline.scala:27:7]
wire io_to_int_ready_0 = io_to_int_ready; // @[fp-pipeline.scala:27:7]
wire [63:0] io_debug_tsc_reg_0 = io_debug_tsc_reg; // @[fp-pipeline.scala:27:7]
wire [31:0] io_status_isa = 32'h14112D; // @[fp-pipeline.scala:27:7]
wire [22:0] io_status_zero2 = 23'h0; // @[fp-pipeline.scala:27:7]
wire io_status_mbe = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_status_sbe = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_status_sd_rv32 = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_status_ube = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_status_upie = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_status_hie = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_status_uie = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_predicated = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_ll_wports_0_bits_fflags_valid = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_rebusy = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_bypassable = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_rebusy = 1'h0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_predicated = 1'h0; // @[fp-pipeline.scala:27:7]
wire fp_bypasses_0_bits_predicated = 1'h0; // @[fp-pipeline.scala:82:25]
wire fp_wakeups_0_bits_rebusy = 1'h0; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_bypassable = 1'h0; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_rebusy = 1'h0; // @[fp-pipeline.scala:83:24]
wire ll_wbarb_io_in_0_bits_out_predicated = 1'h0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_fflags_valid = 1'h0; // @[util.scala:109:23]
wire [7:0] io_status_zero1 = 8'h0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_status_xs = 2'h0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_status_vs = 2'h0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_bypassable = 1'h1; // @[fp-pipeline.scala:27:7]
wire fp_wakeups_0_bits_bypassable = 1'h1; // @[fp-pipeline.scala:83:24]
wire [2:0] io_wakeups_0_bits_speculative_mask = 3'h0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_speculative_mask = 3'h0; // @[fp-pipeline.scala:27:7]
wire [2:0] fp_wakeups_0_bits_speculative_mask = 3'h0; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_speculative_mask = 3'h0; // @[fp-pipeline.scala:83:24]
wire [4:0] io_ll_wports_0_bits_fflags_bits = 5'h0; // @[fp-pipeline.scala:27:7]
wire [4:0] ll_wbarb_io_in_0_bits_out_fflags_bits = 5'h0; // @[util.scala:109:23]
wire [1:0] io_status_sxl = 2'h2; // @[fp-pipeline.scala:27:7]
wire [1:0] io_status_uxl = 2'h2; // @[fp-pipeline.scala:27:7]
wire [31:0] ll_wbarb_io_in_0_bits_out_uop_inst = io_ll_wports_0_bits_uop_inst_0; // @[util.scala:109:23]
wire [31:0] ll_wbarb_io_in_0_bits_out_uop_debug_inst = io_ll_wports_0_bits_uop_debug_inst_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_rvc = io_ll_wports_0_bits_uop_is_rvc_0; // @[util.scala:109:23]
wire [39:0] ll_wbarb_io_in_0_bits_out_uop_debug_pc = io_ll_wports_0_bits_uop_debug_pc_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iq_type_0 = io_ll_wports_0_bits_uop_iq_type_0_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iq_type_1 = io_ll_wports_0_bits_uop_iq_type_1_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iq_type_2 = io_ll_wports_0_bits_uop_iq_type_2_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iq_type_3 = io_ll_wports_0_bits_uop_iq_type_3_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_0 = io_ll_wports_0_bits_uop_fu_code_0_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_1 = io_ll_wports_0_bits_uop_fu_code_1_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_2 = io_ll_wports_0_bits_uop_fu_code_2_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_3 = io_ll_wports_0_bits_uop_fu_code_3_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_4 = io_ll_wports_0_bits_uop_fu_code_4_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_5 = io_ll_wports_0_bits_uop_fu_code_5_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_6 = io_ll_wports_0_bits_uop_fu_code_6_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_7 = io_ll_wports_0_bits_uop_fu_code_7_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_8 = io_ll_wports_0_bits_uop_fu_code_8_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fu_code_9 = io_ll_wports_0_bits_uop_fu_code_9_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iw_issued = io_ll_wports_0_bits_uop_iw_issued_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iw_issued_partial_agen = io_ll_wports_0_bits_uop_iw_issued_partial_agen_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iw_issued_partial_dgen = io_ll_wports_0_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_iw_p1_speculative_child = io_ll_wports_0_bits_uop_iw_p1_speculative_child_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_iw_p2_speculative_child = io_ll_wports_0_bits_uop_iw_p2_speculative_child_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iw_p1_bypass_hint = io_ll_wports_0_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iw_p2_bypass_hint = io_ll_wports_0_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_iw_p3_bypass_hint = io_ll_wports_0_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_dis_col_sel = io_ll_wports_0_bits_uop_dis_col_sel_0; // @[util.scala:109:23]
wire [3:0] ll_wbarb_io_in_0_bits_out_uop_br_tag = io_ll_wports_0_bits_uop_br_tag_0; // @[util.scala:109:23]
wire [3:0] ll_wbarb_io_in_0_bits_out_uop_br_type = io_ll_wports_0_bits_uop_br_type_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_sfb = io_ll_wports_0_bits_uop_is_sfb_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_fence = io_ll_wports_0_bits_uop_is_fence_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_fencei = io_ll_wports_0_bits_uop_is_fencei_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_sfence = io_ll_wports_0_bits_uop_is_sfence_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_amo = io_ll_wports_0_bits_uop_is_amo_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_eret = io_ll_wports_0_bits_uop_is_eret_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_sys_pc2epc = io_ll_wports_0_bits_uop_is_sys_pc2epc_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_rocc = io_ll_wports_0_bits_uop_is_rocc_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_mov = io_ll_wports_0_bits_uop_is_mov_0; // @[util.scala:109:23]
wire [4:0] ll_wbarb_io_in_0_bits_out_uop_ftq_idx = io_ll_wports_0_bits_uop_ftq_idx_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_edge_inst = io_ll_wports_0_bits_uop_edge_inst_0; // @[util.scala:109:23]
wire [5:0] ll_wbarb_io_in_0_bits_out_uop_pc_lob = io_ll_wports_0_bits_uop_pc_lob_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_taken = io_ll_wports_0_bits_uop_taken_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_imm_rename = io_ll_wports_0_bits_uop_imm_rename_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_imm_sel = io_ll_wports_0_bits_uop_imm_sel_0; // @[util.scala:109:23]
wire [4:0] ll_wbarb_io_in_0_bits_out_uop_pimm = io_ll_wports_0_bits_uop_pimm_0; // @[util.scala:109:23]
wire [19:0] ll_wbarb_io_in_0_bits_out_uop_imm_packed = io_ll_wports_0_bits_uop_imm_packed_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_op1_sel = io_ll_wports_0_bits_uop_op1_sel_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_op2_sel = io_ll_wports_0_bits_uop_op2_sel_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_ldst = io_ll_wports_0_bits_uop_fp_ctrl_ldst_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_wen = io_ll_wports_0_bits_uop_fp_ctrl_wen_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_ren1 = io_ll_wports_0_bits_uop_fp_ctrl_ren1_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_ren2 = io_ll_wports_0_bits_uop_fp_ctrl_ren2_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_ren3 = io_ll_wports_0_bits_uop_fp_ctrl_ren3_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_swap12 = io_ll_wports_0_bits_uop_fp_ctrl_swap12_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_swap23 = io_ll_wports_0_bits_uop_fp_ctrl_swap23_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_typeTagIn = io_ll_wports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_typeTagOut = io_ll_wports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_fromint = io_ll_wports_0_bits_uop_fp_ctrl_fromint_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_toint = io_ll_wports_0_bits_uop_fp_ctrl_toint_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_fastpipe = io_ll_wports_0_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_fma = io_ll_wports_0_bits_uop_fp_ctrl_fma_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_div = io_ll_wports_0_bits_uop_fp_ctrl_div_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_sqrt = io_ll_wports_0_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_wflags = io_ll_wports_0_bits_uop_fp_ctrl_wflags_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_ctrl_vec = io_ll_wports_0_bits_uop_fp_ctrl_vec_0; // @[util.scala:109:23]
wire [6:0] ll_wbarb_io_in_0_bits_out_uop_rob_idx = io_ll_wports_0_bits_uop_rob_idx_0; // @[util.scala:109:23]
wire [4:0] ll_wbarb_io_in_0_bits_out_uop_ldq_idx = io_ll_wports_0_bits_uop_ldq_idx_0; // @[util.scala:109:23]
wire [4:0] ll_wbarb_io_in_0_bits_out_uop_stq_idx = io_ll_wports_0_bits_uop_stq_idx_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_rxq_idx = io_ll_wports_0_bits_uop_rxq_idx_0; // @[util.scala:109:23]
wire [6:0] ll_wbarb_io_in_0_bits_out_uop_pdst = io_ll_wports_0_bits_uop_pdst_0; // @[util.scala:109:23]
wire [6:0] ll_wbarb_io_in_0_bits_out_uop_prs1 = io_ll_wports_0_bits_uop_prs1_0; // @[util.scala:109:23]
wire [6:0] ll_wbarb_io_in_0_bits_out_uop_prs2 = io_ll_wports_0_bits_uop_prs2_0; // @[util.scala:109:23]
wire [6:0] ll_wbarb_io_in_0_bits_out_uop_prs3 = io_ll_wports_0_bits_uop_prs3_0; // @[util.scala:109:23]
wire [4:0] ll_wbarb_io_in_0_bits_out_uop_ppred = io_ll_wports_0_bits_uop_ppred_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_prs1_busy = io_ll_wports_0_bits_uop_prs1_busy_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_prs2_busy = io_ll_wports_0_bits_uop_prs2_busy_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_prs3_busy = io_ll_wports_0_bits_uop_prs3_busy_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_ppred_busy = io_ll_wports_0_bits_uop_ppred_busy_0; // @[util.scala:109:23]
wire [6:0] ll_wbarb_io_in_0_bits_out_uop_stale_pdst = io_ll_wports_0_bits_uop_stale_pdst_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_exception = io_ll_wports_0_bits_uop_exception_0; // @[util.scala:109:23]
wire [63:0] ll_wbarb_io_in_0_bits_out_uop_exc_cause = io_ll_wports_0_bits_uop_exc_cause_0; // @[util.scala:109:23]
wire [4:0] ll_wbarb_io_in_0_bits_out_uop_mem_cmd = io_ll_wports_0_bits_uop_mem_cmd_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_mem_size = io_ll_wports_0_bits_uop_mem_size_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_mem_signed = io_ll_wports_0_bits_uop_mem_signed_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_uses_ldq = io_ll_wports_0_bits_uop_uses_ldq_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_uses_stq = io_ll_wports_0_bits_uop_uses_stq_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_is_unique = io_ll_wports_0_bits_uop_is_unique_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_flush_on_commit = io_ll_wports_0_bits_uop_flush_on_commit_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_csr_cmd = io_ll_wports_0_bits_uop_csr_cmd_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_ldst_is_rs1 = io_ll_wports_0_bits_uop_ldst_is_rs1_0; // @[util.scala:109:23]
wire [5:0] ll_wbarb_io_in_0_bits_out_uop_ldst = io_ll_wports_0_bits_uop_ldst_0; // @[util.scala:109:23]
wire [5:0] ll_wbarb_io_in_0_bits_out_uop_lrs1 = io_ll_wports_0_bits_uop_lrs1_0; // @[util.scala:109:23]
wire [5:0] ll_wbarb_io_in_0_bits_out_uop_lrs2 = io_ll_wports_0_bits_uop_lrs2_0; // @[util.scala:109:23]
wire [5:0] ll_wbarb_io_in_0_bits_out_uop_lrs3 = io_ll_wports_0_bits_uop_lrs3_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_dst_rtype = io_ll_wports_0_bits_uop_dst_rtype_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_lrs1_rtype = io_ll_wports_0_bits_uop_lrs1_rtype_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_lrs2_rtype = io_ll_wports_0_bits_uop_lrs2_rtype_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_frs3_en = io_ll_wports_0_bits_uop_frs3_en_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fcn_dw = io_ll_wports_0_bits_uop_fcn_dw_0; // @[util.scala:109:23]
wire [4:0] ll_wbarb_io_in_0_bits_out_uop_fcn_op = io_ll_wports_0_bits_uop_fcn_op_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_fp_val = io_ll_wports_0_bits_uop_fp_val_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_fp_rm = io_ll_wports_0_bits_uop_fp_rm_0; // @[util.scala:109:23]
wire [1:0] ll_wbarb_io_in_0_bits_out_uop_fp_typ = io_ll_wports_0_bits_uop_fp_typ_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_xcpt_pf_if = io_ll_wports_0_bits_uop_xcpt_pf_if_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_xcpt_ae_if = io_ll_wports_0_bits_uop_xcpt_ae_if_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_xcpt_ma_if = io_ll_wports_0_bits_uop_xcpt_ma_if_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_bp_debug_if = io_ll_wports_0_bits_uop_bp_debug_if_0; // @[util.scala:109:23]
wire ll_wbarb_io_in_0_bits_out_uop_bp_xcpt_if = io_ll_wports_0_bits_uop_bp_xcpt_if_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_debug_fsrc = io_ll_wports_0_bits_uop_debug_fsrc_0; // @[util.scala:109:23]
wire [2:0] ll_wbarb_io_in_0_bits_out_uop_debug_tsrc = io_ll_wports_0_bits_uop_debug_tsrc_0; // @[util.scala:109:23]
wire [64:0] ll_wbarb_io_in_0_bits_out_data = io_ll_wports_0_bits_data_0; // @[util.scala:109:23]
wire fp_wakeups_0_valid; // @[fp-pipeline.scala:83:24]
wire [31:0] fp_wakeups_0_bits_uop_inst; // @[fp-pipeline.scala:83:24]
wire [31:0] fp_wakeups_0_bits_uop_debug_inst; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_rvc; // @[fp-pipeline.scala:83:24]
wire [39:0] fp_wakeups_0_bits_uop_debug_pc; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iq_type_0; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iq_type_1; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iq_type_2; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iq_type_3; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_0; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_1; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_2; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_3; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_4; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_5; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_6; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_7; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_8; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fu_code_9; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iw_issued; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_dis_col_sel; // @[fp-pipeline.scala:83:24]
wire [15:0] fp_wakeups_0_bits_uop_br_mask; // @[fp-pipeline.scala:83:24]
wire [3:0] fp_wakeups_0_bits_uop_br_tag; // @[fp-pipeline.scala:83:24]
wire [3:0] fp_wakeups_0_bits_uop_br_type; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_sfb; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_fence; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_fencei; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_sfence; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_amo; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_eret; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_rocc; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_mov; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_0_bits_uop_ftq_idx; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_edge_inst; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_0_bits_uop_pc_lob; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_taken; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_imm_rename; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_imm_sel; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_0_bits_uop_pimm; // @[fp-pipeline.scala:83:24]
wire [19:0] fp_wakeups_0_bits_uop_imm_packed; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_op1_sel; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_op2_sel; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_0_bits_uop_rob_idx; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_0_bits_uop_ldq_idx; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_0_bits_uop_stq_idx; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_rxq_idx; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_0_bits_uop_pdst; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_0_bits_uop_prs1; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_0_bits_uop_prs2; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_0_bits_uop_prs3; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_0_bits_uop_ppred; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_prs1_busy; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_prs2_busy; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_prs3_busy; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_ppred_busy; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_0_bits_uop_stale_pdst; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_exception; // @[fp-pipeline.scala:83:24]
wire [63:0] fp_wakeups_0_bits_uop_exc_cause; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_0_bits_uop_mem_cmd; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_mem_size; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_mem_signed; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_uses_ldq; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_uses_stq; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_is_unique; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_flush_on_commit; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_csr_cmd; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_0_bits_uop_ldst; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_0_bits_uop_lrs1; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_0_bits_uop_lrs2; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_0_bits_uop_lrs3; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_dst_rtype; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_frs3_en; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fcn_dw; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_0_bits_uop_fcn_op; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_fp_val; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_fp_rm; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_0_bits_uop_fp_typ; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_bp_debug_if; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_0_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_debug_fsrc; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_0_bits_uop_debug_tsrc; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_valid; // @[fp-pipeline.scala:83:24]
wire [31:0] fp_wakeups_1_bits_uop_inst; // @[fp-pipeline.scala:83:24]
wire [31:0] fp_wakeups_1_bits_uop_debug_inst; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_rvc; // @[fp-pipeline.scala:83:24]
wire [39:0] fp_wakeups_1_bits_uop_debug_pc; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iq_type_0; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iq_type_1; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iq_type_2; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iq_type_3; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_0; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_1; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_2; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_3; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_4; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_5; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_6; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_7; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_8; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fu_code_9; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iw_issued; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_dis_col_sel; // @[fp-pipeline.scala:83:24]
wire [15:0] fp_wakeups_1_bits_uop_br_mask; // @[fp-pipeline.scala:83:24]
wire [3:0] fp_wakeups_1_bits_uop_br_tag; // @[fp-pipeline.scala:83:24]
wire [3:0] fp_wakeups_1_bits_uop_br_type; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_sfb; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_fence; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_fencei; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_sfence; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_amo; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_eret; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_rocc; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_mov; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_1_bits_uop_ftq_idx; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_edge_inst; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_1_bits_uop_pc_lob; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_taken; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_imm_rename; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_imm_sel; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_1_bits_uop_pimm; // @[fp-pipeline.scala:83:24]
wire [19:0] fp_wakeups_1_bits_uop_imm_packed; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_op1_sel; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_op2_sel; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_1_bits_uop_rob_idx; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_1_bits_uop_ldq_idx; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_1_bits_uop_stq_idx; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_rxq_idx; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_1_bits_uop_pdst; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_1_bits_uop_prs1; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_1_bits_uop_prs2; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_1_bits_uop_prs3; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_1_bits_uop_ppred; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_prs1_busy; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_prs2_busy; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_prs3_busy; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_ppred_busy; // @[fp-pipeline.scala:83:24]
wire [6:0] fp_wakeups_1_bits_uop_stale_pdst; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_exception; // @[fp-pipeline.scala:83:24]
wire [63:0] fp_wakeups_1_bits_uop_exc_cause; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_1_bits_uop_mem_cmd; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_mem_size; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_mem_signed; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_uses_ldq; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_uses_stq; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_is_unique; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_flush_on_commit; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_csr_cmd; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_1_bits_uop_ldst; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_1_bits_uop_lrs1; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_1_bits_uop_lrs2; // @[fp-pipeline.scala:83:24]
wire [5:0] fp_wakeups_1_bits_uop_lrs3; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_dst_rtype; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_frs3_en; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fcn_dw; // @[fp-pipeline.scala:83:24]
wire [4:0] fp_wakeups_1_bits_uop_fcn_op; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_fp_val; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_fp_rm; // @[fp-pipeline.scala:83:24]
wire [1:0] fp_wakeups_1_bits_uop_fp_typ; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_bp_debug_if; // @[fp-pipeline.scala:83:24]
wire fp_wakeups_1_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_debug_fsrc; // @[fp-pipeline.scala:83:24]
wire [2:0] fp_wakeups_1_bits_uop_debug_tsrc; // @[fp-pipeline.scala:83:24]
wire io_dis_uops_0_ready_0; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_1_ready_0; // @[fp-pipeline.scala:27:7]
wire io_dis_uops_2_ready_0; // @[fp-pipeline.scala:27:7]
wire io_from_int_ready_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iq_type_0_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iq_type_1_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iq_type_2_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iq_type_3_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_0_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_1_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_2_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_3_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_4_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_5_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_6_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_7_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_8_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fu_code_9_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_ldst_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_wen_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_ren1_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_ren2_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_ren3_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_swap12_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_swap23_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_fp_ctrl_typeTagIn_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_fp_ctrl_typeTagOut_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_fromint_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_toint_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_fastpipe_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_fma_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_div_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_sqrt_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_wflags_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_ctrl_vec_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_dgen_bits_uop_inst_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_dgen_bits_uop_debug_inst_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_rvc_0; // @[fp-pipeline.scala:27:7]
wire [39:0] io_dgen_bits_uop_debug_pc_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iw_issued_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iw_issued_partial_agen_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iw_issued_partial_dgen_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_iw_p1_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_iw_p2_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iw_p1_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iw_p2_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_iw_p3_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_dis_col_sel_0; // @[fp-pipeline.scala:27:7]
wire [15:0] io_dgen_bits_uop_br_mask_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_dgen_bits_uop_br_tag_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_dgen_bits_uop_br_type_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_sfb_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_fence_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_fencei_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_sfence_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_amo_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_eret_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_sys_pc2epc_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_rocc_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_mov_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dgen_bits_uop_ftq_idx_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_edge_inst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dgen_bits_uop_pc_lob_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_taken_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_imm_rename_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_imm_sel_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dgen_bits_uop_pimm_0; // @[fp-pipeline.scala:27:7]
wire [19:0] io_dgen_bits_uop_imm_packed_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_op1_sel_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_op2_sel_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dgen_bits_uop_rob_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dgen_bits_uop_ldq_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dgen_bits_uop_stq_idx_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_rxq_idx_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dgen_bits_uop_pdst_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dgen_bits_uop_prs1_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dgen_bits_uop_prs2_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dgen_bits_uop_prs3_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dgen_bits_uop_ppred_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_prs1_busy_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_prs2_busy_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_prs3_busy_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_ppred_busy_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_dgen_bits_uop_stale_pdst_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_exception_0; // @[fp-pipeline.scala:27:7]
wire [63:0] io_dgen_bits_uop_exc_cause_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dgen_bits_uop_mem_cmd_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_mem_size_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_mem_signed_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_uses_ldq_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_uses_stq_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_is_unique_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_flush_on_commit_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_csr_cmd_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_ldst_is_rs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dgen_bits_uop_ldst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dgen_bits_uop_lrs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dgen_bits_uop_lrs2_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_dgen_bits_uop_lrs3_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_dst_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_lrs1_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_lrs2_rtype_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_frs3_en_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fcn_dw_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_dgen_bits_uop_fcn_op_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_fp_val_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_fp_rm_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_dgen_bits_uop_fp_typ_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_xcpt_pf_if_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_xcpt_ae_if_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_xcpt_ma_if_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_bp_debug_if_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_bits_uop_bp_xcpt_if_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_debug_fsrc_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_dgen_bits_uop_debug_tsrc_0; // @[fp-pipeline.scala:27:7]
wire [63:0] io_dgen_bits_data_0; // @[fp-pipeline.scala:27:7]
wire io_dgen_valid_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iq_type_0_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iq_type_1_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iq_type_2_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iq_type_3_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_0_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_1_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_2_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_3_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_4_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_5_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_6_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_7_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_8_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fu_code_9_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_ldst_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_wen_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_ren1_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_ren2_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_ren3_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_swap12_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_swap23_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_fp_ctrl_typeTagIn_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_fp_ctrl_typeTagOut_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_fromint_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_toint_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_fastpipe_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_fma_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_div_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_sqrt_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_wflags_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_ctrl_vec_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_to_int_bits_uop_inst_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_to_int_bits_uop_debug_inst_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_rvc_0; // @[fp-pipeline.scala:27:7]
wire [39:0] io_to_int_bits_uop_debug_pc_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iw_issued_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iw_issued_partial_agen_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iw_issued_partial_dgen_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_iw_p1_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_iw_p2_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iw_p1_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iw_p2_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_iw_p3_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_dis_col_sel_0; // @[fp-pipeline.scala:27:7]
wire [15:0] io_to_int_bits_uop_br_mask_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_to_int_bits_uop_br_tag_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_to_int_bits_uop_br_type_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_sfb_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_fence_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_fencei_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_sfence_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_amo_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_eret_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_sys_pc2epc_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_rocc_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_mov_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_to_int_bits_uop_ftq_idx_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_edge_inst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_to_int_bits_uop_pc_lob_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_taken_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_imm_rename_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_imm_sel_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_to_int_bits_uop_pimm_0; // @[fp-pipeline.scala:27:7]
wire [19:0] io_to_int_bits_uop_imm_packed_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_op1_sel_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_op2_sel_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_to_int_bits_uop_rob_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_to_int_bits_uop_ldq_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_to_int_bits_uop_stq_idx_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_rxq_idx_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_to_int_bits_uop_pdst_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_to_int_bits_uop_prs1_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_to_int_bits_uop_prs2_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_to_int_bits_uop_prs3_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_to_int_bits_uop_ppred_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_prs1_busy_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_prs2_busy_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_prs3_busy_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_ppred_busy_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_to_int_bits_uop_stale_pdst_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_exception_0; // @[fp-pipeline.scala:27:7]
wire [63:0] io_to_int_bits_uop_exc_cause_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_to_int_bits_uop_mem_cmd_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_mem_size_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_mem_signed_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_uses_ldq_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_uses_stq_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_is_unique_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_flush_on_commit_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_csr_cmd_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_ldst_is_rs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_to_int_bits_uop_ldst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_to_int_bits_uop_lrs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_to_int_bits_uop_lrs2_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_to_int_bits_uop_lrs3_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_dst_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_lrs1_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_lrs2_rtype_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_frs3_en_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fcn_dw_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_to_int_bits_uop_fcn_op_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_fp_val_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_fp_rm_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_to_int_bits_uop_fp_typ_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_xcpt_pf_if_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_xcpt_ae_if_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_xcpt_ma_if_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_bp_debug_if_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_uop_bp_xcpt_if_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_debug_fsrc_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_to_int_bits_uop_debug_tsrc_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_fflags_valid_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_to_int_bits_fflags_bits_0; // @[fp-pipeline.scala:27:7]
wire [63:0] io_to_int_bits_data_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_bits_predicated_0; // @[fp-pipeline.scala:27:7]
wire io_to_int_valid_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iq_type_0_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iq_type_1_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iq_type_2_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iq_type_3_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_0_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_1_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_2_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_3_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_4_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_5_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_6_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_7_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_8_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_9_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ldst_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_wen_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren1_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren2_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren3_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_swap12_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_swap23_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fromint_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_toint_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fma_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_div_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_wflags_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_vec_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_wakeups_0_bits_uop_inst_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_wakeups_0_bits_uop_debug_inst_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_rvc_0; // @[fp-pipeline.scala:27:7]
wire [39:0] io_wakeups_0_bits_uop_debug_pc_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iw_issued_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iw_issued_partial_agen_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_iw_p1_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_iw_p2_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_dis_col_sel_0; // @[fp-pipeline.scala:27:7]
wire [15:0] io_wakeups_0_bits_uop_br_mask_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_wakeups_0_bits_uop_br_tag_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_wakeups_0_bits_uop_br_type_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_sfb_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_fence_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_fencei_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_sfence_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_amo_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_eret_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_sys_pc2epc_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_rocc_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_mov_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_ftq_idx_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_edge_inst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_pc_lob_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_taken_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_imm_rename_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_imm_sel_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_pimm_0; // @[fp-pipeline.scala:27:7]
wire [19:0] io_wakeups_0_bits_uop_imm_packed_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_op1_sel_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_op2_sel_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_rob_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_ldq_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_stq_idx_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_pdst_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_prs1_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_prs2_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_prs3_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_ppred_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_prs1_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_prs2_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_prs3_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_ppred_busy_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_stale_pdst_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_exception_0; // @[fp-pipeline.scala:27:7]
wire [63:0] io_wakeups_0_bits_uop_exc_cause_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_mem_size_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_mem_signed_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_uses_ldq_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_uses_stq_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_is_unique_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_flush_on_commit_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_csr_cmd_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_ldst_is_rs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_ldst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_lrs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_lrs2_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_lrs3_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_frs3_en_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fcn_dw_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_fcn_op_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_fp_val_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_fp_rm_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_fp_typ_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_xcpt_pf_if_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_xcpt_ae_if_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_xcpt_ma_if_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_bp_debug_if_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_bits_uop_bp_xcpt_if_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_debug_fsrc_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_debug_tsrc_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_0_valid_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iq_type_0_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iq_type_1_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iq_type_2_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iq_type_3_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_0_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_1_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_2_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_3_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_4_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_5_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_6_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_7_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_8_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_9_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ldst_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_wen_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren1_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren2_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren3_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_swap12_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_swap23_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fromint_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_toint_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fma_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_div_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_sqrt_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_wflags_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_vec_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_wakeups_1_bits_uop_inst_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_wakeups_1_bits_uop_debug_inst_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_rvc_0; // @[fp-pipeline.scala:27:7]
wire [39:0] io_wakeups_1_bits_uop_debug_pc_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iw_issued_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iw_issued_partial_agen_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iw_issued_partial_dgen_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_iw_p1_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_iw_p2_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iw_p1_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iw_p2_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_iw_p3_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_dis_col_sel_0; // @[fp-pipeline.scala:27:7]
wire [15:0] io_wakeups_1_bits_uop_br_mask_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_wakeups_1_bits_uop_br_tag_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_wakeups_1_bits_uop_br_type_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_sfb_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_fence_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_fencei_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_sfence_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_amo_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_eret_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_sys_pc2epc_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_rocc_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_mov_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_ftq_idx_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_edge_inst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_pc_lob_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_taken_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_imm_rename_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_imm_sel_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_pimm_0; // @[fp-pipeline.scala:27:7]
wire [19:0] io_wakeups_1_bits_uop_imm_packed_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_op1_sel_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_op2_sel_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_rob_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_ldq_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_stq_idx_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_pdst_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_prs1_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_prs2_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_prs3_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_ppred_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_prs1_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_prs2_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_prs3_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_ppred_busy_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_stale_pdst_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_exception_0; // @[fp-pipeline.scala:27:7]
wire [63:0] io_wakeups_1_bits_uop_exc_cause_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_mem_size_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_mem_signed_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_uses_ldq_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_uses_stq_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_is_unique_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_flush_on_commit_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_csr_cmd_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_ldst_is_rs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_ldst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_lrs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_lrs2_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_lrs3_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_frs3_en_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fcn_dw_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_fcn_op_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_fp_val_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_fp_rm_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_fp_typ_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_xcpt_pf_if_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_xcpt_ae_if_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_xcpt_ma_if_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_bp_debug_if_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_bits_uop_bp_xcpt_if_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_debug_fsrc_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_debug_tsrc_0; // @[fp-pipeline.scala:27:7]
wire io_wakeups_1_valid_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iq_type_0_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iq_type_1_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iq_type_2_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iq_type_3_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_0_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_1_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_2_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_3_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_4_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_5_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_6_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_7_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_8_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fu_code_9_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_ldst_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_wen_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_ren1_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_ren2_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_ren3_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_swap12_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_swap23_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_fp_ctrl_typeTagIn_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_fp_ctrl_typeTagOut_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_fromint_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_toint_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_fastpipe_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_fma_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_div_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_sqrt_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_wflags_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_ctrl_vec_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_wb_0_bits_uop_inst_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_wb_0_bits_uop_debug_inst_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_rvc_0; // @[fp-pipeline.scala:27:7]
wire [39:0] io_wb_0_bits_uop_debug_pc_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iw_issued_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iw_issued_partial_agen_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iw_issued_partial_dgen_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_iw_p1_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_iw_p2_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iw_p1_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iw_p2_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_iw_p3_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_dis_col_sel_0; // @[fp-pipeline.scala:27:7]
wire [15:0] io_wb_0_bits_uop_br_mask_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_wb_0_bits_uop_br_tag_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_wb_0_bits_uop_br_type_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_sfb_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_fence_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_fencei_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_sfence_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_amo_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_eret_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_sys_pc2epc_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_rocc_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_mov_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_0_bits_uop_ftq_idx_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_edge_inst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_0_bits_uop_pc_lob_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_taken_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_imm_rename_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_imm_sel_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_0_bits_uop_pimm_0; // @[fp-pipeline.scala:27:7]
wire [19:0] io_wb_0_bits_uop_imm_packed_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_op1_sel_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_op2_sel_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_0_bits_uop_rob_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_0_bits_uop_ldq_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_0_bits_uop_stq_idx_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_rxq_idx_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_0_bits_uop_pdst_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_0_bits_uop_prs1_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_0_bits_uop_prs2_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_0_bits_uop_prs3_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_0_bits_uop_ppred_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_prs1_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_prs2_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_prs3_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_ppred_busy_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_0_bits_uop_stale_pdst_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_exception_0; // @[fp-pipeline.scala:27:7]
wire [63:0] io_wb_0_bits_uop_exc_cause_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_0_bits_uop_mem_cmd_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_mem_size_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_mem_signed_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_uses_ldq_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_uses_stq_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_is_unique_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_flush_on_commit_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_csr_cmd_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_ldst_is_rs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_0_bits_uop_ldst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_0_bits_uop_lrs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_0_bits_uop_lrs2_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_0_bits_uop_lrs3_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_dst_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_lrs1_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_lrs2_rtype_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_frs3_en_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fcn_dw_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_0_bits_uop_fcn_op_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_fp_val_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_fp_rm_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_0_bits_uop_fp_typ_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_xcpt_pf_if_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_xcpt_ae_if_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_xcpt_ma_if_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_bp_debug_if_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_uop_bp_xcpt_if_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_debug_fsrc_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_0_bits_uop_debug_tsrc_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_bits_fflags_valid_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_0_bits_fflags_bits_0; // @[fp-pipeline.scala:27:7]
wire [64:0] io_wb_0_bits_data_0; // @[fp-pipeline.scala:27:7]
wire io_wb_0_valid_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iq_type_0_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iq_type_1_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iq_type_2_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iq_type_3_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_0_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_1_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_2_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_3_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_4_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_5_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_6_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_7_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_8_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fu_code_9_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_ldst_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_wen_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_ren1_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_ren2_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_ren3_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_swap12_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_swap23_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_fp_ctrl_typeTagIn_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_fp_ctrl_typeTagOut_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_fromint_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_toint_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_fastpipe_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_fma_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_div_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_sqrt_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_wflags_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_ctrl_vec_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_wb_1_bits_uop_inst_0; // @[fp-pipeline.scala:27:7]
wire [31:0] io_wb_1_bits_uop_debug_inst_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_rvc_0; // @[fp-pipeline.scala:27:7]
wire [39:0] io_wb_1_bits_uop_debug_pc_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iw_issued_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iw_issued_partial_agen_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iw_issued_partial_dgen_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_iw_p1_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_iw_p2_speculative_child_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iw_p1_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iw_p2_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_iw_p3_bypass_hint_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_dis_col_sel_0; // @[fp-pipeline.scala:27:7]
wire [15:0] io_wb_1_bits_uop_br_mask_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_wb_1_bits_uop_br_tag_0; // @[fp-pipeline.scala:27:7]
wire [3:0] io_wb_1_bits_uop_br_type_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_sfb_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_fence_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_fencei_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_sfence_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_amo_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_eret_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_sys_pc2epc_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_rocc_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_mov_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_1_bits_uop_ftq_idx_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_edge_inst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_1_bits_uop_pc_lob_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_taken_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_imm_rename_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_imm_sel_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_1_bits_uop_pimm_0; // @[fp-pipeline.scala:27:7]
wire [19:0] io_wb_1_bits_uop_imm_packed_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_op1_sel_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_op2_sel_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_1_bits_uop_rob_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_1_bits_uop_ldq_idx_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_1_bits_uop_stq_idx_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_rxq_idx_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_1_bits_uop_pdst_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_1_bits_uop_prs1_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_1_bits_uop_prs2_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_1_bits_uop_prs3_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_1_bits_uop_ppred_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_prs1_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_prs2_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_prs3_busy_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_ppred_busy_0; // @[fp-pipeline.scala:27:7]
wire [6:0] io_wb_1_bits_uop_stale_pdst_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_exception_0; // @[fp-pipeline.scala:27:7]
wire [63:0] io_wb_1_bits_uop_exc_cause_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_1_bits_uop_mem_cmd_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_mem_size_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_mem_signed_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_uses_ldq_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_uses_stq_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_is_unique_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_flush_on_commit_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_csr_cmd_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_ldst_is_rs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_1_bits_uop_ldst_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_1_bits_uop_lrs1_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_1_bits_uop_lrs2_0; // @[fp-pipeline.scala:27:7]
wire [5:0] io_wb_1_bits_uop_lrs3_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_dst_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_lrs1_rtype_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_lrs2_rtype_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_frs3_en_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fcn_dw_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_1_bits_uop_fcn_op_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_fp_val_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_fp_rm_0; // @[fp-pipeline.scala:27:7]
wire [1:0] io_wb_1_bits_uop_fp_typ_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_xcpt_pf_if_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_xcpt_ae_if_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_xcpt_ma_if_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_bp_debug_if_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_uop_bp_xcpt_if_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_debug_fsrc_0; // @[fp-pipeline.scala:27:7]
wire [2:0] io_wb_1_bits_uop_debug_tsrc_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_fflags_valid_0; // @[fp-pipeline.scala:27:7]
wire [4:0] io_wb_1_bits_fflags_bits_0; // @[fp-pipeline.scala:27:7]
wire [64:0] io_wb_1_bits_data_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_bits_predicated_0; // @[fp-pipeline.scala:27:7]
wire io_wb_1_valid_0; // @[fp-pipeline.scala:27:7]
wire _fp_bypasses_0_valid_T_1; // @[fp-pipeline.scala:211:60]
wire fp_bypasses_0_bits_uop_iq_type_0; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iq_type_1; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iq_type_2; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iq_type_3; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_0; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_1; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_2; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_3; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_4; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_5; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_6; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_7; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_8; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fu_code_9; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:82:25]
wire [31:0] fp_bypasses_0_bits_uop_inst; // @[fp-pipeline.scala:82:25]
wire [31:0] fp_bypasses_0_bits_uop_debug_inst; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_rvc; // @[fp-pipeline.scala:82:25]
wire [39:0] fp_bypasses_0_bits_uop_debug_pc; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iw_issued; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_dis_col_sel; // @[fp-pipeline.scala:82:25]
wire [15:0] fp_bypasses_0_bits_uop_br_mask; // @[fp-pipeline.scala:82:25]
wire [3:0] fp_bypasses_0_bits_uop_br_tag; // @[fp-pipeline.scala:82:25]
wire [3:0] fp_bypasses_0_bits_uop_br_type; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_sfb; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_fence; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_fencei; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_sfence; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_amo; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_eret; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_rocc; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_mov; // @[fp-pipeline.scala:82:25]
wire [4:0] fp_bypasses_0_bits_uop_ftq_idx; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_edge_inst; // @[fp-pipeline.scala:82:25]
wire [5:0] fp_bypasses_0_bits_uop_pc_lob; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_taken; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_imm_rename; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_imm_sel; // @[fp-pipeline.scala:82:25]
wire [4:0] fp_bypasses_0_bits_uop_pimm; // @[fp-pipeline.scala:82:25]
wire [19:0] fp_bypasses_0_bits_uop_imm_packed; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_op1_sel; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_op2_sel; // @[fp-pipeline.scala:82:25]
wire [6:0] fp_bypasses_0_bits_uop_rob_idx; // @[fp-pipeline.scala:82:25]
wire [4:0] fp_bypasses_0_bits_uop_ldq_idx; // @[fp-pipeline.scala:82:25]
wire [4:0] fp_bypasses_0_bits_uop_stq_idx; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_rxq_idx; // @[fp-pipeline.scala:82:25]
wire [6:0] fp_bypasses_0_bits_uop_pdst; // @[fp-pipeline.scala:82:25]
wire [6:0] fp_bypasses_0_bits_uop_prs1; // @[fp-pipeline.scala:82:25]
wire [6:0] fp_bypasses_0_bits_uop_prs2; // @[fp-pipeline.scala:82:25]
wire [6:0] fp_bypasses_0_bits_uop_prs3; // @[fp-pipeline.scala:82:25]
wire [4:0] fp_bypasses_0_bits_uop_ppred; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_prs1_busy; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_prs2_busy; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_prs3_busy; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_ppred_busy; // @[fp-pipeline.scala:82:25]
wire [6:0] fp_bypasses_0_bits_uop_stale_pdst; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_exception; // @[fp-pipeline.scala:82:25]
wire [63:0] fp_bypasses_0_bits_uop_exc_cause; // @[fp-pipeline.scala:82:25]
wire [4:0] fp_bypasses_0_bits_uop_mem_cmd; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_mem_size; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_mem_signed; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_uses_ldq; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_uses_stq; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_is_unique; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_flush_on_commit; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_csr_cmd; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:82:25]
wire [5:0] fp_bypasses_0_bits_uop_ldst; // @[fp-pipeline.scala:82:25]
wire [5:0] fp_bypasses_0_bits_uop_lrs1; // @[fp-pipeline.scala:82:25]
wire [5:0] fp_bypasses_0_bits_uop_lrs2; // @[fp-pipeline.scala:82:25]
wire [5:0] fp_bypasses_0_bits_uop_lrs3; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_dst_rtype; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_frs3_en; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fcn_dw; // @[fp-pipeline.scala:82:25]
wire [4:0] fp_bypasses_0_bits_uop_fcn_op; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_fp_val; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_fp_rm; // @[fp-pipeline.scala:82:25]
wire [1:0] fp_bypasses_0_bits_uop_fp_typ; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_bp_debug_if; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_debug_fsrc; // @[fp-pipeline.scala:82:25]
wire [2:0] fp_bypasses_0_bits_uop_debug_tsrc; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_bits_fflags_valid; // @[fp-pipeline.scala:82:25]
wire [4:0] fp_bypasses_0_bits_fflags_bits; // @[fp-pipeline.scala:82:25]
wire [64:0] fp_bypasses_0_bits_data; // @[fp-pipeline.scala:82:25]
wire fp_bypasses_0_valid; // @[fp-pipeline.scala:82:25]
assign io_wakeups_0_valid_0 = fp_wakeups_0_valid; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_inst_0 = fp_wakeups_0_bits_uop_inst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_debug_inst_0 = fp_wakeups_0_bits_uop_debug_inst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_rvc_0 = fp_wakeups_0_bits_uop_is_rvc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_debug_pc_0 = fp_wakeups_0_bits_uop_debug_pc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iq_type_0_0 = fp_wakeups_0_bits_uop_iq_type_0; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iq_type_1_0 = fp_wakeups_0_bits_uop_iq_type_1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iq_type_2_0 = fp_wakeups_0_bits_uop_iq_type_2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iq_type_3_0 = fp_wakeups_0_bits_uop_iq_type_3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_0_0 = fp_wakeups_0_bits_uop_fu_code_0; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_1_0 = fp_wakeups_0_bits_uop_fu_code_1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_2_0 = fp_wakeups_0_bits_uop_fu_code_2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_3_0 = fp_wakeups_0_bits_uop_fu_code_3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_4_0 = fp_wakeups_0_bits_uop_fu_code_4; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_5_0 = fp_wakeups_0_bits_uop_fu_code_5; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_6_0 = fp_wakeups_0_bits_uop_fu_code_6; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_7_0 = fp_wakeups_0_bits_uop_fu_code_7; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_8_0 = fp_wakeups_0_bits_uop_fu_code_8; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fu_code_9_0 = fp_wakeups_0_bits_uop_fu_code_9; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iw_issued_0 = fp_wakeups_0_bits_uop_iw_issued; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iw_issued_partial_agen_0 = fp_wakeups_0_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iw_issued_partial_dgen_0 = fp_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iw_p1_speculative_child_0 = fp_wakeups_0_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iw_p2_speculative_child_0 = fp_wakeups_0_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iw_p1_bypass_hint_0 = fp_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iw_p2_bypass_hint_0 = fp_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_iw_p3_bypass_hint_0 = fp_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_dis_col_sel_0 = fp_wakeups_0_bits_uop_dis_col_sel; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_br_mask_0 = fp_wakeups_0_bits_uop_br_mask; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_br_tag_0 = fp_wakeups_0_bits_uop_br_tag; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_br_type_0 = fp_wakeups_0_bits_uop_br_type; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_sfb_0 = fp_wakeups_0_bits_uop_is_sfb; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_fence_0 = fp_wakeups_0_bits_uop_is_fence; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_fencei_0 = fp_wakeups_0_bits_uop_is_fencei; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_sfence_0 = fp_wakeups_0_bits_uop_is_sfence; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_amo_0 = fp_wakeups_0_bits_uop_is_amo; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_eret_0 = fp_wakeups_0_bits_uop_is_eret; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_sys_pc2epc_0 = fp_wakeups_0_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_rocc_0 = fp_wakeups_0_bits_uop_is_rocc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_mov_0 = fp_wakeups_0_bits_uop_is_mov; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_ftq_idx_0 = fp_wakeups_0_bits_uop_ftq_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_edge_inst_0 = fp_wakeups_0_bits_uop_edge_inst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_pc_lob_0 = fp_wakeups_0_bits_uop_pc_lob; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_taken_0 = fp_wakeups_0_bits_uop_taken; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_imm_rename_0 = fp_wakeups_0_bits_uop_imm_rename; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_imm_sel_0 = fp_wakeups_0_bits_uop_imm_sel; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_pimm_0 = fp_wakeups_0_bits_uop_pimm; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_imm_packed_0 = fp_wakeups_0_bits_uop_imm_packed; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_op1_sel_0 = fp_wakeups_0_bits_uop_op1_sel; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_op2_sel_0 = fp_wakeups_0_bits_uop_op2_sel; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_ldst_0 = fp_wakeups_0_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_wen_0 = fp_wakeups_0_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_ren1_0 = fp_wakeups_0_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_ren2_0 = fp_wakeups_0_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_ren3_0 = fp_wakeups_0_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_swap12_0 = fp_wakeups_0_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_swap23_0 = fp_wakeups_0_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = fp_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = fp_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_fromint_0 = fp_wakeups_0_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_toint_0 = fp_wakeups_0_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0 = fp_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_fma_0 = fp_wakeups_0_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_div_0 = fp_wakeups_0_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_sqrt_0 = fp_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_wflags_0 = fp_wakeups_0_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_ctrl_vec_0 = fp_wakeups_0_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_rob_idx_0 = fp_wakeups_0_bits_uop_rob_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_ldq_idx_0 = fp_wakeups_0_bits_uop_ldq_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_stq_idx_0 = fp_wakeups_0_bits_uop_stq_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_rxq_idx_0 = fp_wakeups_0_bits_uop_rxq_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_pdst_0 = fp_wakeups_0_bits_uop_pdst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_prs1_0 = fp_wakeups_0_bits_uop_prs1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_prs2_0 = fp_wakeups_0_bits_uop_prs2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_prs3_0 = fp_wakeups_0_bits_uop_prs3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_ppred_0 = fp_wakeups_0_bits_uop_ppred; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_prs1_busy_0 = fp_wakeups_0_bits_uop_prs1_busy; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_prs2_busy_0 = fp_wakeups_0_bits_uop_prs2_busy; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_prs3_busy_0 = fp_wakeups_0_bits_uop_prs3_busy; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_ppred_busy_0 = fp_wakeups_0_bits_uop_ppred_busy; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_stale_pdst_0 = fp_wakeups_0_bits_uop_stale_pdst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_exception_0 = fp_wakeups_0_bits_uop_exception; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_exc_cause_0 = fp_wakeups_0_bits_uop_exc_cause; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_mem_cmd_0 = fp_wakeups_0_bits_uop_mem_cmd; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_mem_size_0 = fp_wakeups_0_bits_uop_mem_size; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_mem_signed_0 = fp_wakeups_0_bits_uop_mem_signed; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_uses_ldq_0 = fp_wakeups_0_bits_uop_uses_ldq; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_uses_stq_0 = fp_wakeups_0_bits_uop_uses_stq; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_is_unique_0 = fp_wakeups_0_bits_uop_is_unique; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_flush_on_commit_0 = fp_wakeups_0_bits_uop_flush_on_commit; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_csr_cmd_0 = fp_wakeups_0_bits_uop_csr_cmd; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_ldst_is_rs1_0 = fp_wakeups_0_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_ldst_0 = fp_wakeups_0_bits_uop_ldst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_lrs1_0 = fp_wakeups_0_bits_uop_lrs1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_lrs2_0 = fp_wakeups_0_bits_uop_lrs2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_lrs3_0 = fp_wakeups_0_bits_uop_lrs3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_dst_rtype_0 = fp_wakeups_0_bits_uop_dst_rtype; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_lrs1_rtype_0 = fp_wakeups_0_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_lrs2_rtype_0 = fp_wakeups_0_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_frs3_en_0 = fp_wakeups_0_bits_uop_frs3_en; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fcn_dw_0 = fp_wakeups_0_bits_uop_fcn_dw; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fcn_op_0 = fp_wakeups_0_bits_uop_fcn_op; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_val_0 = fp_wakeups_0_bits_uop_fp_val; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_rm_0 = fp_wakeups_0_bits_uop_fp_rm; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_fp_typ_0 = fp_wakeups_0_bits_uop_fp_typ; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_xcpt_pf_if_0 = fp_wakeups_0_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_xcpt_ae_if_0 = fp_wakeups_0_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_xcpt_ma_if_0 = fp_wakeups_0_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_bp_debug_if_0 = fp_wakeups_0_bits_uop_bp_debug_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_bp_xcpt_if_0 = fp_wakeups_0_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_debug_fsrc_0 = fp_wakeups_0_bits_uop_debug_fsrc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_0_bits_uop_debug_tsrc_0 = fp_wakeups_0_bits_uop_debug_tsrc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_valid_0 = fp_wakeups_1_valid; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_inst_0 = fp_wakeups_1_bits_uop_inst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_debug_inst_0 = fp_wakeups_1_bits_uop_debug_inst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_rvc_0 = fp_wakeups_1_bits_uop_is_rvc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_debug_pc_0 = fp_wakeups_1_bits_uop_debug_pc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iq_type_0_0 = fp_wakeups_1_bits_uop_iq_type_0; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iq_type_1_0 = fp_wakeups_1_bits_uop_iq_type_1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iq_type_2_0 = fp_wakeups_1_bits_uop_iq_type_2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iq_type_3_0 = fp_wakeups_1_bits_uop_iq_type_3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_0_0 = fp_wakeups_1_bits_uop_fu_code_0; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_1_0 = fp_wakeups_1_bits_uop_fu_code_1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_2_0 = fp_wakeups_1_bits_uop_fu_code_2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_3_0 = fp_wakeups_1_bits_uop_fu_code_3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_4_0 = fp_wakeups_1_bits_uop_fu_code_4; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_5_0 = fp_wakeups_1_bits_uop_fu_code_5; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_6_0 = fp_wakeups_1_bits_uop_fu_code_6; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_7_0 = fp_wakeups_1_bits_uop_fu_code_7; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_8_0 = fp_wakeups_1_bits_uop_fu_code_8; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fu_code_9_0 = fp_wakeups_1_bits_uop_fu_code_9; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iw_issued_0 = fp_wakeups_1_bits_uop_iw_issued; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iw_issued_partial_agen_0 = fp_wakeups_1_bits_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iw_issued_partial_dgen_0 = fp_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iw_p1_speculative_child_0 = fp_wakeups_1_bits_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iw_p2_speculative_child_0 = fp_wakeups_1_bits_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iw_p1_bypass_hint_0 = fp_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iw_p2_bypass_hint_0 = fp_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_iw_p3_bypass_hint_0 = fp_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_dis_col_sel_0 = fp_wakeups_1_bits_uop_dis_col_sel; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_br_mask_0 = fp_wakeups_1_bits_uop_br_mask; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_br_tag_0 = fp_wakeups_1_bits_uop_br_tag; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_br_type_0 = fp_wakeups_1_bits_uop_br_type; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_sfb_0 = fp_wakeups_1_bits_uop_is_sfb; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_fence_0 = fp_wakeups_1_bits_uop_is_fence; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_fencei_0 = fp_wakeups_1_bits_uop_is_fencei; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_sfence_0 = fp_wakeups_1_bits_uop_is_sfence; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_amo_0 = fp_wakeups_1_bits_uop_is_amo; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_eret_0 = fp_wakeups_1_bits_uop_is_eret; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_sys_pc2epc_0 = fp_wakeups_1_bits_uop_is_sys_pc2epc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_rocc_0 = fp_wakeups_1_bits_uop_is_rocc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_mov_0 = fp_wakeups_1_bits_uop_is_mov; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_ftq_idx_0 = fp_wakeups_1_bits_uop_ftq_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_edge_inst_0 = fp_wakeups_1_bits_uop_edge_inst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_pc_lob_0 = fp_wakeups_1_bits_uop_pc_lob; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_taken_0 = fp_wakeups_1_bits_uop_taken; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_imm_rename_0 = fp_wakeups_1_bits_uop_imm_rename; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_imm_sel_0 = fp_wakeups_1_bits_uop_imm_sel; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_pimm_0 = fp_wakeups_1_bits_uop_pimm; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_imm_packed_0 = fp_wakeups_1_bits_uop_imm_packed; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_op1_sel_0 = fp_wakeups_1_bits_uop_op1_sel; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_op2_sel_0 = fp_wakeups_1_bits_uop_op2_sel; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_ldst_0 = fp_wakeups_1_bits_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_wen_0 = fp_wakeups_1_bits_uop_fp_ctrl_wen; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_ren1_0 = fp_wakeups_1_bits_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_ren2_0 = fp_wakeups_1_bits_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_ren3_0 = fp_wakeups_1_bits_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_swap12_0 = fp_wakeups_1_bits_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_swap23_0 = fp_wakeups_1_bits_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0 = fp_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0 = fp_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_fromint_0 = fp_wakeups_1_bits_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_toint_0 = fp_wakeups_1_bits_uop_fp_ctrl_toint; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0 = fp_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_fma_0 = fp_wakeups_1_bits_uop_fp_ctrl_fma; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_div_0 = fp_wakeups_1_bits_uop_fp_ctrl_div; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_sqrt_0 = fp_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_wflags_0 = fp_wakeups_1_bits_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_ctrl_vec_0 = fp_wakeups_1_bits_uop_fp_ctrl_vec; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_rob_idx_0 = fp_wakeups_1_bits_uop_rob_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_ldq_idx_0 = fp_wakeups_1_bits_uop_ldq_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_stq_idx_0 = fp_wakeups_1_bits_uop_stq_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_rxq_idx_0 = fp_wakeups_1_bits_uop_rxq_idx; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_pdst_0 = fp_wakeups_1_bits_uop_pdst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_prs1_0 = fp_wakeups_1_bits_uop_prs1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_prs2_0 = fp_wakeups_1_bits_uop_prs2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_prs3_0 = fp_wakeups_1_bits_uop_prs3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_ppred_0 = fp_wakeups_1_bits_uop_ppred; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_prs1_busy_0 = fp_wakeups_1_bits_uop_prs1_busy; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_prs2_busy_0 = fp_wakeups_1_bits_uop_prs2_busy; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_prs3_busy_0 = fp_wakeups_1_bits_uop_prs3_busy; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_ppred_busy_0 = fp_wakeups_1_bits_uop_ppred_busy; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_stale_pdst_0 = fp_wakeups_1_bits_uop_stale_pdst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_exception_0 = fp_wakeups_1_bits_uop_exception; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_exc_cause_0 = fp_wakeups_1_bits_uop_exc_cause; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_mem_cmd_0 = fp_wakeups_1_bits_uop_mem_cmd; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_mem_size_0 = fp_wakeups_1_bits_uop_mem_size; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_mem_signed_0 = fp_wakeups_1_bits_uop_mem_signed; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_uses_ldq_0 = fp_wakeups_1_bits_uop_uses_ldq; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_uses_stq_0 = fp_wakeups_1_bits_uop_uses_stq; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_is_unique_0 = fp_wakeups_1_bits_uop_is_unique; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_flush_on_commit_0 = fp_wakeups_1_bits_uop_flush_on_commit; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_csr_cmd_0 = fp_wakeups_1_bits_uop_csr_cmd; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_ldst_is_rs1_0 = fp_wakeups_1_bits_uop_ldst_is_rs1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_ldst_0 = fp_wakeups_1_bits_uop_ldst; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_lrs1_0 = fp_wakeups_1_bits_uop_lrs1; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_lrs2_0 = fp_wakeups_1_bits_uop_lrs2; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_lrs3_0 = fp_wakeups_1_bits_uop_lrs3; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_dst_rtype_0 = fp_wakeups_1_bits_uop_dst_rtype; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_lrs1_rtype_0 = fp_wakeups_1_bits_uop_lrs1_rtype; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_lrs2_rtype_0 = fp_wakeups_1_bits_uop_lrs2_rtype; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_frs3_en_0 = fp_wakeups_1_bits_uop_frs3_en; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fcn_dw_0 = fp_wakeups_1_bits_uop_fcn_dw; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fcn_op_0 = fp_wakeups_1_bits_uop_fcn_op; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_val_0 = fp_wakeups_1_bits_uop_fp_val; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_rm_0 = fp_wakeups_1_bits_uop_fp_rm; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_fp_typ_0 = fp_wakeups_1_bits_uop_fp_typ; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_xcpt_pf_if_0 = fp_wakeups_1_bits_uop_xcpt_pf_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_xcpt_ae_if_0 = fp_wakeups_1_bits_uop_xcpt_ae_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_xcpt_ma_if_0 = fp_wakeups_1_bits_uop_xcpt_ma_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_bp_debug_if_0 = fp_wakeups_1_bits_uop_bp_debug_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_bp_xcpt_if_0 = fp_wakeups_1_bits_uop_bp_xcpt_if; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_debug_fsrc_0 = fp_wakeups_1_bits_uop_debug_fsrc; // @[fp-pipeline.scala:27:7, :83:24]
assign io_wakeups_1_bits_uop_debug_tsrc_0 = fp_wakeups_1_bits_uop_debug_tsrc; // @[fp-pipeline.scala:27:7, :83:24]
wire [15:0] _ll_wbarb_io_in_0_valid_T = io_brupdate_b1_mispredict_mask_0 & io_ll_wports_0_bits_uop_br_mask_0; // @[util.scala:126:51]
wire _ll_wbarb_io_in_0_valid_T_1 = |_ll_wbarb_io_in_0_valid_T; // @[util.scala:126:{51,59}]
wire _ll_wbarb_io_in_0_valid_T_2 = _ll_wbarb_io_in_0_valid_T_1 | io_flush_pipeline_0; // @[util.scala:61:61, :126:59]
wire _ll_wbarb_io_in_0_valid_T_3 = ~_ll_wbarb_io_in_0_valid_T_2; // @[util.scala:61:61]
wire _ll_wbarb_io_in_0_valid_T_4 = io_ll_wports_0_valid_0 & _ll_wbarb_io_in_0_valid_T_3; // @[fp-pipeline.scala:27:7, :174:60, :175:5]
reg ll_wbarb_io_in_0_valid_REG; // @[fp-pipeline.scala:174:37]
wire [15:0] _ll_wbarb_io_in_0_bits_out_uop_br_mask_T_1; // @[util.scala:97:21]
wire [15:0] ll_wbarb_io_in_0_bits_out_uop_br_mask; // @[util.scala:109:23]
wire [15:0] _ll_wbarb_io_in_0_bits_out_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23]
assign _ll_wbarb_io_in_0_bits_out_uop_br_mask_T_1 = io_ll_wports_0_bits_uop_br_mask_0 & _ll_wbarb_io_in_0_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}]
assign ll_wbarb_io_in_0_bits_out_uop_br_mask = _ll_wbarb_io_in_0_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23]
reg [31:0] ll_wbarb_io_in_0_bits_REG_uop_inst; // @[fp-pipeline.scala:176:37]
reg [31:0] ll_wbarb_io_in_0_bits_REG_uop_debug_inst; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_rvc; // @[fp-pipeline.scala:176:37]
reg [39:0] ll_wbarb_io_in_0_bits_REG_uop_debug_pc; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iq_type_0; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iq_type_1; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iq_type_2; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iq_type_3; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_0; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_1; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_2; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_3; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_4; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_5; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_6; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_7; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_8; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fu_code_9; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iw_issued; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iw_issued_partial_agen; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iw_issued_partial_dgen; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_iw_p1_speculative_child; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_iw_p2_speculative_child; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iw_p1_bypass_hint; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iw_p2_bypass_hint; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_iw_p3_bypass_hint; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_dis_col_sel; // @[fp-pipeline.scala:176:37]
reg [15:0] ll_wbarb_io_in_0_bits_REG_uop_br_mask; // @[fp-pipeline.scala:176:37]
reg [3:0] ll_wbarb_io_in_0_bits_REG_uop_br_tag; // @[fp-pipeline.scala:176:37]
reg [3:0] ll_wbarb_io_in_0_bits_REG_uop_br_type; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_sfb; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_fence; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_fencei; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_sfence; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_amo; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_eret; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_sys_pc2epc; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_rocc; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_mov; // @[fp-pipeline.scala:176:37]
reg [4:0] ll_wbarb_io_in_0_bits_REG_uop_ftq_idx; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_edge_inst; // @[fp-pipeline.scala:176:37]
reg [5:0] ll_wbarb_io_in_0_bits_REG_uop_pc_lob; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_taken; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_imm_rename; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_imm_sel; // @[fp-pipeline.scala:176:37]
reg [4:0] ll_wbarb_io_in_0_bits_REG_uop_pimm; // @[fp-pipeline.scala:176:37]
reg [19:0] ll_wbarb_io_in_0_bits_REG_uop_imm_packed; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_op1_sel; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_op2_sel; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_ldst; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_wen; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_ren1; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_ren2; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_ren3; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_swap12; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_swap23; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_typeTagIn; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_typeTagOut; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_fromint; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_toint; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_fastpipe; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_fma; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_div; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_sqrt; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_wflags; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_ctrl_vec; // @[fp-pipeline.scala:176:37]
reg [6:0] ll_wbarb_io_in_0_bits_REG_uop_rob_idx; // @[fp-pipeline.scala:176:37]
reg [4:0] ll_wbarb_io_in_0_bits_REG_uop_ldq_idx; // @[fp-pipeline.scala:176:37]
reg [4:0] ll_wbarb_io_in_0_bits_REG_uop_stq_idx; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_rxq_idx; // @[fp-pipeline.scala:176:37]
reg [6:0] ll_wbarb_io_in_0_bits_REG_uop_pdst; // @[fp-pipeline.scala:176:37]
reg [6:0] ll_wbarb_io_in_0_bits_REG_uop_prs1; // @[fp-pipeline.scala:176:37]
reg [6:0] ll_wbarb_io_in_0_bits_REG_uop_prs2; // @[fp-pipeline.scala:176:37]
reg [6:0] ll_wbarb_io_in_0_bits_REG_uop_prs3; // @[fp-pipeline.scala:176:37]
reg [4:0] ll_wbarb_io_in_0_bits_REG_uop_ppred; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_prs1_busy; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_prs2_busy; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_prs3_busy; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_ppred_busy; // @[fp-pipeline.scala:176:37]
reg [6:0] ll_wbarb_io_in_0_bits_REG_uop_stale_pdst; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_exception; // @[fp-pipeline.scala:176:37]
reg [63:0] ll_wbarb_io_in_0_bits_REG_uop_exc_cause; // @[fp-pipeline.scala:176:37]
reg [4:0] ll_wbarb_io_in_0_bits_REG_uop_mem_cmd; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_mem_size; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_mem_signed; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_uses_ldq; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_uses_stq; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_is_unique; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_flush_on_commit; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_csr_cmd; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_ldst_is_rs1; // @[fp-pipeline.scala:176:37]
reg [5:0] ll_wbarb_io_in_0_bits_REG_uop_ldst; // @[fp-pipeline.scala:176:37]
reg [5:0] ll_wbarb_io_in_0_bits_REG_uop_lrs1; // @[fp-pipeline.scala:176:37]
reg [5:0] ll_wbarb_io_in_0_bits_REG_uop_lrs2; // @[fp-pipeline.scala:176:37]
reg [5:0] ll_wbarb_io_in_0_bits_REG_uop_lrs3; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_dst_rtype; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_lrs1_rtype; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_lrs2_rtype; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_frs3_en; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fcn_dw; // @[fp-pipeline.scala:176:37]
reg [4:0] ll_wbarb_io_in_0_bits_REG_uop_fcn_op; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_fp_val; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_fp_rm; // @[fp-pipeline.scala:176:37]
reg [1:0] ll_wbarb_io_in_0_bits_REG_uop_fp_typ; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_xcpt_pf_if; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_xcpt_ae_if; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_xcpt_ma_if; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_bp_debug_if; // @[fp-pipeline.scala:176:37]
reg ll_wbarb_io_in_0_bits_REG_uop_bp_xcpt_if; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_debug_fsrc; // @[fp-pipeline.scala:176:37]
reg [2:0] ll_wbarb_io_in_0_bits_REG_uop_debug_tsrc; // @[fp-pipeline.scala:176:37]
reg [64:0] ll_wbarb_io_in_0_bits_REG_data; // @[fp-pipeline.scala:176:37]
reg [64:0] ll_wbarb_io_in_0_bits_data_REG; // @[fp-pipeline.scala:177:48]
wire _ll_wbarb_io_in_0_bits_data_T = io_ll_wports_0_bits_uop_mem_size_0 != 2'h2; // @[fp-pipeline.scala:27:7, :178:83]
reg ll_wbarb_io_in_0_bits_data_REG_1; // @[fp-pipeline.scala:178:48]
wire _ll_wbarb_io_in_0_bits_data_T_1 = ll_wbarb_io_in_0_bits_data_REG_1; // @[package.scala:39:86]
wire [63:0] _ll_wbarb_io_in_0_bits_data_T_2 = _ll_wbarb_io_in_0_bits_data_T_1 ? 64'h0 : 64'hFFFFFFFF00000000; // @[package.scala:39:{76,86}]
wire [64:0] _ll_wbarb_io_in_0_bits_data_T_3 = {1'h0, _ll_wbarb_io_in_0_bits_data_T_2} | ll_wbarb_io_in_0_bits_data_REG; // @[package.scala:39:76]
wire ll_wbarb_io_in_0_bits_data_rawIn_sign = _ll_wbarb_io_in_0_bits_data_T_3[63]; // @[FPU.scala:431:23]
wire ll_wbarb_io_in_0_bits_data_rawIn_sign_0 = ll_wbarb_io_in_0_bits_data_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [10:0] ll_wbarb_io_in_0_bits_data_rawIn_expIn = _ll_wbarb_io_in_0_bits_data_T_3[62:52]; // @[FPU.scala:431:23]
wire [51:0] ll_wbarb_io_in_0_bits_data_rawIn_fractIn = _ll_wbarb_io_in_0_bits_data_T_3[51:0]; // @[FPU.scala:431:23]
wire ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn = ll_wbarb_io_in_0_bits_data_rawIn_expIn == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn = ll_wbarb_io_in_0_bits_data_rawIn_fractIn == 52'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_1 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_2 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_3 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_4 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_5 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_6 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_7 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_8 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_9 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_10 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_11 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_12 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_13 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_14 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_15 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_16 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_17 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_18 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_19 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_20 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_21 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_22 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_23 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[23]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_24 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[24]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_25 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[25]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_26 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[26]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_27 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[27]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_28 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[28]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_29 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[29]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_30 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[30]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_31 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[31]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_32 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[32]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_33 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[33]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_34 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[34]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_35 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[35]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_36 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[36]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_37 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[37]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_38 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[38]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_39 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[39]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_40 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[40]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_41 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[41]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_42 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[42]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_43 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[43]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_44 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[44]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_45 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[45]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_46 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[46]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_47 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[47]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_48 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[48]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_49 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[49]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_50 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[50]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_51 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn[51]; // @[rawFloatFromFN.scala:46:21]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_52 = {5'h19, ~_ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_53 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_2 ? 6'h31 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_52; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_54 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_3 ? 6'h30 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_53; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_55 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_4 ? 6'h2F : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_54; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_56 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_5 ? 6'h2E : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_55; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_57 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_6 ? 6'h2D : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_56; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_58 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_7 ? 6'h2C : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_57; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_59 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_8 ? 6'h2B : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_58; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_60 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_9 ? 6'h2A : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_59; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_61 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_10 ? 6'h29 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_60; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_62 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_11 ? 6'h28 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_61; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_63 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_12 ? 6'h27 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_62; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_64 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_13 ? 6'h26 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_63; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_65 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_14 ? 6'h25 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_66 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_15 ? 6'h24 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_67 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_16 ? 6'h23 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_68 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_17 ? 6'h22 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_69 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_18 ? 6'h21 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_70 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_19 ? 6'h20 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_71 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_20 ? 6'h1F : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_72 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_21 ? 6'h1E : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_73 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_22 ? 6'h1D : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_74 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_23 ? 6'h1C : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_75 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_24 ? 6'h1B : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_76 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_25 ? 6'h1A : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_77 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_26 ? 6'h19 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_78 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_27 ? 6'h18 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_79 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_28 ? 6'h17 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_80 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_29 ? 6'h16 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_81 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_30 ? 6'h15 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_82 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_31 ? 6'h14 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_83 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_32 ? 6'h13 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_84 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_33 ? 6'h12 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_85 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_34 ? 6'h11 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_86 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_35 ? 6'h10 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_87 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_36 ? 6'hF : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_88 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_37 ? 6'hE : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_89 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_38 ? 6'hD : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_90 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_39 ? 6'hC : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_91 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_40 ? 6'hB : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_92 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_41 ? 6'hA : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_93 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_42 ? 6'h9 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_94 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_43 ? 6'h8 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_95 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_44 ? 6'h7 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_96 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_45 ? 6'h6 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_97 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_46 ? 6'h5 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_98 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_47 ? 6'h4 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_99 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_48 ? 6'h3 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_100 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_49 ? 6'h2 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_101 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_50 ? 6'h1 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_100; // @[Mux.scala:50:70]
wire [5:0] ll_wbarb_io_in_0_bits_data_rawIn_normDist = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_51 ? 6'h0 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_101; // @[Mux.scala:50:70]
wire [114:0] _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T = {63'h0, ll_wbarb_io_in_0_bits_data_rawIn_fractIn} << ll_wbarb_io_in_0_bits_data_rawIn_normDist; // @[Mux.scala:50:70]
wire [50:0] _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_1 = _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T[50:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [51:0] ll_wbarb_io_in_0_bits_data_rawIn_subnormFract = {_ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [11:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T = {6'h3F, ~ll_wbarb_io_in_0_bits_data_rawIn_normDist}; // @[Mux.scala:50:70]
wire [11:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_1 = ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn ? _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T : {1'h0, ll_wbarb_io_in_0_bits_data_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_2 = ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [10:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_3 = {9'h100, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [12:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_4 = {1'h0, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_1} + {2'h0, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [11:0] ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp = _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_4[11:0]; // @[rawFloatFromFN.scala:57:9]
wire [11:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T = ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire ll_wbarb_io_in_0_bits_data_rawIn_isZero = ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn & ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire ll_wbarb_io_in_0_bits_data_rawIn_isZero_0 = ll_wbarb_io_in_0_bits_data_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_T = ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp[11:10]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire ll_wbarb_io_in_0_bits_data_rawIn_isSpecial = &_ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _ll_wbarb_io_in_0_bits_data_T_6 = ll_wbarb_io_in_0_bits_data_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [12:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [53:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire ll_wbarb_io_in_0_bits_data_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [12:0] ll_wbarb_io_in_0_bits_data_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [53:0] ll_wbarb_io_in_0_bits_data_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T = ~ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_1 = ll_wbarb_io_in_0_bits_data_rawIn_isSpecial & _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign ll_wbarb_io_in_0_bits_data_rawIn_isNaN = _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T = ll_wbarb_io_in_0_bits_data_rawIn_isSpecial & ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign ll_wbarb_io_in_0_bits_data_rawIn_isInf = _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_1 = {1'h0, _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign ll_wbarb_io_in_0_bits_data_rawIn_sExp = _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T = ~ll_wbarb_io_in_0_bits_data_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_1 = {1'h0, _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [51:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_2 = ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn ? ll_wbarb_io_in_0_bits_data_rawIn_subnormFract : ll_wbarb_io_in_0_bits_data_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_3 = {_ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_1, _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign ll_wbarb_io_in_0_bits_data_rawIn_sig = _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _ll_wbarb_io_in_0_bits_data_T_4 = ll_wbarb_io_in_0_bits_data_rawIn_sExp[11:9]; // @[recFNFromFN.scala:48:50]
wire [2:0] _ll_wbarb_io_in_0_bits_data_T_5 = ll_wbarb_io_in_0_bits_data_rawIn_isZero_0 ? 3'h0 : _ll_wbarb_io_in_0_bits_data_T_4; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _ll_wbarb_io_in_0_bits_data_T_7 = {_ll_wbarb_io_in_0_bits_data_T_5[2:1], _ll_wbarb_io_in_0_bits_data_T_5[0] | _ll_wbarb_io_in_0_bits_data_T_6}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _ll_wbarb_io_in_0_bits_data_T_8 = {ll_wbarb_io_in_0_bits_data_rawIn_sign_0, _ll_wbarb_io_in_0_bits_data_T_7}; // @[recFNFromFN.scala:47:20, :48:76]
wire [8:0] _ll_wbarb_io_in_0_bits_data_T_9 = ll_wbarb_io_in_0_bits_data_rawIn_sExp[8:0]; // @[recFNFromFN.scala:50:23]
wire [12:0] _ll_wbarb_io_in_0_bits_data_T_10 = {_ll_wbarb_io_in_0_bits_data_T_8, _ll_wbarb_io_in_0_bits_data_T_9}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [51:0] _ll_wbarb_io_in_0_bits_data_T_11 = ll_wbarb_io_in_0_bits_data_rawIn_sig[51:0]; // @[recFNFromFN.scala:51:22]
wire [64:0] _ll_wbarb_io_in_0_bits_data_T_12 = {_ll_wbarb_io_in_0_bits_data_T_10, _ll_wbarb_io_in_0_bits_data_T_11}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire ll_wbarb_io_in_0_bits_data_rawIn_sign_1 = _ll_wbarb_io_in_0_bits_data_T_3[31]; // @[FPU.scala:431:23]
wire ll_wbarb_io_in_0_bits_data_rawIn_1_sign = ll_wbarb_io_in_0_bits_data_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] ll_wbarb_io_in_0_bits_data_rawIn_expIn_1 = _ll_wbarb_io_in_0_bits_data_T_3[30:23]; // @[FPU.scala:431:23]
wire [22:0] ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1 = _ll_wbarb_io_in_0_bits_data_T_3[22:0]; // @[FPU.scala:431:23]
wire ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1 = ll_wbarb_io_in_0_bits_data_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn_1 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_102 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_103 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_104 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_105 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_106 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_107 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_108 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_109 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_110 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_111 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_112 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_113 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_114 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_115 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_116 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_117 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_118 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_119 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_120 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_121 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_122 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_123 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_124 = ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_125 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_103 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_126 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_104 ? 5'h14 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_127 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_105 ? 5'h13 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_128 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_106 ? 5'h12 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_129 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_107 ? 5'h11 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_130 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_108 ? 5'h10 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_131 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_109 ? 5'hF : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_132 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_110 ? 5'hE : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_133 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_111 ? 5'hD : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_132; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_134 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_112 ? 5'hC : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_133; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_135 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_113 ? 5'hB : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_134; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_136 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_114 ? 5'hA : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_135; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_137 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_115 ? 5'h9 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_136; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_138 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_116 ? 5'h8 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_137; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_139 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_117 ? 5'h7 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_138; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_140 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_118 ? 5'h6 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_139; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_141 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_119 ? 5'h5 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_140; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_142 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_120 ? 5'h4 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_141; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_143 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_121 ? 5'h3 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_142; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_144 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_122 ? 5'h2 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_143; // @[Mux.scala:50:70]
wire [4:0] _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_145 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_123 ? 5'h1 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_144; // @[Mux.scala:50:70]
wire [4:0] ll_wbarb_io_in_0_bits_data_rawIn_normDist_1 = _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_124 ? 5'h0 : _ll_wbarb_io_in_0_bits_data_rawIn_normDist_T_145; // @[Mux.scala:50:70]
wire [53:0] _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_2 = {31'h0, ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1} << ll_wbarb_io_in_0_bits_data_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_3 = _ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_1 = {_ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_5 = {4'hF, ~ll_wbarb_io_in_0_bits_data_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_6 = ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1 ? _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_5 : {1'h0, ll_wbarb_io_in_0_bits_data_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_7 = ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_8 = {6'h20, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_9 = {1'h0, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_6} + {2'h0, _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_1 = _ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_2 = ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire ll_wbarb_io_in_0_bits_data_rawIn_isZero_1 = ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1 & ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire ll_wbarb_io_in_0_bits_data_rawIn_1_isZero = ll_wbarb_io_in_0_bits_data_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_T_1 = ll_wbarb_io_in_0_bits_data_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_1 = &_ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _ll_wbarb_io_in_0_bits_data_T_15 = ll_wbarb_io_in_0_bits_data_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire ll_wbarb_io_in_0_bits_data_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] ll_wbarb_io_in_0_bits_data_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] ll_wbarb_io_in_0_bits_data_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_2 = ~ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_3 = ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_1 & _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign ll_wbarb_io_in_0_bits_data_rawIn_1_isNaN = _ll_wbarb_io_in_0_bits_data_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T_1 = ll_wbarb_io_in_0_bits_data_rawIn_isSpecial_1 & ll_wbarb_io_in_0_bits_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign ll_wbarb_io_in_0_bits_data_rawIn_1_isInf = _ll_wbarb_io_in_0_bits_data_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_3 = {1'h0, _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign ll_wbarb_io_in_0_bits_data_rawIn_1_sExp = _ll_wbarb_io_in_0_bits_data_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_4 = ~ll_wbarb_io_in_0_bits_data_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_5 = {1'h0, _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_6 = ll_wbarb_io_in_0_bits_data_rawIn_isZeroExpIn_1 ? ll_wbarb_io_in_0_bits_data_rawIn_subnormFract_1 : ll_wbarb_io_in_0_bits_data_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_7 = {_ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_5, _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign ll_wbarb_io_in_0_bits_data_rawIn_1_sig = _ll_wbarb_io_in_0_bits_data_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _ll_wbarb_io_in_0_bits_data_T_13 = ll_wbarb_io_in_0_bits_data_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _ll_wbarb_io_in_0_bits_data_T_14 = ll_wbarb_io_in_0_bits_data_rawIn_1_isZero ? 3'h0 : _ll_wbarb_io_in_0_bits_data_T_13; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _ll_wbarb_io_in_0_bits_data_T_16 = {_ll_wbarb_io_in_0_bits_data_T_14[2:1], _ll_wbarb_io_in_0_bits_data_T_14[0] | _ll_wbarb_io_in_0_bits_data_T_15}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _ll_wbarb_io_in_0_bits_data_T_17 = {ll_wbarb_io_in_0_bits_data_rawIn_1_sign, _ll_wbarb_io_in_0_bits_data_T_16}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _ll_wbarb_io_in_0_bits_data_T_18 = ll_wbarb_io_in_0_bits_data_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _ll_wbarb_io_in_0_bits_data_T_19 = {_ll_wbarb_io_in_0_bits_data_T_17, _ll_wbarb_io_in_0_bits_data_T_18}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _ll_wbarb_io_in_0_bits_data_T_20 = ll_wbarb_io_in_0_bits_data_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] _ll_wbarb_io_in_0_bits_data_T_21 = {_ll_wbarb_io_in_0_bits_data_T_19, _ll_wbarb_io_in_0_bits_data_T_20}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [3:0] _ll_wbarb_io_in_0_bits_data_swizzledNaN_T = _ll_wbarb_io_in_0_bits_data_T_12[64:61]; // @[FPU.scala:337:8]
wire [19:0] _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_1 = _ll_wbarb_io_in_0_bits_data_T_12[51:32]; // @[FPU.scala:338:8]
wire [19:0] _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_5 = _ll_wbarb_io_in_0_bits_data_T_12[51:32]; // @[FPU.scala:338:8, :341:8]
wire _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_2 = &_ll_wbarb_io_in_0_bits_data_swizzledNaN_T_1; // @[FPU.scala:338:{8,42}]
wire [6:0] _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_3 = _ll_wbarb_io_in_0_bits_data_T_12[59:53]; // @[FPU.scala:339:8]
wire _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_4 = _ll_wbarb_io_in_0_bits_data_T_21[31]; // @[FPU.scala:340:8]
wire _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_6 = _ll_wbarb_io_in_0_bits_data_T_21[32]; // @[FPU.scala:342:8]
wire [30:0] _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_7 = _ll_wbarb_io_in_0_bits_data_T_21[30:0]; // @[FPU.scala:343:8]
wire [20:0] ll_wbarb_io_in_0_bits_data_swizzledNaN_lo_hi = {_ll_wbarb_io_in_0_bits_data_swizzledNaN_T_5, _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_6}; // @[FPU.scala:336:26, :341:8, :342:8]
wire [51:0] ll_wbarb_io_in_0_bits_data_swizzledNaN_lo = {ll_wbarb_io_in_0_bits_data_swizzledNaN_lo_hi, _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8]
wire [7:0] ll_wbarb_io_in_0_bits_data_swizzledNaN_hi_lo = {_ll_wbarb_io_in_0_bits_data_swizzledNaN_T_3, _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_4}; // @[FPU.scala:336:26, :339:8, :340:8]
wire [4:0] ll_wbarb_io_in_0_bits_data_swizzledNaN_hi_hi = {_ll_wbarb_io_in_0_bits_data_swizzledNaN_T, _ll_wbarb_io_in_0_bits_data_swizzledNaN_T_2}; // @[FPU.scala:336:26, :337:8, :338:42]
wire [12:0] ll_wbarb_io_in_0_bits_data_swizzledNaN_hi = {ll_wbarb_io_in_0_bits_data_swizzledNaN_hi_hi, ll_wbarb_io_in_0_bits_data_swizzledNaN_hi_lo}; // @[FPU.scala:336:26]
wire [64:0] ll_wbarb_io_in_0_bits_data_swizzledNaN = {ll_wbarb_io_in_0_bits_data_swizzledNaN_hi, ll_wbarb_io_in_0_bits_data_swizzledNaN_lo}; // @[FPU.scala:336:26]
wire [2:0] _ll_wbarb_io_in_0_bits_data_T_22 = _ll_wbarb_io_in_0_bits_data_T_12[63:61]; // @[FPU.scala:249:25]
wire _ll_wbarb_io_in_0_bits_data_T_23 = &_ll_wbarb_io_in_0_bits_data_T_22; // @[FPU.scala:249:{25,56}]
wire [64:0] _ll_wbarb_io_in_0_bits_data_T_24 = _ll_wbarb_io_in_0_bits_data_T_23 ? ll_wbarb_io_in_0_bits_data_swizzledNaN : _ll_wbarb_io_in_0_bits_data_T_12; // @[FPU.scala:249:56, :336:26, :344:8]
wire _fregfile_io_write_ports_0_valid_T = _ll_wbarb_io_out_bits_uop_dst_rtype == 2'h1; // @[fp-pipeline.scala:167:24, :189:99]
wire _fregfile_io_write_ports_0_valid_T_1 = _ll_wbarb_io_out_valid & _fregfile_io_write_ports_0_valid_T; // @[fp-pipeline.scala:167:24, :189:{61,99}] |
Generate the Verilog code corresponding to this FIRRTL code module PTW :
input clock : Clock
input reset : Reset
output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<20>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<1>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<32>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, flip hgatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, flip vsatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<32>, value : UInt<32>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<32>}[4]}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<32>, mask : UInt<4>}}, s1_kill : UInt<1>, s1_data : { data : UInt<32>, mask : UInt<4>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<32>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<32>, mask : UInt<4>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<32>, data_raw : UInt<32>, store_data : UInt<32>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<32>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, flip hgatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, flip vsatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<32>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<32>, value : UInt<32>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<32>}[4]}, clock_enabled : UInt<1>}}
regreset state : UInt<3>, clock, reset, UInt<3>(0h0)
wire l2_refill_wire : UInt<1>
inst arb of Arbiter2_Valid_PTWReq
connect arb.clock, clock
connect arb.reset, reset
connect arb.io.in[0], io.requestor[0].req
connect arb.io.in[1], io.requestor[1].req
node _arb_io_out_ready_T = eq(state, UInt<3>(0h0))
node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0))
node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1)
connect arb.io.out.ready, _arb_io_out_ready_T_2
wire _resp_valid_WIRE : UInt<1>[2]
connect _resp_valid_WIRE[0], UInt<1>(0h0)
connect _resp_valid_WIRE[1], UInt<1>(0h0)
reg resp_valid : UInt<1>[2], clock
connect resp_valid, _resp_valid_WIRE
node _clock_en_T = neq(state, UInt<3>(0h0))
node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire)
node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid)
node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid)
node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[0].value, 0, 0)
node clock_en = or(_clock_en_T_3, _clock_en_T_4)
node _io_dpath_clock_enabled_T = and(UInt<1>(0h0), clock_en)
connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T
reg invalidated : UInt<1>, clock
reg count : UInt<1>, clock
reg resp_ae_ptw : UInt<1>, clock
reg resp_ae_final : UInt<1>, clock
reg resp_pf : UInt<1>, clock
reg resp_gf : UInt<1>, clock
reg resp_hr : UInt<1>, clock
reg resp_hw : UInt<1>, clock
reg resp_hx : UInt<1>, clock
reg resp_fragmented_superpage : UInt<1>, clock
reg r_req : { addr : UInt<20>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock
reg r_req_dest : UInt, clock
reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg r_hgatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, clock
reg aux_count : UInt<1>, clock
reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg gpa_pgoff : UInt<12>, clock
reg stage2 : UInt<1>, clock
reg stage2_final : UInt<1>, clock
node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
node _r_hgatp_initial_count_T = sub(UInt<2>(0h2), UInt<2>(0h2))
node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1)
node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0))
node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1)
node do_both_stages = and(r_req.vstage1, r_req.stage2)
node _max_count_T = lt(count, aux_count)
node max_count = mux(_max_count_T, aux_count, count)
node _vpn_T = and(r_req.vstage1, stage2)
node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr)
reg mem_resp_valid : UInt<1>, clock
connect mem_resp_valid, io.mem.resp.valid
reg mem_resp_data : UInt, clock
connect mem_resp_data, io.mem.resp.bits.data
wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
wire _tmp_WIRE : UInt<64>
connect _tmp_WIRE, mem_resp_data
node _tmp_T = bits(_tmp_WIRE, 0, 0)
connect tmp.v, _tmp_T
node _tmp_T_1 = bits(_tmp_WIRE, 1, 1)
connect tmp.r, _tmp_T_1
node _tmp_T_2 = bits(_tmp_WIRE, 2, 2)
connect tmp.w, _tmp_T_2
node _tmp_T_3 = bits(_tmp_WIRE, 3, 3)
connect tmp.x, _tmp_T_3
node _tmp_T_4 = bits(_tmp_WIRE, 4, 4)
connect tmp.u, _tmp_T_4
node _tmp_T_5 = bits(_tmp_WIRE, 5, 5)
connect tmp.g, _tmp_T_5
node _tmp_T_6 = bits(_tmp_WIRE, 6, 6)
connect tmp.a, _tmp_T_6
node _tmp_T_7 = bits(_tmp_WIRE, 7, 7)
connect tmp.d, _tmp_T_7
node _tmp_T_8 = bits(_tmp_WIRE, 9, 8)
connect tmp.reserved_for_software, _tmp_T_8
node _tmp_T_9 = bits(_tmp_WIRE, 53, 10)
connect tmp.ppn, _tmp_T_9
node _tmp_T_10 = bits(_tmp_WIRE, 63, 54)
connect tmp.reserved_for_future, _tmp_T_10
wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect pte, tmp
node _res_ppn_T = eq(stage2, UInt<1>(0h0))
node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T)
node _res_ppn_T_2 = bits(tmp.ppn, 19, 0)
node _res_ppn_T_3 = bits(tmp.ppn, 19, 0)
node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3)
connect pte.ppn, _res_ppn_T_4
node _T = or(tmp.r, tmp.w)
node _T_1 = or(_T, tmp.x)
when _T_1 :
node _T_2 = leq(count, UInt<1>(0h0))
node _T_3 = bits(tmp.ppn, 9, 0)
node _T_4 = neq(_T_3, UInt<1>(0h0))
node _T_5 = and(_T_2, _T_4)
when _T_5 :
connect pte.v, UInt<1>(0h0)
node _T_6 = eq(stage2, UInt<1>(0h0))
node _T_7 = and(do_both_stages, _T_6)
node _T_8 = shr(tmp.ppn, 20)
node _T_9 = neq(_T_8, UInt<1>(0h0))
node _T_10 = shr(tmp.ppn, 20)
node _T_11 = neq(_T_10, UInt<1>(0h0))
node invalid_paddr = mux(_T_7, _T_9, _T_11)
node _T_12 = eq(stage2, UInt<1>(0h0))
node _T_13 = and(do_both_stages, _T_12)
node _count_T = sub(UInt<2>(0h2), UInt<2>(0h2))
node _count_T_1 = tail(_count_T, 1)
node _count_T_2 = sub(_count_T_1, UInt<1>(0h0))
node count_1 = tail(_count_T_2, 1)
node idxs_0 = shr(tmp.ppn, 22)
wire _WIRE : UInt<22>[1]
connect _WIRE[0], idxs_0
node _T_14 = or(count_1, UInt<0>(0h0))
node _T_15 = neq(_WIRE[0], UInt<1>(0h0))
node invalid_gpa = and(_T_13, _T_15)
node _traverse_T = eq(pte.r, UInt<1>(0h0))
node _traverse_T_1 = and(pte.v, _traverse_T)
node _traverse_T_2 = eq(pte.w, UInt<1>(0h0))
node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2)
node _traverse_T_4 = eq(pte.x, UInt<1>(0h0))
node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4)
node _traverse_T_6 = eq(pte.d, UInt<1>(0h0))
node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6)
node _traverse_T_8 = eq(pte.a, UInt<1>(0h0))
node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8)
node _traverse_T_10 = eq(pte.u, UInt<1>(0h0))
node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10)
node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12)
node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0))
node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14)
node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0))
node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16)
node _traverse_T_18 = lt(count, UInt<1>(0h1))
node traverse = and(_traverse_T_17, _traverse_T_18)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
regreset valid : UInt<8>, clock, reset, UInt<8>(0h0)
reg tags : UInt<32>[8], clock
reg data : UInt<20>[8], clock
node _can_hit_T = lt(count, UInt<1>(0h1))
node _can_hit_T_1 = eq(r_req.stage2, UInt<1>(0h0))
node _can_hit_T_2 = mux(r_req.vstage1, stage2, _can_hit_T_1)
node can_hit = and(_can_hit_T, _can_hit_T_2)
node _tag_T = cat(UInt<31>(0h0), UInt<1>(0h0))
node tag = cat(r_req.vstage1, _tag_T)
node _hits_T = eq(tags[0], tag)
node _hits_T_1 = eq(tags[1], tag)
node _hits_T_2 = eq(tags[2], tag)
node _hits_T_3 = eq(tags[3], tag)
node _hits_T_4 = eq(tags[4], tag)
node _hits_T_5 = eq(tags[5], tag)
node _hits_T_6 = eq(tags[6], tag)
node _hits_T_7 = eq(tags[7], tag)
node hits_lo_lo = cat(_hits_T_1, _hits_T)
node hits_lo_hi = cat(_hits_T_3, _hits_T_2)
node hits_lo = cat(hits_lo_hi, hits_lo_lo)
node hits_hi_lo = cat(_hits_T_5, _hits_T_4)
node hits_hi_hi = cat(_hits_T_7, _hits_T_6)
node hits_hi = cat(hits_hi_hi, hits_hi_lo)
node _hits_T_8 = cat(hits_hi, hits_lo)
node hits = and(_hits_T_8, valid)
node _hit_T = orr(hits)
node pte_cache_hit = and(_hit_T, can_hit)
node _T_16 = and(mem_resp_valid, traverse)
node _T_17 = and(_T_16, can_hit)
node _T_18 = orr(hits)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = and(_T_17, _T_19)
node _T_21 = eq(invalidated, UInt<1>(0h0))
node _T_22 = and(_T_20, _T_21)
when _T_22 :
node _r_T = andr(valid)
node r_left_subtree_older = bits(state_reg, 6, 6)
node r_left_subtree_state = bits(state_reg, 5, 3)
node r_right_subtree_state = bits(state_reg, 2, 0)
node r_left_subtree_older_1 = bits(r_left_subtree_state, 2, 2)
node r_left_subtree_state_1 = bits(r_left_subtree_state, 1, 1)
node r_right_subtree_state_1 = bits(r_left_subtree_state, 0, 0)
node _r_T_1 = bits(r_left_subtree_state_1, 0, 0)
node _r_T_2 = bits(r_right_subtree_state_1, 0, 0)
node _r_T_3 = mux(r_left_subtree_older_1, _r_T_1, _r_T_2)
node _r_T_4 = cat(r_left_subtree_older_1, _r_T_3)
node r_left_subtree_older_2 = bits(r_right_subtree_state, 2, 2)
node r_left_subtree_state_2 = bits(r_right_subtree_state, 1, 1)
node r_right_subtree_state_2 = bits(r_right_subtree_state, 0, 0)
node _r_T_5 = bits(r_left_subtree_state_2, 0, 0)
node _r_T_6 = bits(r_right_subtree_state_2, 0, 0)
node _r_T_7 = mux(r_left_subtree_older_2, _r_T_5, _r_T_6)
node _r_T_8 = cat(r_left_subtree_older_2, _r_T_7)
node _r_T_9 = mux(r_left_subtree_older, _r_T_4, _r_T_8)
node _r_T_10 = cat(r_left_subtree_older, _r_T_9)
node _r_T_11 = not(valid)
node _r_T_12 = bits(_r_T_11, 0, 0)
node _r_T_13 = bits(_r_T_11, 1, 1)
node _r_T_14 = bits(_r_T_11, 2, 2)
node _r_T_15 = bits(_r_T_11, 3, 3)
node _r_T_16 = bits(_r_T_11, 4, 4)
node _r_T_17 = bits(_r_T_11, 5, 5)
node _r_T_18 = bits(_r_T_11, 6, 6)
node _r_T_19 = bits(_r_T_11, 7, 7)
node _r_T_20 = mux(_r_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_T_21 = mux(_r_T_17, UInt<3>(0h5), _r_T_20)
node _r_T_22 = mux(_r_T_16, UInt<3>(0h4), _r_T_21)
node _r_T_23 = mux(_r_T_15, UInt<2>(0h3), _r_T_22)
node _r_T_24 = mux(_r_T_14, UInt<2>(0h2), _r_T_23)
node _r_T_25 = mux(_r_T_13, UInt<1>(0h1), _r_T_24)
node _r_T_26 = mux(_r_T_12, UInt<1>(0h0), _r_T_25)
node r = mux(_r_T, _r_T_10, _r_T_26)
node _valid_T = dshl(UInt<1>(0h1), r)
node _valid_T_1 = or(valid, _valid_T)
connect valid, _valid_T_1
connect tags[r], tag
connect data[r], pte.ppn
node state_reg_touch_way_sized = bits(r, 2, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg, 5, 3)
node state_reg_right_subtree_state = bits(state_reg, 2, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1)
node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0))
node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1)
node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0)
node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0))
node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3)
node _state_reg_T_5 = bits(_state_reg_T, 0, 0)
node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0)
node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0))
node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1)
node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4)
node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8)
node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9)
node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1)
node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0))
node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1)
node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0)
node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0)
node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0))
node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14)
node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0)
node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0))
node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2)
node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15)
node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19)
node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state)
node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10)
node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21)
connect state_reg, _state_reg_T_22
node _T_23 = eq(state, UInt<3>(0h1))
node _T_24 = and(pte_cache_hit, _T_23)
when _T_24 :
node hi = bits(hits, 7, 4)
node lo = bits(hits, 3, 0)
node _T_25 = orr(hi)
node _T_26 = or(hi, lo)
node hi_1 = bits(_T_26, 3, 2)
node lo_1 = bits(_T_26, 1, 0)
node _T_27 = orr(hi_1)
node _T_28 = or(hi_1, lo_1)
node _T_29 = bits(_T_28, 1, 1)
node _T_30 = cat(_T_27, _T_29)
node _T_31 = cat(_T_25, _T_30)
node state_reg_touch_way_sized_1 = bits(_T_31, 2, 0)
node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 2, 2)
node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0))
node state_reg_left_subtree_state_3 = bits(state_reg, 5, 3)
node state_reg_right_subtree_state_3 = bits(state_reg, 2, 0)
node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 1, 0)
node _state_reg_set_left_older_T_4 = bits(_state_reg_T_23, 1, 1)
node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0))
node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0)
node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0)
node _state_reg_T_26 = eq(_state_reg_T_25, UInt<1>(0h0))
node _state_reg_T_27 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_26)
node _state_reg_T_28 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_29 = bits(_state_reg_T_28, 0, 0)
node _state_reg_T_30 = eq(_state_reg_T_29, UInt<1>(0h0))
node _state_reg_T_31 = mux(state_reg_set_left_older_4, _state_reg_T_30, state_reg_right_subtree_state_4)
node state_reg_hi_3 = cat(state_reg_set_left_older_4, _state_reg_T_27)
node _state_reg_T_32 = cat(state_reg_hi_3, _state_reg_T_31)
node _state_reg_T_33 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_32)
node _state_reg_T_34 = bits(state_reg_touch_way_sized_1, 1, 0)
node _state_reg_set_left_older_T_5 = bits(_state_reg_T_34, 1, 1)
node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0))
node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0)
node _state_reg_T_35 = bits(_state_reg_T_34, 0, 0)
node _state_reg_T_36 = bits(_state_reg_T_35, 0, 0)
node _state_reg_T_37 = eq(_state_reg_T_36, UInt<1>(0h0))
node _state_reg_T_38 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_37)
node _state_reg_T_39 = bits(_state_reg_T_34, 0, 0)
node _state_reg_T_40 = bits(_state_reg_T_39, 0, 0)
node _state_reg_T_41 = eq(_state_reg_T_40, UInt<1>(0h0))
node _state_reg_T_42 = mux(state_reg_set_left_older_5, _state_reg_T_41, state_reg_right_subtree_state_5)
node state_reg_hi_4 = cat(state_reg_set_left_older_5, _state_reg_T_38)
node _state_reg_T_43 = cat(state_reg_hi_4, _state_reg_T_42)
node _state_reg_T_44 = mux(state_reg_set_left_older_3, _state_reg_T_43, state_reg_right_subtree_state_3)
node state_reg_hi_5 = cat(state_reg_set_left_older_3, _state_reg_T_33)
node _state_reg_T_45 = cat(state_reg_hi_5, _state_reg_T_44)
connect state_reg, _state_reg_T_45
node _T_32 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0))
node _T_33 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg)
node _T_34 = or(_T_32, _T_33)
node _T_35 = and(io.dpath.sfence.valid, _T_34)
when _T_35 :
connect valid, UInt<1>(0h0)
node _T_36 = eq(state, UInt<3>(0h1))
node _T_37 = and(pte_cache_hit, _T_36)
node _T_38 = eq(count, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
node _T_40 = bits(hits, 0, 0)
node _T_41 = bits(hits, 1, 1)
node _T_42 = bits(hits, 2, 2)
node _T_43 = bits(hits, 3, 3)
node _T_44 = bits(hits, 4, 4)
node _T_45 = bits(hits, 5, 5)
node _T_46 = bits(hits, 6, 6)
node _T_47 = bits(hits, 7, 7)
node _T_48 = mux(_T_40, data[0], UInt<1>(0h0))
node _T_49 = mux(_T_41, data[1], UInt<1>(0h0))
node _T_50 = mux(_T_42, data[2], UInt<1>(0h0))
node _T_51 = mux(_T_43, data[3], UInt<1>(0h0))
node _T_52 = mux(_T_44, data[4], UInt<1>(0h0))
node _T_53 = mux(_T_45, data[5], UInt<1>(0h0))
node _T_54 = mux(_T_46, data[6], UInt<1>(0h0))
node _T_55 = mux(_T_47, data[7], UInt<1>(0h0))
node _T_56 = or(_T_48, _T_49)
node _T_57 = or(_T_56, _T_50)
node _T_58 = or(_T_57, _T_51)
node _T_59 = or(_T_58, _T_52)
node _T_60 = or(_T_59, _T_53)
node _T_61 = or(_T_60, _T_54)
node _T_62 = or(_T_61, _T_55)
wire pte_cache_data : UInt<20>
connect pte_cache_data, _T_62
regreset state_reg_1 : UInt<7>, clock, reset, UInt<7>(0h0)
regreset valid_1 : UInt<8>, clock, reset, UInt<8>(0h0)
reg tags_1 : UInt<32>[8], clock
reg data_1 : UInt<20>[8], clock
node _can_hit_T_3 = eq(count, r_hgatp_initial_count)
node _can_hit_T_4 = lt(aux_count, UInt<1>(0h1))
node _can_hit_T_5 = and(_can_hit_T_3, _can_hit_T_4)
node _can_hit_T_6 = and(_can_hit_T_5, r_req.vstage1)
node _can_hit_T_7 = and(_can_hit_T_6, stage2)
node _can_hit_T_8 = eq(stage2_final, UInt<1>(0h0))
node can_hit_1 = and(_can_hit_T_7, _can_hit_T_8)
node _can_refill_T = eq(stage2, UInt<1>(0h0))
node _can_refill_T_1 = and(do_both_stages, _can_refill_T)
node _can_refill_T_2 = eq(stage2_final, UInt<1>(0h0))
node can_refill = and(_can_refill_T_1, _can_refill_T_2)
node _tag_T_1 = cat(UInt<31>(0h0), UInt<1>(0h0))
node tag_1 = cat(UInt<1>(0h1), _tag_T_1)
node _hits_T_9 = eq(tags_1[0], tag_1)
node _hits_T_10 = eq(tags_1[1], tag_1)
node _hits_T_11 = eq(tags_1[2], tag_1)
node _hits_T_12 = eq(tags_1[3], tag_1)
node _hits_T_13 = eq(tags_1[4], tag_1)
node _hits_T_14 = eq(tags_1[5], tag_1)
node _hits_T_15 = eq(tags_1[6], tag_1)
node _hits_T_16 = eq(tags_1[7], tag_1)
node hits_lo_lo_1 = cat(_hits_T_10, _hits_T_9)
node hits_lo_hi_1 = cat(_hits_T_12, _hits_T_11)
node hits_lo_1 = cat(hits_lo_hi_1, hits_lo_lo_1)
node hits_hi_lo_1 = cat(_hits_T_14, _hits_T_13)
node hits_hi_hi_1 = cat(_hits_T_16, _hits_T_15)
node hits_hi_1 = cat(hits_hi_hi_1, hits_hi_lo_1)
node _hits_T_17 = cat(hits_hi_1, hits_lo_1)
node hits_1 = and(_hits_T_17, valid_1)
node _hit_T_1 = orr(hits_1)
node stage2_pte_cache_hit = and(_hit_T_1, can_hit_1)
node _T_63 = and(mem_resp_valid, traverse)
node _T_64 = and(_T_63, can_refill)
node _T_65 = orr(hits_1)
node _T_66 = eq(_T_65, UInt<1>(0h0))
node _T_67 = and(_T_64, _T_66)
node _T_68 = eq(invalidated, UInt<1>(0h0))
node _T_69 = and(_T_67, _T_68)
when _T_69 :
node _r_T_27 = andr(valid_1)
node r_left_subtree_older_3 = bits(state_reg_1, 6, 6)
node r_left_subtree_state_3 = bits(state_reg_1, 5, 3)
node r_right_subtree_state_3 = bits(state_reg_1, 2, 0)
node r_left_subtree_older_4 = bits(r_left_subtree_state_3, 2, 2)
node r_left_subtree_state_4 = bits(r_left_subtree_state_3, 1, 1)
node r_right_subtree_state_4 = bits(r_left_subtree_state_3, 0, 0)
node _r_T_28 = bits(r_left_subtree_state_4, 0, 0)
node _r_T_29 = bits(r_right_subtree_state_4, 0, 0)
node _r_T_30 = mux(r_left_subtree_older_4, _r_T_28, _r_T_29)
node _r_T_31 = cat(r_left_subtree_older_4, _r_T_30)
node r_left_subtree_older_5 = bits(r_right_subtree_state_3, 2, 2)
node r_left_subtree_state_5 = bits(r_right_subtree_state_3, 1, 1)
node r_right_subtree_state_5 = bits(r_right_subtree_state_3, 0, 0)
node _r_T_32 = bits(r_left_subtree_state_5, 0, 0)
node _r_T_33 = bits(r_right_subtree_state_5, 0, 0)
node _r_T_34 = mux(r_left_subtree_older_5, _r_T_32, _r_T_33)
node _r_T_35 = cat(r_left_subtree_older_5, _r_T_34)
node _r_T_36 = mux(r_left_subtree_older_3, _r_T_31, _r_T_35)
node _r_T_37 = cat(r_left_subtree_older_3, _r_T_36)
node _r_T_38 = not(valid_1)
node _r_T_39 = bits(_r_T_38, 0, 0)
node _r_T_40 = bits(_r_T_38, 1, 1)
node _r_T_41 = bits(_r_T_38, 2, 2)
node _r_T_42 = bits(_r_T_38, 3, 3)
node _r_T_43 = bits(_r_T_38, 4, 4)
node _r_T_44 = bits(_r_T_38, 5, 5)
node _r_T_45 = bits(_r_T_38, 6, 6)
node _r_T_46 = bits(_r_T_38, 7, 7)
node _r_T_47 = mux(_r_T_45, UInt<3>(0h6), UInt<3>(0h7))
node _r_T_48 = mux(_r_T_44, UInt<3>(0h5), _r_T_47)
node _r_T_49 = mux(_r_T_43, UInt<3>(0h4), _r_T_48)
node _r_T_50 = mux(_r_T_42, UInt<2>(0h3), _r_T_49)
node _r_T_51 = mux(_r_T_41, UInt<2>(0h2), _r_T_50)
node _r_T_52 = mux(_r_T_40, UInt<1>(0h1), _r_T_51)
node _r_T_53 = mux(_r_T_39, UInt<1>(0h0), _r_T_52)
node r_1 = mux(_r_T_27, _r_T_37, _r_T_53)
node _valid_T_2 = dshl(UInt<1>(0h1), r_1)
node _valid_T_3 = or(valid_1, _valid_T_2)
connect valid_1, _valid_T_3
connect tags_1[r_1], tag_1
connect data_1[r_1], pte.ppn
node state_reg_touch_way_sized_2 = bits(r_1, 2, 0)
node _state_reg_set_left_older_T_6 = bits(state_reg_touch_way_sized_2, 2, 2)
node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0))
node state_reg_left_subtree_state_6 = bits(state_reg_1, 5, 3)
node state_reg_right_subtree_state_6 = bits(state_reg_1, 2, 0)
node _state_reg_T_46 = bits(state_reg_touch_way_sized_2, 1, 0)
node _state_reg_set_left_older_T_7 = bits(_state_reg_T_46, 1, 1)
node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0))
node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 1, 1)
node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 0, 0)
node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_48 = bits(_state_reg_T_47, 0, 0)
node _state_reg_T_49 = eq(_state_reg_T_48, UInt<1>(0h0))
node _state_reg_T_50 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_49)
node _state_reg_T_51 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_52 = bits(_state_reg_T_51, 0, 0)
node _state_reg_T_53 = eq(_state_reg_T_52, UInt<1>(0h0))
node _state_reg_T_54 = mux(state_reg_set_left_older_7, _state_reg_T_53, state_reg_right_subtree_state_7)
node state_reg_hi_6 = cat(state_reg_set_left_older_7, _state_reg_T_50)
node _state_reg_T_55 = cat(state_reg_hi_6, _state_reg_T_54)
node _state_reg_T_56 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_55)
node _state_reg_T_57 = bits(state_reg_touch_way_sized_2, 1, 0)
node _state_reg_set_left_older_T_8 = bits(_state_reg_T_57, 1, 1)
node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0))
node state_reg_left_subtree_state_8 = bits(state_reg_right_subtree_state_6, 1, 1)
node state_reg_right_subtree_state_8 = bits(state_reg_right_subtree_state_6, 0, 0)
node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_59 = bits(_state_reg_T_58, 0, 0)
node _state_reg_T_60 = eq(_state_reg_T_59, UInt<1>(0h0))
node _state_reg_T_61 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_60)
node _state_reg_T_62 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_63 = bits(_state_reg_T_62, 0, 0)
node _state_reg_T_64 = eq(_state_reg_T_63, UInt<1>(0h0))
node _state_reg_T_65 = mux(state_reg_set_left_older_8, _state_reg_T_64, state_reg_right_subtree_state_8)
node state_reg_hi_7 = cat(state_reg_set_left_older_8, _state_reg_T_61)
node _state_reg_T_66 = cat(state_reg_hi_7, _state_reg_T_65)
node _state_reg_T_67 = mux(state_reg_set_left_older_6, _state_reg_T_66, state_reg_right_subtree_state_6)
node state_reg_hi_8 = cat(state_reg_set_left_older_6, _state_reg_T_56)
node _state_reg_T_68 = cat(state_reg_hi_8, _state_reg_T_67)
connect state_reg_1, _state_reg_T_68
node _T_70 = eq(state, UInt<3>(0h1))
node _T_71 = and(stage2_pte_cache_hit, _T_70)
when _T_71 :
node hi_2 = bits(hits_1, 7, 4)
node lo_2 = bits(hits_1, 3, 0)
node _T_72 = orr(hi_2)
node _T_73 = or(hi_2, lo_2)
node hi_3 = bits(_T_73, 3, 2)
node lo_3 = bits(_T_73, 1, 0)
node _T_74 = orr(hi_3)
node _T_75 = or(hi_3, lo_3)
node _T_76 = bits(_T_75, 1, 1)
node _T_77 = cat(_T_74, _T_76)
node _T_78 = cat(_T_72, _T_77)
node state_reg_touch_way_sized_3 = bits(_T_78, 2, 0)
node _state_reg_set_left_older_T_9 = bits(state_reg_touch_way_sized_3, 2, 2)
node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0))
node state_reg_left_subtree_state_9 = bits(state_reg_1, 5, 3)
node state_reg_right_subtree_state_9 = bits(state_reg_1, 2, 0)
node _state_reg_T_69 = bits(state_reg_touch_way_sized_3, 1, 0)
node _state_reg_set_left_older_T_10 = bits(_state_reg_T_69, 1, 1)
node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0))
node state_reg_left_subtree_state_10 = bits(state_reg_left_subtree_state_9, 1, 1)
node state_reg_right_subtree_state_10 = bits(state_reg_left_subtree_state_9, 0, 0)
node _state_reg_T_70 = bits(_state_reg_T_69, 0, 0)
node _state_reg_T_71 = bits(_state_reg_T_70, 0, 0)
node _state_reg_T_72 = eq(_state_reg_T_71, UInt<1>(0h0))
node _state_reg_T_73 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_72)
node _state_reg_T_74 = bits(_state_reg_T_69, 0, 0)
node _state_reg_T_75 = bits(_state_reg_T_74, 0, 0)
node _state_reg_T_76 = eq(_state_reg_T_75, UInt<1>(0h0))
node _state_reg_T_77 = mux(state_reg_set_left_older_10, _state_reg_T_76, state_reg_right_subtree_state_10)
node state_reg_hi_9 = cat(state_reg_set_left_older_10, _state_reg_T_73)
node _state_reg_T_78 = cat(state_reg_hi_9, _state_reg_T_77)
node _state_reg_T_79 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_78)
node _state_reg_T_80 = bits(state_reg_touch_way_sized_3, 1, 0)
node _state_reg_set_left_older_T_11 = bits(_state_reg_T_80, 1, 1)
node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0))
node state_reg_left_subtree_state_11 = bits(state_reg_right_subtree_state_9, 1, 1)
node state_reg_right_subtree_state_11 = bits(state_reg_right_subtree_state_9, 0, 0)
node _state_reg_T_81 = bits(_state_reg_T_80, 0, 0)
node _state_reg_T_82 = bits(_state_reg_T_81, 0, 0)
node _state_reg_T_83 = eq(_state_reg_T_82, UInt<1>(0h0))
node _state_reg_T_84 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_83)
node _state_reg_T_85 = bits(_state_reg_T_80, 0, 0)
node _state_reg_T_86 = bits(_state_reg_T_85, 0, 0)
node _state_reg_T_87 = eq(_state_reg_T_86, UInt<1>(0h0))
node _state_reg_T_88 = mux(state_reg_set_left_older_11, _state_reg_T_87, state_reg_right_subtree_state_11)
node state_reg_hi_10 = cat(state_reg_set_left_older_11, _state_reg_T_84)
node _state_reg_T_89 = cat(state_reg_hi_10, _state_reg_T_88)
node _state_reg_T_90 = mux(state_reg_set_left_older_9, _state_reg_T_89, state_reg_right_subtree_state_9)
node state_reg_hi_11 = cat(state_reg_set_left_older_9, _state_reg_T_79)
node _state_reg_T_91 = cat(state_reg_hi_11, _state_reg_T_90)
connect state_reg_1, _state_reg_T_91
node _T_79 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0))
node _T_80 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg)
node _T_81 = or(_T_79, _T_80)
node _T_82 = and(io.dpath.sfence.valid, _T_81)
when _T_82 :
connect valid_1, UInt<1>(0h0)
node _T_83 = eq(state, UInt<3>(0h1))
node _T_84 = and(stage2_pte_cache_hit, _T_83)
node _T_85 = eq(aux_count, UInt<1>(0h0))
node _T_86 = and(_T_84, _T_85)
node _T_87 = bits(hits_1, 0, 0)
node _T_88 = bits(hits_1, 1, 1)
node _T_89 = bits(hits_1, 2, 2)
node _T_90 = bits(hits_1, 3, 3)
node _T_91 = bits(hits_1, 4, 4)
node _T_92 = bits(hits_1, 5, 5)
node _T_93 = bits(hits_1, 6, 6)
node _T_94 = bits(hits_1, 7, 7)
node _T_95 = mux(_T_87, data_1[0], UInt<1>(0h0))
node _T_96 = mux(_T_88, data_1[1], UInt<1>(0h0))
node _T_97 = mux(_T_89, data_1[2], UInt<1>(0h0))
node _T_98 = mux(_T_90, data_1[3], UInt<1>(0h0))
node _T_99 = mux(_T_91, data_1[4], UInt<1>(0h0))
node _T_100 = mux(_T_92, data_1[5], UInt<1>(0h0))
node _T_101 = mux(_T_93, data_1[6], UInt<1>(0h0))
node _T_102 = mux(_T_94, data_1[7], UInt<1>(0h0))
node _T_103 = or(_T_95, _T_96)
node _T_104 = or(_T_103, _T_97)
node _T_105 = or(_T_104, _T_98)
node _T_106 = or(_T_105, _T_99)
node _T_107 = or(_T_106, _T_100)
node _T_108 = or(_T_107, _T_101)
node _T_109 = or(_T_108, _T_102)
wire stage2_pte_cache_data : UInt<20>
connect stage2_pte_cache_data, _T_109
reg pte_hit : UInt<1>, clock
connect pte_hit, UInt<1>(0h0)
connect io.dpath.perf.pte_miss, UInt<1>(0h0)
node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1))
node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T)
node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0))
node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2)
connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3
node _T_110 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit)
node _T_111 = and(io.dpath.perf.l2hit, _T_110)
node _T_112 = eq(_T_111, UInt<1>(0h0))
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(_T_112, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf
assert(clock, _T_112, UInt<1>(0h1), "") : assert
reg l2_refill : UInt<1>, clock
connect l2_refill, UInt<1>(0h0)
connect l2_refill_wire, l2_refill
connect io.dpath.perf.l2miss, UInt<1>(0h0)
connect io.dpath.perf.l2hit, UInt<1>(0h0)
wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect _WIRE_1.v, UInt<1>(0h0)
connect _WIRE_1.r, UInt<1>(0h0)
connect _WIRE_1.w, UInt<1>(0h0)
connect _WIRE_1.x, UInt<1>(0h0)
connect _WIRE_1.u, UInt<1>(0h0)
connect _WIRE_1.g, UInt<1>(0h0)
connect _WIRE_1.a, UInt<1>(0h0)
connect _WIRE_1.d, UInt<1>(0h0)
connect _WIRE_1.reserved_for_software, UInt<2>(0h0)
connect _WIRE_1.ppn, UInt<44>(0h0)
connect _WIRE_1.reserved_for_future, UInt<10>(0h0)
wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect l2_pte, _WIRE_1
node _invalidated_T = neq(state, UInt<3>(0h0))
node _invalidated_T_1 = and(invalidated, _invalidated_T)
node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1)
connect invalidated, _invalidated_T_2
connect io.mem.keep_clock_enabled, UInt<1>(0h0)
node _io_mem_req_valid_T = eq(state, UInt<3>(0h1))
node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3))
node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1)
connect io.mem.req.valid, _io_mem_req_valid_T_2
connect io.mem.req.bits.phys, UInt<1>(0h1)
connect io.mem.req.bits.cmd, UInt<1>(0h0)
connect io.mem.req.bits.size, UInt<2>(0h2)
connect io.mem.req.bits.signed, UInt<1>(0h0)
connect io.mem.req.bits.addr, UInt<1>(0h0)
connect io.mem.req.bits.dprv, UInt<1>(0h1)
node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0))
node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T)
connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1
invalidate io.mem.req.bits.tag
connect io.mem.req.bits.no_resp, UInt<1>(0h0)
invalidate io.mem.req.bits.no_alloc
invalidate io.mem.req.bits.no_xcpt
invalidate io.mem.req.bits.data
invalidate io.mem.req.bits.mask
node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2))
node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T)
node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf)
connect io.mem.s1_kill, _io_mem_s1_kill_T_2
invalidate io.mem.s1_data.mask
invalidate io.mem.s1_data.data
connect io.mem.s2_kill, UInt<1>(0h0)
node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_1 = xor(_pmaPgLevelHomogeneous_T, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_2 = cvt(_pmaPgLevelHomogeneous_T_1)
node _pmaPgLevelHomogeneous_T_3 = and(_pmaPgLevelHomogeneous_T_2, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_4 = asSInt(_pmaPgLevelHomogeneous_T_3)
node _pmaPgLevelHomogeneous_T_5 = eq(_pmaPgLevelHomogeneous_T_4, asSInt(UInt<1>(0h0)))
node pmaPgLevelHomogeneous_0 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_5)
node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_7 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_10 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_11 = xor(_pmaPgLevelHomogeneous_T_10, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_12 = cvt(_pmaPgLevelHomogeneous_T_11)
node _pmaPgLevelHomogeneous_T_13 = and(_pmaPgLevelHomogeneous_T_12, asSInt(UInt<14>(0h2000)))
node _pmaPgLevelHomogeneous_T_14 = asSInt(_pmaPgLevelHomogeneous_T_13)
node _pmaPgLevelHomogeneous_T_15 = eq(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_16 = xor(_pmaPgLevelHomogeneous_T_10, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_17 = cvt(_pmaPgLevelHomogeneous_T_16)
node _pmaPgLevelHomogeneous_T_18 = and(_pmaPgLevelHomogeneous_T_17, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_19 = asSInt(_pmaPgLevelHomogeneous_T_18)
node _pmaPgLevelHomogeneous_T_20 = eq(_pmaPgLevelHomogeneous_T_19, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_10, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21)
node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23)
node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_26 = xor(_pmaPgLevelHomogeneous_T_10, UInt<21>(0h100000))
node _pmaPgLevelHomogeneous_T_27 = cvt(_pmaPgLevelHomogeneous_T_26)
node _pmaPgLevelHomogeneous_T_28 = and(_pmaPgLevelHomogeneous_T_27, asSInt(UInt<18>(0h2f000)))
node _pmaPgLevelHomogeneous_T_29 = asSInt(_pmaPgLevelHomogeneous_T_28)
node _pmaPgLevelHomogeneous_T_30 = eq(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_31 = xor(_pmaPgLevelHomogeneous_T_10, UInt<26>(0h2000000))
node _pmaPgLevelHomogeneous_T_32 = cvt(_pmaPgLevelHomogeneous_T_31)
node _pmaPgLevelHomogeneous_T_33 = and(_pmaPgLevelHomogeneous_T_32, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_34 = asSInt(_pmaPgLevelHomogeneous_T_33)
node _pmaPgLevelHomogeneous_T_35 = eq(_pmaPgLevelHomogeneous_T_34, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_36 = xor(_pmaPgLevelHomogeneous_T_10, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_37 = cvt(_pmaPgLevelHomogeneous_T_36)
node _pmaPgLevelHomogeneous_T_38 = and(_pmaPgLevelHomogeneous_T_37, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_39 = asSInt(_pmaPgLevelHomogeneous_T_38)
node _pmaPgLevelHomogeneous_T_40 = eq(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_41 = xor(_pmaPgLevelHomogeneous_T_10, UInt<29>(0h10020000))
node _pmaPgLevelHomogeneous_T_42 = cvt(_pmaPgLevelHomogeneous_T_41)
node _pmaPgLevelHomogeneous_T_43 = and(_pmaPgLevelHomogeneous_T_42, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_44 = asSInt(_pmaPgLevelHomogeneous_T_43)
node _pmaPgLevelHomogeneous_T_45 = eq(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_46 = xor(_pmaPgLevelHomogeneous_T_10, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_47 = cvt(_pmaPgLevelHomogeneous_T_46)
node _pmaPgLevelHomogeneous_T_48 = and(_pmaPgLevelHomogeneous_T_47, asSInt(UInt<15>(0h4000)))
node _pmaPgLevelHomogeneous_T_49 = asSInt(_pmaPgLevelHomogeneous_T_48)
node _pmaPgLevelHomogeneous_T_50 = eq(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_51 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_15)
node _pmaPgLevelHomogeneous_T_52 = or(_pmaPgLevelHomogeneous_T_51, _pmaPgLevelHomogeneous_T_20)
node _pmaPgLevelHomogeneous_T_53 = or(_pmaPgLevelHomogeneous_T_52, _pmaPgLevelHomogeneous_T_25)
node _pmaPgLevelHomogeneous_T_54 = or(_pmaPgLevelHomogeneous_T_53, _pmaPgLevelHomogeneous_T_30)
node _pmaPgLevelHomogeneous_T_55 = or(_pmaPgLevelHomogeneous_T_54, _pmaPgLevelHomogeneous_T_35)
node _pmaPgLevelHomogeneous_T_56 = or(_pmaPgLevelHomogeneous_T_55, _pmaPgLevelHomogeneous_T_40)
node _pmaPgLevelHomogeneous_T_57 = or(_pmaPgLevelHomogeneous_T_56, _pmaPgLevelHomogeneous_T_45)
node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_57, _pmaPgLevelHomogeneous_T_50)
node _pmaPgLevelHomogeneous_T_58 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_59 = xor(_pmaPgLevelHomogeneous_T_10, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_60 = cvt(_pmaPgLevelHomogeneous_T_59)
node _pmaPgLevelHomogeneous_T_61 = and(_pmaPgLevelHomogeneous_T_60, asSInt(UInt<33>(0h98110000)))
node _pmaPgLevelHomogeneous_T_62 = asSInt(_pmaPgLevelHomogeneous_T_61)
node _pmaPgLevelHomogeneous_T_63 = eq(_pmaPgLevelHomogeneous_T_62, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_64 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_63)
node _pmaPgLevelHomogeneous_T_65 = eq(_pmaPgLevelHomogeneous_T_64, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_66 = xor(_pmaPgLevelHomogeneous_T_10, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_67 = cvt(_pmaPgLevelHomogeneous_T_66)
node _pmaPgLevelHomogeneous_T_68 = and(_pmaPgLevelHomogeneous_T_67, asSInt(UInt<33>(0h9a113000)))
node _pmaPgLevelHomogeneous_T_69 = asSInt(_pmaPgLevelHomogeneous_T_68)
node _pmaPgLevelHomogeneous_T_70 = eq(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_71 = xor(_pmaPgLevelHomogeneous_T_10, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_72 = cvt(_pmaPgLevelHomogeneous_T_71)
node _pmaPgLevelHomogeneous_T_73 = and(_pmaPgLevelHomogeneous_T_72, asSInt(UInt<33>(0h9a113000)))
node _pmaPgLevelHomogeneous_T_74 = asSInt(_pmaPgLevelHomogeneous_T_73)
node _pmaPgLevelHomogeneous_T_75 = eq(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_76 = xor(_pmaPgLevelHomogeneous_T_10, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_77 = cvt(_pmaPgLevelHomogeneous_T_76)
node _pmaPgLevelHomogeneous_T_78 = and(_pmaPgLevelHomogeneous_T_77, asSInt(UInt<33>(0h9a110000)))
node _pmaPgLevelHomogeneous_T_79 = asSInt(_pmaPgLevelHomogeneous_T_78)
node _pmaPgLevelHomogeneous_T_80 = eq(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_81 = xor(_pmaPgLevelHomogeneous_T_10, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_82 = cvt(_pmaPgLevelHomogeneous_T_81)
node _pmaPgLevelHomogeneous_T_83 = and(_pmaPgLevelHomogeneous_T_82, asSInt(UInt<33>(0h9a110000)))
node _pmaPgLevelHomogeneous_T_84 = asSInt(_pmaPgLevelHomogeneous_T_83)
node _pmaPgLevelHomogeneous_T_85 = eq(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_86 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_70)
node _pmaPgLevelHomogeneous_T_87 = or(_pmaPgLevelHomogeneous_T_86, _pmaPgLevelHomogeneous_T_75)
node _pmaPgLevelHomogeneous_T_88 = or(_pmaPgLevelHomogeneous_T_87, _pmaPgLevelHomogeneous_T_80)
node _pmaPgLevelHomogeneous_T_89 = or(_pmaPgLevelHomogeneous_T_88, _pmaPgLevelHomogeneous_T_85)
node _pmaPgLevelHomogeneous_T_90 = xor(_pmaPgLevelHomogeneous_T_10, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_91 = cvt(_pmaPgLevelHomogeneous_T_90)
node _pmaPgLevelHomogeneous_T_92 = and(_pmaPgLevelHomogeneous_T_91, asSInt(UInt<33>(0h98110000)))
node _pmaPgLevelHomogeneous_T_93 = asSInt(_pmaPgLevelHomogeneous_T_92)
node _pmaPgLevelHomogeneous_T_94 = eq(_pmaPgLevelHomogeneous_T_93, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_95 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_94)
node _pmaPgLevelHomogeneous_T_96 = eq(_pmaPgLevelHomogeneous_T_95, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_97 = xor(_pmaPgLevelHomogeneous_T_10, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_98 = cvt(_pmaPgLevelHomogeneous_T_97)
node _pmaPgLevelHomogeneous_T_99 = and(_pmaPgLevelHomogeneous_T_98, asSInt(UInt<33>(0h98110000)))
node _pmaPgLevelHomogeneous_T_100 = asSInt(_pmaPgLevelHomogeneous_T_99)
node _pmaPgLevelHomogeneous_T_101 = eq(_pmaPgLevelHomogeneous_T_100, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_102 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_101)
node _pmaPgLevelHomogeneous_T_103 = eq(_pmaPgLevelHomogeneous_T_102, UInt<1>(0h0))
node _pmaHomogeneous_T = eq(count, UInt<1>(0h1))
node pmaHomogeneous = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, pmaPgLevelHomogeneous_0)
node _pmpHomogeneous_T = shl(r_pte.ppn, 12)
wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0)
connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0)
connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0)
node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 21, 21)
node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_2 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T)
node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2)
node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3))
node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4)
node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5)
node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 22)
node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0))
node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9)
node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3))
node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11)
node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12)
node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 12)
node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0))
node _pmpHomogeneous_T_16 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_17 = mux(_pmpHomogeneous_T_16, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8)
node _pmpHomogeneous_T_18 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_17)
node _pmpHomogeneous_T_19 = bits(io.dpath.pmp[0].cfg.a, 0, 0)
node _pmpHomogeneous_T_20 = eq(_pmpHomogeneous_T_19, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T)
node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2)
node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3)
node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T)
node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2)
node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3)
node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1))
node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hfffff000), UInt<32>(0hffc00000))
node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask)
node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1)
node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3)
node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask)
node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5)
node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask)
node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1)
node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3)
node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask)
node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5)
node _pmpHomogeneous_T_21 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper)
node _pmpHomogeneous_T_22 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper)
node _pmpHomogeneous_T_23 = or(_pmpHomogeneous_T_21, _pmpHomogeneous_T_22)
node _pmpHomogeneous_T_24 = or(_pmpHomogeneous_T_20, _pmpHomogeneous_T_23)
node _pmpHomogeneous_T_25 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_18, _pmpHomogeneous_T_24)
node _pmpHomogeneous_T_26 = and(UInt<1>(0h1), _pmpHomogeneous_T_25)
node _pmpHomogeneous_T_27 = bits(io.dpath.pmp[1].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_3 = bits(io.dpath.pmp[1].mask, 21, 21)
node _pmpHomogeneous_maskHomogeneous_T_4 = bits(io.dpath.pmp[1].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_4, _pmpHomogeneous_maskHomogeneous_T_3)
node _pmpHomogeneous_T_28 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_29 = not(_pmpHomogeneous_T_28)
node _pmpHomogeneous_T_30 = or(_pmpHomogeneous_T_29, UInt<2>(0h3))
node _pmpHomogeneous_T_31 = not(_pmpHomogeneous_T_30)
node _pmpHomogeneous_T_32 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_31)
node _pmpHomogeneous_T_33 = shr(_pmpHomogeneous_T_32, 22)
node _pmpHomogeneous_T_34 = neq(_pmpHomogeneous_T_33, UInt<1>(0h0))
node _pmpHomogeneous_T_35 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_36 = not(_pmpHomogeneous_T_35)
node _pmpHomogeneous_T_37 = or(_pmpHomogeneous_T_36, UInt<2>(0h3))
node _pmpHomogeneous_T_38 = not(_pmpHomogeneous_T_37)
node _pmpHomogeneous_T_39 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_38)
node _pmpHomogeneous_T_40 = shr(_pmpHomogeneous_T_39, 12)
node _pmpHomogeneous_T_41 = neq(_pmpHomogeneous_T_40, UInt<1>(0h0))
node _pmpHomogeneous_T_42 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_43 = mux(_pmpHomogeneous_T_42, _pmpHomogeneous_T_41, _pmpHomogeneous_T_34)
node _pmpHomogeneous_T_44 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_43)
node _pmpHomogeneous_T_45 = bits(io.dpath.pmp[1].cfg.a, 0, 0)
node _pmpHomogeneous_T_46 = eq(_pmpHomogeneous_T_45, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5)
node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7)
node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8)
node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5)
node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7)
node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8)
node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_1 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_1, UInt<32>(0hfffff000), UInt<32>(0hffc00000))
node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1)
node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7)
node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9)
node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1)
node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11)
node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1)
node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7)
node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9)
node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1)
node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11)
node _pmpHomogeneous_T_47 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1)
node _pmpHomogeneous_T_48 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1)
node _pmpHomogeneous_T_49 = or(_pmpHomogeneous_T_47, _pmpHomogeneous_T_48)
node _pmpHomogeneous_T_50 = or(_pmpHomogeneous_T_46, _pmpHomogeneous_T_49)
node _pmpHomogeneous_T_51 = mux(_pmpHomogeneous_T_27, _pmpHomogeneous_T_44, _pmpHomogeneous_T_50)
node _pmpHomogeneous_T_52 = and(_pmpHomogeneous_T_26, _pmpHomogeneous_T_51)
node _pmpHomogeneous_T_53 = bits(io.dpath.pmp[2].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_6 = bits(io.dpath.pmp[2].mask, 21, 21)
node _pmpHomogeneous_maskHomogeneous_T_7 = bits(io.dpath.pmp[2].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_8 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_8, _pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_6)
node _pmpHomogeneous_T_54 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_55 = not(_pmpHomogeneous_T_54)
node _pmpHomogeneous_T_56 = or(_pmpHomogeneous_T_55, UInt<2>(0h3))
node _pmpHomogeneous_T_57 = not(_pmpHomogeneous_T_56)
node _pmpHomogeneous_T_58 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_57)
node _pmpHomogeneous_T_59 = shr(_pmpHomogeneous_T_58, 22)
node _pmpHomogeneous_T_60 = neq(_pmpHomogeneous_T_59, UInt<1>(0h0))
node _pmpHomogeneous_T_61 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_62 = not(_pmpHomogeneous_T_61)
node _pmpHomogeneous_T_63 = or(_pmpHomogeneous_T_62, UInt<2>(0h3))
node _pmpHomogeneous_T_64 = not(_pmpHomogeneous_T_63)
node _pmpHomogeneous_T_65 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_64)
node _pmpHomogeneous_T_66 = shr(_pmpHomogeneous_T_65, 12)
node _pmpHomogeneous_T_67 = neq(_pmpHomogeneous_T_66, UInt<1>(0h0))
node _pmpHomogeneous_T_68 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_69 = mux(_pmpHomogeneous_T_68, _pmpHomogeneous_T_67, _pmpHomogeneous_T_60)
node _pmpHomogeneous_T_70 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_69)
node _pmpHomogeneous_T_71 = bits(io.dpath.pmp[2].cfg.a, 0, 0)
node _pmpHomogeneous_T_72 = eq(_pmpHomogeneous_T_71, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10)
node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12)
node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13)
node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10)
node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12)
node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13)
node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hfffff000), UInt<32>(0hffc00000))
node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2)
node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13)
node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15)
node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2)
node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17)
node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2)
node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13)
node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15)
node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2)
node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17)
node _pmpHomogeneous_T_73 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2)
node _pmpHomogeneous_T_74 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2)
node _pmpHomogeneous_T_75 = or(_pmpHomogeneous_T_73, _pmpHomogeneous_T_74)
node _pmpHomogeneous_T_76 = or(_pmpHomogeneous_T_72, _pmpHomogeneous_T_75)
node _pmpHomogeneous_T_77 = mux(_pmpHomogeneous_T_53, _pmpHomogeneous_T_70, _pmpHomogeneous_T_76)
node _pmpHomogeneous_T_78 = and(_pmpHomogeneous_T_52, _pmpHomogeneous_T_77)
node _pmpHomogeneous_T_79 = bits(io.dpath.pmp[3].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[3].mask, 21, 21)
node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[3].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_9)
node _pmpHomogeneous_T_80 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_81 = not(_pmpHomogeneous_T_80)
node _pmpHomogeneous_T_82 = or(_pmpHomogeneous_T_81, UInt<2>(0h3))
node _pmpHomogeneous_T_83 = not(_pmpHomogeneous_T_82)
node _pmpHomogeneous_T_84 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_83)
node _pmpHomogeneous_T_85 = shr(_pmpHomogeneous_T_84, 22)
node _pmpHomogeneous_T_86 = neq(_pmpHomogeneous_T_85, UInt<1>(0h0))
node _pmpHomogeneous_T_87 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_88 = not(_pmpHomogeneous_T_87)
node _pmpHomogeneous_T_89 = or(_pmpHomogeneous_T_88, UInt<2>(0h3))
node _pmpHomogeneous_T_90 = not(_pmpHomogeneous_T_89)
node _pmpHomogeneous_T_91 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_90)
node _pmpHomogeneous_T_92 = shr(_pmpHomogeneous_T_91, 12)
node _pmpHomogeneous_T_93 = neq(_pmpHomogeneous_T_92, UInt<1>(0h0))
node _pmpHomogeneous_T_94 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_95 = mux(_pmpHomogeneous_T_94, _pmpHomogeneous_T_93, _pmpHomogeneous_T_86)
node _pmpHomogeneous_T_96 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_95)
node _pmpHomogeneous_T_97 = bits(io.dpath.pmp[3].cfg.a, 0, 0)
node _pmpHomogeneous_T_98 = eq(_pmpHomogeneous_T_97, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15)
node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17)
node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18)
node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15)
node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17)
node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18)
node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_3 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_3, UInt<32>(0hfffff000), UInt<32>(0hffc00000))
node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3)
node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19)
node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21)
node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3)
node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23)
node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3)
node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19)
node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21)
node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3)
node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23)
node _pmpHomogeneous_T_99 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3)
node _pmpHomogeneous_T_100 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3)
node _pmpHomogeneous_T_101 = or(_pmpHomogeneous_T_99, _pmpHomogeneous_T_100)
node _pmpHomogeneous_T_102 = or(_pmpHomogeneous_T_98, _pmpHomogeneous_T_101)
node _pmpHomogeneous_T_103 = mux(_pmpHomogeneous_T_79, _pmpHomogeneous_T_96, _pmpHomogeneous_T_102)
node _pmpHomogeneous_T_104 = and(_pmpHomogeneous_T_78, _pmpHomogeneous_T_103)
node _pmpHomogeneous_T_105 = bits(io.dpath.pmp[4].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_12 = bits(io.dpath.pmp[4].mask, 21, 21)
node _pmpHomogeneous_maskHomogeneous_T_13 = bits(io.dpath.pmp[4].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_14 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_14, _pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_12)
node _pmpHomogeneous_T_106 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_107 = not(_pmpHomogeneous_T_106)
node _pmpHomogeneous_T_108 = or(_pmpHomogeneous_T_107, UInt<2>(0h3))
node _pmpHomogeneous_T_109 = not(_pmpHomogeneous_T_108)
node _pmpHomogeneous_T_110 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_109)
node _pmpHomogeneous_T_111 = shr(_pmpHomogeneous_T_110, 22)
node _pmpHomogeneous_T_112 = neq(_pmpHomogeneous_T_111, UInt<1>(0h0))
node _pmpHomogeneous_T_113 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113)
node _pmpHomogeneous_T_115 = or(_pmpHomogeneous_T_114, UInt<2>(0h3))
node _pmpHomogeneous_T_116 = not(_pmpHomogeneous_T_115)
node _pmpHomogeneous_T_117 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_116)
node _pmpHomogeneous_T_118 = shr(_pmpHomogeneous_T_117, 12)
node _pmpHomogeneous_T_119 = neq(_pmpHomogeneous_T_118, UInt<1>(0h0))
node _pmpHomogeneous_T_120 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_121 = mux(_pmpHomogeneous_T_120, _pmpHomogeneous_T_119, _pmpHomogeneous_T_112)
node _pmpHomogeneous_T_122 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_121)
node _pmpHomogeneous_T_123 = bits(io.dpath.pmp[4].cfg.a, 0, 0)
node _pmpHomogeneous_T_124 = eq(_pmpHomogeneous_T_123, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20)
node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22)
node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23)
node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20)
node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22)
node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23)
node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), UInt<32>(0hffc00000))
node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4)
node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25)
node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27)
node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4)
node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29)
node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4)
node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25)
node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27)
node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4)
node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29)
node _pmpHomogeneous_T_125 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4)
node _pmpHomogeneous_T_126 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4)
node _pmpHomogeneous_T_127 = or(_pmpHomogeneous_T_125, _pmpHomogeneous_T_126)
node _pmpHomogeneous_T_128 = or(_pmpHomogeneous_T_124, _pmpHomogeneous_T_127)
node _pmpHomogeneous_T_129 = mux(_pmpHomogeneous_T_105, _pmpHomogeneous_T_122, _pmpHomogeneous_T_128)
node _pmpHomogeneous_T_130 = and(_pmpHomogeneous_T_104, _pmpHomogeneous_T_129)
node _pmpHomogeneous_T_131 = bits(io.dpath.pmp[5].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_15 = bits(io.dpath.pmp[5].mask, 21, 21)
node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[5].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_17 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_16, _pmpHomogeneous_maskHomogeneous_T_15)
node _pmpHomogeneous_T_132 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_133 = not(_pmpHomogeneous_T_132)
node _pmpHomogeneous_T_134 = or(_pmpHomogeneous_T_133, UInt<2>(0h3))
node _pmpHomogeneous_T_135 = not(_pmpHomogeneous_T_134)
node _pmpHomogeneous_T_136 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_135)
node _pmpHomogeneous_T_137 = shr(_pmpHomogeneous_T_136, 22)
node _pmpHomogeneous_T_138 = neq(_pmpHomogeneous_T_137, UInt<1>(0h0))
node _pmpHomogeneous_T_139 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_140 = not(_pmpHomogeneous_T_139)
node _pmpHomogeneous_T_141 = or(_pmpHomogeneous_T_140, UInt<2>(0h3))
node _pmpHomogeneous_T_142 = not(_pmpHomogeneous_T_141)
node _pmpHomogeneous_T_143 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_142)
node _pmpHomogeneous_T_144 = shr(_pmpHomogeneous_T_143, 12)
node _pmpHomogeneous_T_145 = neq(_pmpHomogeneous_T_144, UInt<1>(0h0))
node _pmpHomogeneous_T_146 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_147 = mux(_pmpHomogeneous_T_146, _pmpHomogeneous_T_145, _pmpHomogeneous_T_138)
node _pmpHomogeneous_T_148 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_147)
node _pmpHomogeneous_T_149 = bits(io.dpath.pmp[5].cfg.a, 0, 0)
node _pmpHomogeneous_T_150 = eq(_pmpHomogeneous_T_149, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25)
node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27)
node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28)
node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25)
node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27)
node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28)
node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hfffff000), UInt<32>(0hffc00000))
node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5)
node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31)
node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33)
node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5)
node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35)
node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5)
node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31)
node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33)
node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5)
node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35)
node _pmpHomogeneous_T_151 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5)
node _pmpHomogeneous_T_152 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5)
node _pmpHomogeneous_T_153 = or(_pmpHomogeneous_T_151, _pmpHomogeneous_T_152)
node _pmpHomogeneous_T_154 = or(_pmpHomogeneous_T_150, _pmpHomogeneous_T_153)
node _pmpHomogeneous_T_155 = mux(_pmpHomogeneous_T_131, _pmpHomogeneous_T_148, _pmpHomogeneous_T_154)
node _pmpHomogeneous_T_156 = and(_pmpHomogeneous_T_130, _pmpHomogeneous_T_155)
node _pmpHomogeneous_T_157 = bits(io.dpath.pmp[6].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[6].mask, 21, 21)
node _pmpHomogeneous_maskHomogeneous_T_19 = bits(io.dpath.pmp[6].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_20 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_20, _pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_18)
node _pmpHomogeneous_T_158 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_159 = not(_pmpHomogeneous_T_158)
node _pmpHomogeneous_T_160 = or(_pmpHomogeneous_T_159, UInt<2>(0h3))
node _pmpHomogeneous_T_161 = not(_pmpHomogeneous_T_160)
node _pmpHomogeneous_T_162 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_161)
node _pmpHomogeneous_T_163 = shr(_pmpHomogeneous_T_162, 22)
node _pmpHomogeneous_T_164 = neq(_pmpHomogeneous_T_163, UInt<1>(0h0))
node _pmpHomogeneous_T_165 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_166 = not(_pmpHomogeneous_T_165)
node _pmpHomogeneous_T_167 = or(_pmpHomogeneous_T_166, UInt<2>(0h3))
node _pmpHomogeneous_T_168 = not(_pmpHomogeneous_T_167)
node _pmpHomogeneous_T_169 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_168)
node _pmpHomogeneous_T_170 = shr(_pmpHomogeneous_T_169, 12)
node _pmpHomogeneous_T_171 = neq(_pmpHomogeneous_T_170, UInt<1>(0h0))
node _pmpHomogeneous_T_172 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_173 = mux(_pmpHomogeneous_T_172, _pmpHomogeneous_T_171, _pmpHomogeneous_T_164)
node _pmpHomogeneous_T_174 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_173)
node _pmpHomogeneous_T_175 = bits(io.dpath.pmp[6].cfg.a, 0, 0)
node _pmpHomogeneous_T_176 = eq(_pmpHomogeneous_T_175, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30)
node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32)
node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33)
node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30)
node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32)
node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33)
node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_6 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_6, UInt<32>(0hfffff000), UInt<32>(0hffc00000))
node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6)
node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37)
node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39)
node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6)
node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41)
node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6)
node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37)
node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39)
node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6)
node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41)
node _pmpHomogeneous_T_177 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6)
node _pmpHomogeneous_T_178 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6)
node _pmpHomogeneous_T_179 = or(_pmpHomogeneous_T_177, _pmpHomogeneous_T_178)
node _pmpHomogeneous_T_180 = or(_pmpHomogeneous_T_176, _pmpHomogeneous_T_179)
node _pmpHomogeneous_T_181 = mux(_pmpHomogeneous_T_157, _pmpHomogeneous_T_174, _pmpHomogeneous_T_180)
node _pmpHomogeneous_T_182 = and(_pmpHomogeneous_T_156, _pmpHomogeneous_T_181)
node _pmpHomogeneous_T_183 = bits(io.dpath.pmp[7].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_21 = bits(io.dpath.pmp[7].mask, 21, 21)
node _pmpHomogeneous_maskHomogeneous_T_22 = bits(io.dpath.pmp[7].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_22, _pmpHomogeneous_maskHomogeneous_T_21)
node _pmpHomogeneous_T_184 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_185 = not(_pmpHomogeneous_T_184)
node _pmpHomogeneous_T_186 = or(_pmpHomogeneous_T_185, UInt<2>(0h3))
node _pmpHomogeneous_T_187 = not(_pmpHomogeneous_T_186)
node _pmpHomogeneous_T_188 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_187)
node _pmpHomogeneous_T_189 = shr(_pmpHomogeneous_T_188, 22)
node _pmpHomogeneous_T_190 = neq(_pmpHomogeneous_T_189, UInt<1>(0h0))
node _pmpHomogeneous_T_191 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_192 = not(_pmpHomogeneous_T_191)
node _pmpHomogeneous_T_193 = or(_pmpHomogeneous_T_192, UInt<2>(0h3))
node _pmpHomogeneous_T_194 = not(_pmpHomogeneous_T_193)
node _pmpHomogeneous_T_195 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_194)
node _pmpHomogeneous_T_196 = shr(_pmpHomogeneous_T_195, 12)
node _pmpHomogeneous_T_197 = neq(_pmpHomogeneous_T_196, UInt<1>(0h0))
node _pmpHomogeneous_T_198 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_199 = mux(_pmpHomogeneous_T_198, _pmpHomogeneous_T_197, _pmpHomogeneous_T_190)
node _pmpHomogeneous_T_200 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_199)
node _pmpHomogeneous_T_201 = bits(io.dpath.pmp[7].cfg.a, 0, 0)
node _pmpHomogeneous_T_202 = eq(_pmpHomogeneous_T_201, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35)
node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37)
node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38)
node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35)
node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37)
node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38)
node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<1>(0h1))
node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hfffff000), UInt<32>(0hffc00000))
node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7)
node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43)
node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45)
node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7)
node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47)
node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7)
node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43)
node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45)
node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7)
node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47)
node _pmpHomogeneous_T_203 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7)
node _pmpHomogeneous_T_204 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7)
node _pmpHomogeneous_T_205 = or(_pmpHomogeneous_T_203, _pmpHomogeneous_T_204)
node _pmpHomogeneous_T_206 = or(_pmpHomogeneous_T_202, _pmpHomogeneous_T_205)
node _pmpHomogeneous_T_207 = mux(_pmpHomogeneous_T_183, _pmpHomogeneous_T_200, _pmpHomogeneous_T_206)
node pmpHomogeneous = and(_pmpHomogeneous_T_182, _pmpHomogeneous_T_207)
node homogeneous = and(pmaHomogeneous, pmpHomogeneous)
connect io.requestor[0].resp.valid, resp_valid[0]
connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[0].resp.bits.ae_final, resp_ae_final
connect io.requestor[0].resp.bits.pf, resp_pf
connect io.requestor[0].resp.bits.gf, resp_gf
connect io.requestor[0].resp.bits.hr, resp_hr
connect io.requestor[0].resp.bits.hw, resp_hw
connect io.requestor[0].resp.bits.hx, resp_hx
connect io.requestor[0].resp.bits.pte, r_pte
connect io.requestor[0].resp.bits.level, max_count
node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T
node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T
connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1)
node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<1>(0h1))
node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3)
node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 10)
node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 9, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6)
node _io_requestor_0_resp_bits_gpa_bits_T_8 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_7)
node _io_requestor_0_resp_bits_gpa_bits_T_9 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, gpa_pgoff)
connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_9
node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T
connect io.requestor[0].ptbr, io.dpath.ptbr
connect io.requestor[0].hgatp, io.dpath.hgatp
connect io.requestor[0].vsatp, io.dpath.vsatp
connect io.requestor[0].customCSRs, io.dpath.customCSRs
connect io.requestor[0].status, io.dpath.status
connect io.requestor[0].hstatus, io.dpath.hstatus
connect io.requestor[0].gstatus, io.dpath.gstatus
connect io.requestor[0].pmp, io.dpath.pmp
connect io.requestor[1].resp.valid, resp_valid[1]
connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[1].resp.bits.ae_final, resp_ae_final
connect io.requestor[1].resp.bits.pf, resp_pf
connect io.requestor[1].resp.bits.gf, resp_gf
connect io.requestor[1].resp.bits.hr, resp_hr
connect io.requestor[1].resp.bits.hw, resp_hw
connect io.requestor[1].resp.bits.hx, resp_hx
connect io.requestor[1].resp.bits.pte, r_pte
connect io.requestor[1].resp.bits.level, max_count
node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T
node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T
connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1)
node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<1>(0h1))
node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3)
node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 10)
node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 9, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6)
node _io_requestor_1_resp_bits_gpa_bits_T_8 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_7)
node _io_requestor_1_resp_bits_gpa_bits_T_9 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, gpa_pgoff)
connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_9
node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T
connect io.requestor[1].ptbr, io.dpath.ptbr
connect io.requestor[1].hgatp, io.dpath.hgatp
connect io.requestor[1].vsatp, io.dpath.vsatp
connect io.requestor[1].customCSRs, io.dpath.customCSRs
connect io.requestor[1].status, io.dpath.status
connect io.requestor[1].hstatus, io.dpath.hstatus
connect io.requestor[1].gstatus, io.dpath.gstatus
connect io.requestor[1].pmp, io.dpath.pmp
wire next_state : UInt
connect next_state, state
inst state_barrier of OptimizationBarrier_UInt
connect state_barrier.clock, clock
connect state_barrier.reset, reset
connect state_barrier.io.x, next_state
connect state, state_barrier.io.y
wire do_switch : UInt<1>
connect do_switch, UInt<1>(0h0)
node _T_116 = eq(UInt<3>(0h0), state)
when _T_116 :
node _T_117 = and(arb.io.out.ready, arb.io.out.valid)
when _T_117 :
node _satp_initial_count_T = sub(UInt<2>(0h2), UInt<2>(0h2))
node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1)
node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0))
node satp_initial_count = tail(_satp_initial_count_T_2, 1)
node _vsatp_initial_count_T = sub(UInt<2>(0h2), UInt<2>(0h2))
node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1)
node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0))
node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1)
node _hgatp_initial_count_T = sub(UInt<2>(0h2), UInt<2>(0h2))
node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1)
node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0))
node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1)
node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
connect r_req, arb.io.out.bits.bits
connect r_req_dest, arb.io.chosen
node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0))
connect next_state, _next_state_T
connect stage2, arb.io.out.bits.bits.stage2
node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0))
node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T)
connect stage2_final, _stage2_final_T_1
node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
connect count, _count_T_3
node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0))
connect aux_count, _aux_count_T
connect aux_pte.ppn, aux_ppn
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect resp_ae_ptw, UInt<1>(0h0)
connect resp_ae_final, UInt<1>(0h0)
connect resp_pf, UInt<1>(0h0)
node _resp_gf_count_T = sub(UInt<2>(0h2), UInt<2>(0h2))
node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1)
node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0))
node resp_gf_count = tail(_resp_gf_count_T_2, 1)
node resp_gf_idxs_0 = shr(aux_ppn, 22)
wire _resp_gf_WIRE : UInt<0>[1]
connect _resp_gf_WIRE[0], resp_gf_idxs_0
node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0))
node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0))
node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2)
connect resp_gf, _resp_gf_T_2
connect resp_hr, UInt<1>(0h1)
connect resp_hw, UInt<1>(0h1)
connect resp_hx, UInt<1>(0h1)
connect resp_fragmented_superpage, UInt<1>(0h0)
connect r_hgatp, io.dpath.hgatp
node _T_118 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0))
node _T_119 = or(_T_118, arb.io.out.bits.bits.stage2)
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_1
assert(clock, _T_119, UInt<1>(0h1), "") : assert_1
else :
node _T_123 = eq(UInt<3>(0h1), state)
when _T_123 :
node _T_124 = eq(count, r_hgatp_initial_count)
node _T_125 = and(stage2, _T_124)
when _T_125 :
node _gpa_pgoff_T = eq(aux_count, UInt<1>(0h1))
node _gpa_pgoff_T_1 = shl(r_req.addr, 2)
node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0))
connect gpa_pgoff, _gpa_pgoff_T_2
when stage2_pte_cache_hit :
node _aux_count_T_1 = add(aux_count, UInt<1>(0h1))
node _aux_count_T_2 = tail(_aux_count_T_1, 1)
connect aux_count, _aux_count_T_2
connect aux_pte.ppn, stage2_pte_cache_data
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect pte_hit, UInt<1>(0h1)
else :
when pte_cache_hit :
node _count_T_4 = add(count, UInt<1>(0h1))
node _count_T_5 = tail(_count_T_4, 1)
connect count, _count_T_5
connect pte_hit, UInt<1>(0h1)
else :
node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1))
connect next_state, _next_state_T_1
when resp_gf :
connect next_state, UInt<3>(0h0)
node _T_126 = or(r_req_dest, UInt<1>(0h0))
node _T_127 = bits(_T_126, 0, 0)
connect resp_valid[_T_127], UInt<1>(0h1)
else :
node _T_128 = eq(UInt<3>(0h2), state)
when _T_128 :
node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4))
connect next_state, _next_state_T_2
else :
node _T_129 = eq(UInt<3>(0h4), state)
when _T_129 :
connect next_state, UInt<3>(0h5)
node _io_dpath_perf_pte_miss_T = lt(count, UInt<1>(0h1))
connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T
when io.mem.s2_xcpt.ae.ld :
connect resp_ae_ptw, UInt<1>(0h1)
connect next_state, UInt<3>(0h0)
node _T_130 = or(r_req_dest, UInt<1>(0h0))
node _T_131 = bits(_T_130, 0, 0)
connect resp_valid[_T_131], UInt<1>(0h1)
else :
node _T_132 = eq(UInt<3>(0h7), state)
when _T_132 :
connect next_state, UInt<3>(0h0)
node _T_133 = or(r_req_dest, UInt<1>(0h0))
node _T_134 = bits(_T_133, 0, 0)
connect resp_valid[_T_134], UInt<1>(0h1)
node _T_135 = eq(homogeneous, UInt<1>(0h0))
when _T_135 :
connect count, UInt<1>(0h1)
connect resp_fragmented_superpage, UInt<1>(0h1)
when do_both_stages :
connect resp_fragmented_superpage, UInt<1>(0h1)
node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<1>(0h1))
node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1))
node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hfffffffffff), UInt<44>(0hffffffffc00))
node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 10)
node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 9, 0)
node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1)
node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1))
node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T, pte.ppn, merged_pte_stage1_ppns_0)
node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask)
wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect merged_pte, aux_pte
connect merged_pte.ppn, _merged_pte_T
node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T)
node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0))
node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2)
node _r_pte_T_4 = eq(state, UInt<3>(0h1))
node _r_pte_T_5 = and(_r_pte_T_4, stage2_pte_cache_hit)
node _r_pte_count_T = sub(UInt<2>(0h2), UInt<2>(0h2))
node _r_pte_count_T_1 = tail(_r_pte_count_T, 1)
node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0))
node r_pte_count = tail(_r_pte_count_T_2, 1)
node r_pte_idxs_0 = shr(stage2_pte_cache_data, 20)
wire r_pte_lsbs : UInt<2>
connect r_pte_lsbs, r_pte_idxs_0
wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte, l2_pte
node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs)
connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1
node _r_pte_T_6 = eq(state, UInt<3>(0h1))
node _r_pte_T_7 = and(_r_pte_T_6, pte_cache_hit)
wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_1, l2_pte
connect r_pte_pte_1.ppn, pte_cache_data
node _r_pte_count_T_3 = sub(UInt<2>(0h2), UInt<2>(0h2))
node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1)
node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0))
node r_pte_count_1 = tail(_r_pte_count_T_5, 1)
node r_pte_idxs_0_1 = shr(pte.ppn, 20)
wire r_pte_lsbs_1 : UInt<2>
connect r_pte_lsbs_1, r_pte_idxs_0_1
wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_2, r_pte
node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1)
connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3
node _r_pte_T_8 = eq(traverse, UInt<1>(0h0))
node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1)
node _r_pte_T_10 = and(_r_pte_T_9, stage2)
node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte)
node _r_pte_T_12 = eq(state, UInt<3>(0h7))
node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0))
node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13)
node _r_pte_T_15 = neq(count, UInt<1>(0h1))
node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15)
node _r_pte_T_17 = shr(r_pte.ppn, 10)
node _r_pte_T_18 = bits(r_req.addr, 9, 0)
node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18)
wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_3, r_pte
connect r_pte_pte_3.ppn, _r_pte_T_19
node _r_pte_T_20 = and(arb.io.out.ready, arb.io.out.valid)
node _r_pte_count_T_6 = sub(UInt<2>(0h2), UInt<2>(0h2))
node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1)
node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0))
node r_pte_count_2 = tail(_r_pte_count_T_8, 1)
node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 20)
wire r_pte_lsbs_2 : UInt<2>
connect r_pte_lsbs_2, r_pte_idxs_0_2
wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_4, r_pte
node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2)
node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2)
connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5
wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_5, r_pte
connect r_pte_pte_5.ppn, satp.ppn
node _r_pte_T_21 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5)
node _r_pte_T_22 = mux(_r_pte_T_20, _r_pte_T_21, r_pte)
node _r_pte_T_23 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_22)
node _r_pte_T_24 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_23)
node _r_pte_T_25 = mux(do_switch, r_pte_pte_2, _r_pte_T_24)
node _r_pte_T_26 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_25)
node _r_pte_T_27 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_26)
node _r_pte_T_28 = mux(_r_pte_T_3, l2_pte, _r_pte_T_27)
inst r_pte_barrier of OptimizationBarrier_PTE
connect r_pte_barrier.clock, clock
connect r_pte_barrier.reset, reset
connect r_pte_barrier.io.x.v, _r_pte_T_28.v
connect r_pte_barrier.io.x.r, _r_pte_T_28.r
connect r_pte_barrier.io.x.w, _r_pte_T_28.w
connect r_pte_barrier.io.x.x, _r_pte_T_28.x
connect r_pte_barrier.io.x.u, _r_pte_T_28.u
connect r_pte_barrier.io.x.g, _r_pte_T_28.g
connect r_pte_barrier.io.x.a, _r_pte_T_28.a
connect r_pte_barrier.io.x.d, _r_pte_T_28.d
connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_28.reserved_for_software
connect r_pte_barrier.io.x.ppn, _r_pte_T_28.ppn
connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_28.reserved_for_future
connect r_pte, r_pte_barrier.io.y
node _T_136 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_137 = and(UInt<1>(0h0), _T_136)
node _T_138 = eq(resp_gf, UInt<1>(0h0))
node _T_139 = and(_T_137, _T_138)
when _T_139 :
node _T_140 = eq(state, UInt<3>(0h1))
node _T_141 = eq(state, UInt<3>(0h2))
node _T_142 = or(_T_140, _T_141)
node _T_143 = asUInt(reset)
node _T_144 = eq(_T_143, UInt<1>(0h0))
when _T_144 :
node _T_145 = eq(_T_142, UInt<1>(0h0))
when _T_145 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_2
assert(clock, _T_142, UInt<1>(0h1), "") : assert_2
connect next_state, UInt<3>(0h0)
node _T_146 = or(r_req_dest, UInt<1>(0h0))
node _T_147 = bits(_T_146, 0, 0)
connect resp_valid[_T_147], UInt<1>(0h1)
connect count, UInt<1>(0h1)
when mem_resp_valid :
node _T_148 = eq(state, UInt<3>(0h5))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_3
assert(clock, _T_148, UInt<1>(0h1), "") : assert_3
connect next_state, UInt<3>(0h1)
when traverse :
node _T_152 = eq(stage2, UInt<1>(0h0))
node _T_153 = and(do_both_stages, _T_152)
when _T_153 :
connect do_switch, UInt<1>(0h1)
node _count_T_6 = add(count, UInt<1>(0h1))
node _count_T_7 = tail(_count_T_6, 1)
connect count, _count_T_7
else :
node _gf_T = eq(stage2_final, UInt<1>(0h0))
node _gf_T_1 = and(stage2, _gf_T)
node _gf_T_2 = eq(pte.w, UInt<1>(0h0))
node _gf_T_3 = and(pte.x, _gf_T_2)
node _gf_T_4 = or(pte.r, _gf_T_3)
node _gf_T_5 = and(pte.v, _gf_T_4)
node _gf_T_6 = and(_gf_T_5, pte.a)
node _gf_T_7 = and(_gf_T_6, pte.r)
node _gf_T_8 = and(_gf_T_7, pte.u)
node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0))
node _gf_T_10 = and(_gf_T_1, _gf_T_9)
node _gf_T_11 = eq(pte.w, UInt<1>(0h0))
node _gf_T_12 = and(pte.x, _gf_T_11)
node _gf_T_13 = or(pte.r, _gf_T_12)
node _gf_T_14 = and(pte.v, _gf_T_13)
node _gf_T_15 = and(_gf_T_14, pte.a)
node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _gf_T_17 = and(_gf_T_15, _gf_T_16)
node _gf_T_18 = and(_gf_T_17, invalid_gpa)
node gf = or(_gf_T_10, _gf_T_18)
node ae = and(pte.v, invalid_paddr)
node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0))
node pf = and(pte.v, _pf_T)
node _success_T = eq(ae, UInt<1>(0h0))
node _success_T_1 = and(pte.v, _success_T)
node _success_T_2 = eq(pf, UInt<1>(0h0))
node _success_T_3 = and(_success_T_1, _success_T_2)
node _success_T_4 = eq(gf, UInt<1>(0h0))
node success = and(_success_T_3, _success_T_4)
node _T_154 = eq(stage2_final, UInt<1>(0h0))
node _T_155 = and(do_both_stages, _T_154)
node _T_156 = and(_T_155, success)
when _T_156 :
when stage2 :
connect stage2, UInt<1>(0h0)
connect count, aux_count
else :
connect stage2_final, UInt<1>(0h1)
connect do_switch, UInt<1>(0h1)
else :
node _l2_refill_T = eq(count, UInt<1>(0h1))
node _l2_refill_T_1 = and(success, _l2_refill_T)
node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0))
node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2)
node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0))
node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0))
node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5)
node _l2_refill_T_7 = eq(aux_count, UInt<1>(0h1))
node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7)
node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9)
node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10)
node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11)
node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a)
node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w)
node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d)
node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u)
node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17)
node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18)
node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19)
node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a)
node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x)
node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u)
node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23)
node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24)
node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25)
node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26)
connect l2_refill, _l2_refill_T_27
connect count, max_count
node _T_157 = eq(count, UInt<1>(0h1))
node _T_158 = eq(do_both_stages, UInt<1>(0h0))
node _T_159 = eq(aux_count, UInt<1>(0h1))
node _T_160 = or(_T_158, _T_159)
node _T_161 = and(_T_157, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = and(UInt<1>(0h0), _T_162)
when _T_163 :
connect next_state, UInt<3>(0h7)
else :
connect next_state, UInt<3>(0h0)
node _T_164 = or(r_req_dest, UInt<1>(0h0))
node _T_165 = bits(_T_164, 0, 0)
connect resp_valid[_T_165], UInt<1>(0h1)
node _resp_ae_ptw_T = lt(count, UInt<1>(0h1))
node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T)
node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0))
node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2)
node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4)
node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0))
node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6)
node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0))
node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8)
node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0))
node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10)
node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0))
node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12)
node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14)
node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15)
connect resp_ae_ptw, _resp_ae_ptw_T_16
node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0))
node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T)
node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1)
node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2)
node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a)
node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4)
connect resp_ae_final, _resp_ae_final_T_5
node _resp_pf_T = eq(stage2, UInt<1>(0h0))
node _resp_pf_T_1 = and(pf, _resp_pf_T)
connect resp_pf, _resp_pf_T_1
node _resp_gf_T_3 = and(pf, stage2)
node _resp_gf_T_4 = or(gf, _resp_gf_T_3)
connect resp_gf, _resp_gf_T_4
node _resp_hr_T = eq(stage2, UInt<1>(0h0))
node _resp_hr_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hr_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2)
node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4)
node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5)
node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6)
node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a)
node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r)
node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u)
node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10)
node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11)
connect resp_hr, _resp_hr_T_12
node _resp_hw_T = eq(stage2, UInt<1>(0h0))
node _resp_hw_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hw_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2)
node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4)
node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5)
node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6)
node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a)
node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w)
node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d)
node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u)
node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11)
node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12)
connect resp_hw, _resp_hw_T_13
node _resp_hx_T = eq(stage2, UInt<1>(0h0))
node _resp_hx_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hx_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2)
node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4)
node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5)
node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6)
node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a)
node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x)
node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u)
node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10)
node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11)
connect resp_hx, _resp_hx_T_12
when io.mem.s2_nack :
node _T_166 = eq(state, UInt<3>(0h4))
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(_T_166, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_4
assert(clock, _T_166, UInt<1>(0h1), "") : assert_4
connect next_state, UInt<3>(0h1)
when do_switch :
node _aux_count_T_3 = add(count, UInt<1>(0h1))
node _aux_count_T_4 = tail(_aux_count_T_3, 1)
node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count)
connect aux_count, _aux_count_T_5
connect count, r_hgatp_initial_count
node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 10)
node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 9, 0)
node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1)
node _aux_pte_T = eq(count, UInt<1>(0h1))
node _aux_pte_T_1 = mux(_aux_pte_T, pte.ppn, aux_pte_s1_ppns_0)
wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect aux_pte_pte, pte
connect aux_pte_pte.ppn, _aux_pte_T_1
node _aux_pte_T_2 = mux(traverse, pte, aux_pte_pte)
connect aux_pte, _aux_pte_T_2
connect stage2, UInt<1>(0h1)
node _leaf_T = eq(traverse, UInt<1>(0h0))
node _leaf_T_1 = and(mem_resp_valid, _leaf_T)
node _leaf_T_2 = eq(count, UInt<1>(0h0))
node leaf = and(_leaf_T_1, _leaf_T_2)
node _T_170 = and(leaf, pte.v)
node _T_171 = eq(invalid_paddr, UInt<1>(0h0))
node _T_172 = and(_T_170, _T_171)
node _T_173 = eq(invalid_gpa, UInt<1>(0h0))
node _T_174 = and(_T_172, _T_173)
node _T_175 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_176 = and(_T_174, _T_175)
node _T_177 = and(leaf, pte.v)
node _T_178 = and(_T_177, invalid_paddr)
node _T_179 = and(leaf, pte.v)
node _T_180 = and(_T_179, invalid_gpa)
node _T_181 = and(leaf, pte.v)
node _T_182 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_183 = and(_T_181, _T_182)
node _T_184 = bits(mem_resp_data, 0, 0)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = and(leaf, _T_185)
node _T_187 = eq(pte.v, UInt<1>(0h0))
node _T_188 = and(leaf, _T_187)
node _T_189 = bits(mem_resp_data, 0, 0)
node _T_190 = and(_T_188, _T_189)
node _leaf_T_3 = eq(traverse, UInt<1>(0h0))
node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3)
node _leaf_T_5 = eq(count, UInt<1>(0h1))
node leaf_1 = and(_leaf_T_4, _leaf_T_5)
node _T_191 = and(leaf_1, pte.v)
node _T_192 = eq(invalid_paddr, UInt<1>(0h0))
node _T_193 = and(_T_191, _T_192)
node _T_194 = eq(invalid_gpa, UInt<1>(0h0))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_197 = and(_T_195, _T_196)
node _T_198 = and(leaf_1, pte.v)
node _T_199 = and(_T_198, invalid_paddr)
node _T_200 = and(leaf_1, pte.v)
node _T_201 = and(_T_200, invalid_gpa)
node _T_202 = and(leaf_1, pte.v)
node _T_203 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_204 = and(_T_202, _T_203)
node _T_205 = bits(mem_resp_data, 0, 0)
node _T_206 = eq(_T_205, UInt<1>(0h0))
node _T_207 = and(leaf_1, _T_206)
node _T_208 = eq(count, UInt<1>(0h1))
node _T_209 = and(mem_resp_valid, _T_208)
node _T_210 = eq(pte.r, UInt<1>(0h0))
node _T_211 = and(pte.v, _T_210)
node _T_212 = eq(pte.w, UInt<1>(0h0))
node _T_213 = and(_T_211, _T_212)
node _T_214 = eq(pte.x, UInt<1>(0h0))
node _T_215 = and(_T_213, _T_214)
node _T_216 = eq(pte.d, UInt<1>(0h0))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(pte.a, UInt<1>(0h0))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(pte.u, UInt<1>(0h0))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_223 = and(_T_221, _T_222)
node _T_224 = and(_T_209, _T_223)
node _T_225 = eq(state, UInt<3>(0h4))
node _T_226 = and(_T_225, io.mem.s2_xcpt.ae.ld) | module PTW( // @[PTW.scala:219:7]
input clock, // @[PTW.scala:219:7]
input reset, // @[PTW.scala:219:7]
output io_requestor_0_req_ready, // @[PTW.scala:220:14]
input [19:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
input io_requestor_0_req_bits_bits_vstage1, // @[PTW.scala:220:14]
input io_requestor_0_req_bits_bits_stage2, // @[PTW.scala:220:14]
output io_requestor_0_resp_valid, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output io_requestor_0_status_debug, // @[PTW.scala:220:14]
output io_requestor_0_status_cease, // @[PTW.scala:220:14]
output io_requestor_0_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14]
output io_requestor_0_status_dv, // @[PTW.scala:220:14]
output io_requestor_0_status_v, // @[PTW.scala:220:14]
output io_requestor_0_status_mpv, // @[PTW.scala:220:14]
output io_requestor_0_status_gva, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14]
output io_requestor_0_status_mpie, // @[PTW.scala:220:14]
output io_requestor_0_status_mie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_v, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sd_rv32, // @[PTW.scala:220:14]
output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
output io_requestor_1_req_ready, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_valid, // @[PTW.scala:220:14]
input [19:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_bits_vstage1, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_bits_stage2, // @[PTW.scala:220:14]
output io_requestor_1_resp_valid, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output io_requestor_1_status_debug, // @[PTW.scala:220:14]
output io_requestor_1_status_cease, // @[PTW.scala:220:14]
output io_requestor_1_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_status_isa, // @[PTW.scala:220:14]
output io_requestor_1_status_dv, // @[PTW.scala:220:14]
output io_requestor_1_status_v, // @[PTW.scala:220:14]
output io_requestor_1_status_mpv, // @[PTW.scala:220:14]
output io_requestor_1_status_gva, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14]
output io_requestor_1_status_mpie, // @[PTW.scala:220:14]
output io_requestor_1_status_mie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_v, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sd_rv32, // @[PTW.scala:220:14]
output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
input io_dpath_sfence_valid, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14]
input [31:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14]
input io_dpath_status_debug, // @[PTW.scala:220:14]
input io_dpath_status_cease, // @[PTW.scala:220:14]
input io_dpath_status_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14]
input io_dpath_status_dv, // @[PTW.scala:220:14]
input io_dpath_status_v, // @[PTW.scala:220:14]
input io_dpath_status_mpv, // @[PTW.scala:220:14]
input io_dpath_status_gva, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14]
input io_dpath_status_mpie, // @[PTW.scala:220:14]
input io_dpath_status_mie, // @[PTW.scala:220:14]
input io_dpath_gstatus_debug, // @[PTW.scala:220:14]
input io_dpath_gstatus_cease, // @[PTW.scala:220:14]
input io_dpath_gstatus_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14]
input io_dpath_gstatus_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14]
input io_dpath_gstatus_v, // @[PTW.scala:220:14]
input io_dpath_gstatus_sd, // @[PTW.scala:220:14]
input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14]
input io_dpath_gstatus_mpv, // @[PTW.scala:220:14]
input io_dpath_gstatus_gva, // @[PTW.scala:220:14]
input io_dpath_gstatus_mbe, // @[PTW.scala:220:14]
input io_dpath_gstatus_sbe, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14]
input io_dpath_gstatus_sd_rv32, // @[PTW.scala:220:14]
input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14]
input io_dpath_gstatus_tsr, // @[PTW.scala:220:14]
input io_dpath_gstatus_tw, // @[PTW.scala:220:14]
input io_dpath_gstatus_tvm, // @[PTW.scala:220:14]
input io_dpath_gstatus_mxr, // @[PTW.scala:220:14]
input io_dpath_gstatus_sum, // @[PTW.scala:220:14]
input io_dpath_gstatus_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14]
input io_dpath_gstatus_spp, // @[PTW.scala:220:14]
input io_dpath_gstatus_mpie, // @[PTW.scala:220:14]
input io_dpath_gstatus_ube, // @[PTW.scala:220:14]
input io_dpath_gstatus_spie, // @[PTW.scala:220:14]
input io_dpath_gstatus_upie, // @[PTW.scala:220:14]
input io_dpath_gstatus_mie, // @[PTW.scala:220:14]
input io_dpath_gstatus_hie, // @[PTW.scala:220:14]
input io_dpath_gstatus_sie, // @[PTW.scala:220:14]
input io_dpath_gstatus_uie, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14]
output io_dpath_perf_pte_miss, // @[PTW.scala:220:14]
output io_dpath_perf_pte_hit, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
input [31:0] io_dpath_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
input [31:0] io_dpath_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
input [31:0] io_dpath_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
input [31:0] io_dpath_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
input [31:0] io_dpath_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
input [31:0] io_dpath_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
input [31:0] io_dpath_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
input [31:0] io_dpath_customCSRs_csrs_3_value // @[PTW.scala:220:14]
);
wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25]
wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25]
wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_d; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_a; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_g; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_u; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_x; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_w; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_r; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_v; // @[package.scala:267:25]
wire [2:0] _state_barrier_io_y; // @[package.scala:267:25]
wire _arb_io_out_bits_valid; // @[PTW.scala:236:19]
wire [19:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19]
wire _arb_io_out_bits_bits_vstage1; // @[PTW.scala:236:19]
wire _arb_io_out_bits_bits_stage2; // @[PTW.scala:236:19]
wire [19:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_vstage1_0 = io_requestor_0_req_bits_bits_vstage1; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_stage2_0 = io_requestor_0_req_bits_bits_stage2; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_valid_0 = io_requestor_1_req_bits_valid; // @[PTW.scala:219:7]
wire [19:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_vstage1_0 = io_requestor_1_req_bits_bits_vstage1; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_stage2_0 = io_requestor_1_req_bits_bits_stage2; // @[PTW.scala:219:7]
wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7]
wire [31:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7]
wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7]
wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7]
wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7]
wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7]
wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7]
wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7]
wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7]
wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7]
wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7]
wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7]
wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_0 = io_dpath_gstatus_sd; // @[PTW.scala:219:7]
wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_rv32_0 = io_dpath_gstatus_sd_rv32; // @[PTW.scala:219:7]
wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_fs_0 = io_dpath_gstatus_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value; // @[PTW.scala:219:7]
wire io_requestor_0_req_valid = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_ptbr_mode = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hgatp_mode = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_vsatp_mode = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mxr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sum = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mprv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spp = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spvp = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_req_valid = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_ptbr_mode = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hgatp_mode = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_vsatp_mode = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sd = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mxr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sum = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mprv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_spp = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_spie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_spvp = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_spv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_ready = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_nack = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_nack_cause_raw = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_uncached = 1'h0; // @[PTW.scala:219:7]
wire io_mem_resp_valid = 1'h0; // @[PTW.scala:219:7]
wire io_mem_resp_bits_signed = 1'h0; // @[PTW.scala:219:7]
wire io_mem_resp_bits_dv = 1'h0; // @[PTW.scala:219:7]
wire io_mem_resp_bits_replay = 1'h0; // @[PTW.scala:219:7]
wire io_mem_resp_bits_has_data = 1'h0; // @[PTW.scala:219:7]
wire io_mem_replay_next = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7]
wire io_mem_ordered = 1'h0; // @[PTW.scala:219:7]
wire io_mem_store_pending = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_acquire = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_release = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_grant = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_tlbMiss = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_blocked = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[PTW.scala:219:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7]
wire io_mem_clock_enabled = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_ptbr_mode = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hgatp_mode = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_vsatp_mode = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sd = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_tsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_tw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_tvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_mxr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sum = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_mprv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_spp = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_spie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spvp = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_clock_enabled = 1'h0; // @[PTW.scala:219:7]
wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35]
wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35]
wire _io_dpath_clock_enabled_T = 1'h0; // @[PTW.scala:245:39]
wire satp_mode = 1'h0; // @[PTW.scala:285:17]
wire tmp_d = 1'h0; // @[PTW.scala:304:37]
wire tmp_a = 1'h0; // @[PTW.scala:304:37]
wire tmp_g = 1'h0; // @[PTW.scala:304:37]
wire tmp_u = 1'h0; // @[PTW.scala:304:37]
wire tmp_x = 1'h0; // @[PTW.scala:304:37]
wire tmp_w = 1'h0; // @[PTW.scala:304:37]
wire tmp_r = 1'h0; // @[PTW.scala:304:37]
wire tmp_v = 1'h0; // @[PTW.scala:304:37]
wire _tmp_T = 1'h0; // @[PTW.scala:304:37]
wire _tmp_T_1 = 1'h0; // @[PTW.scala:304:37]
wire _tmp_T_2 = 1'h0; // @[PTW.scala:304:37]
wire _tmp_T_3 = 1'h0; // @[PTW.scala:304:37]
wire _tmp_T_4 = 1'h0; // @[PTW.scala:304:37]
wire _tmp_T_5 = 1'h0; // @[PTW.scala:304:37]
wire _tmp_T_6 = 1'h0; // @[PTW.scala:304:37]
wire _tmp_T_7 = 1'h0; // @[PTW.scala:304:37]
wire pte_d = 1'h0; // @[PTW.scala:305:26]
wire pte_a = 1'h0; // @[PTW.scala:305:26]
wire pte_g = 1'h0; // @[PTW.scala:305:26]
wire pte_u = 1'h0; // @[PTW.scala:305:26]
wire pte_x = 1'h0; // @[PTW.scala:305:26]
wire pte_w = 1'h0; // @[PTW.scala:305:26]
wire pte_r = 1'h0; // @[PTW.scala:305:26]
wire pte_v = 1'h0; // @[PTW.scala:305:26]
wire invalid_paddr = 1'h0; // @[PTW.scala:313:9]
wire invalid_gpa = 1'h0; // @[PTW.scala:314:32]
wire _traverse_T_1 = 1'h0; // @[PTW.scala:139:33]
wire _traverse_T_3 = 1'h0; // @[PTW.scala:139:39]
wire _traverse_T_5 = 1'h0; // @[PTW.scala:139:45]
wire _traverse_T_7 = 1'h0; // @[PTW.scala:139:51]
wire _traverse_T_9 = 1'h0; // @[PTW.scala:139:57]
wire _traverse_T_11 = 1'h0; // @[PTW.scala:139:63]
wire _traverse_T_13 = 1'h0; // @[PTW.scala:139:69]
wire _traverse_T_15 = 1'h0; // @[PTW.scala:317:30]
wire _traverse_T_17 = 1'h0; // @[PTW.scala:317:48]
wire traverse = 1'h0; // @[PTW.scala:317:64]
wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27]
wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20]
wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24]
wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13]
wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62]
wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13]
wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62]
wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17]
wire l2_pte_d = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_a = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_g = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_u = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_x = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_w = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_r = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_v = 1'h0; // @[PTW.scala:403:113]
wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32]
wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40]
wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire do_switch = 1'h0; // @[PTW.scala:581:30]
wire resp_gf_idxs_0 = 1'h0; // @[PTW.scala:787:58]
wire _resp_gf_T_1 = 1'h0; // @[PTW.scala:788:25]
wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71]
wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16]
wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29]
wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25]
wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58]
wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26]
wire _r_pte_T_20 = 1'h0; // @[Decoupled.scala:51:35]
wire _gf_T_3 = 1'h0; // @[PTW.scala:141:44]
wire _gf_T_4 = 1'h0; // @[PTW.scala:141:38]
wire _gf_T_5 = 1'h0; // @[PTW.scala:141:32]
wire _gf_T_6 = 1'h0; // @[PTW.scala:141:52]
wire _gf_T_7 = 1'h0; // @[PTW.scala:149:35]
wire _gf_T_8 = 1'h0; // @[PTW.scala:143:33]
wire _gf_T_12 = 1'h0; // @[PTW.scala:141:44]
wire _gf_T_13 = 1'h0; // @[PTW.scala:141:38]
wire _gf_T_14 = 1'h0; // @[PTW.scala:141:32]
wire _gf_T_15 = 1'h0; // @[PTW.scala:141:52]
wire _gf_T_17 = 1'h0; // @[PTW.scala:698:70]
wire _gf_T_18 = 1'h0; // @[PTW.scala:698:105]
wire ae = 1'h0; // @[PTW.scala:699:22]
wire _pf_T = 1'h0; // @[PTW.scala:700:49]
wire pf = 1'h0; // @[PTW.scala:700:22]
wire _success_T_1 = 1'h0; // @[PTW.scala:701:27]
wire _success_T_3 = 1'h0; // @[PTW.scala:701:34]
wire success = 1'h0; // @[PTW.scala:701:41]
wire _l2_refill_T_1 = 1'h0; // @[PTW.scala:713:30]
wire _l2_refill_T_3 = 1'h0; // @[PTW.scala:713:58]
wire _l2_refill_T_10 = 1'h0; // @[PTW.scala:141:44]
wire _l2_refill_T_11 = 1'h0; // @[PTW.scala:141:38]
wire _l2_refill_T_12 = 1'h0; // @[PTW.scala:141:32]
wire _l2_refill_T_13 = 1'h0; // @[PTW.scala:141:52]
wire _l2_refill_T_14 = 1'h0; // @[PTW.scala:151:35]
wire _l2_refill_T_15 = 1'h0; // @[PTW.scala:151:40]
wire _l2_refill_T_16 = 1'h0; // @[PTW.scala:145:33]
wire _l2_refill_T_18 = 1'h0; // @[PTW.scala:141:44]
wire _l2_refill_T_19 = 1'h0; // @[PTW.scala:141:38]
wire _l2_refill_T_20 = 1'h0; // @[PTW.scala:141:32]
wire _l2_refill_T_21 = 1'h0; // @[PTW.scala:141:52]
wire _l2_refill_T_22 = 1'h0; // @[PTW.scala:153:35]
wire _l2_refill_T_23 = 1'h0; // @[PTW.scala:147:33]
wire _l2_refill_T_24 = 1'h0; // @[PTW.scala:155:41]
wire _l2_refill_T_25 = 1'h0; // @[PTW.scala:715:59]
wire _l2_refill_T_27 = 1'h0; // @[PTW.scala:713:77]
wire _resp_ae_ptw_T_1 = 1'h0; // @[PTW.scala:725:27]
wire _resp_ae_ptw_T_3 = 1'h0; // @[PTW.scala:139:33]
wire _resp_ae_ptw_T_5 = 1'h0; // @[PTW.scala:139:39]
wire _resp_ae_ptw_T_7 = 1'h0; // @[PTW.scala:139:45]
wire _resp_ae_ptw_T_9 = 1'h0; // @[PTW.scala:139:51]
wire _resp_ae_ptw_T_11 = 1'h0; // @[PTW.scala:139:57]
wire _resp_ae_ptw_T_13 = 1'h0; // @[PTW.scala:139:63]
wire _resp_ae_ptw_T_15 = 1'h0; // @[PTW.scala:139:69]
wire _resp_ae_ptw_T_16 = 1'h0; // @[PTW.scala:725:53]
wire _resp_ae_final_T_1 = 1'h0; // @[PTW.scala:141:44]
wire _resp_ae_final_T_2 = 1'h0; // @[PTW.scala:141:38]
wire _resp_ae_final_T_3 = 1'h0; // @[PTW.scala:141:32]
wire _resp_ae_final_T_4 = 1'h0; // @[PTW.scala:141:52]
wire _resp_ae_final_T_5 = 1'h0; // @[PTW.scala:726:29]
wire _resp_pf_T_1 = 1'h0; // @[PTW.scala:727:23]
wire _resp_gf_T_3 = 1'h0; // @[PTW.scala:728:30]
wire _resp_hr_T_5 = 1'h0; // @[PTW.scala:141:44]
wire _resp_hr_T_6 = 1'h0; // @[PTW.scala:141:38]
wire _resp_hr_T_7 = 1'h0; // @[PTW.scala:141:32]
wire _resp_hr_T_8 = 1'h0; // @[PTW.scala:141:52]
wire _resp_hr_T_9 = 1'h0; // @[PTW.scala:149:35]
wire _resp_hr_T_10 = 1'h0; // @[PTW.scala:143:33]
wire _resp_hr_T_11 = 1'h0; // @[PTW.scala:729:43]
wire _resp_hw_T_5 = 1'h0; // @[PTW.scala:141:44]
wire _resp_hw_T_6 = 1'h0; // @[PTW.scala:141:38]
wire _resp_hw_T_7 = 1'h0; // @[PTW.scala:141:32]
wire _resp_hw_T_8 = 1'h0; // @[PTW.scala:141:52]
wire _resp_hw_T_9 = 1'h0; // @[PTW.scala:151:35]
wire _resp_hw_T_10 = 1'h0; // @[PTW.scala:151:40]
wire _resp_hw_T_11 = 1'h0; // @[PTW.scala:145:33]
wire _resp_hw_T_12 = 1'h0; // @[PTW.scala:730:43]
wire _resp_hx_T_5 = 1'h0; // @[PTW.scala:141:44]
wire _resp_hx_T_6 = 1'h0; // @[PTW.scala:141:38]
wire _resp_hx_T_7 = 1'h0; // @[PTW.scala:141:32]
wire _resp_hx_T_8 = 1'h0; // @[PTW.scala:141:52]
wire _resp_hx_T_9 = 1'h0; // @[PTW.scala:153:35]
wire _resp_hx_T_10 = 1'h0; // @[PTW.scala:147:33]
wire _resp_hx_T_11 = 1'h0; // @[PTW.scala:731:43]
wire aux_pte_pte_d = 1'h0; // @[PTW.scala:771:26]
wire aux_pte_pte_a = 1'h0; // @[PTW.scala:771:26]
wire aux_pte_pte_g = 1'h0; // @[PTW.scala:771:26]
wire aux_pte_pte_u = 1'h0; // @[PTW.scala:771:26]
wire aux_pte_pte_x = 1'h0; // @[PTW.scala:771:26]
wire aux_pte_pte_w = 1'h0; // @[PTW.scala:771:26]
wire aux_pte_pte_r = 1'h0; // @[PTW.scala:771:26]
wire aux_pte_pte_v = 1'h0; // @[PTW.scala:771:26]
wire _aux_pte_T_2_d = 1'h0; // @[PTW.scala:743:19]
wire _aux_pte_T_2_a = 1'h0; // @[PTW.scala:743:19]
wire _aux_pte_T_2_g = 1'h0; // @[PTW.scala:743:19]
wire _aux_pte_T_2_u = 1'h0; // @[PTW.scala:743:19]
wire _aux_pte_T_2_x = 1'h0; // @[PTW.scala:743:19]
wire _aux_pte_T_2_w = 1'h0; // @[PTW.scala:743:19]
wire _aux_pte_T_2_r = 1'h0; // @[PTW.scala:743:19]
wire _aux_pte_T_2_v = 1'h0; // @[PTW.scala:743:19]
wire _leaf_T_1 = 1'h0; // @[PTW.scala:751:31]
wire leaf = 1'h0; // @[PTW.scala:751:44]
wire _leaf_T_4 = 1'h0; // @[PTW.scala:751:31]
wire leaf_1 = 1'h0; // @[PTW.scala:751:44]
wire [8:0] io_requestor_0_ptbr_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_0_hgatp_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_0_vsatp_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_1_ptbr_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_1_hgatp_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_1_vsatp_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_ptbr_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_hgatp_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_vsatp_asid = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] satp_asid = 9'h0; // @[PTW.scala:285:17]
wire [21:0] io_requestor_0_ptbr_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] io_requestor_0_hgatp_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] io_requestor_0_vsatp_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] io_requestor_1_ptbr_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] io_requestor_1_hgatp_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] io_requestor_1_vsatp_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] io_dpath_ptbr_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] io_dpath_hgatp_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] io_dpath_vsatp_ppn = 22'h0; // @[PTW.scala:219:7]
wire [21:0] satp_ppn = 22'h0; // @[PTW.scala:285:17]
wire [21:0] idxs_0 = 22'h0; // @[PTW.scala:787:58]
wire [21:0] _r_pte_pte_ppn_T_5 = 22'h0; // @[PTW.scala:781:19]
wire [1:0] io_requestor_0_status_dprv = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_prv = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_dprv = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_prv = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_dprv = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_prv = 2'h3; // @[PTW.scala:219:7]
wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27]
wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43]
wire [1:0] io_requestor_0_status_sxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_fs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_sxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_fs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_size = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_dprv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_sxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_fs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42]
wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58]
wire [1:0] tmp_reserved_for_software = 2'h0; // @[PTW.scala:304:37]
wire [1:0] _tmp_T_8 = 2'h0; // @[PTW.scala:304:37]
wire [1:0] pte_reserved_for_software = 2'h0; // @[PTW.scala:305:26]
wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44]
wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13]
wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62]
wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113]
wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45]
wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61]
wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46]
wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62]
wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46]
wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62]
wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27]
wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27]
wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44]
wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40]
wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27]
wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26]
wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26]
wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs_1 = 2'h0; // @[PTW.scala:779:27]
wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_idxs_0_2 = 2'h0; // @[PTW.scala:778:58]
wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27]
wire [1:0] aux_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:771:26]
wire [1:0] _aux_pte_T_2_reserved_for_software = 2'h0; // @[PTW.scala:743:19]
wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40]
wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7]
wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7]
wire _traverse_T = 1'h1; // @[PTW.scala:139:36]
wire _traverse_T_2 = 1'h1; // @[PTW.scala:139:42]
wire _traverse_T_4 = 1'h1; // @[PTW.scala:139:48]
wire _traverse_T_6 = 1'h1; // @[PTW.scala:139:54]
wire _traverse_T_8 = 1'h1; // @[PTW.scala:139:60]
wire _traverse_T_10 = 1'h1; // @[PTW.scala:139:66]
wire _traverse_T_12 = 1'h1; // @[PTW.scala:139:92]
wire _traverse_T_14 = 1'h1; // @[PTW.scala:317:33]
wire _traverse_T_16 = 1'h1; // @[PTW.scala:317:51]
wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33]
wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33]
wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16]
wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33]
wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16]
wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60]
wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_7 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_8 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_9 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_58 = 1'h1; // @[TLBPermissions.scala:87:22]
wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28]
wire _r_pte_T = 1'h1; // @[PTW.scala:670:19]
wire _r_pte_T_8 = 1'h1; // @[PTW.scala:678:29]
wire _gf_T_2 = 1'h1; // @[PTW.scala:141:47]
wire _gf_T_9 = 1'h1; // @[PTW.scala:698:44]
wire _gf_T_11 = 1'h1; // @[PTW.scala:141:47]
wire _gf_T_16 = 1'h1; // @[PTW.scala:698:97]
wire _success_T = 1'h1; // @[PTW.scala:701:30]
wire _success_T_2 = 1'h1; // @[PTW.scala:701:37]
wire _l2_refill_T_9 = 1'h1; // @[PTW.scala:141:47]
wire _l2_refill_T_17 = 1'h1; // @[PTW.scala:141:47]
wire _resp_ae_ptw_T_2 = 1'h1; // @[PTW.scala:139:36]
wire _resp_ae_ptw_T_4 = 1'h1; // @[PTW.scala:139:42]
wire _resp_ae_ptw_T_6 = 1'h1; // @[PTW.scala:139:48]
wire _resp_ae_ptw_T_8 = 1'h1; // @[PTW.scala:139:54]
wire _resp_ae_ptw_T_10 = 1'h1; // @[PTW.scala:139:60]
wire _resp_ae_ptw_T_12 = 1'h1; // @[PTW.scala:139:66]
wire _resp_ae_ptw_T_14 = 1'h1; // @[PTW.scala:139:92]
wire _resp_ae_final_T = 1'h1; // @[PTW.scala:141:47]
wire _resp_hr_T_1 = 1'h1; // @[PTW.scala:729:32]
wire _resp_hr_T_4 = 1'h1; // @[PTW.scala:141:47]
wire _resp_hw_T_1 = 1'h1; // @[PTW.scala:730:32]
wire _resp_hw_T_4 = 1'h1; // @[PTW.scala:141:47]
wire _resp_hx_T_1 = 1'h1; // @[PTW.scala:731:32]
wire _resp_hx_T_4 = 1'h1; // @[PTW.scala:141:47]
wire _leaf_T = 1'h1; // @[PTW.scala:751:34]
wire _leaf_T_3 = 1'h1; // @[PTW.scala:751:34]
wire [9:0] tmp_reserved_for_future = 10'h0; // @[PTW.scala:304:37]
wire [9:0] _tmp_T_10 = 10'h0; // @[PTW.scala:304:37]
wire [9:0] pte_reserved_for_future = 10'h0; // @[PTW.scala:305:26]
wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113]
wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26]
wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26]
wire [9:0] aux_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:771:26]
wire [9:0] _aux_pte_T_2_reserved_for_future = 10'h0; // @[PTW.scala:743:19]
wire [33:0] _merged_pte_stage1_ppns_T = 34'h0; // @[PTW.scala:663:64]
wire [33:0] _aux_pte_s1_ppns_T = 34'h0; // @[PTW.scala:744:62]
wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42]
wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58]
wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13]
wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45]
wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61]
wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46]
wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62]
wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46]
wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62]
wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44]
wire [43:0] tmp_ppn = 44'h0; // @[PTW.scala:304:37]
wire [43:0] _tmp_T_9 = 44'h0; // @[PTW.scala:304:37]
wire [43:0] pte_ppn = 44'h0; // @[PTW.scala:305:26]
wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113]
wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26]
wire [43:0] r_pte_pte_5_ppn = 44'h0; // @[PTW.scala:771:26]
wire [43:0] _r_pte_T_21_ppn = 44'h0; // @[PTW.scala:682:29]
wire [19:0] _res_ppn_T_2 = 20'h0; // @[PTW.scala:306:54]
wire [19:0] _res_ppn_T_3 = 20'h0; // @[PTW.scala:306:99]
wire [19:0] _res_ppn_T_4 = 20'h0; // @[PTW.scala:306:19]
wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _r_pte_pte_ppn_T_4 = 20'h0; // @[PTW.scala:781:30]
wire [23:0] r_pte_idxs_0_1 = 24'h0; // @[PTW.scala:778:58]
wire [3:0] io_mem_req_bits_mask = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_mem_s1_data_mask = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_mem_resp_bits_mask = 4'h0; // @[PTW.scala:219:7]
wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27]
wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27]
wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18]
wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18]
wire [63:0] _tmp_WIRE = 64'h0; // @[PTW.scala:304:37]
wire [31:0] io_requestor_0_customCSRs_csrs_0_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_1_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_2_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_3_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_0_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_1_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_2_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_3_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_req_bits_addr = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_req_bits_data = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_s1_data_data = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_s2_paddr = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_resp_bits_addr = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_resp_bits_data = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_resp_bits_data_word_bypass = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_resp_bits_data_raw = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_resp_bits_store_data = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_mem_s2_gpa = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_0_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_1_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_2_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_dpath_customCSRs_csrs_3_sdata = 32'h0; // @[PTW.scala:219:7]
wire [31:0] _tag_T = 32'h0; // @[package.scala:138:15]
wire [31:0] _tag_T_1 = 32'h0; // @[package.scala:138:15]
wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58]
wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7]
wire [6:0] io_mem_resp_bits_tag = 7'h0; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_size = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7]
wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24]
wire [2:0] _next_state_T_1 = 3'h1; // @[PTW.scala:627:26]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48]
wire [32:0] tag_1 = 33'h100000000; // @[PTW.scala:363:18]
wire max_count; // @[PTW.scala:289:25]
wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39]
wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40]
wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51]
wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_rv32_0 = io_dpath_gstatus_sd_rv32_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sd_rv32_0 = io_dpath_gstatus_sd_rv32_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7]
wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57]
wire io_requestor_0_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7]
wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7]
wire io_mem_req_bits_dv; // @[PTW.scala:219:7]
wire io_mem_req_valid; // @[PTW.scala:219:7]
wire io_mem_s1_kill; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7]
reg [2:0] state; // @[PTW.scala:233:22]
wire l2_refill_wire; // @[PTW.scala:234:28]
wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30]
wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46]
wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}]
reg resp_valid_0; // @[PTW.scala:242:27]
assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27]
reg resp_valid_1; // @[PTW.scala:242:27]
assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27]
wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24]
wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}]
wire _clock_en_T_2 = _clock_en_T_1; // @[PTW.scala:244:{36,54}]
wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}]
wire _clock_en_T_4 = io_dpath_customCSRs_csrs_0_value_0[0]; // @[CustomCSRs.scala:43:61]
wire clock_en = _clock_en_T_3 | _clock_en_T_4; // @[CustomCSRs.scala:43:61]
reg invalidated; // @[PTW.scala:251:24]
reg count; // @[PTW.scala:259:18]
wire _pmaHomogeneous_T = count; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_2 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_16 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T = count; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_5 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_42 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_1 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_8 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_68 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_2 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_11 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_94 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_3 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_14 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_120 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_4 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_17 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_146 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_5 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_20 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_172 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_6 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_23 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_198 = count; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_7 = count; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T = count; // @[package.scala:39:86]
wire _l2_refill_T = count; // @[PTW.scala:259:18, :713:39]
wire _aux_count_T_5 = count; // @[PTW.scala:259:18, :741:21]
wire _aux_pte_T = count; // @[package.scala:39:86]
wire _leaf_T_5 = count; // @[PTW.scala:259:18, :751:53]
reg resp_ae_ptw; // @[PTW.scala:260:24]
assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
reg resp_ae_final; // @[PTW.scala:261:26]
assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
reg resp_pf; // @[PTW.scala:262:20]
assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
reg resp_gf; // @[PTW.scala:263:20]
assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
reg resp_hr; // @[PTW.scala:264:20]
assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
reg resp_hw; // @[PTW.scala:265:20]
assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
reg resp_hx; // @[PTW.scala:266:20]
assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
reg resp_fragmented_superpage; // @[PTW.scala:267:38]
reg [19:0] r_req_addr; // @[PTW.scala:270:18]
reg r_req_need_gpa; // @[PTW.scala:270:18]
assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
reg r_req_vstage1; // @[PTW.scala:270:18]
wire _r_pte_T_9 = r_req_vstage1; // @[PTW.scala:270:18, :678:39]
reg r_req_stage2; // @[PTW.scala:270:18]
reg r_req_dest; // @[PTW.scala:272:23]
reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
wire [9:0] _r_pte_T_22_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :682:8]
reg [43:0] r_pte_ppn; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
wire [43:0] _r_pte_T_22_ppn = r_pte_ppn; // @[PTW.scala:275:18, :682:8]
reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
wire [1:0] _r_pte_T_22_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :682:8]
reg r_pte_d; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
wire _r_pte_T_22_d = r_pte_d; // @[PTW.scala:275:18, :682:8]
reg r_pte_a; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
wire _r_pte_T_22_a = r_pte_a; // @[PTW.scala:275:18, :682:8]
reg r_pte_g; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
wire _r_pte_T_22_g = r_pte_g; // @[PTW.scala:275:18, :682:8]
reg r_pte_u; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
wire _r_pte_T_22_u = r_pte_u; // @[PTW.scala:275:18, :682:8]
reg r_pte_x; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
wire _r_pte_T_22_x = r_pte_x; // @[PTW.scala:275:18, :682:8]
reg r_pte_w; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
wire _r_pte_T_22_w = r_pte_w; // @[PTW.scala:275:18, :682:8]
reg r_pte_r; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
wire _r_pte_T_22_r = r_pte_r; // @[PTW.scala:275:18, :682:8]
reg r_pte_v; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
wire _r_pte_T_22_v = r_pte_v; // @[PTW.scala:275:18, :682:8]
reg r_hgatp_mode; // @[PTW.scala:276:20]
reg [8:0] r_hgatp_asid; // @[PTW.scala:276:20]
reg [21:0] r_hgatp_ppn; // @[PTW.scala:276:20]
reg aux_count; // @[PTW.scala:278:22]
wire _io_requestor_0_resp_bits_gpa_bits_T_3 = aux_count; // @[PTW.scala:278:22, :566:60]
wire _io_requestor_1_resp_bits_gpa_bits_T_3 = aux_count; // @[PTW.scala:278:22, :566:60]
wire _gpa_pgoff_T = aux_count; // @[PTW.scala:278:22, :615:36]
wire _l2_refill_T_7 = aux_count; // @[PTW.scala:278:22, :715:40]
reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20]
wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26]
reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20]
reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20]
wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26]
reg aux_pte_d; // @[PTW.scala:280:20]
wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26]
reg aux_pte_a; // @[PTW.scala:280:20]
wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26]
reg aux_pte_g; // @[PTW.scala:280:20]
wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26]
reg aux_pte_u; // @[PTW.scala:280:20]
wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26]
reg aux_pte_x; // @[PTW.scala:280:20]
wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26]
reg aux_pte_w; // @[PTW.scala:280:20]
wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26]
reg aux_pte_r; // @[PTW.scala:280:20]
wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26]
reg aux_pte_v; // @[PTW.scala:280:20]
wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26]
reg [11:0] gpa_pgoff; // @[PTW.scala:281:22]
reg stage2; // @[PTW.scala:282:19]
reg stage2_final; // @[PTW.scala:283:25]
wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38]
wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25]
assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25]
assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31]
wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {24'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}]
wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38]
wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}]
wire _traverse_T_18 = ~count; // @[PTW.scala:259:18, :317:73]
reg [6:0] state_reg; // @[Replacement.scala:168:70]
reg [7:0] valid; // @[PTW.scala:352:24]
reg [31:0] tags_0; // @[PTW.scala:353:19]
reg [31:0] tags_1; // @[PTW.scala:353:19]
reg [31:0] tags_2; // @[PTW.scala:353:19]
reg [31:0] tags_3; // @[PTW.scala:353:19]
reg [31:0] tags_4; // @[PTW.scala:353:19]
reg [31:0] tags_5; // @[PTW.scala:353:19]
reg [31:0] tags_6; // @[PTW.scala:353:19]
reg [31:0] tags_7; // @[PTW.scala:353:19]
reg [19:0] data_0; // @[PTW.scala:355:19]
reg [19:0] data_1; // @[PTW.scala:355:19]
reg [19:0] data_2; // @[PTW.scala:355:19]
reg [19:0] data_3; // @[PTW.scala:355:19]
reg [19:0] data_4; // @[PTW.scala:355:19]
reg [19:0] data_5; // @[PTW.scala:355:19]
reg [19:0] data_6; // @[PTW.scala:355:19]
reg [19:0] data_7; // @[PTW.scala:355:19]
wire _can_hit_T = ~count; // @[PTW.scala:259:18, :317:73, :358:18]
wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65]
wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}]
wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}]
wire [32:0] tag = {r_req_vstage1, 32'h0}; // @[PTW.scala:270:18, :364:15]
wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27]
wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27]
wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27]
wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27]
wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27]
wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27]
wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27]
wire _hit_T = |hits; // @[PTW.scala:366:43, :367:20]
wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}]
wire _r_T = &valid; // @[PTW.scala:352:24, :370:25]
wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38]
wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38]
wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13]
wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13]
wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13]
wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57]
wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45]
wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45]
wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45]
wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45]
wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45]
wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45]
wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45]
wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45]
wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70]
wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13]
wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35]
wire [7:0] _valid_T_1 = valid | _valid_T; // @[OneHot.scala:58:35]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13]
wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13]
wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13]
wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13]
wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16]
wire _T_140 = state == 3'h1; // @[PTW.scala:233:22, :377:24]
wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46]
assign _io_dpath_perf_pte_hit_T = _T_140; // @[PTW.scala:377:24, :394:46]
wire _io_mem_req_valid_T; // @[PTW.scala:515:29]
assign _io_mem_req_valid_T = _T_140; // @[PTW.scala:377:24, :515:29]
wire _r_pte_T_4; // @[PTW.scala:672:15]
assign _r_pte_T_4 = _T_140; // @[PTW.scala:377:24, :672:15]
wire _r_pte_T_6; // @[PTW.scala:674:15]
assign _r_pte_T_6 = _T_140; // @[PTW.scala:377:24, :674:15]
wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18]
wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18]
wire [3:0] _T_26 = hi | lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_1 = _T_26[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_1 = _T_26[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_reg_touch_way_sized_1 = {|hi, |hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13]
wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13]
wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13]
wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13]
wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13]
wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13]
wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13]
wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13]
wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16]
wire _leaf_T_2 = ~count; // @[PTW.scala:259:18, :382:47, :751:53]
wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) | (hits[1] ? data_1 : 20'h0) | (hits[2] ? data_2 : 20'h0) | (hits[3] ? data_3 : 20'h0) | (hits[4] ? data_4 : 20'h0) | (hits[5] ? data_5 : 20'h0) | (hits[6] ? data_6 : 20'h0) | (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36]
reg [6:0] state_reg_1; // @[Replacement.scala:168:70]
reg [7:0] valid_1; // @[PTW.scala:352:24]
reg [19:0] data_1_0; // @[PTW.scala:355:19]
reg [19:0] data_1_1; // @[PTW.scala:355:19]
reg [19:0] data_1_2; // @[PTW.scala:355:19]
reg [19:0] data_1_3; // @[PTW.scala:355:19]
reg [19:0] data_1_4; // @[PTW.scala:355:19]
reg [19:0] data_1_5; // @[PTW.scala:355:19]
reg [19:0] data_1_6; // @[PTW.scala:355:19]
reg [19:0] data_1_7; // @[PTW.scala:355:19]
wire _can_hit_T_3 = ~count; // @[PTW.scala:259:18, :357:21]
wire _can_hit_T_4 = ~aux_count; // @[PTW.scala:278:22, :357:60]
wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}]
wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}]
wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}]
wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107]
wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}]
wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33]
wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}]
wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44]
wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}]
wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25]
wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38]
wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38]
wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13]
wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13]
wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13]
wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12]
wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38]
wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13]
wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13]
wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38]
wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12]
wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57]
wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45]
wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45]
wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45]
wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45]
wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45]
wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45]
wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45]
wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45]
wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45]
wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45]
wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45]
wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45]
wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45]
wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45]
wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70]
wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13]
wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35]
wire [7:0] _valid_T_3 = valid_1 | _valid_T_2; // @[OneHot.scala:58:35]
wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13]
wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13]
wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13]
wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13]
wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13]
wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13]
wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13]
wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13]
wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13]
wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13]
wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13]
wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13]
wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13]
wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16]
wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12]
wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13]
wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13]
wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38]
wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16]
wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12]
wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16]
wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16]
wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16]
reg pte_hit; // @[PTW.scala:392:24]
wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}]
assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1; // @[PTW.scala:394:{36,57}]
assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57]
reg l2_refill; // @[PTW.scala:398:26]
assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26]
wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65]
wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}]
wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}]
wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48]
assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}]
assign io_mem_req_valid = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39]
wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43]
assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}]
assign io_mem_req_bits_dv = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40]
wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38]
wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}]
assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}]
assign io_mem_s1_kill = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51]
wire [55:0] _GEN = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96]
wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_10; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_10 = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80]
assign _pmpHomogeneous_T = _GEN; // @[PTW.scala:544:96, :548:80]
wire [55:0] _pmaPgLevelHomogeneous_T_1 = {_pmaPgLevelHomogeneous_T[55:28], _pmaPgLevelHomogeneous_T[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_2 = {1'h0, _pmaPgLevelHomogeneous_T_1}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_3 = _pmaPgLevelHomogeneous_T_2 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_4 = _pmaPgLevelHomogeneous_T_3; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_5 = _pmaPgLevelHomogeneous_T_4 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire pmaPgLevelHomogeneous_0 = _pmaPgLevelHomogeneous_T_5; // @[TLBPermissions.scala:101:65]
wire [55:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_10; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_12 = {1'h0, _pmaPgLevelHomogeneous_T_11}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_13 = _pmaPgLevelHomogeneous_T_12 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_14 = _pmaPgLevelHomogeneous_T_13; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_15; // @[TLBPermissions.scala:101:65]
wire [55:0] _GEN_0 = {_pmaPgLevelHomogeneous_T_10[55:14], _pmaPgLevelHomogeneous_T_10[13:0] ^ 14'h3000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_16; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_16 = _GEN_0; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_71; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_71 = _GEN_0; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_17 = {1'h0, _pmaPgLevelHomogeneous_T_16}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_17 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_19 = _pmaPgLevelHomogeneous_T_18; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_20 = _pmaPgLevelHomogeneous_T_19 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_10[55:17], _pmaPgLevelHomogeneous_T_10[16:0] ^ 17'h10000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_21; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_21 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_59; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_59 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_76; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_76 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_90; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_90 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_97; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_97 = _GEN_1; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_26 = {_pmaPgLevelHomogeneous_T_10[55:21], _pmaPgLevelHomogeneous_T_10[20:0] ^ 21'h100000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_27 = {1'h0, _pmaPgLevelHomogeneous_T_26}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_27 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_29 = _pmaPgLevelHomogeneous_T_28; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_31 = {_pmaPgLevelHomogeneous_T_10[55:26], _pmaPgLevelHomogeneous_T_10[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_32 = {1'h0, _pmaPgLevelHomogeneous_T_31}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_34 = _pmaPgLevelHomogeneous_T_33; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_35 = _pmaPgLevelHomogeneous_T_34 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_36 = {_pmaPgLevelHomogeneous_T_10[55:28], _pmaPgLevelHomogeneous_T_10[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_37 = {1'h0, _pmaPgLevelHomogeneous_T_36}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_39 = _pmaPgLevelHomogeneous_T_38; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_41 = {_pmaPgLevelHomogeneous_T_10[55:29], _pmaPgLevelHomogeneous_T_10[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_42 = {1'h0, _pmaPgLevelHomogeneous_T_41}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_43 = _pmaPgLevelHomogeneous_T_42 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_44 = _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_10[55:32], _pmaPgLevelHomogeneous_T_10[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_46; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_46 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_81; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_81 = _GEN_2; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_47 = {1'h0, _pmaPgLevelHomogeneous_T_46}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_48 = _pmaPgLevelHomogeneous_T_47 & 57'h1FFFFFFFFFFC000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_49 = _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 | _pmaPgLevelHomogeneous_T_20; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_53 = _pmaPgLevelHomogeneous_T_52 | _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_54 = _pmaPgLevelHomogeneous_T_53 | _pmaPgLevelHomogeneous_T_30; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 | _pmaPgLevelHomogeneous_T_35; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55 | _pmaPgLevelHomogeneous_T_40; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 | _pmaPgLevelHomogeneous_T_45; // @[TLBPermissions.scala:101:65]
wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_57 | _pmaPgLevelHomogeneous_T_50; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_60 = {1'h0, _pmaPgLevelHomogeneous_T_59}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60 & 57'h98110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_63 = _pmaPgLevelHomogeneous_T_62 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_64 = _pmaPgLevelHomogeneous_T_63; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_65 = ~_pmaPgLevelHomogeneous_T_64; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_67 = {1'h0, _pmaPgLevelHomogeneous_T_66}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_68 = _pmaPgLevelHomogeneous_T_67 & 57'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_69 = _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_70; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_72 = {1'h0, _pmaPgLevelHomogeneous_T_71}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_73 = _pmaPgLevelHomogeneous_T_72 & 57'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_74 = _pmaPgLevelHomogeneous_T_73; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_77 = {1'h0, _pmaPgLevelHomogeneous_T_76}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_78 = _pmaPgLevelHomogeneous_T_77 & 57'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_79 = _pmaPgLevelHomogeneous_T_78; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_82 = {1'h0, _pmaPgLevelHomogeneous_T_81}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_83 = _pmaPgLevelHomogeneous_T_82 & 57'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_84 = _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 | _pmaPgLevelHomogeneous_T_75; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_87 | _pmaPgLevelHomogeneous_T_80; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 | _pmaPgLevelHomogeneous_T_85; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_91 = {1'h0, _pmaPgLevelHomogeneous_T_90}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 & 57'h98110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_96 = ~_pmaPgLevelHomogeneous_T_95; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_98 = {1'h0, _pmaPgLevelHomogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_99 = _pmaPgLevelHomogeneous_T_98 & 57'h98110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_103 = ~_pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:{22,66}]
wire pmaHomogeneous = _pmaHomogeneous_T ? pmaPgLevelHomogeneous_1 : pmaPgLevelHomogeneous_0; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[21]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7]
wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_2 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_3 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_2 = _GEN_3; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_9 = _GEN_3; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_3; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_3; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_3; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_3; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80]
wire [33:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:22]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_17 = _pmpHomogeneous_T_16 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_18 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_17; // @[package.scala:39:76]
wire _pmpHomogeneous_T_19 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_20 = ~_pmpHomogeneous_T_19; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}]
wire _pmpHomogeneous_T_21 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21]
wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T ? 32'hFFFFF000 : 32'hFFC00000; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_4 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T = _GEN_4; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_4; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_22 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62]
wire _pmpHomogeneous_T_23 = _pmpHomogeneous_T_21 | _pmpHomogeneous_T_22; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_20 | _pmpHomogeneous_T_23; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_25 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_18 : _pmpHomogeneous_T_24; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_27 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_3 = io_dpath_pmp_1_mask_0[21]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_4 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7]
wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_4 : _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_5 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_28; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_28 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_35 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_29 = ~_pmpHomogeneous_T_28; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_30 = {_pmpHomogeneous_T_29[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_32 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_31}; // @[PTW.scala:548:80]
wire [33:0] _pmpHomogeneous_T_33 = _pmpHomogeneous_T_32[55:22]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_34 = |_pmpHomogeneous_T_33; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_36 = ~_pmpHomogeneous_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_37 = {_pmpHomogeneous_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_38 = ~_pmpHomogeneous_T_37; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_39 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_38}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_40 = _pmpHomogeneous_T_39[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_41 = |_pmpHomogeneous_T_40; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_43 = _pmpHomogeneous_T_42 ? _pmpHomogeneous_T_41 : _pmpHomogeneous_T_34; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_44 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_43; // @[package.scala:39:76]
wire _pmpHomogeneous_T_45 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_46 = ~_pmpHomogeneous_T_45; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}]
wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_1 ? 32'hFFFFF000 : 32'hFFC00000; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_6 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_6; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_6; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_47 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_48 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_49 = _pmpHomogeneous_T_47 | _pmpHomogeneous_T_48; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_50 = _pmpHomogeneous_T_46 | _pmpHomogeneous_T_49; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_51 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_44 : _pmpHomogeneous_T_50; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_52 = _pmpHomogeneous_T_26 & _pmpHomogeneous_T_51; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_53 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_6 = io_dpath_pmp_2_mask_0[21]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_7 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7]
wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_8 ? _pmpHomogeneous_maskHomogeneous_T_7 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_7 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_54; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_54 = _GEN_7; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_61; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_61 = _GEN_7; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_7; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_7; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_7; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_7; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_55 = ~_pmpHomogeneous_T_54; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_56 = {_pmpHomogeneous_T_55[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_57 = ~_pmpHomogeneous_T_56; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_58 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_57}; // @[PTW.scala:548:80]
wire [33:0] _pmpHomogeneous_T_59 = _pmpHomogeneous_T_58[55:22]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_60 = |_pmpHomogeneous_T_59; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_62 = ~_pmpHomogeneous_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_63 = {_pmpHomogeneous_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_64 = ~_pmpHomogeneous_T_63; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_65 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_64}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_66 = _pmpHomogeneous_T_65[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_67 = |_pmpHomogeneous_T_66; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_69 = _pmpHomogeneous_T_68 ? _pmpHomogeneous_T_67 : _pmpHomogeneous_T_60; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_70 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_69; // @[package.scala:39:76]
wire _pmpHomogeneous_T_71 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_72 = ~_pmpHomogeneous_T_71; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}]
wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : 32'hFFC00000; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_8 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_8; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_8; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_73 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_74 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_75 = _pmpHomogeneous_T_73 | _pmpHomogeneous_T_74; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_76 = _pmpHomogeneous_T_72 | _pmpHomogeneous_T_75; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_77 = _pmpHomogeneous_T_53 ? _pmpHomogeneous_T_70 : _pmpHomogeneous_T_76; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_78 = _pmpHomogeneous_T_52 & _pmpHomogeneous_T_77; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_79 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_3_mask_0[21]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7]
wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_9; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_9 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_80; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_80 = _GEN_9; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_87; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_87 = _GEN_9; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_9; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_9; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_9; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_9; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_81 = ~_pmpHomogeneous_T_80; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_82 = {_pmpHomogeneous_T_81[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_83 = ~_pmpHomogeneous_T_82; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_84 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_83}; // @[PTW.scala:548:80]
wire [33:0] _pmpHomogeneous_T_85 = _pmpHomogeneous_T_84[55:22]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_86 = |_pmpHomogeneous_T_85; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_88 = ~_pmpHomogeneous_T_87; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_89 = {_pmpHomogeneous_T_88[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_90 = ~_pmpHomogeneous_T_89; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_91 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_90}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_92 = _pmpHomogeneous_T_91[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_93 = |_pmpHomogeneous_T_92; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94 ? _pmpHomogeneous_T_93 : _pmpHomogeneous_T_86; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_96 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_95; // @[package.scala:39:76]
wire _pmpHomogeneous_T_97 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_98 = ~_pmpHomogeneous_T_97; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}]
wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_3 ? 32'hFFFFF000 : 32'hFFC00000; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_10 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_10; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_10; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_99 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_100 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_101 = _pmpHomogeneous_T_99 | _pmpHomogeneous_T_100; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_98 | _pmpHomogeneous_T_101; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_103 = _pmpHomogeneous_T_79 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_102; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_104 = _pmpHomogeneous_T_78 & _pmpHomogeneous_T_103; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_105 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_12 = io_dpath_pmp_4_mask_0[21]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_13 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7]
wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_14 ? _pmpHomogeneous_maskHomogeneous_T_13 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_11 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_106; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_106 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_113 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_107 = ~_pmpHomogeneous_T_106; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_108 = {_pmpHomogeneous_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_109 = ~_pmpHomogeneous_T_108; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_110 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_109}; // @[PTW.scala:548:80]
wire [33:0] _pmpHomogeneous_T_111 = _pmpHomogeneous_T_110[55:22]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_112 = |_pmpHomogeneous_T_111; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_119 = |_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_121 = _pmpHomogeneous_T_120 ? _pmpHomogeneous_T_119 : _pmpHomogeneous_T_112; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_122 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_121; // @[package.scala:39:76]
wire _pmpHomogeneous_T_123 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_124 = ~_pmpHomogeneous_T_123; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}]
wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : 32'hFFC00000; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_12 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_12; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_12; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_125 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_126 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_127 = _pmpHomogeneous_T_125 | _pmpHomogeneous_T_126; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_128 = _pmpHomogeneous_T_124 | _pmpHomogeneous_T_127; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_129 = _pmpHomogeneous_T_105 ? _pmpHomogeneous_T_122 : _pmpHomogeneous_T_128; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_130 = _pmpHomogeneous_T_104 & _pmpHomogeneous_T_129; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_131 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_15 = io_dpath_pmp_5_mask_0[21]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7]
wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_17 ? _pmpHomogeneous_maskHomogeneous_T_16 : _pmpHomogeneous_maskHomogeneous_T_15; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_13 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_132; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_132 = _GEN_13; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_139; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_139 = _GEN_13; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_13; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_13; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_13; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_13; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_133 = ~_pmpHomogeneous_T_132; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_134 = {_pmpHomogeneous_T_133[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_135 = ~_pmpHomogeneous_T_134; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_136 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_135}; // @[PTW.scala:548:80]
wire [33:0] _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136[55:22]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_138 = |_pmpHomogeneous_T_137; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_140 = ~_pmpHomogeneous_T_139; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_141 = {_pmpHomogeneous_T_140[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_143 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_142}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_144 = _pmpHomogeneous_T_143[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_145 = |_pmpHomogeneous_T_144; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_146 ? _pmpHomogeneous_T_145 : _pmpHomogeneous_T_138; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_148 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_147; // @[package.scala:39:76]
wire _pmpHomogeneous_T_149 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_150 = ~_pmpHomogeneous_T_149; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}]
wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFFFF000 : 32'hFFC00000; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_14 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_14; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_14; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_151 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_152 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_153 = _pmpHomogeneous_T_151 | _pmpHomogeneous_T_152; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_154 = _pmpHomogeneous_T_150 | _pmpHomogeneous_T_153; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_155 = _pmpHomogeneous_T_131 ? _pmpHomogeneous_T_148 : _pmpHomogeneous_T_154; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_156 = _pmpHomogeneous_T_130 & _pmpHomogeneous_T_155; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_157 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_6_mask_0[21]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_19 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7]
wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_20 ? _pmpHomogeneous_maskHomogeneous_T_19 : _pmpHomogeneous_maskHomogeneous_T_18; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_15 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_158; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_158 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_165; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_165 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_159 = ~_pmpHomogeneous_T_158; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_160 = {_pmpHomogeneous_T_159[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_161 = ~_pmpHomogeneous_T_160; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_162 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_161}; // @[PTW.scala:548:80]
wire [33:0] _pmpHomogeneous_T_163 = _pmpHomogeneous_T_162[55:22]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_164 = |_pmpHomogeneous_T_163; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_166 = ~_pmpHomogeneous_T_165; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_167 = {_pmpHomogeneous_T_166[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_168 = ~_pmpHomogeneous_T_167; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_169 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_168}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_170 = _pmpHomogeneous_T_169[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_171 = |_pmpHomogeneous_T_170; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_173 = _pmpHomogeneous_T_172 ? _pmpHomogeneous_T_171 : _pmpHomogeneous_T_164; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_174 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_173; // @[package.scala:39:76]
wire _pmpHomogeneous_T_175 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_176 = ~_pmpHomogeneous_T_175; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}]
wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_6 ? 32'hFFFFF000 : 32'hFFC00000; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_16 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_16; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_16; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_177 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_178 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_179 = _pmpHomogeneous_T_177 | _pmpHomogeneous_T_178; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_180 = _pmpHomogeneous_T_176 | _pmpHomogeneous_T_179; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_181 = _pmpHomogeneous_T_157 ? _pmpHomogeneous_T_174 : _pmpHomogeneous_T_180; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_156 & _pmpHomogeneous_T_181; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_183 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_21 = io_dpath_pmp_7_mask_0[21]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_22 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7]
wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_22 : _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_17 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_184; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_184 = _GEN_17; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_191; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_191 = _GEN_17; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_17; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_17; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_185 = ~_pmpHomogeneous_T_184; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_186 = {_pmpHomogeneous_T_185[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_187 = ~_pmpHomogeneous_T_186; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_188 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_187}; // @[PTW.scala:548:80]
wire [33:0] _pmpHomogeneous_T_189 = _pmpHomogeneous_T_188[55:22]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_190 = |_pmpHomogeneous_T_189; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_192 = ~_pmpHomogeneous_T_191; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_193 = {_pmpHomogeneous_T_192[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_194 = ~_pmpHomogeneous_T_193; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_195 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_194}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_196 = _pmpHomogeneous_T_195[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_197 = |_pmpHomogeneous_T_196; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198 ? _pmpHomogeneous_T_197 : _pmpHomogeneous_T_190; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_200 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_199; // @[package.scala:39:76]
wire _pmpHomogeneous_T_201 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}]
wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : 32'hFFC00000; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_18 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_18; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_18; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_203 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_204 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_205 = _pmpHomogeneous_T_203 | _pmpHomogeneous_T_204; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_206 = _pmpHomogeneous_T_202 | _pmpHomogeneous_T_205; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_207 = _pmpHomogeneous_T_183 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_206; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire pmpHomogeneous = _pmpHomogeneous_T_182 & _pmpHomogeneous_T_207; // @[PMP.scala:118:8, :138:10]
wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76]
assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15]
wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [33:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:10]; // @[PTW.scala:280:20, :343:49]
wire [33:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:10]; // @[PTW.scala:280:20, :343:49]
wire [9:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[9:0]; // @[PTW.scala:270:18, :343:79]
wire [9:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[9:0]; // @[PTW.scala:270:18, :343:79]
wire [9:0] _r_pte_T_18 = r_req_addr[9:0]; // @[PTW.scala:270:18, :343:79]
wire [9:0] _aux_pte_s1_ppns_T_1 = r_req_addr[9:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[PTW.scala:280:20, :343:44, :566:{14,47}]
wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = {_io_requestor_0_resp_bits_gpa_bits_T_8, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_9[31:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45]
assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15]
wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[PTW.scala:280:20, :343:44, :566:{14,47}]
wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = {_io_requestor_1_resp_bits_gpa_bits_T_8, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_9[31:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45]
assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
wire [2:0] next_state; // @[PTW.scala:579:31]
wire [21:0] aux_ppn = _arb_io_out_bits_bits_vstage1 ? 22'h0 : {2'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38]
wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26]
wire _stage2_final_T = ~_arb_io_out_bits_bits_vstage1; // @[PTW.scala:236:19, :595:56]
wire _stage2_final_T_1 = _arb_io_out_bits_bits_stage2 & _stage2_final_T; // @[PTW.scala:236:19, :595:{53,56}]
wire [21:0] _gpa_pgoff_T_1 = {r_req_addr, 2'h0}; // @[PTW.scala:270:18, :615:67]
wire [21:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 22'h0; // @[PTW.scala:615:{25,36,67}]
wire [1:0] _aux_count_T_1 = {1'h0, aux_count} + 2'h1; // @[PTW.scala:278:22, :619:32]
wire _aux_count_T_2 = _aux_count_T_1[0]; // @[PTW.scala:619:32]
wire [1:0] _GEN_19 = {1'h0, count} + 2'h1; // @[PTW.scala:259:18, :357:21, :624:24]
wire [1:0] _count_T_4; // @[PTW.scala:624:24]
assign _count_T_4 = _GEN_19; // @[PTW.scala:624:24]
wire [1:0] _count_T_6; // @[PTW.scala:696:22]
assign _count_T_6 = _GEN_19; // @[PTW.scala:624:24, :696:22]
wire [1:0] _aux_count_T_3; // @[PTW.scala:741:38]
assign _aux_count_T_3 = _GEN_19; // @[PTW.scala:624:24, :741:38]
wire _count_T_5 = _count_T_4[0]; // @[PTW.scala:624:24]
wire _T_128 = state == 3'h2; // @[PTW.scala:233:22, :583:18]
wire _T_129 = state == 3'h4; // @[PTW.scala:233:22, :583:18]
wire _io_dpath_perf_pte_miss_T = ~count; // @[PTW.scala:259:18, :317:73, :640:39]
assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _T_140 | _T_128) & _T_129 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :377:24, :393:26, :583:18, :640:{30,39}]
assign next_state = (|state) ? (_T_140 ? (resp_gf ? 3'h0 : pte_cache_hit ? state : 3'h1) : _T_128 ? 3'h4 : _T_129 ? 3'h5 : (&state) ? 3'h0 : state) : state; // @[PTW.scala:233:22, :240:30, :263:20, :367:24, :377:24, :579:31, :583:18, :585:30, :618:35, :623:34, :627:20, :629:21, :630:20, :636:18, :641:35, :648:18]
wire _merged_pte_superpage_mask_T = ~stage2_final | max_count; // @[PTW.scala:283:25, :289:25, :662:45]
wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T; // @[package.scala:39:86]
wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFFFF : 44'hFFFFFFFFC00; // @[package.scala:39:{76,86}]
wire [9:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[9:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_0 = {34'h0, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,125}]
wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T ? 44'h0 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76]
wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26]
wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32]
wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26]
wire [19:0] _r_pte_pte_ppn_T = r_hgatp_ppn[21:2]; // @[PTW.scala:276:20, :781:30]
wire [19:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[21:2]; // @[PTW.scala:276:20, :781:30]
wire [21:0] _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}]
assign r_pte_pte_ppn = {22'h0, _r_pte_pte_ppn_T_1}; // @[PTW.scala:780:26, :781:{13,19}]
wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}]
wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26]
assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73]
wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26]
wire [21:0] _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, 2'h0}; // @[PTW.scala:781:{19,30}]
assign r_pte_pte_2_ppn = {22'h0, _r_pte_pte_ppn_T_3}; // @[PTW.scala:780:26, :781:{13,19}]
wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}]
wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : 10'h0; // @[PTW.scala:678:{28,56}, :771:26]
wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : 44'h0; // @[PTW.scala:678:{28,56}, :771:26]
wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : 2'h0; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_11_d = _r_pte_T_10 & merged_pte_d; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_11_a = _r_pte_T_10 & merged_pte_a; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_11_g = _r_pte_T_10 & merged_pte_g; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_11_u = _r_pte_T_10 & merged_pte_u; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_11_x = _r_pte_T_10 & merged_pte_x; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_11_w = _r_pte_T_10 & merged_pte_w; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_11_r = _r_pte_T_10 & merged_pte_r; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_11_v = _r_pte_T_10 & merged_pte_v; // @[PTW.scala:678:{28,56}, :771:26]
wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15]
wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43]
wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}]
wire _r_pte_T_15 = ~count; // @[PTW.scala:259:18, :317:73, :680:65]
wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}]
wire [33:0] _r_pte_T_17 = r_pte_ppn[43:10]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}]
wire [43:0] r_pte_pte_3_ppn = _r_pte_T_19; // @[PTW.scala:343:44, :771:26]
wire [9:0] _r_pte_T_21_reserved_for_future = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_reserved_for_future : r_pte_pte_5_reserved_for_future; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire [1:0] _r_pte_T_21_reserved_for_software = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_reserved_for_software : r_pte_pte_5_reserved_for_software; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire _r_pte_T_21_d = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_d : r_pte_pte_5_d; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire _r_pte_T_21_a = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_a : r_pte_pte_5_a; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire _r_pte_T_21_g = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_g : r_pte_pte_5_g; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire _r_pte_T_21_u = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_u : r_pte_pte_5_u; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire _r_pte_T_21_x = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_x : r_pte_pte_5_x; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire _r_pte_T_21_w = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_w : r_pte_pte_5_w; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire _r_pte_T_21_r = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_r : r_pte_pte_5_r; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire _r_pte_T_21_v = _arb_io_out_bits_bits_stage2 ? r_pte_pte_4_v : r_pte_pte_5_v; // @[PTW.scala:236:19, :682:29, :771:26, :780:26]
wire [9:0] _r_pte_T_23_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_22_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [43:0] _r_pte_T_23_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_22_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [1:0] _r_pte_T_23_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_22_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_23_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_22_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_23_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_22_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_23_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_22_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_23_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_22_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_23_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_22_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_23_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_22_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_23_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_22_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_23_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_22_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [9:0] _r_pte_T_24_reserved_for_future = _r_pte_T_23_reserved_for_future; // @[PTW.scala:678:8, :680:8]
wire [43:0] _r_pte_T_24_ppn = _r_pte_T_23_ppn; // @[PTW.scala:678:8, :680:8]
wire [1:0] _r_pte_T_24_reserved_for_software = _r_pte_T_23_reserved_for_software; // @[PTW.scala:678:8, :680:8]
wire _r_pte_T_24_d = _r_pte_T_23_d; // @[PTW.scala:678:8, :680:8]
wire _r_pte_T_24_a = _r_pte_T_23_a; // @[PTW.scala:678:8, :680:8]
wire _r_pte_T_24_g = _r_pte_T_23_g; // @[PTW.scala:678:8, :680:8]
wire _r_pte_T_24_u = _r_pte_T_23_u; // @[PTW.scala:678:8, :680:8]
wire _r_pte_T_24_x = _r_pte_T_23_x; // @[PTW.scala:678:8, :680:8]
wire _r_pte_T_24_w = _r_pte_T_23_w; // @[PTW.scala:678:8, :680:8]
wire _r_pte_T_24_r = _r_pte_T_23_r; // @[PTW.scala:678:8, :680:8]
wire _r_pte_T_24_v = _r_pte_T_23_v; // @[PTW.scala:678:8, :680:8]
wire [9:0] _r_pte_T_25_reserved_for_future = _r_pte_T_24_reserved_for_future; // @[PTW.scala:676:8, :678:8]
wire [43:0] _r_pte_T_25_ppn = _r_pte_T_24_ppn; // @[PTW.scala:676:8, :678:8]
wire [1:0] _r_pte_T_25_reserved_for_software = _r_pte_T_24_reserved_for_software; // @[PTW.scala:676:8, :678:8]
wire _r_pte_T_25_d = _r_pte_T_24_d; // @[PTW.scala:676:8, :678:8]
wire _r_pte_T_25_a = _r_pte_T_24_a; // @[PTW.scala:676:8, :678:8]
wire _r_pte_T_25_g = _r_pte_T_24_g; // @[PTW.scala:676:8, :678:8]
wire _r_pte_T_25_u = _r_pte_T_24_u; // @[PTW.scala:676:8, :678:8]
wire _r_pte_T_25_x = _r_pte_T_24_x; // @[PTW.scala:676:8, :678:8]
wire _r_pte_T_25_w = _r_pte_T_24_w; // @[PTW.scala:676:8, :678:8]
wire _r_pte_T_25_r = _r_pte_T_24_r; // @[PTW.scala:676:8, :678:8]
wire _r_pte_T_25_v = _r_pte_T_24_v; // @[PTW.scala:676:8, :678:8]
wire [9:0] _r_pte_T_26_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_25_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8]
wire [43:0] _r_pte_T_26_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_25_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26]
wire [1:0] _r_pte_T_26_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_25_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_26_d = ~_r_pte_T_7 & _r_pte_T_25_d; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_26_a = ~_r_pte_T_7 & _r_pte_T_25_a; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_26_g = ~_r_pte_T_7 & _r_pte_T_25_g; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_26_u = ~_r_pte_T_7 & _r_pte_T_25_u; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_26_x = ~_r_pte_T_7 & _r_pte_T_25_x; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_26_w = ~_r_pte_T_7 & _r_pte_T_25_w; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_26_r = ~_r_pte_T_7 & _r_pte_T_25_r; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_26_v = ~_r_pte_T_7 & _r_pte_T_25_v; // @[PTW.scala:674:{8,25}, :676:8]
wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_26_reserved_for_future; // @[PTW.scala:672:8, :674:8]
wire [43:0] _r_pte_T_27_ppn = _r_pte_T_26_ppn; // @[PTW.scala:672:8, :674:8]
wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_26_reserved_for_software; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_27_d = _r_pte_T_26_d; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_27_a = _r_pte_T_26_a; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_27_g = _r_pte_T_26_g; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_27_u = _r_pte_T_26_u; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_27_x = _r_pte_T_26_x; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_27_w = _r_pte_T_26_w; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_27_r = _r_pte_T_26_r; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_27_v = _r_pte_T_26_v; // @[PTW.scala:672:8, :674:8]
wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_27_reserved_for_future; // @[PTW.scala:670:8, :672:8]
wire [43:0] _r_pte_T_28_ppn = _r_pte_T_27_ppn; // @[PTW.scala:670:8, :672:8]
wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_27_reserved_for_software; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_28_d = _r_pte_T_27_d; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_28_a = _r_pte_T_27_a; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_28_g = _r_pte_T_27_g; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_28_u = _r_pte_T_27_u; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_28_x = _r_pte_T_27_x; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_28_w = _r_pte_T_27_w; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_28_r = _r_pte_T_27_r; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_28_v = _r_pte_T_27_v; // @[PTW.scala:670:8, :672:8]
wire _count_T_7 = _count_T_6[0]; // @[PTW.scala:696:22]
wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27]
wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}]
wire _gf_T_10 = _gf_T_1; // @[PTW.scala:698:{24,41}]
wire gf = _gf_T_10; // @[PTW.scala:698:{41,55}]
wire _resp_gf_T_4 = gf; // @[PTW.scala:698:55, :728:23]
wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44]
wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61]
wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12]
wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30]
wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}]
wire _l2_refill_T_26 = _l2_refill_T_6; // @[PTW.scala:714:{27,44}]
wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}]
wire _resp_ae_ptw_T = ~count; // @[PTW.scala:259:18, :317:73, :725:36]
wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26]
wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20]
wire _resp_hr_T_12 = _resp_hr_T; // @[PTW.scala:729:{20,28}]
wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39]
wire _resp_hr_T_3 = _resp_hr_T_2; // @[PTW.scala:729:{36,39}]
wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20]
wire _resp_hw_T_13 = _resp_hw_T; // @[PTW.scala:730:{20,28}]
wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39]
wire _resp_hw_T_3 = _resp_hw_T_2; // @[PTW.scala:730:{36,39}]
wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20]
wire _resp_hx_T_12 = _resp_hx_T; // @[PTW.scala:731:{20,28}]
wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39]
wire _resp_hx_T_3 = _resp_hx_T_2; // @[PTW.scala:731:{36,39}]
wire _aux_count_T_4 = _aux_count_T_3[0]; // @[PTW.scala:741:38]
wire [43:0] aux_pte_s1_ppns_0 = {34'h0, _aux_pte_s1_ppns_T_1}; // @[PTW.scala:744:{54,122}]
wire [43:0] _aux_pte_T_1 = _aux_pte_T ? 44'h0 : aux_pte_s1_ppns_0; // @[package.scala:39:{76,86}]
wire [43:0] aux_pte_pte_ppn = _aux_pte_T_1; // @[package.scala:39:76]
wire [43:0] _aux_pte_T_2_ppn = aux_pte_pte_ppn; // @[PTW.scala:743:19, :771:26]
wire _GEN_20 = _T_128 | _T_129; // @[PTW.scala:242:27, :583:18, :641:35]
always @(posedge clock) begin // @[PTW.scala:219:7]
if (reset) begin // @[PTW.scala:219:7]
state <= 3'h0; // @[PTW.scala:233:22]
state_reg <= 7'h0; // @[Replacement.scala:168:70]
valid <= 8'h0; // @[PTW.scala:352:24]
state_reg_1 <= 7'h0; // @[Replacement.scala:168:70]
valid_1 <= 8'h0; // @[PTW.scala:352:24]
end
else begin // @[PTW.scala:219:7]
state <= _state_barrier_io_y; // @[package.scala:267:25]
if (pte_cache_hit & _T_140) // @[PTW.scala:367:24, :377:{15,24}]
state_reg <= _state_reg_T_45; // @[Replacement.scala:168:70, :202:12]
if (io_dpath_sfence_valid_0 & ~io_dpath_sfence_bits_rs1_0) // @[PTW.scala:219:7, :378:{33,37}]
valid <= 8'h0; // @[PTW.scala:352:24]
if (io_dpath_sfence_valid_0 & ~io_dpath_sfence_bits_rs1_0) // @[PTW.scala:219:7, :378:{33,37}]
valid_1 <= 8'h0; // @[PTW.scala:352:24]
end
resp_valid_0 <= (|state) & (_T_140 ? resp_gf & ~r_req_dest : ~_GEN_20 & (&state) & ~r_req_dest); // @[PTW.scala:233:22, :240:30, :242:27, :263:20, :272:23, :377:24, :583:18, :629:21, :631:32, :641:35, :649:30]
resp_valid_1 <= (|state) & (_T_140 ? resp_gf & r_req_dest : ~_GEN_20 & (&state) & r_req_dest); // @[PTW.scala:233:22, :240:30, :242:27, :263:20, :272:23, :377:24, :583:18, :629:21, :631:32, :641:35, :649:30]
invalidated <= _invalidated_T_2; // @[PTW.scala:251:24, :511:40]
if (|state) begin // @[PTW.scala:233:22, :240:30]
if (_T_140) begin // @[PTW.scala:377:24]
if (pte_cache_hit) // @[PTW.scala:367:24]
count <= _count_T_5; // @[PTW.scala:259:18, :624:24]
end
else // @[PTW.scala:377:24]
count <= ~_GEN_20 & (&state) & ~homogeneous | count; // @[PTW.scala:233:22, :242:27, :259:18, :549:36, :583:18, :641:35, :650:{13,27}, :651:15]
end
resp_fragmented_superpage <= (|state) & ~(_T_140 | _GEN_20) & (&state) & (do_both_stages | ~homogeneous) | resp_fragmented_superpage; // @[PTW.scala:233:22, :240:30, :242:27, :267:38, :288:38, :377:24, :549:36, :583:18, :585:30, :641:35, :650:{13,27}, :652:35, :654:29, :655:35]
r_pte_reserved_for_future <= _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25]
r_pte_ppn <= _r_pte_barrier_io_y_ppn; // @[package.scala:267:25]
r_pte_reserved_for_software <= _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25]
r_pte_d <= _r_pte_barrier_io_y_d; // @[package.scala:267:25]
r_pte_a <= _r_pte_barrier_io_y_a; // @[package.scala:267:25]
r_pte_g <= _r_pte_barrier_io_y_g; // @[package.scala:267:25]
r_pte_u <= _r_pte_barrier_io_y_u; // @[package.scala:267:25]
r_pte_x <= _r_pte_barrier_io_y_x; // @[package.scala:267:25]
r_pte_w <= _r_pte_barrier_io_y_w; // @[package.scala:267:25]
r_pte_r <= _r_pte_barrier_io_y_r; // @[package.scala:267:25]
r_pte_v <= _r_pte_barrier_io_y_v; // @[package.scala:267:25]
if ((|state) & _T_140 & stage2 & ~count) // @[PTW.scala:233:22, :240:30, :259:18, :281:22, :282:19, :357:21, :377:24, :583:18, :614:{19,55}, :615:19]
gpa_pgoff <= _gpa_pgoff_T_2[11:0]; // @[PTW.scala:281:22, :615:{19,25}]
pte_hit <= (|state) & _T_140 & pte_cache_hit; // @[PTW.scala:233:22, :240:30, :367:24, :377:24, :392:24, :583:18, :618:35]
l2_refill <= 1'h0; // @[PTW.scala:398:26]
always @(posedge)
Arbiter2_Valid_PTWReq arb ( // @[PTW.scala:236:19]
.clock (clock),
.reset (reset),
.io_in_0_ready (io_requestor_0_req_ready_0),
.io_in_0_bits_bits_addr (io_requestor_0_req_bits_bits_addr_0), // @[PTW.scala:219:7]
.io_in_0_bits_bits_need_gpa (io_requestor_0_req_bits_bits_need_gpa_0), // @[PTW.scala:219:7]
.io_in_0_bits_bits_vstage1 (io_requestor_0_req_bits_bits_vstage1_0), // @[PTW.scala:219:7]
.io_in_0_bits_bits_stage2 (io_requestor_0_req_bits_bits_stage2_0), // @[PTW.scala:219:7]
.io_in_1_ready (io_requestor_1_req_ready_0),
.io_in_1_bits_valid (io_requestor_1_req_bits_valid_0), // @[PTW.scala:219:7]
.io_in_1_bits_bits_addr (io_requestor_1_req_bits_bits_addr_0), // @[PTW.scala:219:7]
.io_in_1_bits_bits_need_gpa (io_requestor_1_req_bits_bits_need_gpa_0), // @[PTW.scala:219:7]
.io_in_1_bits_bits_vstage1 (io_requestor_1_req_bits_bits_vstage1_0), // @[PTW.scala:219:7]
.io_in_1_bits_bits_stage2 (io_requestor_1_req_bits_bits_stage2_0), // @[PTW.scala:219:7]
.io_out_ready (_arb_io_out_ready_T_2), // @[PTW.scala:240:43]
.io_out_bits_valid (_arb_io_out_bits_valid),
.io_out_bits_bits_addr (_arb_io_out_bits_bits_addr),
.io_out_bits_bits_need_gpa (/* unused */),
.io_out_bits_bits_vstage1 (_arb_io_out_bits_bits_vstage1),
.io_out_bits_bits_stage2 (_arb_io_out_bits_bits_stage2)
); // @[PTW.scala:236:19]
OptimizationBarrier_UInt state_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x (next_state), // @[PTW.scala:579:31]
.io_y (_state_barrier_io_y)
); // @[package.scala:267:25]
OptimizationBarrier_PTE r_pte_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_reserved_for_future (_r_pte_T_28_reserved_for_future), // @[PTW.scala:670:8]
.io_x_ppn (_r_pte_T_28_ppn), // @[PTW.scala:670:8]
.io_x_reserved_for_software (_r_pte_T_28_reserved_for_software), // @[PTW.scala:670:8]
.io_x_d (_r_pte_T_28_d), // @[PTW.scala:670:8]
.io_x_a (_r_pte_T_28_a), // @[PTW.scala:670:8]
.io_x_g (_r_pte_T_28_g), // @[PTW.scala:670:8]
.io_x_u (_r_pte_T_28_u), // @[PTW.scala:670:8]
.io_x_x (_r_pte_T_28_x), // @[PTW.scala:670:8]
.io_x_w (_r_pte_T_28_w), // @[PTW.scala:670:8]
.io_x_r (_r_pte_T_28_r), // @[PTW.scala:670:8]
.io_x_v (_r_pte_T_28_v), // @[PTW.scala:670:8]
.io_y_reserved_for_future (_r_pte_barrier_io_y_reserved_for_future),
.io_y_ppn (_r_pte_barrier_io_y_ppn),
.io_y_reserved_for_software (_r_pte_barrier_io_y_reserved_for_software),
.io_y_d (_r_pte_barrier_io_y_d),
.io_y_a (_r_pte_barrier_io_y_a),
.io_y_g (_r_pte_barrier_io_y_g),
.io_y_u (_r_pte_barrier_io_y_u),
.io_y_x (_r_pte_barrier_io_y_x),
.io_y_w (_r_pte_barrier_io_y_w),
.io_y_r (_r_pte_barrier_io_y_r),
.io_y_v (_r_pte_barrier_io_y_v)
); // @[package.scala:267:25]
assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_ae_ptw = io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_ae_final = io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pf = io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_gf = io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_hr = io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_hw = io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_hx = io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_reserved_for_future = io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_ppn = io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_reserved_for_software = io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_d = io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_a = io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_g = io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_u = io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_x = io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_w = io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_r = io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_pte_v = io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_level = io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_homogeneous = io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_gpa_valid = io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_gpa_bits = io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
assign io_requestor_0_resp_bits_gpa_is_pte = io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_debug = io_requestor_0_status_debug_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_cease = io_requestor_0_status_cease_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_wfi = io_requestor_0_status_wfi_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_isa = io_requestor_0_status_isa_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_dv = io_requestor_0_status_dv_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_v = io_requestor_0_status_v_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_mpv = io_requestor_0_status_mpv_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_gva = io_requestor_0_status_gva_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_mpp = io_requestor_0_status_mpp_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_mpie = io_requestor_0_status_mpie_0; // @[PTW.scala:219:7]
assign io_requestor_0_status_mie = io_requestor_0_status_mie_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_debug = io_requestor_0_gstatus_debug_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_cease = io_requestor_0_gstatus_cease_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_wfi = io_requestor_0_gstatus_wfi_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_isa = io_requestor_0_gstatus_isa_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_dprv = io_requestor_0_gstatus_dprv_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_dv = io_requestor_0_gstatus_dv_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_prv = io_requestor_0_gstatus_prv_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_v = io_requestor_0_gstatus_v_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_sd = io_requestor_0_gstatus_sd_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_zero2 = io_requestor_0_gstatus_zero2_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_mpv = io_requestor_0_gstatus_mpv_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_gva = io_requestor_0_gstatus_gva_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_mbe = io_requestor_0_gstatus_mbe_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_sbe = io_requestor_0_gstatus_sbe_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_sxl = io_requestor_0_gstatus_sxl_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_sd_rv32 = io_requestor_0_gstatus_sd_rv32_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_zero1 = io_requestor_0_gstatus_zero1_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_tsr = io_requestor_0_gstatus_tsr_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_tw = io_requestor_0_gstatus_tw_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_tvm = io_requestor_0_gstatus_tvm_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_mxr = io_requestor_0_gstatus_mxr_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_sum = io_requestor_0_gstatus_sum_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_mprv = io_requestor_0_gstatus_mprv_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_fs = io_requestor_0_gstatus_fs_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_mpp = io_requestor_0_gstatus_mpp_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_vs = io_requestor_0_gstatus_vs_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_spp = io_requestor_0_gstatus_spp_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_mpie = io_requestor_0_gstatus_mpie_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_ube = io_requestor_0_gstatus_ube_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_spie = io_requestor_0_gstatus_spie_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_upie = io_requestor_0_gstatus_upie_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_mie = io_requestor_0_gstatus_mie_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_hie = io_requestor_0_gstatus_hie_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_sie = io_requestor_0_gstatus_sie_0; // @[PTW.scala:219:7]
assign io_requestor_0_gstatus_uie = io_requestor_0_gstatus_uie_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_0_cfg_l = io_requestor_0_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_0_cfg_a = io_requestor_0_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_0_cfg_x = io_requestor_0_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_0_cfg_w = io_requestor_0_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_0_cfg_r = io_requestor_0_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_0_addr = io_requestor_0_pmp_0_addr_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_0_mask = io_requestor_0_pmp_0_mask_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_1_cfg_l = io_requestor_0_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_1_cfg_a = io_requestor_0_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_1_cfg_x = io_requestor_0_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_1_cfg_w = io_requestor_0_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_1_cfg_r = io_requestor_0_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_1_addr = io_requestor_0_pmp_1_addr_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_1_mask = io_requestor_0_pmp_1_mask_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_2_cfg_l = io_requestor_0_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_2_cfg_a = io_requestor_0_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_2_cfg_x = io_requestor_0_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_2_cfg_w = io_requestor_0_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_2_cfg_r = io_requestor_0_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_2_addr = io_requestor_0_pmp_2_addr_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_2_mask = io_requestor_0_pmp_2_mask_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_3_cfg_l = io_requestor_0_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_3_cfg_a = io_requestor_0_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_3_cfg_x = io_requestor_0_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_3_cfg_w = io_requestor_0_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_3_cfg_r = io_requestor_0_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_3_addr = io_requestor_0_pmp_3_addr_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_3_mask = io_requestor_0_pmp_3_mask_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_4_cfg_l = io_requestor_0_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_4_cfg_a = io_requestor_0_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_4_cfg_x = io_requestor_0_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_4_cfg_w = io_requestor_0_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_4_cfg_r = io_requestor_0_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_4_addr = io_requestor_0_pmp_4_addr_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_4_mask = io_requestor_0_pmp_4_mask_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_5_cfg_l = io_requestor_0_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_5_cfg_a = io_requestor_0_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_5_cfg_x = io_requestor_0_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_5_cfg_w = io_requestor_0_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_5_cfg_r = io_requestor_0_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_5_addr = io_requestor_0_pmp_5_addr_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_5_mask = io_requestor_0_pmp_5_mask_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_6_cfg_l = io_requestor_0_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_6_cfg_a = io_requestor_0_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_6_cfg_x = io_requestor_0_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_6_cfg_w = io_requestor_0_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_6_cfg_r = io_requestor_0_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_6_addr = io_requestor_0_pmp_6_addr_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_6_mask = io_requestor_0_pmp_6_mask_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_7_cfg_l = io_requestor_0_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_7_cfg_a = io_requestor_0_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_7_cfg_x = io_requestor_0_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_7_cfg_w = io_requestor_0_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_7_cfg_r = io_requestor_0_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_7_addr = io_requestor_0_pmp_7_addr_0; // @[PTW.scala:219:7]
assign io_requestor_0_pmp_7_mask = io_requestor_0_pmp_7_mask_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_0_ren = io_requestor_0_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_0_wen = io_requestor_0_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_0_wdata = io_requestor_0_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_0_value = io_requestor_0_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_1_ren = io_requestor_0_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_1_wen = io_requestor_0_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_1_wdata = io_requestor_0_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_1_value = io_requestor_0_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_2_ren = io_requestor_0_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_2_wen = io_requestor_0_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_2_wdata = io_requestor_0_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_2_value = io_requestor_0_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_3_ren = io_requestor_0_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_3_wen = io_requestor_0_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_3_wdata = io_requestor_0_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
assign io_requestor_0_customCSRs_csrs_3_value = io_requestor_0_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_ae_ptw = io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_ae_final = io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pf = io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_gf = io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_hr = io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_hw = io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_hx = io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_reserved_for_future = io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_ppn = io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_reserved_for_software = io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_d = io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_a = io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_g = io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_u = io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_x = io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_w = io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_r = io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_pte_v = io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_level = io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_homogeneous = io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_gpa_valid = io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_gpa_bits = io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
assign io_requestor_1_resp_bits_gpa_is_pte = io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_debug = io_requestor_1_status_debug_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_cease = io_requestor_1_status_cease_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_wfi = io_requestor_1_status_wfi_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_isa = io_requestor_1_status_isa_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_dv = io_requestor_1_status_dv_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_v = io_requestor_1_status_v_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_mpv = io_requestor_1_status_mpv_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_gva = io_requestor_1_status_gva_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_mpp = io_requestor_1_status_mpp_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_mpie = io_requestor_1_status_mpie_0; // @[PTW.scala:219:7]
assign io_requestor_1_status_mie = io_requestor_1_status_mie_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_debug = io_requestor_1_gstatus_debug_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_cease = io_requestor_1_gstatus_cease_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_wfi = io_requestor_1_gstatus_wfi_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_isa = io_requestor_1_gstatus_isa_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_dprv = io_requestor_1_gstatus_dprv_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_dv = io_requestor_1_gstatus_dv_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_prv = io_requestor_1_gstatus_prv_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_v = io_requestor_1_gstatus_v_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_sd = io_requestor_1_gstatus_sd_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_zero2 = io_requestor_1_gstatus_zero2_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_mpv = io_requestor_1_gstatus_mpv_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_gva = io_requestor_1_gstatus_gva_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_mbe = io_requestor_1_gstatus_mbe_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_sbe = io_requestor_1_gstatus_sbe_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_sxl = io_requestor_1_gstatus_sxl_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_sd_rv32 = io_requestor_1_gstatus_sd_rv32_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_zero1 = io_requestor_1_gstatus_zero1_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_tsr = io_requestor_1_gstatus_tsr_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_tw = io_requestor_1_gstatus_tw_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_tvm = io_requestor_1_gstatus_tvm_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_mxr = io_requestor_1_gstatus_mxr_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_sum = io_requestor_1_gstatus_sum_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_mprv = io_requestor_1_gstatus_mprv_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_fs = io_requestor_1_gstatus_fs_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_mpp = io_requestor_1_gstatus_mpp_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_vs = io_requestor_1_gstatus_vs_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_spp = io_requestor_1_gstatus_spp_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_mpie = io_requestor_1_gstatus_mpie_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_ube = io_requestor_1_gstatus_ube_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_spie = io_requestor_1_gstatus_spie_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_upie = io_requestor_1_gstatus_upie_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_mie = io_requestor_1_gstatus_mie_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_hie = io_requestor_1_gstatus_hie_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_sie = io_requestor_1_gstatus_sie_0; // @[PTW.scala:219:7]
assign io_requestor_1_gstatus_uie = io_requestor_1_gstatus_uie_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_0_cfg_l = io_requestor_1_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_0_cfg_a = io_requestor_1_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_0_cfg_x = io_requestor_1_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_0_cfg_w = io_requestor_1_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_0_cfg_r = io_requestor_1_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_0_addr = io_requestor_1_pmp_0_addr_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_0_mask = io_requestor_1_pmp_0_mask_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_1_cfg_l = io_requestor_1_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_1_cfg_a = io_requestor_1_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_1_cfg_x = io_requestor_1_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_1_cfg_w = io_requestor_1_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_1_cfg_r = io_requestor_1_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_1_addr = io_requestor_1_pmp_1_addr_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_1_mask = io_requestor_1_pmp_1_mask_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_2_cfg_l = io_requestor_1_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_2_cfg_a = io_requestor_1_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_2_cfg_x = io_requestor_1_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_2_cfg_w = io_requestor_1_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_2_cfg_r = io_requestor_1_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_2_addr = io_requestor_1_pmp_2_addr_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_2_mask = io_requestor_1_pmp_2_mask_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_3_cfg_l = io_requestor_1_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_3_cfg_a = io_requestor_1_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_3_cfg_x = io_requestor_1_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_3_cfg_w = io_requestor_1_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_3_cfg_r = io_requestor_1_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_3_addr = io_requestor_1_pmp_3_addr_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_3_mask = io_requestor_1_pmp_3_mask_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_4_cfg_l = io_requestor_1_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_4_cfg_a = io_requestor_1_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_4_cfg_x = io_requestor_1_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_4_cfg_w = io_requestor_1_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_4_cfg_r = io_requestor_1_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_4_addr = io_requestor_1_pmp_4_addr_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_4_mask = io_requestor_1_pmp_4_mask_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_5_cfg_l = io_requestor_1_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_5_cfg_a = io_requestor_1_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_5_cfg_x = io_requestor_1_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_5_cfg_w = io_requestor_1_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_5_cfg_r = io_requestor_1_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_5_addr = io_requestor_1_pmp_5_addr_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_5_mask = io_requestor_1_pmp_5_mask_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_6_cfg_l = io_requestor_1_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_6_cfg_a = io_requestor_1_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_6_cfg_x = io_requestor_1_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_6_cfg_w = io_requestor_1_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_6_cfg_r = io_requestor_1_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_6_addr = io_requestor_1_pmp_6_addr_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_6_mask = io_requestor_1_pmp_6_mask_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_7_cfg_l = io_requestor_1_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_7_cfg_a = io_requestor_1_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_7_cfg_x = io_requestor_1_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_7_cfg_w = io_requestor_1_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_7_cfg_r = io_requestor_1_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_7_addr = io_requestor_1_pmp_7_addr_0; // @[PTW.scala:219:7]
assign io_requestor_1_pmp_7_mask = io_requestor_1_pmp_7_mask_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_0_ren = io_requestor_1_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_0_wen = io_requestor_1_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_0_wdata = io_requestor_1_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_0_value = io_requestor_1_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_1_ren = io_requestor_1_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_1_wen = io_requestor_1_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_1_wdata = io_requestor_1_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_1_value = io_requestor_1_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_2_ren = io_requestor_1_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_2_wen = io_requestor_1_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_2_wdata = io_requestor_1_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_2_value = io_requestor_1_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_3_ren = io_requestor_1_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_3_wen = io_requestor_1_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_3_wdata = io_requestor_1_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
assign io_requestor_1_customCSRs_csrs_3_value = io_requestor_1_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
assign io_dpath_perf_pte_miss = io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7]
assign io_dpath_perf_pte_hit = io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e8_s24 :
input clock : Clock
input reset : Reset
output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>, validout : UInt<1>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_80
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_80
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
wire valid_stage0 : UInt<1>
wire roundingMode_stage0 : UInt<3>
wire detectTininess_stage0 : UInt<1>
regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny
regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<49>, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<49>}
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits
regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b
connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits
regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundingMode_stage0_pipe_v, io.validin
reg roundingMode_stage0_pipe_b : UInt<3>, clock
when io.validin :
connect roundingMode_stage0_pipe_b, io.roundingMode
wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v
connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b
connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits
regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect detectTininess_stage0_pipe_v, io.validin
reg detectTininess_stage0_pipe_b : UInt<1>, clock
when io.validin :
connect detectTininess_stage0_pipe_b, io.detectTininess
wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v
connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b
connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits
regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect valid_stage0_pipe_v, io.validin
reg valid_stage0_pipe_b : UInt<1>, clock
when io.validin :
connect valid_stage0_pipe_b, UInt<1>(0h0)
wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v
connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b
connect valid_stage0, valid_stage0_pipe_out.valid
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_136
regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc
wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v
connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b
connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits
regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut
wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v
connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b
connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig
connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp
connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign
connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero
connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf
connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN
regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0
wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v
connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b
connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits
regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0
wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v
connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b
connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits
regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_validout_pipe_v, valid_stage0
reg io_validout_pipe_b : UInt<1>, clock
when valid_stage0 :
connect io_validout_pipe_b, UInt<1>(0h0)
wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect io_validout_pipe_out.valid, io_validout_pipe_v
connect io_validout_pipe_out.bits, io_validout_pipe_b
connect io.validout, io_validout_pipe_out.valid
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFNPipe_l2_e8_s24( // @[FPU.scala:633:7]
input clock, // @[FPU.scala:633:7]
input reset, // @[FPU.scala:633:7]
input io_validin, // @[FPU.scala:638:16]
input [1:0] io_op, // @[FPU.scala:638:16]
input [32:0] io_a, // @[FPU.scala:638:16]
input [32:0] io_b, // @[FPU.scala:638:16]
input [32:0] io_c, // @[FPU.scala:638:16]
input [2:0] io_roundingMode, // @[FPU.scala:638:16]
output [32:0] io_out, // @[FPU.scala:638:16]
output [4:0] io_exceptionFlags, // @[FPU.scala:638:16]
output io_validout // @[FPU.scala:638:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41]
wire io_validin_0 = io_validin; // @[FPU.scala:633:7]
wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7]
wire [32:0] io_a_0 = io_a; // @[FPU.scala:633:7]
wire [32:0] io_b_0 = io_b; // @[FPU.scala:633:7]
wire [32:0] io_c_0 = io_c; // @[FPU.scala:633:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7]
wire io_detectTininess = 1'h1; // @[FPU.scala:633:7]
wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37]
wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21]
wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_valid; // @[Valid.scala:135:21]
wire [32:0] io_out_0; // @[FPU.scala:633:7]
wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7]
wire io_validout_0; // @[FPU.scala:633:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50]
wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
wire valid_stage0; // @[FPU.scala:667:28]
wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26]
reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26]
wire [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26]
reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26]
wire [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26]
reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26]
wire [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26]
wire [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24]
wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26]
assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26]
assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24]
wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg valid_stage0_pipe_v; // @[Valid.scala:141:24]
assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26]
reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26]
wire [9:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26]
reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26]
wire [26:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26]
reg io_validout_pipe_v; // @[Valid.scala:141:24]
assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24]
assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:633:7]
if (reset) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
end
if (io_validin_0) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
end
if (valid_stage0) begin // @[FPU.scala:667:28]
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26]
end
roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
always @(posedge)
MulAddRecFNToRaw_preMul_e8_s24_80 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41]
.io_op (io_op_0), // @[FPU.scala:633:7]
.io_a (io_a_0), // @[FPU.scala:633:7]
.io_b (io_b_0), // @[FPU.scala:633:7]
.io_c (io_c_0), // @[FPU.scala:633:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[FPU.scala:654:41]
MulAddRecFNToRaw_postMul_e8_s24_80 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42]
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21]
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21]
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21]
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21]
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21]
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21]
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21]
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21]
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21]
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21]
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21]
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21]
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[FPU.scala:655:42]
RoundRawFNToRecFN_e8_s24_136 roundRawFNToRecFN ( // @[FPU.scala:682:35]
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21]
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21]
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21]
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21]
.io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21]
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21]
.io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21]
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[FPU.scala:682:35]
assign io_out = io_out_0; // @[FPU.scala:633:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7]
assign io_validout = io_validout_0; // @[FPU.scala:633:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[18]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
node _source_ok_T_38 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[2])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[3])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[4])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[5])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[6])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[7])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[8])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[9])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[10])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[11])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[12])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[13])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[14])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[15])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[16])
node source_ok = or(_source_ok_T_53, _source_ok_WIRE[17])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = and(_T_11, _T_24)
node _T_169 = and(_T_168, _T_37)
node _T_170 = and(_T_169, _T_50)
node _T_171 = and(_T_170, _T_63)
node _T_172 = and(_T_171, _T_71)
node _T_173 = and(_T_172, _T_79)
node _T_174 = and(_T_173, _T_87)
node _T_175 = and(_T_174, _T_95)
node _T_176 = and(_T_175, _T_103)
node _T_177 = and(_T_176, _T_111)
node _T_178 = and(_T_177, _T_119)
node _T_179 = and(_T_178, _T_127)
node _T_180 = and(_T_179, _T_135)
node _T_181 = and(_T_180, _T_143)
node _T_182 = and(_T_181, _T_151)
node _T_183 = and(_T_182, _T_159)
node _T_184 = and(_T_183, _T_167)
node _T_185 = asUInt(reset)
node _T_186 = eq(_T_185, UInt<1>(0h0))
when _T_186 :
node _T_187 = eq(_T_184, UInt<1>(0h0))
when _T_187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_184, UInt<1>(0h1), "") : assert_1
node _T_188 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_188 :
node _T_189 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_190 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_191 = and(_T_189, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_193 = shr(io.in.a.bits.source, 2)
node _T_194 = eq(_T_193, UInt<1>(0h0))
node _T_195 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_196 = and(_T_194, _T_195)
node _T_197 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_199 = shr(io.in.a.bits.source, 2)
node _T_200 = eq(_T_199, UInt<1>(0h1))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_204 = and(_T_202, _T_203)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<2>(0h2))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<2>(0h3))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_220 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_221 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_222 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_226 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_227 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_228 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_230 = or(_T_192, _T_198)
node _T_231 = or(_T_230, _T_204)
node _T_232 = or(_T_231, _T_210)
node _T_233 = or(_T_232, _T_216)
node _T_234 = or(_T_233, _T_217)
node _T_235 = or(_T_234, _T_218)
node _T_236 = or(_T_235, _T_219)
node _T_237 = or(_T_236, _T_220)
node _T_238 = or(_T_237, _T_221)
node _T_239 = or(_T_238, _T_222)
node _T_240 = or(_T_239, _T_223)
node _T_241 = or(_T_240, _T_224)
node _T_242 = or(_T_241, _T_225)
node _T_243 = or(_T_242, _T_226)
node _T_244 = or(_T_243, _T_227)
node _T_245 = or(_T_244, _T_228)
node _T_246 = or(_T_245, _T_229)
node _T_247 = and(_T_191, _T_246)
node _T_248 = or(UInt<1>(0h0), _T_247)
node _T_249 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<13>(0h1000)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_256 = cvt(_T_255)
node _T_257 = and(_T_256, asSInt(UInt<13>(0h1000)))
node _T_258 = asSInt(_T_257)
node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0)))
node _T_260 = or(_T_254, _T_259)
node _T_261 = and(_T_249, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = and(_T_248, _T_262)
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_263, UInt<1>(0h1), "") : assert_2
node _T_267 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_268 = shr(io.in.a.bits.source, 2)
node _T_269 = eq(_T_268, UInt<1>(0h0))
node _T_270 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_271 = and(_T_269, _T_270)
node _T_272 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_273 = and(_T_271, _T_272)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_274 = shr(io.in.a.bits.source, 2)
node _T_275 = eq(_T_274, UInt<1>(0h1))
node _T_276 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_277 = and(_T_275, _T_276)
node _T_278 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_279 = and(_T_277, _T_278)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_280 = shr(io.in.a.bits.source, 2)
node _T_281 = eq(_T_280, UInt<2>(0h2))
node _T_282 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_283 = and(_T_281, _T_282)
node _T_284 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_285 = and(_T_283, _T_284)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_286 = shr(io.in.a.bits.source, 2)
node _T_287 = eq(_T_286, UInt<2>(0h3))
node _T_288 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_289 = and(_T_287, _T_288)
node _T_290 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_291 = and(_T_289, _T_290)
node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_294 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_295 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_299 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_300 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_301 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_302 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_303 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_304 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[18]
connect _WIRE[0], _T_267
connect _WIRE[1], _T_273
connect _WIRE[2], _T_279
connect _WIRE[3], _T_285
connect _WIRE[4], _T_291
connect _WIRE[5], _T_292
connect _WIRE[6], _T_293
connect _WIRE[7], _T_294
connect _WIRE[8], _T_295
connect _WIRE[9], _T_296
connect _WIRE[10], _T_297
connect _WIRE[11], _T_298
connect _WIRE[12], _T_299
connect _WIRE[13], _T_300
connect _WIRE[14], _T_301
connect _WIRE[15], _T_302
connect _WIRE[16], _T_303
connect _WIRE[17], _T_304
node _T_305 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_306 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_308 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_309 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_310 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_311 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_312 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_313 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_314 = mux(_WIRE[5], _T_305, UInt<1>(0h0))
node _T_315 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_316 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_317 = mux(_WIRE[8], _T_306, UInt<1>(0h0))
node _T_318 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_320 = mux(_WIRE[11], _T_307, UInt<1>(0h0))
node _T_321 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_322 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_323 = mux(_WIRE[14], _T_308, UInt<1>(0h0))
node _T_324 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_325 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_326 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_327 = or(_T_309, _T_310)
node _T_328 = or(_T_327, _T_311)
node _T_329 = or(_T_328, _T_312)
node _T_330 = or(_T_329, _T_313)
node _T_331 = or(_T_330, _T_314)
node _T_332 = or(_T_331, _T_315)
node _T_333 = or(_T_332, _T_316)
node _T_334 = or(_T_333, _T_317)
node _T_335 = or(_T_334, _T_318)
node _T_336 = or(_T_335, _T_319)
node _T_337 = or(_T_336, _T_320)
node _T_338 = or(_T_337, _T_321)
node _T_339 = or(_T_338, _T_322)
node _T_340 = or(_T_339, _T_323)
node _T_341 = or(_T_340, _T_324)
node _T_342 = or(_T_341, _T_325)
node _T_343 = or(_T_342, _T_326)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_343
node _T_344 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_345 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_346 = and(_T_344, _T_345)
node _T_347 = or(UInt<1>(0h0), _T_346)
node _T_348 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_349 = cvt(_T_348)
node _T_350 = and(_T_349, asSInt(UInt<13>(0h1000)))
node _T_351 = asSInt(_T_350)
node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0)))
node _T_353 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = or(_T_352, _T_357)
node _T_359 = and(_T_347, _T_358)
node _T_360 = or(UInt<1>(0h0), _T_359)
node _T_361 = and(_WIRE_1, _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_361, UInt<1>(0h1), "") : assert_3
node _T_365 = asUInt(reset)
node _T_366 = eq(_T_365, UInt<1>(0h0))
when _T_366 :
node _T_367 = eq(source_ok, UInt<1>(0h0))
when _T_367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_368 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_368, UInt<1>(0h1), "") : assert_5
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(is_aligned, UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_375 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_375, UInt<1>(0h1), "") : assert_7
node _T_379 = not(io.in.a.bits.mask)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_380, UInt<1>(0h1), "") : assert_8
node _T_384 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_385 = asUInt(reset)
node _T_386 = eq(_T_385, UInt<1>(0h0))
when _T_386 :
node _T_387 = eq(_T_384, UInt<1>(0h0))
when _T_387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_384, UInt<1>(0h1), "") : assert_9
node _T_388 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_388 :
node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_391 = and(_T_389, _T_390)
node _T_392 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<1>(0h0))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_399 = shr(io.in.a.bits.source, 2)
node _T_400 = eq(_T_399, UInt<1>(0h1))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_405 = shr(io.in.a.bits.source, 2)
node _T_406 = eq(_T_405, UInt<2>(0h2))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_410 = and(_T_408, _T_409)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_411 = shr(io.in.a.bits.source, 2)
node _T_412 = eq(_T_411, UInt<2>(0h3))
node _T_413 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_414 = and(_T_412, _T_413)
node _T_415 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_416 = and(_T_414, _T_415)
node _T_417 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_429 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_430 = or(_T_392, _T_398)
node _T_431 = or(_T_430, _T_404)
node _T_432 = or(_T_431, _T_410)
node _T_433 = or(_T_432, _T_416)
node _T_434 = or(_T_433, _T_417)
node _T_435 = or(_T_434, _T_418)
node _T_436 = or(_T_435, _T_419)
node _T_437 = or(_T_436, _T_420)
node _T_438 = or(_T_437, _T_421)
node _T_439 = or(_T_438, _T_422)
node _T_440 = or(_T_439, _T_423)
node _T_441 = or(_T_440, _T_424)
node _T_442 = or(_T_441, _T_425)
node _T_443 = or(_T_442, _T_426)
node _T_444 = or(_T_443, _T_427)
node _T_445 = or(_T_444, _T_428)
node _T_446 = or(_T_445, _T_429)
node _T_447 = and(_T_391, _T_446)
node _T_448 = or(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_450 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_451 = cvt(_T_450)
node _T_452 = and(_T_451, asSInt(UInt<13>(0h1000)))
node _T_453 = asSInt(_T_452)
node _T_454 = eq(_T_453, asSInt(UInt<1>(0h0)))
node _T_455 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_456 = cvt(_T_455)
node _T_457 = and(_T_456, asSInt(UInt<13>(0h1000)))
node _T_458 = asSInt(_T_457)
node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0)))
node _T_460 = or(_T_454, _T_459)
node _T_461 = and(_T_449, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = and(_T_448, _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_463, UInt<1>(0h1), "") : assert_10
node _T_467 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_468 = shr(io.in.a.bits.source, 2)
node _T_469 = eq(_T_468, UInt<1>(0h0))
node _T_470 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_471 = and(_T_469, _T_470)
node _T_472 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_473 = and(_T_471, _T_472)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_474 = shr(io.in.a.bits.source, 2)
node _T_475 = eq(_T_474, UInt<1>(0h1))
node _T_476 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_477 = and(_T_475, _T_476)
node _T_478 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_480 = shr(io.in.a.bits.source, 2)
node _T_481 = eq(_T_480, UInt<2>(0h2))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_485 = and(_T_483, _T_484)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_486 = shr(io.in.a.bits.source, 2)
node _T_487 = eq(_T_486, UInt<2>(0h3))
node _T_488 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_489 = and(_T_487, _T_488)
node _T_490 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_491 = and(_T_489, _T_490)
node _T_492 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_493 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_494 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_495 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_496 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_497 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_501 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_502 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_503 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_504 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[18]
connect _WIRE_2[0], _T_467
connect _WIRE_2[1], _T_473
connect _WIRE_2[2], _T_479
connect _WIRE_2[3], _T_485
connect _WIRE_2[4], _T_491
connect _WIRE_2[5], _T_492
connect _WIRE_2[6], _T_493
connect _WIRE_2[7], _T_494
connect _WIRE_2[8], _T_495
connect _WIRE_2[9], _T_496
connect _WIRE_2[10], _T_497
connect _WIRE_2[11], _T_498
connect _WIRE_2[12], _T_499
connect _WIRE_2[13], _T_500
connect _WIRE_2[14], _T_501
connect _WIRE_2[15], _T_502
connect _WIRE_2[16], _T_503
connect _WIRE_2[17], _T_504
node _T_505 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_506 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_507 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_508 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_509 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_510 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_512 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_513 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_514 = mux(_WIRE_2[5], _T_505, UInt<1>(0h0))
node _T_515 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_516 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_517 = mux(_WIRE_2[8], _T_506, UInt<1>(0h0))
node _T_518 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_519 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_520 = mux(_WIRE_2[11], _T_507, UInt<1>(0h0))
node _T_521 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_522 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_523 = mux(_WIRE_2[14], _T_508, UInt<1>(0h0))
node _T_524 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_525 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_527 = or(_T_509, _T_510)
node _T_528 = or(_T_527, _T_511)
node _T_529 = or(_T_528, _T_512)
node _T_530 = or(_T_529, _T_513)
node _T_531 = or(_T_530, _T_514)
node _T_532 = or(_T_531, _T_515)
node _T_533 = or(_T_532, _T_516)
node _T_534 = or(_T_533, _T_517)
node _T_535 = or(_T_534, _T_518)
node _T_536 = or(_T_535, _T_519)
node _T_537 = or(_T_536, _T_520)
node _T_538 = or(_T_537, _T_521)
node _T_539 = or(_T_538, _T_522)
node _T_540 = or(_T_539, _T_523)
node _T_541 = or(_T_540, _T_524)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_526)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_543
node _T_544 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_545 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_546 = and(_T_544, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_549 = cvt(_T_548)
node _T_550 = and(_T_549, asSInt(UInt<13>(0h1000)))
node _T_551 = asSInt(_T_550)
node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0)))
node _T_553 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_554 = cvt(_T_553)
node _T_555 = and(_T_554, asSInt(UInt<13>(0h1000)))
node _T_556 = asSInt(_T_555)
node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0)))
node _T_558 = or(_T_552, _T_557)
node _T_559 = and(_T_547, _T_558)
node _T_560 = or(UInt<1>(0h0), _T_559)
node _T_561 = and(_WIRE_3, _T_560)
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(_T_561, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_561, UInt<1>(0h1), "") : assert_11
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(source_ok, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_568 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_568, UInt<1>(0h1), "") : assert_13
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(is_aligned, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_575 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_576 = asUInt(reset)
node _T_577 = eq(_T_576, UInt<1>(0h0))
when _T_577 :
node _T_578 = eq(_T_575, UInt<1>(0h0))
when _T_578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_575, UInt<1>(0h1), "") : assert_15
node _T_579 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_579, UInt<1>(0h1), "") : assert_16
node _T_583 = not(io.in.a.bits.mask)
node _T_584 = eq(_T_583, UInt<1>(0h0))
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_584, UInt<1>(0h1), "") : assert_17
node _T_588 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_588, UInt<1>(0h1), "") : assert_18
node _T_592 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_592 :
node _T_593 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_594 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_595 = and(_T_593, _T_594)
node _T_596 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_597 = shr(io.in.a.bits.source, 2)
node _T_598 = eq(_T_597, UInt<1>(0h0))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_602 = and(_T_600, _T_601)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_603 = shr(io.in.a.bits.source, 2)
node _T_604 = eq(_T_603, UInt<1>(0h1))
node _T_605 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_606 = and(_T_604, _T_605)
node _T_607 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_609 = shr(io.in.a.bits.source, 2)
node _T_610 = eq(_T_609, UInt<2>(0h2))
node _T_611 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_612 = and(_T_610, _T_611)
node _T_613 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_614 = and(_T_612, _T_613)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_615 = shr(io.in.a.bits.source, 2)
node _T_616 = eq(_T_615, UInt<2>(0h3))
node _T_617 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_618 = and(_T_616, _T_617)
node _T_619 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_620 = and(_T_618, _T_619)
node _T_621 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_622 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_623 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_628 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_629 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_630 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_631 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_632 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_633 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_634 = or(_T_596, _T_602)
node _T_635 = or(_T_634, _T_608)
node _T_636 = or(_T_635, _T_614)
node _T_637 = or(_T_636, _T_620)
node _T_638 = or(_T_637, _T_621)
node _T_639 = or(_T_638, _T_622)
node _T_640 = or(_T_639, _T_623)
node _T_641 = or(_T_640, _T_624)
node _T_642 = or(_T_641, _T_625)
node _T_643 = or(_T_642, _T_626)
node _T_644 = or(_T_643, _T_627)
node _T_645 = or(_T_644, _T_628)
node _T_646 = or(_T_645, _T_629)
node _T_647 = or(_T_646, _T_630)
node _T_648 = or(_T_647, _T_631)
node _T_649 = or(_T_648, _T_632)
node _T_650 = or(_T_649, _T_633)
node _T_651 = and(_T_595, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_652, UInt<1>(0h1), "") : assert_19
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_658 = and(_T_656, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_658)
node _T_660 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = or(_T_664, _T_669)
node _T_671 = and(_T_659, _T_670)
node _T_672 = or(UInt<1>(0h0), _T_671)
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(_T_672, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_672, UInt<1>(0h1), "") : assert_20
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(source_ok, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(is_aligned, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_682 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_T_682, UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_682, UInt<1>(0h1), "") : assert_23
node _T_686 = eq(io.in.a.bits.mask, mask)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_686, UInt<1>(0h1), "") : assert_24
node _T_690 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_690, UInt<1>(0h1), "") : assert_25
node _T_694 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_694 :
node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_697 = and(_T_695, _T_696)
node _T_698 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_699 = shr(io.in.a.bits.source, 2)
node _T_700 = eq(_T_699, UInt<1>(0h0))
node _T_701 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_702 = and(_T_700, _T_701)
node _T_703 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_704 = and(_T_702, _T_703)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_705 = shr(io.in.a.bits.source, 2)
node _T_706 = eq(_T_705, UInt<1>(0h1))
node _T_707 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_708 = and(_T_706, _T_707)
node _T_709 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_710 = and(_T_708, _T_709)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_711 = shr(io.in.a.bits.source, 2)
node _T_712 = eq(_T_711, UInt<2>(0h2))
node _T_713 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_714 = and(_T_712, _T_713)
node _T_715 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_716 = and(_T_714, _T_715)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_717 = shr(io.in.a.bits.source, 2)
node _T_718 = eq(_T_717, UInt<2>(0h3))
node _T_719 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_720 = and(_T_718, _T_719)
node _T_721 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_722 = and(_T_720, _T_721)
node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_727 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_728 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_729 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_730 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_731 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_732 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_733 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_734 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_735 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_736 = or(_T_698, _T_704)
node _T_737 = or(_T_736, _T_710)
node _T_738 = or(_T_737, _T_716)
node _T_739 = or(_T_738, _T_722)
node _T_740 = or(_T_739, _T_723)
node _T_741 = or(_T_740, _T_724)
node _T_742 = or(_T_741, _T_725)
node _T_743 = or(_T_742, _T_726)
node _T_744 = or(_T_743, _T_727)
node _T_745 = or(_T_744, _T_728)
node _T_746 = or(_T_745, _T_729)
node _T_747 = or(_T_746, _T_730)
node _T_748 = or(_T_747, _T_731)
node _T_749 = or(_T_748, _T_732)
node _T_750 = or(_T_749, _T_733)
node _T_751 = or(_T_750, _T_734)
node _T_752 = or(_T_751, _T_735)
node _T_753 = and(_T_697, _T_752)
node _T_754 = or(UInt<1>(0h0), _T_753)
node _T_755 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_756 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_757 = and(_T_755, _T_756)
node _T_758 = or(UInt<1>(0h0), _T_757)
node _T_759 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_765 = cvt(_T_764)
node _T_766 = and(_T_765, asSInt(UInt<13>(0h1000)))
node _T_767 = asSInt(_T_766)
node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0)))
node _T_769 = or(_T_763, _T_768)
node _T_770 = and(_T_758, _T_769)
node _T_771 = or(UInt<1>(0h0), _T_770)
node _T_772 = and(_T_754, _T_771)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_772, UInt<1>(0h1), "") : assert_26
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(source_ok, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(is_aligned, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_782 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_T_782, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_782, UInt<1>(0h1), "") : assert_29
node _T_786 = eq(io.in.a.bits.mask, mask)
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_786, UInt<1>(0h1), "") : assert_30
node _T_790 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_790 :
node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_792 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_793 = and(_T_791, _T_792)
node _T_794 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_795 = shr(io.in.a.bits.source, 2)
node _T_796 = eq(_T_795, UInt<1>(0h0))
node _T_797 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_798 = and(_T_796, _T_797)
node _T_799 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_800 = and(_T_798, _T_799)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_801 = shr(io.in.a.bits.source, 2)
node _T_802 = eq(_T_801, UInt<1>(0h1))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_806 = and(_T_804, _T_805)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_807 = shr(io.in.a.bits.source, 2)
node _T_808 = eq(_T_807, UInt<2>(0h2))
node _T_809 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_810 = and(_T_808, _T_809)
node _T_811 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_812 = and(_T_810, _T_811)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_813 = shr(io.in.a.bits.source, 2)
node _T_814 = eq(_T_813, UInt<2>(0h3))
node _T_815 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_816 = and(_T_814, _T_815)
node _T_817 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_818 = and(_T_816, _T_817)
node _T_819 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_820 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_821 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_822 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_823 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_824 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_825 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_826 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_827 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_828 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_829 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_830 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_831 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_832 = or(_T_794, _T_800)
node _T_833 = or(_T_832, _T_806)
node _T_834 = or(_T_833, _T_812)
node _T_835 = or(_T_834, _T_818)
node _T_836 = or(_T_835, _T_819)
node _T_837 = or(_T_836, _T_820)
node _T_838 = or(_T_837, _T_821)
node _T_839 = or(_T_838, _T_822)
node _T_840 = or(_T_839, _T_823)
node _T_841 = or(_T_840, _T_824)
node _T_842 = or(_T_841, _T_825)
node _T_843 = or(_T_842, _T_826)
node _T_844 = or(_T_843, _T_827)
node _T_845 = or(_T_844, _T_828)
node _T_846 = or(_T_845, _T_829)
node _T_847 = or(_T_846, _T_830)
node _T_848 = or(_T_847, _T_831)
node _T_849 = and(_T_793, _T_848)
node _T_850 = or(UInt<1>(0h0), _T_849)
node _T_851 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_852 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_853 = and(_T_851, _T_852)
node _T_854 = or(UInt<1>(0h0), _T_853)
node _T_855 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_856 = cvt(_T_855)
node _T_857 = and(_T_856, asSInt(UInt<13>(0h1000)))
node _T_858 = asSInt(_T_857)
node _T_859 = eq(_T_858, asSInt(UInt<1>(0h0)))
node _T_860 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_861 = cvt(_T_860)
node _T_862 = and(_T_861, asSInt(UInt<13>(0h1000)))
node _T_863 = asSInt(_T_862)
node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0)))
node _T_865 = or(_T_859, _T_864)
node _T_866 = and(_T_854, _T_865)
node _T_867 = or(UInt<1>(0h0), _T_866)
node _T_868 = and(_T_850, _T_867)
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_868, UInt<1>(0h1), "") : assert_31
node _T_872 = asUInt(reset)
node _T_873 = eq(_T_872, UInt<1>(0h0))
when _T_873 :
node _T_874 = eq(source_ok, UInt<1>(0h0))
when _T_874 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(is_aligned, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_878 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_878, UInt<1>(0h1), "") : assert_34
node _T_882 = not(mask)
node _T_883 = and(io.in.a.bits.mask, _T_882)
node _T_884 = eq(_T_883, UInt<1>(0h0))
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(_T_884, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_884, UInt<1>(0h1), "") : assert_35
node _T_888 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_888 :
node _T_889 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_890 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_891 = and(_T_889, _T_890)
node _T_892 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_893 = shr(io.in.a.bits.source, 2)
node _T_894 = eq(_T_893, UInt<1>(0h0))
node _T_895 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_896 = and(_T_894, _T_895)
node _T_897 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_898 = and(_T_896, _T_897)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_899 = shr(io.in.a.bits.source, 2)
node _T_900 = eq(_T_899, UInt<1>(0h1))
node _T_901 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_902 = and(_T_900, _T_901)
node _T_903 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_904 = and(_T_902, _T_903)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_905 = shr(io.in.a.bits.source, 2)
node _T_906 = eq(_T_905, UInt<2>(0h2))
node _T_907 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_908 = and(_T_906, _T_907)
node _T_909 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_910 = and(_T_908, _T_909)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_911 = shr(io.in.a.bits.source, 2)
node _T_912 = eq(_T_911, UInt<2>(0h3))
node _T_913 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_914 = and(_T_912, _T_913)
node _T_915 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_916 = and(_T_914, _T_915)
node _T_917 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_918 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_919 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_920 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_921 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_922 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_923 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_924 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_925 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_926 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_927 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_928 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_929 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_930 = or(_T_892, _T_898)
node _T_931 = or(_T_930, _T_904)
node _T_932 = or(_T_931, _T_910)
node _T_933 = or(_T_932, _T_916)
node _T_934 = or(_T_933, _T_917)
node _T_935 = or(_T_934, _T_918)
node _T_936 = or(_T_935, _T_919)
node _T_937 = or(_T_936, _T_920)
node _T_938 = or(_T_937, _T_921)
node _T_939 = or(_T_938, _T_922)
node _T_940 = or(_T_939, _T_923)
node _T_941 = or(_T_940, _T_924)
node _T_942 = or(_T_941, _T_925)
node _T_943 = or(_T_942, _T_926)
node _T_944 = or(_T_943, _T_927)
node _T_945 = or(_T_944, _T_928)
node _T_946 = or(_T_945, _T_929)
node _T_947 = and(_T_891, _T_946)
node _T_948 = or(UInt<1>(0h0), _T_947)
node _T_949 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_950 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_951 = and(_T_949, _T_950)
node _T_952 = or(UInt<1>(0h0), _T_951)
node _T_953 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_954 = cvt(_T_953)
node _T_955 = and(_T_954, asSInt(UInt<13>(0h1000)))
node _T_956 = asSInt(_T_955)
node _T_957 = eq(_T_956, asSInt(UInt<1>(0h0)))
node _T_958 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_959 = cvt(_T_958)
node _T_960 = and(_T_959, asSInt(UInt<13>(0h1000)))
node _T_961 = asSInt(_T_960)
node _T_962 = eq(_T_961, asSInt(UInt<1>(0h0)))
node _T_963 = or(_T_957, _T_962)
node _T_964 = and(_T_952, _T_963)
node _T_965 = or(UInt<1>(0h0), _T_964)
node _T_966 = and(_T_948, _T_965)
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_966, UInt<1>(0h1), "") : assert_36
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(source_ok, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(is_aligned, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_976 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_976, UInt<1>(0h1), "") : assert_39
node _T_980 = eq(io.in.a.bits.mask, mask)
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_980, UInt<1>(0h1), "") : assert_40
node _T_984 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_984 :
node _T_985 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_986 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_987 = and(_T_985, _T_986)
node _T_988 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_989 = shr(io.in.a.bits.source, 2)
node _T_990 = eq(_T_989, UInt<1>(0h0))
node _T_991 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_992 = and(_T_990, _T_991)
node _T_993 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_994 = and(_T_992, _T_993)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_995 = shr(io.in.a.bits.source, 2)
node _T_996 = eq(_T_995, UInt<1>(0h1))
node _T_997 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_998 = and(_T_996, _T_997)
node _T_999 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1000 = and(_T_998, _T_999)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1001 = shr(io.in.a.bits.source, 2)
node _T_1002 = eq(_T_1001, UInt<2>(0h2))
node _T_1003 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1004 = and(_T_1002, _T_1003)
node _T_1005 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1006 = and(_T_1004, _T_1005)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1007 = shr(io.in.a.bits.source, 2)
node _T_1008 = eq(_T_1007, UInt<2>(0h3))
node _T_1009 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1010 = and(_T_1008, _T_1009)
node _T_1011 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1012 = and(_T_1010, _T_1011)
node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1018 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1019 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1025 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1026 = or(_T_988, _T_994)
node _T_1027 = or(_T_1026, _T_1000)
node _T_1028 = or(_T_1027, _T_1006)
node _T_1029 = or(_T_1028, _T_1012)
node _T_1030 = or(_T_1029, _T_1013)
node _T_1031 = or(_T_1030, _T_1014)
node _T_1032 = or(_T_1031, _T_1015)
node _T_1033 = or(_T_1032, _T_1016)
node _T_1034 = or(_T_1033, _T_1017)
node _T_1035 = or(_T_1034, _T_1018)
node _T_1036 = or(_T_1035, _T_1019)
node _T_1037 = or(_T_1036, _T_1020)
node _T_1038 = or(_T_1037, _T_1021)
node _T_1039 = or(_T_1038, _T_1022)
node _T_1040 = or(_T_1039, _T_1023)
node _T_1041 = or(_T_1040, _T_1024)
node _T_1042 = or(_T_1041, _T_1025)
node _T_1043 = and(_T_987, _T_1042)
node _T_1044 = or(UInt<1>(0h0), _T_1043)
node _T_1045 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1046 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1047 = and(_T_1045, _T_1046)
node _T_1048 = or(UInt<1>(0h0), _T_1047)
node _T_1049 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1050 = cvt(_T_1049)
node _T_1051 = and(_T_1050, asSInt(UInt<13>(0h1000)))
node _T_1052 = asSInt(_T_1051)
node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0)))
node _T_1054 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1055 = cvt(_T_1054)
node _T_1056 = and(_T_1055, asSInt(UInt<13>(0h1000)))
node _T_1057 = asSInt(_T_1056)
node _T_1058 = eq(_T_1057, asSInt(UInt<1>(0h0)))
node _T_1059 = or(_T_1053, _T_1058)
node _T_1060 = and(_T_1048, _T_1059)
node _T_1061 = or(UInt<1>(0h0), _T_1060)
node _T_1062 = and(_T_1044, _T_1061)
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_41
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(source_ok, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(is_aligned, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1072 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_44
node _T_1076 = eq(io.in.a.bits.mask, mask)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_45
node _T_1080 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1080 :
node _T_1081 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1082 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1083 = and(_T_1081, _T_1082)
node _T_1084 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1085 = shr(io.in.a.bits.source, 2)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
node _T_1087 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1088 = and(_T_1086, _T_1087)
node _T_1089 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1090 = and(_T_1088, _T_1089)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1091 = shr(io.in.a.bits.source, 2)
node _T_1092 = eq(_T_1091, UInt<1>(0h1))
node _T_1093 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1094 = and(_T_1092, _T_1093)
node _T_1095 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1096 = and(_T_1094, _T_1095)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1097 = shr(io.in.a.bits.source, 2)
node _T_1098 = eq(_T_1097, UInt<2>(0h2))
node _T_1099 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1102 = and(_T_1100, _T_1101)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1103 = shr(io.in.a.bits.source, 2)
node _T_1104 = eq(_T_1103, UInt<2>(0h3))
node _T_1105 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1106 = and(_T_1104, _T_1105)
node _T_1107 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1121 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1122 = or(_T_1084, _T_1090)
node _T_1123 = or(_T_1122, _T_1096)
node _T_1124 = or(_T_1123, _T_1102)
node _T_1125 = or(_T_1124, _T_1108)
node _T_1126 = or(_T_1125, _T_1109)
node _T_1127 = or(_T_1126, _T_1110)
node _T_1128 = or(_T_1127, _T_1111)
node _T_1129 = or(_T_1128, _T_1112)
node _T_1130 = or(_T_1129, _T_1113)
node _T_1131 = or(_T_1130, _T_1114)
node _T_1132 = or(_T_1131, _T_1115)
node _T_1133 = or(_T_1132, _T_1116)
node _T_1134 = or(_T_1133, _T_1117)
node _T_1135 = or(_T_1134, _T_1118)
node _T_1136 = or(_T_1135, _T_1119)
node _T_1137 = or(_T_1136, _T_1120)
node _T_1138 = or(_T_1137, _T_1121)
node _T_1139 = and(_T_1083, _T_1138)
node _T_1140 = or(UInt<1>(0h0), _T_1139)
node _T_1141 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1142 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1143 = cvt(_T_1142)
node _T_1144 = and(_T_1143, asSInt(UInt<13>(0h1000)))
node _T_1145 = asSInt(_T_1144)
node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1148 = cvt(_T_1147)
node _T_1149 = and(_T_1148, asSInt(UInt<13>(0h1000)))
node _T_1150 = asSInt(_T_1149)
node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0)))
node _T_1152 = or(_T_1146, _T_1151)
node _T_1153 = and(_T_1141, _T_1152)
node _T_1154 = or(UInt<1>(0h0), _T_1153)
node _T_1155 = and(_T_1140, _T_1154)
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_T_1155, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1155, UInt<1>(0h1), "") : assert_46
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(source_ok, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(is_aligned, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1165 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_49
node _T_1169 = eq(io.in.a.bits.mask, mask)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_50
node _T_1173 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1177 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_52
node _source_ok_T_54 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<1>(0h0))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h1))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_67 = shr(io.in.d.bits.source, 2)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<2>(0h2))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_73 = shr(io.in.d.bits.source, 2)
node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h3))
node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_T_77 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_80 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_81 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_82 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[18]
connect _source_ok_WIRE_1[0], _source_ok_T_54
connect _source_ok_WIRE_1[1], _source_ok_T_60
connect _source_ok_WIRE_1[2], _source_ok_T_66
connect _source_ok_WIRE_1[3], _source_ok_T_72
connect _source_ok_WIRE_1[4], _source_ok_T_78
connect _source_ok_WIRE_1[5], _source_ok_T_79
connect _source_ok_WIRE_1[6], _source_ok_T_80
connect _source_ok_WIRE_1[7], _source_ok_T_81
connect _source_ok_WIRE_1[8], _source_ok_T_82
connect _source_ok_WIRE_1[9], _source_ok_T_83
connect _source_ok_WIRE_1[10], _source_ok_T_84
connect _source_ok_WIRE_1[11], _source_ok_T_85
connect _source_ok_WIRE_1[12], _source_ok_T_86
connect _source_ok_WIRE_1[13], _source_ok_T_87
connect _source_ok_WIRE_1[14], _source_ok_T_88
connect _source_ok_WIRE_1[15], _source_ok_T_89
connect _source_ok_WIRE_1[16], _source_ok_T_90
connect _source_ok_WIRE_1[17], _source_ok_T_91
node _source_ok_T_92 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[2])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[3])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[4])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[5])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[6])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[7])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[8])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[9])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[10])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[11])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[12])
node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[13])
node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[14])
node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[15])
node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[16])
node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[17])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1181 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1181 :
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(source_ok_1, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1185 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_54
node _T_1189 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_55
node _T_1193 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1194 = asUInt(reset)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
when _T_1195 :
node _T_1196 = eq(_T_1193, UInt<1>(0h0))
when _T_1196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1193, UInt<1>(0h1), "") : assert_56
node _T_1197 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1198 = asUInt(reset)
node _T_1199 = eq(_T_1198, UInt<1>(0h0))
when _T_1199 :
node _T_1200 = eq(_T_1197, UInt<1>(0h0))
when _T_1200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1197, UInt<1>(0h1), "") : assert_57
node _T_1201 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1201 :
node _T_1202 = asUInt(reset)
node _T_1203 = eq(_T_1202, UInt<1>(0h0))
when _T_1203 :
node _T_1204 = eq(source_ok_1, UInt<1>(0h0))
when _T_1204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1205 = asUInt(reset)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = eq(sink_ok, UInt<1>(0h0))
when _T_1207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1208 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_60
node _T_1212 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(_T_1212, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1212, UInt<1>(0h1), "") : assert_61
node _T_1216 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_62
node _T_1220 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_63
node _T_1224 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1225 = or(UInt<1>(0h0), _T_1224)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_64
node _T_1229 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1229 :
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(source_ok_1, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1233 = asUInt(reset)
node _T_1234 = eq(_T_1233, UInt<1>(0h0))
when _T_1234 :
node _T_1235 = eq(sink_ok, UInt<1>(0h0))
when _T_1235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1236 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_67
node _T_1240 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_68
node _T_1244 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_69
node _T_1248 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1249 = or(_T_1248, io.in.d.bits.corrupt)
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(_T_1249, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1249, UInt<1>(0h1), "") : assert_70
node _T_1253 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1254 = or(UInt<1>(0h0), _T_1253)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_71
node _T_1258 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(source_ok_1, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1262 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_73
node _T_1266 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1267 = asUInt(reset)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
when _T_1268 :
node _T_1269 = eq(_T_1266, UInt<1>(0h0))
when _T_1269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1266, UInt<1>(0h1), "") : assert_74
node _T_1270 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1271 = or(UInt<1>(0h0), _T_1270)
node _T_1272 = asUInt(reset)
node _T_1273 = eq(_T_1272, UInt<1>(0h0))
when _T_1273 :
node _T_1274 = eq(_T_1271, UInt<1>(0h0))
when _T_1274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1271, UInt<1>(0h1), "") : assert_75
node _T_1275 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1275 :
node _T_1276 = asUInt(reset)
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(source_ok_1, UInt<1>(0h0))
when _T_1278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1279 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_77
node _T_1283 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1284 = or(_T_1283, io.in.d.bits.corrupt)
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_78
node _T_1288 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1289 = or(UInt<1>(0h0), _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_79
node _T_1293 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1293 :
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(source_ok_1, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1297 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_81
node _T_1301 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1302 = asUInt(reset)
node _T_1303 = eq(_T_1302, UInt<1>(0h0))
when _T_1303 :
node _T_1304 = eq(_T_1301, UInt<1>(0h0))
when _T_1304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1301, UInt<1>(0h1), "") : assert_82
node _T_1305 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1306 = or(UInt<1>(0h0), _T_1305)
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1310 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1314 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1318 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1319 = asUInt(reset)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
when _T_1320 :
node _T_1321 = eq(_T_1318, UInt<1>(0h0))
when _T_1321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1318, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1322 = eq(a_first, UInt<1>(0h0))
node _T_1323 = and(io.in.a.valid, _T_1322)
when _T_1323 :
node _T_1324 = eq(io.in.a.bits.opcode, opcode)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_87
node _T_1328 = eq(io.in.a.bits.param, param)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_88
node _T_1332 = eq(io.in.a.bits.size, size)
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_89
node _T_1336 = eq(io.in.a.bits.source, source)
node _T_1337 = asUInt(reset)
node _T_1338 = eq(_T_1337, UInt<1>(0h0))
when _T_1338 :
node _T_1339 = eq(_T_1336, UInt<1>(0h0))
when _T_1339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1336, UInt<1>(0h1), "") : assert_90
node _T_1340 = eq(io.in.a.bits.address, address)
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_91
node _T_1344 = and(io.in.a.ready, io.in.a.valid)
node _T_1345 = and(_T_1344, a_first)
when _T_1345 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1346 = eq(d_first, UInt<1>(0h0))
node _T_1347 = and(io.in.d.valid, _T_1346)
when _T_1347 :
node _T_1348 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1349 = asUInt(reset)
node _T_1350 = eq(_T_1349, UInt<1>(0h0))
when _T_1350 :
node _T_1351 = eq(_T_1348, UInt<1>(0h0))
when _T_1351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1348, UInt<1>(0h1), "") : assert_92
node _T_1352 = eq(io.in.d.bits.param, param_1)
node _T_1353 = asUInt(reset)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
when _T_1354 :
node _T_1355 = eq(_T_1352, UInt<1>(0h0))
when _T_1355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1352, UInt<1>(0h1), "") : assert_93
node _T_1356 = eq(io.in.d.bits.size, size_1)
node _T_1357 = asUInt(reset)
node _T_1358 = eq(_T_1357, UInt<1>(0h0))
when _T_1358 :
node _T_1359 = eq(_T_1356, UInt<1>(0h0))
when _T_1359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1356, UInt<1>(0h1), "") : assert_94
node _T_1360 = eq(io.in.d.bits.source, source_1)
node _T_1361 = asUInt(reset)
node _T_1362 = eq(_T_1361, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = eq(_T_1360, UInt<1>(0h0))
when _T_1363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1360, UInt<1>(0h1), "") : assert_95
node _T_1364 = eq(io.in.d.bits.sink, sink)
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(_T_1364, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1364, UInt<1>(0h1), "") : assert_96
node _T_1368 = eq(io.in.d.bits.denied, denied)
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_97
node _T_1372 = and(io.in.d.ready, io.in.d.valid)
node _T_1373 = and(_T_1372, d_first)
when _T_1373 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1374 = and(io.in.a.valid, a_first_1)
node _T_1375 = and(_T_1374, UInt<1>(0h1))
when _T_1375 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1376 = and(io.in.a.ready, io.in.a.valid)
node _T_1377 = and(_T_1376, a_first_1)
node _T_1378 = and(_T_1377, UInt<1>(0h1))
when _T_1378 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1379 = dshr(inflight, io.in.a.bits.source)
node _T_1380 = bits(_T_1379, 0, 0)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(_T_1381, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1381, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1385 = and(io.in.d.valid, d_first_1)
node _T_1386 = and(_T_1385, UInt<1>(0h1))
node _T_1387 = eq(d_release_ack, UInt<1>(0h0))
node _T_1388 = and(_T_1386, _T_1387)
when _T_1388 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1389 = and(io.in.d.ready, io.in.d.valid)
node _T_1390 = and(_T_1389, d_first_1)
node _T_1391 = and(_T_1390, UInt<1>(0h1))
node _T_1392 = eq(d_release_ack, UInt<1>(0h0))
node _T_1393 = and(_T_1391, _T_1392)
when _T_1393 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1394 = and(io.in.d.valid, d_first_1)
node _T_1395 = and(_T_1394, UInt<1>(0h1))
node _T_1396 = eq(d_release_ack, UInt<1>(0h0))
node _T_1397 = and(_T_1395, _T_1396)
when _T_1397 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1398 = dshr(inflight, io.in.d.bits.source)
node _T_1399 = bits(_T_1398, 0, 0)
node _T_1400 = or(_T_1399, same_cycle_resp)
node _T_1401 = asUInt(reset)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
when _T_1402 :
node _T_1403 = eq(_T_1400, UInt<1>(0h0))
when _T_1403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1400, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1404 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1405 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1406 = or(_T_1404, _T_1405)
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(_T_1406, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1406, UInt<1>(0h1), "") : assert_100
node _T_1410 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1411 = asUInt(reset)
node _T_1412 = eq(_T_1411, UInt<1>(0h0))
when _T_1412 :
node _T_1413 = eq(_T_1410, UInt<1>(0h0))
when _T_1413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1410, UInt<1>(0h1), "") : assert_101
else :
node _T_1414 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1415 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1416 = or(_T_1414, _T_1415)
node _T_1417 = asUInt(reset)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
when _T_1418 :
node _T_1419 = eq(_T_1416, UInt<1>(0h0))
when _T_1419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1416, UInt<1>(0h1), "") : assert_102
node _T_1420 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1421 = asUInt(reset)
node _T_1422 = eq(_T_1421, UInt<1>(0h0))
when _T_1422 :
node _T_1423 = eq(_T_1420, UInt<1>(0h0))
when _T_1423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1420, UInt<1>(0h1), "") : assert_103
node _T_1424 = and(io.in.d.valid, d_first_1)
node _T_1425 = and(_T_1424, a_first_1)
node _T_1426 = and(_T_1425, io.in.a.valid)
node _T_1427 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1428 = and(_T_1426, _T_1427)
node _T_1429 = eq(d_release_ack, UInt<1>(0h0))
node _T_1430 = and(_T_1428, _T_1429)
when _T_1430 :
node _T_1431 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1432 = or(_T_1431, io.in.a.ready)
node _T_1433 = asUInt(reset)
node _T_1434 = eq(_T_1433, UInt<1>(0h0))
when _T_1434 :
node _T_1435 = eq(_T_1432, UInt<1>(0h0))
when _T_1435 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1432, UInt<1>(0h1), "") : assert_104
node _T_1436 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1437 = orr(a_set_wo_ready)
node _T_1438 = eq(_T_1437, UInt<1>(0h0))
node _T_1439 = or(_T_1436, _T_1438)
node _T_1440 = asUInt(reset)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
node _T_1442 = eq(_T_1439, UInt<1>(0h0))
when _T_1442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1439, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_23
node _T_1443 = orr(inflight)
node _T_1444 = eq(_T_1443, UInt<1>(0h0))
node _T_1445 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1446 = or(_T_1444, _T_1445)
node _T_1447 = lt(watchdog, plusarg_reader.out)
node _T_1448 = or(_T_1446, _T_1447)
node _T_1449 = asUInt(reset)
node _T_1450 = eq(_T_1449, UInt<1>(0h0))
when _T_1450 :
node _T_1451 = eq(_T_1448, UInt<1>(0h0))
when _T_1451 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1448, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1452 = and(io.in.a.ready, io.in.a.valid)
node _T_1453 = and(io.in.d.ready, io.in.d.valid)
node _T_1454 = or(_T_1452, _T_1453)
when _T_1454 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1455 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1456 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1457 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1458 = and(_T_1456, _T_1457)
node _T_1459 = and(_T_1455, _T_1458)
when _T_1459 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1460 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1461 = and(_T_1460, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1462 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1463 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1464 = and(_T_1462, _T_1463)
node _T_1465 = and(_T_1461, _T_1464)
when _T_1465 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1466 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1467 = bits(_T_1466, 0, 0)
node _T_1468 = eq(_T_1467, UInt<1>(0h0))
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1472 = and(io.in.d.valid, d_first_2)
node _T_1473 = and(_T_1472, UInt<1>(0h1))
node _T_1474 = and(_T_1473, d_release_ack_1)
when _T_1474 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1475 = and(io.in.d.ready, io.in.d.valid)
node _T_1476 = and(_T_1475, d_first_2)
node _T_1477 = and(_T_1476, UInt<1>(0h1))
node _T_1478 = and(_T_1477, d_release_ack_1)
when _T_1478 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1479 = and(io.in.d.valid, d_first_2)
node _T_1480 = and(_T_1479, UInt<1>(0h1))
node _T_1481 = and(_T_1480, d_release_ack_1)
when _T_1481 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1482 = dshr(inflight_1, io.in.d.bits.source)
node _T_1483 = bits(_T_1482, 0, 0)
node _T_1484 = or(_T_1483, same_cycle_resp_1)
node _T_1485 = asUInt(reset)
node _T_1486 = eq(_T_1485, UInt<1>(0h0))
when _T_1486 :
node _T_1487 = eq(_T_1484, UInt<1>(0h0))
when _T_1487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1484, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1488 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1489 = asUInt(reset)
node _T_1490 = eq(_T_1489, UInt<1>(0h0))
when _T_1490 :
node _T_1491 = eq(_T_1488, UInt<1>(0h0))
when _T_1491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1488, UInt<1>(0h1), "") : assert_109
else :
node _T_1492 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1493 = asUInt(reset)
node _T_1494 = eq(_T_1493, UInt<1>(0h0))
when _T_1494 :
node _T_1495 = eq(_T_1492, UInt<1>(0h0))
when _T_1495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1492, UInt<1>(0h1), "") : assert_110
node _T_1496 = and(io.in.d.valid, d_first_2)
node _T_1497 = and(_T_1496, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1498 = and(_T_1497, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1499 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1500 = and(_T_1498, _T_1499)
node _T_1501 = and(_T_1500, d_release_ack_1)
node _T_1502 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1503 = and(_T_1501, _T_1502)
when _T_1503 :
node _T_1504 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1505 = or(_T_1504, _WIRE_27.ready)
node _T_1506 = asUInt(reset)
node _T_1507 = eq(_T_1506, UInt<1>(0h0))
when _T_1507 :
node _T_1508 = eq(_T_1505, UInt<1>(0h0))
when _T_1508 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1505, UInt<1>(0h1), "") : assert_111
node _T_1509 = orr(c_set_wo_ready)
when _T_1509 :
node _T_1510 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1511 = asUInt(reset)
node _T_1512 = eq(_T_1511, UInt<1>(0h0))
when _T_1512 :
node _T_1513 = eq(_T_1510, UInt<1>(0h0))
when _T_1513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1510, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_24
node _T_1514 = orr(inflight_1)
node _T_1515 = eq(_T_1514, UInt<1>(0h0))
node _T_1516 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1517 = or(_T_1515, _T_1516)
node _T_1518 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1519 = or(_T_1517, _T_1518)
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1523 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1524 = and(io.in.d.ready, io.in.d.valid)
node _T_1525 = or(_T_1523, _T_1524)
when _T_1525 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_7( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_35 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_45
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_35( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_45 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e5_s11_6 :
output io : { flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, mulAddA : UInt<11>, mulAddB : UInt<11>, mulAddC : UInt<22>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 15, 10)
node _rawA_isZero_T = bits(rawA_exp, 5, 3)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 5, 4)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawA_out_isNaN_T = bits(rawA_exp, 3, 3)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 3, 3)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 16, 16)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 9, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 15, 10)
node _rawB_isZero_T = bits(rawB_exp, 5, 3)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 5, 4)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawB_out_isNaN_T = bits(rawB_exp, 3, 3)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 3, 3)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 16, 16)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 9, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 15, 10)
node _rawC_isZero_T = bits(rawC_exp, 5, 3)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 5, 4)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawC_out_isNaN_T = bits(rawC_exp, 3, 3)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 3, 3)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 16, 16)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 9, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<6>(0h2e)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 6, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<4>(0hb))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<6>(0h23))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 5, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<6>(0h23))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<27>(0h7ffffff), UInt<27>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 0)
wire reduced4CExtra_reducedVec : UInt<1>[3]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node reduced4CExtra_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_reducedVec[0])
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 9, 8)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 0, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_3, 1, 1)
node _reduced4CExtra_T_6 = cat(_reduced4CExtra_T_4, _reduced4CExtra_T_5)
node _reduced4CExtra_T_7 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_6)
node reduced4CExtra = orr(_reduced4CExtra_T_7)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 22, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<5>(0hb)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 3, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 35, 23)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e5_s11_6( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [16:0] io_a, // @[MulAddRecFN.scala:74:16]
input [16:0] io_b, // @[MulAddRecFN.scala:74:16]
input [16:0] io_c, // @[MulAddRecFN.scala:74:16]
output [10:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [10:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [21:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [6:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [3:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [21:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [3:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [12:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [6:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [3:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [12:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [10:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [10:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [21:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [5:0] rawA_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawA_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [5:0] rawB_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawB_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [5:0] rawC_exp = io_c_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawC_out_sig_T_2 = io_c_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [7:0] _sExpAlignedProd_T = {rawA_sExp[6], rawA_sExp} + {rawB_sExp[6], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[7], _sExpAlignedProd_T} - 9'h12; // @[MulAddRecFN.scala:100:{19,32}]
wire [7:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[7:0]; // @[MulAddRecFN.scala:100:32]
wire [7:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [8:0] _GEN = {sExpAlignedProd[7], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [8:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[6]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[7:0]; // @[MulAddRecFN.scala:106:42]
wire [7:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [6:0] posNatCAlignDist = sNatCAlignDist[6:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 8'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 7'hC; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 7'h23; // @[MulAddRecFN.scala:107:42, :114:34]
wire [5:0] _CAlignDist_T_1 = posNatCAlignDist[5:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [5:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 6'h23; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [5:0] CAlignDist = isMinCAlign ? 6'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [11:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [26:0] _mainAlignedSigC_T_2 = {27{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [38:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [38:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [38:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [3:0] _reduced4CExtra_T_2 = CAlignDist[5:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [16:0] reduced4CExtra_shift = $signed(17'sh10000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [1:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[9:8]; // @[primitives.scala:76:56, :78:22]
wire _reduced4CExtra_T_4 = _reduced4CExtra_T_3[0]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_5 = _reduced4CExtra_T_3[1]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_6 = {_reduced4CExtra_T_4, _reduced4CExtra_T_5}; // @[primitives.scala:77:20]
wire [2:0] _reduced4CExtra_T_7 = {1'h0, _reduced4CExtra_T_1[1:0] & _reduced4CExtra_T_6}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_7; // @[MulAddRecFN.scala:122:68, :130:11]
wire [35:0] _alignedSigC_T = mainAlignedSigC[38:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [35:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [36:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[10:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[10:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[22:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [8:0] _io_toPostMul_sExpSum_T = _GEN - 9'hB; // @[MulAddRecFN.scala:106:42, :158:53]
wire [7:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[7:0]; // @[MulAddRecFN.scala:158:53]
wire [7:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [7:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[6], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[6:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[3:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[35:23]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_29 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_29
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_29
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_44
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_29( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_29 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_29 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_44 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_82 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_82( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57]
wire excluded_client = 1'h0; // @[MSHR.scala:279:28]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34]
wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53]
wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module PE_482 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_226
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_482( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_226 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_323 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_67
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_323( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_67 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_44 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_44( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_41
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s2k3z4c( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_41 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s2k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s2k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s2k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_b_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_enq_bits_mask (nodeOut_b_bits_mask), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_b_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_b_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s2k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s2k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_74 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_74( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_cbus_in_i2_o1_a29d64s7k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.user.amba_prot.fetch
invalidate anonIn.a.bits.user.amba_prot.secure
invalidate anonIn.a.bits.user.amba_prot.privileged
invalidate anonIn.a.bits.user.amba_prot.writealloc
invalidate anonIn.a.bits.user.amba_prot.readalloc
invalidate anonIn.a.bits.user.amba_prot.modifiable
invalidate anonIn.a.bits.user.amba_prot.bufferable
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor_16
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_17
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.user.amba_prot.fetch
invalidate anonOut.a.bits.user.amba_prot.secure
invalidate anonOut.a.bits.user.amba_prot.privileged
invalidate anonOut.a.bits.user.amba_prot.writealloc
invalidate anonOut.a.bits.user.amba_prot.readalloc
invalidate anonOut.a.bits.user.amba_prot.modifiable
invalidate anonOut.a.bits.user.amba_prot.bufferable
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2]
invalidate in[0].a.bits.user.amba_prot.fetch
invalidate in[0].a.bits.user.amba_prot.secure
invalidate in[0].a.bits.user.amba_prot.privileged
invalidate in[0].a.bits.user.amba_prot.writealloc
invalidate in[0].a.bits.user.amba_prot.readalloc
invalidate in[0].a.bits.user.amba_prot.modifiable
invalidate in[0].a.bits.user.amba_prot.bufferable
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<6>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.user.amba_prot.fetch
invalidate _WIRE_9.bits.user.amba_prot.secure
invalidate _WIRE_9.bits.user.amba_prot.privileged
invalidate _WIRE_9.bits.user.amba_prot.writealloc
invalidate _WIRE_9.bits.user.amba_prot.readalloc
invalidate _WIRE_9.bits.user.amba_prot.modifiable
invalidate _WIRE_9.bits.user.amba_prot.bufferable
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.user.amba_prot.fetch
invalidate _WIRE_11.bits.user.amba_prot.secure
invalidate _WIRE_11.bits.user.amba_prot.privileged
invalidate _WIRE_11.bits.user.amba_prot.writealloc
invalidate _WIRE_11.bits.user.amba_prot.readalloc
invalidate _WIRE_11.bits.user.amba_prot.modifiable
invalidate _WIRE_11.bits.user.amba_prot.bufferable
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 5, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
invalidate in[1].a.bits.user.amba_prot.fetch
invalidate in[1].a.bits.user.amba_prot.secure
invalidate in[1].a.bits.user.amba_prot.privileged
invalidate in[1].a.bits.user.amba_prot.writealloc
invalidate in[1].a.bits.user.amba_prot.readalloc
invalidate in[1].a.bits.user.amba_prot.modifiable
invalidate in[1].a.bits.user.amba_prot.bufferable
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<7>(0h40))
connect in[1].a.bits.source, _in_1_a_bits_source_T
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.ready, UInt<1>(0h1)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<29>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_32.bits.address, UInt<29>(0h0)
connect _WIRE_32.bits.source, UInt<7>(0h0)
connect _WIRE_32.bits.size, UInt<4>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.user.amba_prot.fetch
invalidate _WIRE_33.bits.user.amba_prot.secure
invalidate _WIRE_33.bits.user.amba_prot.privileged
invalidate _WIRE_33.bits.user.amba_prot.writealloc
invalidate _WIRE_33.bits.user.amba_prot.readalloc
invalidate _WIRE_33.bits.user.amba_prot.modifiable
invalidate _WIRE_33.bits.user.amba_prot.bufferable
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<29>(0h0)
connect _WIRE_34.bits.source, UInt<1>(0h0)
connect _WIRE_34.bits.size, UInt<4>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_36.bits.address, UInt<29>(0h0)
connect _WIRE_36.bits.source, UInt<7>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<29>(0h0)
connect _WIRE_38.bits.source, UInt<1>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
connect anonIn_1.d.bits.source, UInt<1>(0h0)
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
invalidate out[0].a.bits.user.amba_prot.fetch
invalidate out[0].a.bits.user.amba_prot.secure
invalidate out[0].a.bits.user.amba_prot.privileged
invalidate out[0].a.bits.user.amba_prot.writealloc
invalidate out[0].a.bits.user.amba_prot.readalloc
invalidate out[0].a.bits.user.amba_prot.modifiable
invalidate out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch
connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure
connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged
connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc
connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc
connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable
connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<29>(0h0)
connect _WIRE_48.bits.source, UInt<7>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<29>(0h0)
connect _WIRE_50.bits.source, UInt<7>(0h0)
connect _WIRE_50.bits.size, UInt<4>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<29>(0h0)
connect _WIRE_52.bits.source, UInt<7>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<29>(0h0)
connect _WIRE_54.bits.source, UInt<7>(0h0)
connect _WIRE_54.bits.size, UInt<4>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_56.bits.address, UInt<29>(0h0)
connect _WIRE_56.bits.source, UInt<7>(0h0)
connect _WIRE_56.bits.size, UInt<4>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.user.amba_prot.fetch
invalidate _WIRE_57.bits.user.amba_prot.secure
invalidate _WIRE_57.bits.user.amba_prot.privileged
invalidate _WIRE_57.bits.user.amba_prot.writealloc
invalidate _WIRE_57.bits.user.amba_prot.readalloc
invalidate _WIRE_57.bits.user.amba_prot.modifiable
invalidate _WIRE_57.bits.user.amba_prot.bufferable
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_58.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_58.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_58.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_58.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_58.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_58.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_58.bits.address, UInt<29>(0h0)
connect _WIRE_58.bits.source, UInt<7>(0h0)
connect _WIRE_58.bits.size, UInt<4>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.user.amba_prot.fetch
invalidate _WIRE_59.bits.user.amba_prot.secure
invalidate _WIRE_59.bits.user.amba_prot.privileged
invalidate _WIRE_59.bits.user.amba_prot.writealloc
invalidate _WIRE_59.bits.user.amba_prot.readalloc
invalidate _WIRE_59.bits.user.amba_prot.modifiable
invalidate _WIRE_59.bits.user.amba_prot.bufferable
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_60.bits.address, UInt<29>(0h0)
connect _WIRE_60.bits.source, UInt<7>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_62.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_62.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_62.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_62.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_62.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_62.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_62.bits.address, UInt<29>(0h0)
connect _WIRE_62.bits.source, UInt<7>(0h0)
connect _WIRE_62.bits.size, UInt<4>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _addressC_WIRE.bits.address, UInt<29>(0h0)
connect _addressC_WIRE.bits.source, UInt<7>(0h0)
connect _addressC_WIRE.bits.size, UInt<4>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.address, UInt<29>(0h0)
connect _addressC_WIRE_2.bits.source, UInt<7>(0h0)
connect _addressC_WIRE_2.bits.size, UInt<4>(0h0)
connect _addressC_WIRE_2.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_2.valid, UInt<1>(0h0)
connect _addressC_WIRE_2.ready, UInt<1>(0h0)
wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits
connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid
connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<6>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 5, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 6)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<6>(0h3f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<7>(0h40))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<6>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 5, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 6)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<6>(0h3f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<7>(0h40))
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<29>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0))
wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.address, UInt<29>(0h0)
connect _beatsCI_WIRE_2.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits
connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid
connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits
connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid
connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1)
wire _portsBIO_WIRE_2 : UInt<1>
connect _portsBIO_WIRE_2, _portsBIO_T_2
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<29>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready
wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.address, UInt<29>(0h0)
connect _portsCOI_WIRE_2.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits
connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid
connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready
wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits
connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid
connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}
wire _out_0_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_7 : UInt<1>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE_6.fetch, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_8 : UInt<1>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE_6.secure, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_9 : UInt<1>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE_6.privileged, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_10 : UInt<1>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE_6.writealloc, _out_0_a_bits_WIRE_10
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_11 : UInt<1>
connect _out_0_a_bits_WIRE_11, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE_6.readalloc, _out_0_a_bits_WIRE_11
node _out_0_a_bits_T_24 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_0_a_bits_T_25 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_25)
wire _out_0_a_bits_WIRE_12 : UInt<1>
connect _out_0_a_bits_WIRE_12, _out_0_a_bits_T_26
connect _out_0_a_bits_WIRE_6.modifiable, _out_0_a_bits_WIRE_12
node _out_0_a_bits_T_27 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_0_a_bits_T_28 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_28)
wire _out_0_a_bits_WIRE_13 : UInt<1>
connect _out_0_a_bits_WIRE_13, _out_0_a_bits_T_29
connect _out_0_a_bits_WIRE_6.bufferable, _out_0_a_bits_WIRE_13
connect _out_0_a_bits_WIRE_5.amba_prot, _out_0_a_bits_WIRE_6
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31)
wire _out_0_a_bits_WIRE_14 : UInt<29>
connect _out_0_a_bits_WIRE_14, _out_0_a_bits_T_32
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_14
node _out_0_a_bits_T_33 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_34 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_34)
wire _out_0_a_bits_WIRE_15 : UInt<7>
connect _out_0_a_bits_WIRE_15, _out_0_a_bits_T_35
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_15
node _out_0_a_bits_T_36 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_37 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_37)
wire _out_0_a_bits_WIRE_16 : UInt<4>
connect _out_0_a_bits_WIRE_16, _out_0_a_bits_T_38
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_16
node _out_0_a_bits_T_39 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_40 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_39, _out_0_a_bits_T_40)
wire _out_0_a_bits_WIRE_17 : UInt<3>
connect _out_0_a_bits_WIRE_17, _out_0_a_bits_T_41
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_17
node _out_0_a_bits_T_42 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_43 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_43)
wire _out_0_a_bits_WIRE_18 : UInt<3>
connect _out_0_a_bits_WIRE_18, _out_0_a_bits_T_44
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_18
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.user.amba_prot.fetch, _out_0_a_bits_WIRE.user.amba_prot.fetch
connect out[0].a.bits.user.amba_prot.secure, _out_0_a_bits_WIRE.user.amba_prot.secure
connect out[0].a.bits.user.amba_prot.privileged, _out_0_a_bits_WIRE.user.amba_prot.privileged
connect out[0].a.bits.user.amba_prot.writealloc, _out_0_a_bits_WIRE.user.amba_prot.writealloc
connect out[0].a.bits.user.amba_prot.readalloc, _out_0_a_bits_WIRE.user.amba_prot.readalloc
connect out[0].a.bits.user.amba_prot.modifiable, _out_0_a_bits_WIRE.user.amba_prot.modifiable
connect out[0].a.bits.user.amba_prot.bufferable, _out_0_a_bits_WIRE.user.amba_prot.bufferable
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_72.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_72.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_72.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_72.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_72.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_72.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_72.bits.address, UInt<29>(0h0)
connect _WIRE_72.bits.source, UInt<7>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<3>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.user.amba_prot.fetch
invalidate _WIRE_73.bits.user.amba_prot.secure
invalidate _WIRE_73.bits.user.amba_prot.privileged
invalidate _WIRE_73.bits.user.amba_prot.writealloc
invalidate _WIRE_73.bits.user.amba_prot.readalloc
invalidate _WIRE_73.bits.user.amba_prot.modifiable
invalidate _WIRE_73.bits.user.amba_prot.bufferable
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_74.bits.sink, UInt<1>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<29>(0h0)
connect _WIRE_76.bits.source, UInt<7>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
invalidate _WIRE_77.bits.corrupt
invalidate _WIRE_77.bits.data
invalidate _WIRE_77.bits.mask
invalidate _WIRE_77.bits.address
invalidate _WIRE_77.bits.source
invalidate _WIRE_77.bits.size
invalidate _WIRE_77.bits.param
invalidate _WIRE_77.bits.opcode
connect in[0].d, portsDIO_filtered[0]
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<29>(0h0)
connect _WIRE_78.bits.source, UInt<7>(0h0)
connect _WIRE_78.bits.size, UInt<4>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
invalidate _WIRE_79.bits.corrupt
invalidate _WIRE_79.bits.data
invalidate _WIRE_79.bits.mask
invalidate _WIRE_79.bits.address
invalidate _WIRE_79.bits.source
invalidate _WIRE_79.bits.size
invalidate _WIRE_79.bits.param
invalidate _WIRE_79.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0)
extmodule plusarg_reader_36 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_37 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLXbar_cbus_in_i2_o1_a29d64s7k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire requestDOI_0_1 = auto_anon_out_d_bits_source == 7'h40; // @[Parameters.scala:46:9]
wire portsDIO_filtered_0_valid = auto_anon_out_d_valid & ~(auto_anon_out_d_bits_source[6]); // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_valid = auto_anon_out_d_valid & requestDOI_0_1; // @[Xbar.scala:355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid = {auto_anon_in_1_a_valid, auto_anon_in_0_a_valid}; // @[Arbiter.scala:68:51]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_in_1_a_valid} | _readys_filter_T_1)); // @[package.scala:262:43]
wire winner_0 = readys_readys[0] & auto_anon_in_0_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_1 = readys_readys[1] & auto_anon_in_1_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire _out_0_a_valid_T = auto_anon_in_0_a_valid | auto_anon_in_1_a_valid; // @[Arbiter.scala:79:31] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_57 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_77
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_57( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_77 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router_7 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_7
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn_1.flit.bits.egress_id
invalidate ingressNodesIn_1.flit.bits.payload
invalidate ingressNodesIn_1.flit.bits.tail
invalidate ingressNodesIn_1.flit.bits.head
invalidate ingressNodesIn_1.flit.valid
invalidate ingressNodesIn_1.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_1.flit.bits.ingress_id
invalidate egressNodesOut_1.flit.bits.payload
invalidate egressNodesOut_1.flit.bits.tail
invalidate egressNodesOut_1.flit.bits.head
invalidate egressNodesOut_1.flit.valid
invalidate egressNodesOut_1.flit.ready
wire egressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_2.flit.bits.ingress_id
invalidate egressNodesOut_2.flit.bits.payload
invalidate egressNodesOut_2.flit.bits.tail
invalidate egressNodesOut_2.flit.bits.head
invalidate egressNodesOut_2.flit.valid
invalidate egressNodesOut_2.flit.ready
wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in_0
connect ingressNodesIn_1, auto.ingress_nodes_in_1
connect auto.egress_nodes_out_0, egressNodesOut
connect auto.egress_nodes_out_1, egressNodesOut_1
connect auto.egress_nodes_out_2, egressNodesOut_2
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_6 of InputUnit_7
connect input_unit_0_from_6.clock, clock
connect input_unit_0_from_6.reset, reset
inst ingress_unit_1_from_21 of IngressUnit_21
connect ingress_unit_1_from_21.clock, clock
connect ingress_unit_1_from_21.reset, reset
inst ingress_unit_2_from_22 of IngressUnit_22
connect ingress_unit_2_from_22.clock, clock
connect ingress_unit_2_from_22.reset, reset
inst output_unit_0_to_8 of OutputUnit_7
connect output_unit_0_to_8.clock, clock
connect output_unit_0_to_8.reset, reset
inst egress_unit_1_to_19 of EgressUnit_19
connect egress_unit_1_to_19.clock, clock
connect egress_unit_1_to_19.reset, reset
inst egress_unit_2_to_20 of EgressUnit_20
connect egress_unit_2_to_20.clock, clock
connect egress_unit_2_to_20.reset, reset
inst egress_unit_3_to_21 of EgressUnit_21
connect egress_unit_3_to_21.clock, clock
connect egress_unit_3_to_21.reset, reset
inst switch of Switch_7
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_7
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_7
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_7
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2)
node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_6
connect input_unit_0_from_6.io.in, destNodesIn
connect ingress_unit_1_from_21.io.in, ingressNodesIn.flit
connect ingress_unit_2_from_22.io.in, ingressNodesIn_1.flit
connect output_unit_0_to_8.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_8.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_8.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_19.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_19.io.out.valid
connect egress_unit_1_to_19.io.out.ready, egressNodesOut.flit.ready
connect egressNodesOut_1.flit.bits, egress_unit_2_to_20.io.out.bits
connect egressNodesOut_1.flit.valid, egress_unit_2_to_20.io.out.valid
connect egress_unit_2_to_20.io.out.ready, egressNodesOut_1.flit.ready
connect egressNodesOut_2.flit.bits, egress_unit_3_to_21.io.out.bits
connect egressNodesOut_2.flit.valid, egress_unit_3_to_21.io.out.valid
connect egress_unit_3_to_21.io.out.ready, egressNodesOut_2.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_6.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_21.io.router_req
connect route_computer.io.req.`2`, ingress_unit_2_from_22.io.router_req
connect input_unit_0_from_6.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_21.io.router_resp, route_computer.io.resp.`1`
connect ingress_unit_2_from_22.io.router_resp, route_computer.io.resp.`2`
connect vc_allocator.io.req.`0`, input_unit_0_from_6.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_21.io.vcalloc_req
connect vc_allocator.io.req.`2`, ingress_unit_2_from_22.io.vcalloc_req
connect input_unit_0_from_6.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_21.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect ingress_unit_2_from_22.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect output_unit_0_to_8.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_19.io.allocs, vc_allocator.io.out_allocs.`1`
connect egress_unit_2_to_20.io.allocs, vc_allocator.io.out_allocs.`2`
connect egress_unit_3_to_21.io.allocs, vc_allocator.io.out_allocs.`3`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_8.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_8.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_8.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_8.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_8.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_8.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_8.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_8.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_8.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_8.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_8.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_8.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_8.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_8.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_8.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_8.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_8.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_8.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_8.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_8.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_8.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_8.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_8.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_8.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_8.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_8.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_8.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_8.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_8.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_8.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_8.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_8.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_8.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_8.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_8.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_8.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_8.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_8.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_8.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_8.io.channel_status[7].occupied
connect vc_allocator.io.channel_status.`0`[8].flow.egress_node_id, output_unit_0_to_8.io.channel_status[8].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[8].flow.egress_node, output_unit_0_to_8.io.channel_status[8].flow.egress_node
connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[8].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node, output_unit_0_to_8.io.channel_status[8].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[8].flow.vnet_id, output_unit_0_to_8.io.channel_status[8].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[8].occupied, output_unit_0_to_8.io.channel_status[8].occupied
connect vc_allocator.io.channel_status.`0`[9].flow.egress_node_id, output_unit_0_to_8.io.channel_status[9].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[9].flow.egress_node, output_unit_0_to_8.io.channel_status[9].flow.egress_node
connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node_id, output_unit_0_to_8.io.channel_status[9].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node, output_unit_0_to_8.io.channel_status[9].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[9].flow.vnet_id, output_unit_0_to_8.io.channel_status[9].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[9].occupied, output_unit_0_to_8.io.channel_status[9].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_19.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_19.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_19.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_19.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_19.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_19.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_20.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_20.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_20.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_20.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_20.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_20.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_21.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_21.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_21.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_21.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_21.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_21.io.channel_status[0].occupied
connect input_unit_0_from_6.io.out_credit_available.`0`[0], output_unit_0_to_8.io.credit_available[0]
connect input_unit_0_from_6.io.out_credit_available.`0`[1], output_unit_0_to_8.io.credit_available[1]
connect input_unit_0_from_6.io.out_credit_available.`0`[2], output_unit_0_to_8.io.credit_available[2]
connect input_unit_0_from_6.io.out_credit_available.`0`[3], output_unit_0_to_8.io.credit_available[3]
connect input_unit_0_from_6.io.out_credit_available.`0`[4], output_unit_0_to_8.io.credit_available[4]
connect input_unit_0_from_6.io.out_credit_available.`0`[5], output_unit_0_to_8.io.credit_available[5]
connect input_unit_0_from_6.io.out_credit_available.`0`[6], output_unit_0_to_8.io.credit_available[6]
connect input_unit_0_from_6.io.out_credit_available.`0`[7], output_unit_0_to_8.io.credit_available[7]
connect input_unit_0_from_6.io.out_credit_available.`0`[8], output_unit_0_to_8.io.credit_available[8]
connect input_unit_0_from_6.io.out_credit_available.`0`[9], output_unit_0_to_8.io.credit_available[9]
connect input_unit_0_from_6.io.out_credit_available.`1`[0], egress_unit_1_to_19.io.credit_available[0]
connect input_unit_0_from_6.io.out_credit_available.`2`[0], egress_unit_2_to_20.io.credit_available[0]
connect input_unit_0_from_6.io.out_credit_available.`3`[0], egress_unit_3_to_21.io.credit_available[0]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[0], output_unit_0_to_8.io.credit_available[0]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[1], output_unit_0_to_8.io.credit_available[1]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[2], output_unit_0_to_8.io.credit_available[2]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[3], output_unit_0_to_8.io.credit_available[3]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[4], output_unit_0_to_8.io.credit_available[4]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[5], output_unit_0_to_8.io.credit_available[5]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[6], output_unit_0_to_8.io.credit_available[6]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[7], output_unit_0_to_8.io.credit_available[7]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[8], output_unit_0_to_8.io.credit_available[8]
connect ingress_unit_1_from_21.io.out_credit_available.`0`[9], output_unit_0_to_8.io.credit_available[9]
connect ingress_unit_1_from_21.io.out_credit_available.`1`[0], egress_unit_1_to_19.io.credit_available[0]
connect ingress_unit_1_from_21.io.out_credit_available.`2`[0], egress_unit_2_to_20.io.credit_available[0]
connect ingress_unit_1_from_21.io.out_credit_available.`3`[0], egress_unit_3_to_21.io.credit_available[0]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[0], output_unit_0_to_8.io.credit_available[0]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[1], output_unit_0_to_8.io.credit_available[1]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[2], output_unit_0_to_8.io.credit_available[2]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[3], output_unit_0_to_8.io.credit_available[3]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[4], output_unit_0_to_8.io.credit_available[4]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[5], output_unit_0_to_8.io.credit_available[5]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[6], output_unit_0_to_8.io.credit_available[6]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[7], output_unit_0_to_8.io.credit_available[7]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[8], output_unit_0_to_8.io.credit_available[8]
connect ingress_unit_2_from_22.io.out_credit_available.`0`[9], output_unit_0_to_8.io.credit_available[9]
connect ingress_unit_2_from_22.io.out_credit_available.`1`[0], egress_unit_1_to_19.io.credit_available[0]
connect ingress_unit_2_from_22.io.out_credit_available.`2`[0], egress_unit_2_to_20.io.credit_available[0]
connect ingress_unit_2_from_22.io.out_credit_available.`3`[0], egress_unit_3_to_21.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_6.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_21.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_22.io.salloc_req[0]
connect output_unit_0_to_8.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_8.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_8.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_8.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_8.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_8.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_8.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_8.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_8.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_8.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_8.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_8.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect output_unit_0_to_8.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail
connect output_unit_0_to_8.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc
connect output_unit_0_to_8.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail
connect output_unit_0_to_8.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc
connect output_unit_0_to_8.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`0`[8].tail
connect output_unit_0_to_8.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`0`[8].alloc
connect output_unit_0_to_8.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`0`[9].tail
connect output_unit_0_to_8.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`0`[9].alloc
connect egress_unit_1_to_19.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_19.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect egress_unit_2_to_20.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect egress_unit_2_to_20.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect egress_unit_3_to_21.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail
connect egress_unit_3_to_21.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_6.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_21.io.out[0]
connect switch.io.in.`2`[0], ingress_unit_2_from_22.io.out[0]
connect output_unit_0_to_8.io.in, switch.io.out.`0`
connect egress_unit_1_to_19.io.in, switch.io.out.`1`
connect egress_unit_2_to_20.io.in, switch.io.out.`2`
connect egress_unit_3_to_21.io.in, switch.io.out.`3`
reg REG : { `3` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0]
connect switch.io.sel.`3`[0].`0`[0], REG.`3`[0].`0`[0]
connect switch.io.sel.`3`[0].`1`[0], REG.`3`[0].`1`[0]
connect switch.io.sel.`3`[0].`2`[0], REG.`3`[0].`2`[0]
connect input_unit_0_from_6.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_21.io.block, UInt<1>(0h0)
connect ingress_unit_2_from_22.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_6.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_21.io.debug.va_stall
connect debugNodeOut.va_stall[2], ingress_unit_2_from_22.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_6.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_21.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], ingress_unit_2_from_22.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_17
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 6 7 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i21 7 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d i22 7 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20
node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_29)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_29)
connect fired_3, _fired_T_3
node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_32 = tail(_T_31, 1)
node _T_33 = eq(debug_sample, _T_32)
node _T_34 = and(_T_30, _T_33)
node _T_35 = and(_T_34, fired_3)
when _T_35 :
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "nocsample %d 7 e19 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_29
node _T_38 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid)
regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_8 = add(util_ctr_4, _T_38)
node _util_ctr_T_9 = tail(_util_ctr_T_8, 1)
connect util_ctr_4, _util_ctr_T_9
node _fired_T_4 = or(fired_4, _T_38)
connect fired_4, _fired_T_4
node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_41 = tail(_T_40, 1)
node _T_42 = eq(debug_sample, _T_41)
node _T_43 = and(_T_39, _T_42)
node _T_44 = and(_T_43, fired_4)
when _T_44 :
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "nocsample %d 7 e20 %d\n", debug_tsc, util_ctr_4) : printf_4
connect fired_4, _T_38
node _T_47 = and(egressNodesOut_2.flit.ready, egressNodesOut_2.flit.valid)
regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_10 = add(util_ctr_5, _T_47)
node _util_ctr_T_11 = tail(_util_ctr_T_10, 1)
connect util_ctr_5, _util_ctr_T_11
node _fired_T_5 = or(fired_5, _T_47)
connect fired_5, _fired_T_5
node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_50 = tail(_T_49, 1)
node _T_51 = eq(debug_sample, _T_50)
node _T_52 = and(_T_48, _T_51)
node _T_53 = and(_T_52, fired_5)
when _T_53 :
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "nocsample %d 7 e21 %d\n", debug_tsc, util_ctr_5) : printf_5
connect fired_5, _T_47 | module Router_7( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [3:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_8; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_9; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_8; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_9; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_8; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_9; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_3_to_21_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_21_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_21_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_2_to_20_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_20_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_20_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_19_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_19_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_19_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_8_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_credit_available_8; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_credit_available_9; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_channel_status_8_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_8_io_channel_status_9_occupied; // @[Router.scala:122:13]
wire [3:0] _ingress_unit_2_from_22_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_22_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_2_from_22_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_22_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_22_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_21_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_21_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_21_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_21_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _input_unit_0_from_6_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_6_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_6_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_6_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_21_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_22_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_3_0_2_0; // @[Router.scala:178:14]
reg REG_3_0_1_0; // @[Router.scala:178:14]
reg REG_3_0_0_0; // @[Router.scala:178:14]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = and(_T_11, _T_24)
node _T_97 = and(_T_96, _T_37)
node _T_98 = and(_T_97, _T_50)
node _T_99 = and(_T_98, _T_63)
node _T_100 = and(_T_99, _T_71)
node _T_101 = and(_T_100, _T_79)
node _T_102 = and(_T_101, _T_87)
node _T_103 = and(_T_102, _T_95)
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_103, UInt<1>(0h1), "") : assert_1
node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_107 :
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_118 = shr(io.in.a.bits.source, 2)
node _T_119 = eq(_T_118, UInt<1>(0h1))
node _T_120 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_121 = and(_T_119, _T_120)
node _T_122 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_123 = and(_T_121, _T_122)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_124 = shr(io.in.a.bits.source, 2)
node _T_125 = eq(_T_124, UInt<2>(0h2))
node _T_126 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_127 = and(_T_125, _T_126)
node _T_128 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_129 = and(_T_127, _T_128)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_130 = shr(io.in.a.bits.source, 2)
node _T_131 = eq(_T_130, UInt<2>(0h3))
node _T_132 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_133 = and(_T_131, _T_132)
node _T_134 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_140 = or(_T_111, _T_117)
node _T_141 = or(_T_140, _T_123)
node _T_142 = or(_T_141, _T_129)
node _T_143 = or(_T_142, _T_135)
node _T_144 = or(_T_143, _T_136)
node _T_145 = or(_T_144, _T_137)
node _T_146 = or(_T_145, _T_138)
node _T_147 = or(_T_146, _T_139)
node _T_148 = and(_T_110, _T_147)
node _T_149 = or(UInt<1>(0h0), _T_148)
node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_151 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = and(_T_150, _T_155)
node _T_157 = or(UInt<1>(0h0), _T_156)
node _T_158 = and(_T_149, _T_157)
node _T_159 = asUInt(reset)
node _T_160 = eq(_T_159, UInt<1>(0h0))
when _T_160 :
node _T_161 = eq(_T_158, UInt<1>(0h0))
when _T_161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_158, UInt<1>(0h1), "") : assert_2
node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_163 = shr(io.in.a.bits.source, 2)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_168 = and(_T_166, _T_167)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_169 = shr(io.in.a.bits.source, 2)
node _T_170 = eq(_T_169, UInt<1>(0h1))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_175 = shr(io.in.a.bits.source, 2)
node _T_176 = eq(_T_175, UInt<2>(0h2))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<2>(0h3))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_162
connect _WIRE[1], _T_168
connect _WIRE[2], _T_174
connect _WIRE[3], _T_180
connect _WIRE[4], _T_186
connect _WIRE[5], _T_187
connect _WIRE[6], _T_188
connect _WIRE[7], _T_189
connect _WIRE[8], _T_190
node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0))
node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_201 = or(_T_192, _T_193)
node _T_202 = or(_T_201, _T_194)
node _T_203 = or(_T_202, _T_195)
node _T_204 = or(_T_203, _T_196)
node _T_205 = or(_T_204, _T_197)
node _T_206 = or(_T_205, _T_198)
node _T_207 = or(_T_206, _T_199)
node _T_208 = or(_T_207, _T_200)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_208
node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_211 = and(_T_209, _T_210)
node _T_212 = or(UInt<1>(0h0), _T_211)
node _T_213 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = and(_T_212, _T_217)
node _T_219 = or(UInt<1>(0h0), _T_218)
node _T_220 = and(_WIRE_1, _T_219)
node _T_221 = asUInt(reset)
node _T_222 = eq(_T_221, UInt<1>(0h0))
when _T_222 :
node _T_223 = eq(_T_220, UInt<1>(0h0))
when _T_223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_220, UInt<1>(0h1), "") : assert_3
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(source_ok, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_228 = asUInt(reset)
node _T_229 = eq(_T_228, UInt<1>(0h0))
when _T_229 :
node _T_230 = eq(_T_227, UInt<1>(0h0))
when _T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_227, UInt<1>(0h1), "") : assert_5
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(is_aligned, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_234, UInt<1>(0h1), "") : assert_7
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_239, UInt<1>(0h1), "") : assert_8
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_243, UInt<1>(0h1), "") : assert_9
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_247 :
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_252 = shr(io.in.a.bits.source, 2)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_255 = and(_T_253, _T_254)
node _T_256 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_257 = and(_T_255, _T_256)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_258 = shr(io.in.a.bits.source, 2)
node _T_259 = eq(_T_258, UInt<1>(0h1))
node _T_260 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_261 = and(_T_259, _T_260)
node _T_262 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_263 = and(_T_261, _T_262)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_264 = shr(io.in.a.bits.source, 2)
node _T_265 = eq(_T_264, UInt<2>(0h2))
node _T_266 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_267 = and(_T_265, _T_266)
node _T_268 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_269 = and(_T_267, _T_268)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_270 = shr(io.in.a.bits.source, 2)
node _T_271 = eq(_T_270, UInt<2>(0h3))
node _T_272 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_273 = and(_T_271, _T_272)
node _T_274 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_275 = and(_T_273, _T_274)
node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_280 = or(_T_251, _T_257)
node _T_281 = or(_T_280, _T_263)
node _T_282 = or(_T_281, _T_269)
node _T_283 = or(_T_282, _T_275)
node _T_284 = or(_T_283, _T_276)
node _T_285 = or(_T_284, _T_277)
node _T_286 = or(_T_285, _T_278)
node _T_287 = or(_T_286, _T_279)
node _T_288 = and(_T_250, _T_287)
node _T_289 = or(UInt<1>(0h0), _T_288)
node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_291 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_292 = cvt(_T_291)
node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000)))
node _T_294 = asSInt(_T_293)
node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0)))
node _T_296 = and(_T_290, _T_295)
node _T_297 = or(UInt<1>(0h0), _T_296)
node _T_298 = and(_T_289, _T_297)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_298, UInt<1>(0h1), "") : assert_10
node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_303 = shr(io.in.a.bits.source, 2)
node _T_304 = eq(_T_303, UInt<1>(0h0))
node _T_305 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_306 = and(_T_304, _T_305)
node _T_307 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_308 = and(_T_306, _T_307)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_309 = shr(io.in.a.bits.source, 2)
node _T_310 = eq(_T_309, UInt<1>(0h1))
node _T_311 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_312 = and(_T_310, _T_311)
node _T_313 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_315 = shr(io.in.a.bits.source, 2)
node _T_316 = eq(_T_315, UInt<2>(0h2))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_321 = shr(io.in.a.bits.source, 2)
node _T_322 = eq(_T_321, UInt<2>(0h3))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_302
connect _WIRE_2[1], _T_308
connect _WIRE_2[2], _T_314
connect _WIRE_2[3], _T_320
connect _WIRE_2[4], _T_326
connect _WIRE_2[5], _T_327
connect _WIRE_2[6], _T_328
connect _WIRE_2[7], _T_329
connect _WIRE_2[8], _T_330
node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0))
node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_341 = or(_T_332, _T_333)
node _T_342 = or(_T_341, _T_334)
node _T_343 = or(_T_342, _T_335)
node _T_344 = or(_T_343, _T_336)
node _T_345 = or(_T_344, _T_337)
node _T_346 = or(_T_345, _T_338)
node _T_347 = or(_T_346, _T_339)
node _T_348 = or(_T_347, _T_340)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_348
node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_351 = and(_T_349, _T_350)
node _T_352 = or(UInt<1>(0h0), _T_351)
node _T_353 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = and(_T_352, _T_357)
node _T_359 = or(UInt<1>(0h0), _T_358)
node _T_360 = and(_WIRE_3, _T_359)
node _T_361 = asUInt(reset)
node _T_362 = eq(_T_361, UInt<1>(0h0))
when _T_362 :
node _T_363 = eq(_T_360, UInt<1>(0h0))
when _T_363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_360, UInt<1>(0h1), "") : assert_11
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(source_ok, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_367, UInt<1>(0h1), "") : assert_13
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(is_aligned, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_374, UInt<1>(0h1), "") : assert_15
node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_378, UInt<1>(0h1), "") : assert_16
node _T_382 = not(io.in.a.bits.mask)
node _T_383 = eq(_T_382, UInt<1>(0h0))
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_383, UInt<1>(0h1), "") : assert_17
node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_387, UInt<1>(0h1), "") : assert_18
node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_391 :
node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_396 = shr(io.in.a.bits.source, 2)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_399 = and(_T_397, _T_398)
node _T_400 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_401 = and(_T_399, _T_400)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_402 = shr(io.in.a.bits.source, 2)
node _T_403 = eq(_T_402, UInt<1>(0h1))
node _T_404 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_405 = and(_T_403, _T_404)
node _T_406 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_407 = and(_T_405, _T_406)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_408 = shr(io.in.a.bits.source, 2)
node _T_409 = eq(_T_408, UInt<2>(0h2))
node _T_410 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_411 = and(_T_409, _T_410)
node _T_412 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_413 = and(_T_411, _T_412)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_414 = shr(io.in.a.bits.source, 2)
node _T_415 = eq(_T_414, UInt<2>(0h3))
node _T_416 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_417 = and(_T_415, _T_416)
node _T_418 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_424 = or(_T_395, _T_401)
node _T_425 = or(_T_424, _T_407)
node _T_426 = or(_T_425, _T_413)
node _T_427 = or(_T_426, _T_419)
node _T_428 = or(_T_427, _T_420)
node _T_429 = or(_T_428, _T_421)
node _T_430 = or(_T_429, _T_422)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_394, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_433, UInt<1>(0h1), "") : assert_19
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = asUInt(reset)
node _T_449 = eq(_T_448, UInt<1>(0h0))
when _T_449 :
node _T_450 = eq(_T_447, UInt<1>(0h0))
when _T_450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_447, UInt<1>(0h1), "") : assert_20
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(source_ok, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(is_aligned, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_457, UInt<1>(0h1), "") : assert_23
node _T_461 = eq(io.in.a.bits.mask, mask)
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_461, UInt<1>(0h1), "") : assert_24
node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_465, UInt<1>(0h1), "") : assert_25
node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_469 :
node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_472 = and(_T_470, _T_471)
node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_474 = shr(io.in.a.bits.source, 2)
node _T_475 = eq(_T_474, UInt<1>(0h0))
node _T_476 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_477 = and(_T_475, _T_476)
node _T_478 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_480 = shr(io.in.a.bits.source, 2)
node _T_481 = eq(_T_480, UInt<1>(0h1))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_485 = and(_T_483, _T_484)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_486 = shr(io.in.a.bits.source, 2)
node _T_487 = eq(_T_486, UInt<2>(0h2))
node _T_488 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_489 = and(_T_487, _T_488)
node _T_490 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_491 = and(_T_489, _T_490)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_492 = shr(io.in.a.bits.source, 2)
node _T_493 = eq(_T_492, UInt<2>(0h3))
node _T_494 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_495 = and(_T_493, _T_494)
node _T_496 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_497 = and(_T_495, _T_496)
node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_502 = or(_T_473, _T_479)
node _T_503 = or(_T_502, _T_485)
node _T_504 = or(_T_503, _T_491)
node _T_505 = or(_T_504, _T_497)
node _T_506 = or(_T_505, _T_498)
node _T_507 = or(_T_506, _T_499)
node _T_508 = or(_T_507, _T_500)
node _T_509 = or(_T_508, _T_501)
node _T_510 = and(_T_472, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_510)
node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_514 = and(_T_512, _T_513)
node _T_515 = or(UInt<1>(0h0), _T_514)
node _T_516 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = and(_T_515, _T_520)
node _T_522 = or(UInt<1>(0h0), _T_521)
node _T_523 = and(_T_511, _T_522)
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_523, UInt<1>(0h1), "") : assert_26
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(source_ok, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(is_aligned, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_534 = asUInt(reset)
node _T_535 = eq(_T_534, UInt<1>(0h0))
when _T_535 :
node _T_536 = eq(_T_533, UInt<1>(0h0))
when _T_536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_533, UInt<1>(0h1), "") : assert_29
node _T_537 = eq(io.in.a.bits.mask, mask)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_537, UInt<1>(0h1), "") : assert_30
node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_541 :
node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_546 = shr(io.in.a.bits.source, 2)
node _T_547 = eq(_T_546, UInt<1>(0h0))
node _T_548 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_549 = and(_T_547, _T_548)
node _T_550 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_551 = and(_T_549, _T_550)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_552 = shr(io.in.a.bits.source, 2)
node _T_553 = eq(_T_552, UInt<1>(0h1))
node _T_554 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_555 = and(_T_553, _T_554)
node _T_556 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_557 = and(_T_555, _T_556)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_558 = shr(io.in.a.bits.source, 2)
node _T_559 = eq(_T_558, UInt<2>(0h2))
node _T_560 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_561 = and(_T_559, _T_560)
node _T_562 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_563 = and(_T_561, _T_562)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_564 = shr(io.in.a.bits.source, 2)
node _T_565 = eq(_T_564, UInt<2>(0h3))
node _T_566 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_567 = and(_T_565, _T_566)
node _T_568 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_569 = and(_T_567, _T_568)
node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_574 = or(_T_545, _T_551)
node _T_575 = or(_T_574, _T_557)
node _T_576 = or(_T_575, _T_563)
node _T_577 = or(_T_576, _T_569)
node _T_578 = or(_T_577, _T_570)
node _T_579 = or(_T_578, _T_571)
node _T_580 = or(_T_579, _T_572)
node _T_581 = or(_T_580, _T_573)
node _T_582 = and(_T_544, _T_581)
node _T_583 = or(UInt<1>(0h0), _T_582)
node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_586 = and(_T_584, _T_585)
node _T_587 = or(UInt<1>(0h0), _T_586)
node _T_588 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_589 = cvt(_T_588)
node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000)))
node _T_591 = asSInt(_T_590)
node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0)))
node _T_593 = and(_T_587, _T_592)
node _T_594 = or(UInt<1>(0h0), _T_593)
node _T_595 = and(_T_583, _T_594)
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_595, UInt<1>(0h1), "") : assert_31
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(source_ok, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(is_aligned, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_605, UInt<1>(0h1), "") : assert_34
node _T_609 = not(mask)
node _T_610 = and(io.in.a.bits.mask, _T_609)
node _T_611 = eq(_T_610, UInt<1>(0h0))
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_T_611, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_611, UInt<1>(0h1), "") : assert_35
node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_615 :
node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_618 = and(_T_616, _T_617)
node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_620 = shr(io.in.a.bits.source, 2)
node _T_621 = eq(_T_620, UInt<1>(0h0))
node _T_622 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_623 = and(_T_621, _T_622)
node _T_624 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_625 = and(_T_623, _T_624)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_626 = shr(io.in.a.bits.source, 2)
node _T_627 = eq(_T_626, UInt<1>(0h1))
node _T_628 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_629 = and(_T_627, _T_628)
node _T_630 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_631 = and(_T_629, _T_630)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_632 = shr(io.in.a.bits.source, 2)
node _T_633 = eq(_T_632, UInt<2>(0h2))
node _T_634 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_635 = and(_T_633, _T_634)
node _T_636 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_637 = and(_T_635, _T_636)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_638 = shr(io.in.a.bits.source, 2)
node _T_639 = eq(_T_638, UInt<2>(0h3))
node _T_640 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_641 = and(_T_639, _T_640)
node _T_642 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_643 = and(_T_641, _T_642)
node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_648 = or(_T_619, _T_625)
node _T_649 = or(_T_648, _T_631)
node _T_650 = or(_T_649, _T_637)
node _T_651 = or(_T_650, _T_643)
node _T_652 = or(_T_651, _T_644)
node _T_653 = or(_T_652, _T_645)
node _T_654 = or(_T_653, _T_646)
node _T_655 = or(_T_654, _T_647)
node _T_656 = and(_T_618, _T_655)
node _T_657 = or(UInt<1>(0h0), _T_656)
node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_659 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_660 = cvt(_T_659)
node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000)))
node _T_662 = asSInt(_T_661)
node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0)))
node _T_664 = and(_T_658, _T_663)
node _T_665 = or(UInt<1>(0h0), _T_664)
node _T_666 = and(_T_657, _T_665)
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(_T_666, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_666, UInt<1>(0h1), "") : assert_36
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(source_ok, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(is_aligned, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_677 = asUInt(reset)
node _T_678 = eq(_T_677, UInt<1>(0h0))
when _T_678 :
node _T_679 = eq(_T_676, UInt<1>(0h0))
when _T_679 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_676, UInt<1>(0h1), "") : assert_39
node _T_680 = eq(io.in.a.bits.mask, mask)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_680, UInt<1>(0h1), "") : assert_40
node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_684 :
node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_687 = and(_T_685, _T_686)
node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_689 = shr(io.in.a.bits.source, 2)
node _T_690 = eq(_T_689, UInt<1>(0h0))
node _T_691 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_692 = and(_T_690, _T_691)
node _T_693 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_695 = shr(io.in.a.bits.source, 2)
node _T_696 = eq(_T_695, UInt<1>(0h1))
node _T_697 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_698 = and(_T_696, _T_697)
node _T_699 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_700 = and(_T_698, _T_699)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_701 = shr(io.in.a.bits.source, 2)
node _T_702 = eq(_T_701, UInt<2>(0h2))
node _T_703 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_704 = and(_T_702, _T_703)
node _T_705 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_706 = and(_T_704, _T_705)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_707 = shr(io.in.a.bits.source, 2)
node _T_708 = eq(_T_707, UInt<2>(0h3))
node _T_709 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_710 = and(_T_708, _T_709)
node _T_711 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_712 = and(_T_710, _T_711)
node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_717 = or(_T_688, _T_694)
node _T_718 = or(_T_717, _T_700)
node _T_719 = or(_T_718, _T_706)
node _T_720 = or(_T_719, _T_712)
node _T_721 = or(_T_720, _T_713)
node _T_722 = or(_T_721, _T_714)
node _T_723 = or(_T_722, _T_715)
node _T_724 = or(_T_723, _T_716)
node _T_725 = and(_T_687, _T_724)
node _T_726 = or(UInt<1>(0h0), _T_725)
node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_728 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = and(_T_727, _T_732)
node _T_734 = or(UInt<1>(0h0), _T_733)
node _T_735 = and(_T_726, _T_734)
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_735, UInt<1>(0h1), "") : assert_41
node _T_739 = asUInt(reset)
node _T_740 = eq(_T_739, UInt<1>(0h0))
when _T_740 :
node _T_741 = eq(source_ok, UInt<1>(0h0))
when _T_741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(is_aligned, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_745, UInt<1>(0h1), "") : assert_44
node _T_749 = eq(io.in.a.bits.mask, mask)
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(_T_749, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_749, UInt<1>(0h1), "") : assert_45
node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_753 :
node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_756 = and(_T_754, _T_755)
node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<1>(0h0))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_763 = and(_T_761, _T_762)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_764 = shr(io.in.a.bits.source, 2)
node _T_765 = eq(_T_764, UInt<1>(0h1))
node _T_766 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_767 = and(_T_765, _T_766)
node _T_768 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_769 = and(_T_767, _T_768)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_770 = shr(io.in.a.bits.source, 2)
node _T_771 = eq(_T_770, UInt<2>(0h2))
node _T_772 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_773 = and(_T_771, _T_772)
node _T_774 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_775 = and(_T_773, _T_774)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_776 = shr(io.in.a.bits.source, 2)
node _T_777 = eq(_T_776, UInt<2>(0h3))
node _T_778 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_779 = and(_T_777, _T_778)
node _T_780 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_781 = and(_T_779, _T_780)
node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_786 = or(_T_757, _T_763)
node _T_787 = or(_T_786, _T_769)
node _T_788 = or(_T_787, _T_775)
node _T_789 = or(_T_788, _T_781)
node _T_790 = or(_T_789, _T_782)
node _T_791 = or(_T_790, _T_783)
node _T_792 = or(_T_791, _T_784)
node _T_793 = or(_T_792, _T_785)
node _T_794 = and(_T_756, _T_793)
node _T_795 = or(UInt<1>(0h0), _T_794)
node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_797 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_798 = cvt(_T_797)
node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000)))
node _T_800 = asSInt(_T_799)
node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0)))
node _T_802 = and(_T_796, _T_801)
node _T_803 = or(UInt<1>(0h0), _T_802)
node _T_804 = and(_T_795, _T_803)
node _T_805 = asUInt(reset)
node _T_806 = eq(_T_805, UInt<1>(0h0))
when _T_806 :
node _T_807 = eq(_T_804, UInt<1>(0h0))
when _T_807 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_804, UInt<1>(0h1), "") : assert_46
node _T_808 = asUInt(reset)
node _T_809 = eq(_T_808, UInt<1>(0h0))
when _T_809 :
node _T_810 = eq(source_ok, UInt<1>(0h0))
when _T_810 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_811 = asUInt(reset)
node _T_812 = eq(_T_811, UInt<1>(0h0))
when _T_812 :
node _T_813 = eq(is_aligned, UInt<1>(0h0))
when _T_813 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_815 = asUInt(reset)
node _T_816 = eq(_T_815, UInt<1>(0h0))
when _T_816 :
node _T_817 = eq(_T_814, UInt<1>(0h0))
when _T_817 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_814, UInt<1>(0h1), "") : assert_49
node _T_818 = eq(io.in.a.bits.mask, mask)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_818, UInt<1>(0h1), "") : assert_50
node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_822, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_827 = asUInt(reset)
node _T_828 = eq(_T_827, UInt<1>(0h0))
when _T_828 :
node _T_829 = eq(_T_826, UInt<1>(0h0))
when _T_829 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_826, UInt<1>(0h1), "") : assert_52
node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_37 = shr(io.in.d.bits.source, 2)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 2)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 2)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_36
connect _source_ok_WIRE_1[1], _source_ok_T_42
connect _source_ok_WIRE_1[2], _source_ok_T_48
connect _source_ok_WIRE_1[3], _source_ok_T_54
connect _source_ok_WIRE_1[4], _source_ok_T_60
connect _source_ok_WIRE_1[5], _source_ok_T_61
connect _source_ok_WIRE_1[6], _source_ok_T_62
connect _source_ok_WIRE_1[7], _source_ok_T_63
connect _source_ok_WIRE_1[8], _source_ok_T_64
node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_830 :
node _T_831 = asUInt(reset)
node _T_832 = eq(_T_831, UInt<1>(0h0))
when _T_832 :
node _T_833 = eq(source_ok_1, UInt<1>(0h0))
when _T_833 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_834, UInt<1>(0h1), "") : assert_54
node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_838, UInt<1>(0h1), "") : assert_55
node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_842, UInt<1>(0h1), "") : assert_56
node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_847 = asUInt(reset)
node _T_848 = eq(_T_847, UInt<1>(0h0))
when _T_848 :
node _T_849 = eq(_T_846, UInt<1>(0h0))
when _T_849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_846, UInt<1>(0h1), "") : assert_57
node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_850 :
node _T_851 = asUInt(reset)
node _T_852 = eq(_T_851, UInt<1>(0h0))
when _T_852 :
node _T_853 = eq(source_ok_1, UInt<1>(0h0))
when _T_853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(sink_ok, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(_T_857, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_857, UInt<1>(0h1), "") : assert_60
node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_T_861, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_861, UInt<1>(0h1), "") : assert_61
node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_865, UInt<1>(0h1), "") : assert_62
node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_869, UInt<1>(0h1), "") : assert_63
node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_874 = or(UInt<1>(0h0), _T_873)
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(_T_874, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_874, UInt<1>(0h1), "") : assert_64
node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_878 :
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(source_ok_1, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(sink_ok, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_885, UInt<1>(0h1), "") : assert_67
node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_889, UInt<1>(0h1), "") : assert_68
node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_893, UInt<1>(0h1), "") : assert_69
node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_898 = or(_T_897, io.in.d.bits.corrupt)
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_898, UInt<1>(0h1), "") : assert_70
node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_903 = or(UInt<1>(0h0), _T_902)
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_903, UInt<1>(0h1), "") : assert_71
node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_907 :
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(source_ok_1, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(_T_911, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_911, UInt<1>(0h1), "") : assert_73
node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_915, UInt<1>(0h1), "") : assert_74
node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_920 = or(UInt<1>(0h0), _T_919)
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_920, UInt<1>(0h1), "") : assert_75
node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_924 :
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(source_ok_1, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_929 = asUInt(reset)
node _T_930 = eq(_T_929, UInt<1>(0h0))
when _T_930 :
node _T_931 = eq(_T_928, UInt<1>(0h0))
when _T_931 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_928, UInt<1>(0h1), "") : assert_77
node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_933 = or(_T_932, io.in.d.bits.corrupt)
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_933, UInt<1>(0h1), "") : assert_78
node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_938 = or(UInt<1>(0h0), _T_937)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_938, UInt<1>(0h1), "") : assert_79
node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_942 :
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(source_ok_1, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_946, UInt<1>(0h1), "") : assert_81
node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_951 = asUInt(reset)
node _T_952 = eq(_T_951, UInt<1>(0h0))
when _T_952 :
node _T_953 = eq(_T_950, UInt<1>(0h0))
when _T_953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_950, UInt<1>(0h1), "") : assert_82
node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_955 = or(UInt<1>(0h0), _T_954)
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_955, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_959, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_963, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_967, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_971 = eq(a_first, UInt<1>(0h0))
node _T_972 = and(io.in.a.valid, _T_971)
when _T_972 :
node _T_973 = eq(io.in.a.bits.opcode, opcode)
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(_T_973, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_973, UInt<1>(0h1), "") : assert_87
node _T_977 = eq(io.in.a.bits.param, param)
node _T_978 = asUInt(reset)
node _T_979 = eq(_T_978, UInt<1>(0h0))
when _T_979 :
node _T_980 = eq(_T_977, UInt<1>(0h0))
when _T_980 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_977, UInt<1>(0h1), "") : assert_88
node _T_981 = eq(io.in.a.bits.size, size)
node _T_982 = asUInt(reset)
node _T_983 = eq(_T_982, UInt<1>(0h0))
when _T_983 :
node _T_984 = eq(_T_981, UInt<1>(0h0))
when _T_984 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_981, UInt<1>(0h1), "") : assert_89
node _T_985 = eq(io.in.a.bits.source, source)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_985, UInt<1>(0h1), "") : assert_90
node _T_989 = eq(io.in.a.bits.address, address)
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_T_989, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_989, UInt<1>(0h1), "") : assert_91
node _T_993 = and(io.in.a.ready, io.in.a.valid)
node _T_994 = and(_T_993, a_first)
when _T_994 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_995 = eq(d_first, UInt<1>(0h0))
node _T_996 = and(io.in.d.valid, _T_995)
when _T_996 :
node _T_997 = eq(io.in.d.bits.opcode, opcode_1)
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_997, UInt<1>(0h1), "") : assert_92
node _T_1001 = eq(io.in.d.bits.param, param_1)
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93
node _T_1005 = eq(io.in.d.bits.size, size_1)
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94
node _T_1009 = eq(io.in.d.bits.source, source_1)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95
node _T_1013 = eq(io.in.d.bits.sink, sink)
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96
node _T_1017 = eq(io.in.d.bits.denied, denied)
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97
node _T_1021 = and(io.in.d.ready, io.in.d.valid)
node _T_1022 = and(_T_1021, d_first)
when _T_1022 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1023 = and(io.in.a.valid, a_first_1)
node _T_1024 = and(_T_1023, UInt<1>(0h1))
when _T_1024 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1025 = and(io.in.a.ready, io.in.a.valid)
node _T_1026 = and(_T_1025, a_first_1)
node _T_1027 = and(_T_1026, UInt<1>(0h1))
when _T_1027 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1028 = dshr(inflight, io.in.a.bits.source)
node _T_1029 = bits(_T_1028, 0, 0)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1034 = and(io.in.d.valid, d_first_1)
node _T_1035 = and(_T_1034, UInt<1>(0h1))
node _T_1036 = eq(d_release_ack, UInt<1>(0h0))
node _T_1037 = and(_T_1035, _T_1036)
when _T_1037 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1038 = and(io.in.d.ready, io.in.d.valid)
node _T_1039 = and(_T_1038, d_first_1)
node _T_1040 = and(_T_1039, UInt<1>(0h1))
node _T_1041 = eq(d_release_ack, UInt<1>(0h0))
node _T_1042 = and(_T_1040, _T_1041)
when _T_1042 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1043 = and(io.in.d.valid, d_first_1)
node _T_1044 = and(_T_1043, UInt<1>(0h1))
node _T_1045 = eq(d_release_ack, UInt<1>(0h0))
node _T_1046 = and(_T_1044, _T_1045)
when _T_1046 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1047 = dshr(inflight, io.in.d.bits.source)
node _T_1048 = bits(_T_1047, 0, 0)
node _T_1049 = or(_T_1048, same_cycle_resp)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1055 = or(_T_1053, _T_1054)
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(_T_1055, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100
node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101
else :
node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1065 = or(_T_1063, _T_1064)
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102
node _T_1069 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103
node _T_1073 = and(io.in.d.valid, d_first_1)
node _T_1074 = and(_T_1073, a_first_1)
node _T_1075 = and(_T_1074, io.in.a.valid)
node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1077 = and(_T_1075, _T_1076)
node _T_1078 = eq(d_release_ack, UInt<1>(0h0))
node _T_1079 = and(_T_1077, _T_1078)
when _T_1079 :
node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1081 = or(_T_1080, io.in.a.ready)
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(_T_1081, UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_121
node _T_1085 = orr(inflight)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1088 = or(_T_1086, _T_1087)
node _T_1089 = lt(watchdog, plusarg_reader.out)
node _T_1090 = or(_T_1088, _T_1089)
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1094 = and(io.in.a.ready, io.in.a.valid)
node _T_1095 = and(io.in.d.ready, io.in.d.valid)
node _T_1096 = or(_T_1094, _T_1095)
when _T_1096 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1097 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = and(_T_1097, _T_1100)
when _T_1101 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1103 = and(_T_1102, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1106 = and(_T_1104, _T_1105)
node _T_1107 = and(_T_1103, _T_1106)
when _T_1107 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1109 = bits(_T_1108, 0, 0)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1114 = and(io.in.d.valid, d_first_2)
node _T_1115 = and(_T_1114, UInt<1>(0h1))
node _T_1116 = and(_T_1115, d_release_ack_1)
when _T_1116 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1117 = and(io.in.d.ready, io.in.d.valid)
node _T_1118 = and(_T_1117, d_first_2)
node _T_1119 = and(_T_1118, UInt<1>(0h1))
node _T_1120 = and(_T_1119, d_release_ack_1)
when _T_1120 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1121 = and(io.in.d.valid, d_first_2)
node _T_1122 = and(_T_1121, UInt<1>(0h1))
node _T_1123 = and(_T_1122, d_release_ack_1)
when _T_1123 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1124 = dshr(inflight_1, io.in.d.bits.source)
node _T_1125 = bits(_T_1124, 0, 0)
node _T_1126 = or(_T_1125, same_cycle_resp_1)
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108
else :
node _T_1134 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109
node _T_1138 = and(io.in.d.valid, d_first_2)
node _T_1139 = and(_T_1138, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1140 = and(_T_1139, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1142 = and(_T_1140, _T_1141)
node _T_1143 = and(_T_1142, d_release_ack_1)
node _T_1144 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1145 = and(_T_1143, _T_1144)
when _T_1145 :
node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1147 = or(_T_1146, _WIRE_27.ready)
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_122
node _T_1151 = orr(inflight_1)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1154 = or(_T_1152, _T_1153)
node _T_1155 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1156 = or(_T_1154, _T_1155)
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1161 = and(io.in.d.ready, io.in.d.valid)
node _T_1162 = or(_T_1160, _T_1161)
when _T_1162 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_59( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_prci_ctrl :
input clock : Clock
input reset : Reset
output auto : { fixer_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst fixer of TLFIFOFixer_3
connect fixer.clock, clock
connect fixer.reset, reset
inst buffer of TLBuffer_a21d64s7k1z3u
connect buffer.clock, clock
connect buffer.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect buffer.auto.in, tlOut
connect fixer.auto.anon_in, buffer.auto.out
connect tlIn, auto.tl_in
connect fixer.auto.anon_out.d, auto.fixer_anon_out.d
connect auto.fixer_anon_out.a.bits, fixer.auto.anon_out.a.bits
connect auto.fixer_anon_out.a.valid, fixer.auto.anon_out.a.valid
connect fixer.auto.anon_out.a.ready, auto.fixer_anon_out.a.ready | module TLInterconnectCoupler_cbus_to_prci_ctrl( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire tlOut_d_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [6:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOut_a_ready; // @[MixedNode.scala:542:17]
wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [20:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire auto_fixer_anon_out_a_ready_0 = auto_fixer_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_d_valid_0 = auto_fixer_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fixer_anon_out_d_bits_opcode_0 = auto_fixer_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fixer_anon_out_d_bits_size_0 = auto_fixer_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_fixer_anon_out_d_bits_source_0 = auto_fixer_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fixer_anon_out_d_bits_data_0 = auto_fixer_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire [21:0] fixer__a_notFIFO_T_2 = 22'h0; // @[Parameters.scala:137:46]
wire [21:0] fixer__a_notFIFO_T_3 = 22'h0; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire [64:0] fixer__allIDs_FIFOed_T = 65'h1FFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48]
wire auto_fixer_anon_out_d_bits_sink = 1'h0; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_d_bits_denied = 1'h0; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_d_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35]
wire [1:0] auto_fixer_anon_out_d_bits_param = 2'h0; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire fixer_auto_anon_out_a_ready = auto_fixer_anon_out_a_ready_0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [20:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_valid = auto_fixer_anon_out_d_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_d_bits_opcode = auto_fixer_anon_out_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_d_bits_size = auto_fixer_anon_out_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_out_d_bits_source = auto_fixer_anon_out_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_d_bits_data = auto_fixer_anon_out_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [6:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [20:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] auto_fixer_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fixer_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fixer_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_fixer_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [20:0] auto_fixer_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fixer_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fixer_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [20:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_valid_0 = fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_bits_opcode_0 = fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_bits_param_0 = fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_bits_size_0 = fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_bits_source_0 = fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [20:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_bits_address_0 = fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_bits_mask_0 = fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_bits_data_0 = fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_a_bits_corrupt_0 = fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_fixer_anon_out_d_ready_0 = fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [20:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [20:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
wire [21:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [21:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire [21:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}]
wire [21:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46]
wire fixer__a_id_T_4 = fixer__a_id_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73]
wire [20:0] fixer__a_id_T_5 = {fixer_anonIn_a_bits_address[20:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [21:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire [21:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}]
wire [21:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46]
wire fixer__a_id_T_9 = fixer__a_id_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}]
wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} | fixer__a_id_T_11; // @[Mux.scala:30:73]
wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73]
wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_16; // @[FIFOFixer.scala:79:27]
reg fixer_flight_17; // @[FIFOFixer.scala:79:27]
reg fixer_flight_18; // @[FIFOFixer.scala:79:27]
reg fixer_flight_19; // @[FIFOFixer.scala:79:27]
reg fixer_flight_20; // @[FIFOFixer.scala:79:27]
reg fixer_flight_21; // @[FIFOFixer.scala:79:27]
reg fixer_flight_22; // @[FIFOFixer.scala:79:27]
reg fixer_flight_23; // @[FIFOFixer.scala:79:27]
reg fixer_flight_24; // @[FIFOFixer.scala:79:27]
reg fixer_flight_25; // @[FIFOFixer.scala:79:27]
reg fixer_flight_26; // @[FIFOFixer.scala:79:27]
reg fixer_flight_27; // @[FIFOFixer.scala:79:27]
reg fixer_flight_28; // @[FIFOFixer.scala:79:27]
reg fixer_flight_29; // @[FIFOFixer.scala:79:27]
reg fixer_flight_30; // @[FIFOFixer.scala:79:27]
reg fixer_flight_31; // @[FIFOFixer.scala:79:27]
reg fixer_flight_32; // @[FIFOFixer.scala:79:27]
reg fixer_flight_33; // @[FIFOFixer.scala:79:27]
reg fixer_flight_34; // @[FIFOFixer.scala:79:27]
reg fixer_flight_35; // @[FIFOFixer.scala:79:27]
reg fixer_flight_36; // @[FIFOFixer.scala:79:27]
reg fixer_flight_37; // @[FIFOFixer.scala:79:27]
reg fixer_flight_38; // @[FIFOFixer.scala:79:27]
reg fixer_flight_39; // @[FIFOFixer.scala:79:27]
reg fixer_flight_40; // @[FIFOFixer.scala:79:27]
reg fixer_flight_41; // @[FIFOFixer.scala:79:27]
reg fixer_flight_42; // @[FIFOFixer.scala:79:27]
reg fixer_flight_43; // @[FIFOFixer.scala:79:27]
reg fixer_flight_44; // @[FIFOFixer.scala:79:27]
reg fixer_flight_45; // @[FIFOFixer.scala:79:27]
reg fixer_flight_46; // @[FIFOFixer.scala:79:27]
reg fixer_flight_47; // @[FIFOFixer.scala:79:27]
reg fixer_flight_48; // @[FIFOFixer.scala:79:27]
reg fixer_flight_49; // @[FIFOFixer.scala:79:27]
reg fixer_flight_50; // @[FIFOFixer.scala:79:27]
reg fixer_flight_51; // @[FIFOFixer.scala:79:27]
reg fixer_flight_52; // @[FIFOFixer.scala:79:27]
reg fixer_flight_53; // @[FIFOFixer.scala:79:27]
reg fixer_flight_54; // @[FIFOFixer.scala:79:27]
reg fixer_flight_55; // @[FIFOFixer.scala:79:27]
reg fixer_flight_56; // @[FIFOFixer.scala:79:27]
reg fixer_flight_57; // @[FIFOFixer.scala:79:27]
reg fixer_flight_58; // @[FIFOFixer.scala:79:27]
reg fixer_flight_59; // @[FIFOFixer.scala:79:27]
reg fixer_flight_60; // @[FIFOFixer.scala:79:27]
reg fixer_flight_61; // @[FIFOFixer.scala:79:27]
reg fixer_flight_62; // @[FIFOFixer.scala:79:27]
reg fixer_flight_63; // @[FIFOFixer.scala:79:27]
reg fixer_flight_64; // @[FIFOFixer.scala:79:27]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [64:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [64:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [64:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [127:0] fixer__SourceIdSet_T = 128'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [127:0] fixer__SourceIdClear_T = 128'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [64:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_param_0 = tlIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_sink_0 = tlIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_denied_0 = tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_corrupt_0 = tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[LazyModuleImp.scala:138:7]
if (reset) begin // @[LazyModuleImp.scala:138:7]
fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 65'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[LazyModuleImp.scala:138:7]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h0 | fixer_flight_0); // @[package.scala:243:71]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
end
always @(posedge)
TLBuffer_a21d64s7k1z3u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (tlOut_a_ready),
.auto_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17]
.auto_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17]
.auto_in_d_valid (tlOut_d_valid),
.auto_in_d_bits_opcode (tlOut_d_bits_opcode),
.auto_in_d_bits_param (tlOut_d_bits_param),
.auto_in_d_bits_size (tlOut_d_bits_size),
.auto_in_d_bits_source (tlOut_d_bits_source),
.auto_in_d_bits_sink (tlOut_d_bits_sink),
.auto_in_d_bits_denied (tlOut_d_bits_denied),
.auto_in_d_bits_data (tlOut_d_bits_data),
.auto_in_d_bits_corrupt (tlOut_d_bits_corrupt),
.auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9]
.auto_out_a_valid (fixer_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt),
.auto_out_d_ready (fixer_auto_anon_in_d_ready),
.auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9]
); // @[Buffer.scala:75:28]
assign auto_fixer_anon_out_a_valid = auto_fixer_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_opcode = auto_fixer_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_param = auto_fixer_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_size = auto_fixer_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_source = auto_fixer_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_address = auto_fixer_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_mask = auto_fixer_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_data = auto_fixer_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_corrupt = auto_fixer_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_d_ready = auto_fixer_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_param = auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_sink = auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_denied = auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_corrupt = auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_254 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_254( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputBuffer_9 :
input clock : Clock
input reset : Reset
output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}}[6]}
cmem mem : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} [20]
wire _heads_WIRE : UInt<5>[6]
connect _heads_WIRE[0], UInt<5>(0h0)
connect _heads_WIRE[1], UInt<5>(0h0)
connect _heads_WIRE[2], UInt<5>(0h4)
connect _heads_WIRE[3], UInt<5>(0h8)
connect _heads_WIRE[4], UInt<5>(0hc)
connect _heads_WIRE[5], UInt<5>(0h10)
regreset heads : UInt<5>[6], clock, reset, _heads_WIRE
wire _tails_WIRE : UInt<5>[6]
connect _tails_WIRE[0], UInt<5>(0h0)
connect _tails_WIRE[1], UInt<5>(0h0)
connect _tails_WIRE[2], UInt<5>(0h4)
connect _tails_WIRE[3], UInt<5>(0h8)
connect _tails_WIRE[4], UInt<5>(0hc)
connect _tails_WIRE[5], UInt<5>(0h10)
regreset tails : UInt<5>[6], clock, reset, _tails_WIRE
node empty_0 = eq(heads[0], tails[0])
node empty_1 = eq(heads[1], tails[1])
node empty_2 = eq(heads[2], tails[2])
node empty_3 = eq(heads[3], tails[3])
node empty_4 = eq(heads[4], tails[4])
node empty_5 = eq(heads[5], tails[5])
inst qs_0 of Queue1_BaseFlit_54
connect qs_0.clock, clock
connect qs_0.reset, reset
inst qs_1 of Queue1_BaseFlit_55
connect qs_1.clock, clock
connect qs_1.reset, reset
inst qs_2 of Queue1_BaseFlit_56
connect qs_2.clock, clock
connect qs_2.reset, reset
inst qs_3 of Queue1_BaseFlit_57
connect qs_3.clock, clock
connect qs_3.reset, reset
inst qs_4 of Queue1_BaseFlit_58
connect qs_4.clock, clock
connect qs_4.reset, reset
inst qs_5 of Queue1_BaseFlit_59
connect qs_5.clock, clock
connect qs_5.reset, reset
connect qs_0.io.enq.valid, UInt<1>(0h0)
connect qs_1.io.enq.valid, UInt<1>(0h0)
connect qs_2.io.enq.valid, UInt<1>(0h0)
connect qs_3.io.enq.valid, UInt<1>(0h0)
connect qs_4.io.enq.valid, UInt<1>(0h0)
connect qs_5.io.enq.valid, UInt<1>(0h0)
invalidate qs_0.io.enq.bits.payload
invalidate qs_0.io.enq.bits.tail
invalidate qs_0.io.enq.bits.head
invalidate qs_1.io.enq.bits.payload
invalidate qs_1.io.enq.bits.tail
invalidate qs_1.io.enq.bits.head
invalidate qs_2.io.enq.bits.payload
invalidate qs_2.io.enq.bits.tail
invalidate qs_2.io.enq.bits.head
invalidate qs_3.io.enq.bits.payload
invalidate qs_3.io.enq.bits.tail
invalidate qs_3.io.enq.bits.head
invalidate qs_4.io.enq.bits.payload
invalidate qs_4.io.enq.bits.tail
invalidate qs_4.io.enq.bits.head
invalidate qs_5.io.enq.bits.payload
invalidate qs_5.io.enq.bits.tail
invalidate qs_5.io.enq.bits.head
node vc_sel = dshl(UInt<1>(0h1), io.enq[0].bits.virt_channel_id)
wire flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}
node _direct_to_q_T = bits(vc_sel, 0, 0)
node _direct_to_q_T_1 = bits(vc_sel, 1, 1)
node _direct_to_q_T_2 = bits(vc_sel, 2, 2)
node _direct_to_q_T_3 = bits(vc_sel, 3, 3)
node _direct_to_q_T_4 = bits(vc_sel, 4, 4)
node _direct_to_q_T_5 = bits(vc_sel, 5, 5)
node _direct_to_q_T_6 = mux(_direct_to_q_T, qs_0.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_7 = mux(_direct_to_q_T_1, qs_1.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_8 = mux(_direct_to_q_T_2, qs_2.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_9 = mux(_direct_to_q_T_3, qs_3.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_10 = mux(_direct_to_q_T_4, qs_4.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_11 = mux(_direct_to_q_T_5, qs_5.io.enq.ready, UInt<1>(0h0))
node _direct_to_q_T_12 = or(_direct_to_q_T_6, _direct_to_q_T_7)
node _direct_to_q_T_13 = or(_direct_to_q_T_12, _direct_to_q_T_8)
node _direct_to_q_T_14 = or(_direct_to_q_T_13, _direct_to_q_T_9)
node _direct_to_q_T_15 = or(_direct_to_q_T_14, _direct_to_q_T_10)
node _direct_to_q_T_16 = or(_direct_to_q_T_15, _direct_to_q_T_11)
wire _direct_to_q_WIRE : UInt<1>
connect _direct_to_q_WIRE, _direct_to_q_T_16
node _direct_to_q_T_17 = bits(vc_sel, 0, 0)
node _direct_to_q_T_18 = bits(vc_sel, 1, 1)
node _direct_to_q_T_19 = bits(vc_sel, 2, 2)
node _direct_to_q_T_20 = bits(vc_sel, 3, 3)
node _direct_to_q_T_21 = bits(vc_sel, 4, 4)
node _direct_to_q_T_22 = bits(vc_sel, 5, 5)
node _direct_to_q_T_23 = mux(_direct_to_q_T_17, empty_0, UInt<1>(0h0))
node _direct_to_q_T_24 = mux(_direct_to_q_T_18, empty_1, UInt<1>(0h0))
node _direct_to_q_T_25 = mux(_direct_to_q_T_19, empty_2, UInt<1>(0h0))
node _direct_to_q_T_26 = mux(_direct_to_q_T_20, empty_3, UInt<1>(0h0))
node _direct_to_q_T_27 = mux(_direct_to_q_T_21, empty_4, UInt<1>(0h0))
node _direct_to_q_T_28 = mux(_direct_to_q_T_22, empty_5, UInt<1>(0h0))
node _direct_to_q_T_29 = or(_direct_to_q_T_23, _direct_to_q_T_24)
node _direct_to_q_T_30 = or(_direct_to_q_T_29, _direct_to_q_T_25)
node _direct_to_q_T_31 = or(_direct_to_q_T_30, _direct_to_q_T_26)
node _direct_to_q_T_32 = or(_direct_to_q_T_31, _direct_to_q_T_27)
node _direct_to_q_T_33 = or(_direct_to_q_T_32, _direct_to_q_T_28)
wire _direct_to_q_WIRE_1 : UInt<1>
connect _direct_to_q_WIRE_1, _direct_to_q_T_33
node _direct_to_q_T_34 = and(_direct_to_q_WIRE, _direct_to_q_WIRE_1)
node direct_to_q = and(_direct_to_q_T_34, UInt<1>(0h1))
connect flit.head, io.enq[0].bits.head
connect flit.tail, io.enq[0].bits.tail
connect flit.payload, io.enq[0].bits.payload
node _T = eq(direct_to_q, UInt<1>(0h0))
node _T_1 = and(io.enq[0].valid, _T)
when _T_1 :
write mport MPORT = mem[tails[io.enq[0].bits.virt_channel_id]], clock
connect MPORT, flit
node _tails_T = bits(vc_sel, 0, 0)
node _tails_T_1 = bits(vc_sel, 1, 1)
node _tails_T_2 = bits(vc_sel, 2, 2)
node _tails_T_3 = bits(vc_sel, 3, 3)
node _tails_T_4 = bits(vc_sel, 4, 4)
node _tails_T_5 = bits(vc_sel, 5, 5)
node _tails_T_6 = mux(_tails_T, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_7 = mux(_tails_T_1, UInt<2>(0h3), UInt<1>(0h0))
node _tails_T_8 = mux(_tails_T_2, UInt<3>(0h7), UInt<1>(0h0))
node _tails_T_9 = mux(_tails_T_3, UInt<4>(0hb), UInt<1>(0h0))
node _tails_T_10 = mux(_tails_T_4, UInt<4>(0hf), UInt<1>(0h0))
node _tails_T_11 = mux(_tails_T_5, UInt<5>(0h13), UInt<1>(0h0))
node _tails_T_12 = or(_tails_T_6, _tails_T_7)
node _tails_T_13 = or(_tails_T_12, _tails_T_8)
node _tails_T_14 = or(_tails_T_13, _tails_T_9)
node _tails_T_15 = or(_tails_T_14, _tails_T_10)
node _tails_T_16 = or(_tails_T_15, _tails_T_11)
wire _tails_WIRE_1 : UInt<5>
connect _tails_WIRE_1, _tails_T_16
node _tails_T_17 = eq(tails[io.enq[0].bits.virt_channel_id], _tails_WIRE_1)
node _tails_T_18 = bits(vc_sel, 0, 0)
node _tails_T_19 = bits(vc_sel, 1, 1)
node _tails_T_20 = bits(vc_sel, 2, 2)
node _tails_T_21 = bits(vc_sel, 3, 3)
node _tails_T_22 = bits(vc_sel, 4, 4)
node _tails_T_23 = bits(vc_sel, 5, 5)
node _tails_T_24 = mux(_tails_T_18, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_25 = mux(_tails_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _tails_T_26 = mux(_tails_T_20, UInt<3>(0h4), UInt<1>(0h0))
node _tails_T_27 = mux(_tails_T_21, UInt<4>(0h8), UInt<1>(0h0))
node _tails_T_28 = mux(_tails_T_22, UInt<4>(0hc), UInt<1>(0h0))
node _tails_T_29 = mux(_tails_T_23, UInt<5>(0h10), UInt<1>(0h0))
node _tails_T_30 = or(_tails_T_24, _tails_T_25)
node _tails_T_31 = or(_tails_T_30, _tails_T_26)
node _tails_T_32 = or(_tails_T_31, _tails_T_27)
node _tails_T_33 = or(_tails_T_32, _tails_T_28)
node _tails_T_34 = or(_tails_T_33, _tails_T_29)
wire _tails_WIRE_2 : UInt<5>
connect _tails_WIRE_2, _tails_T_34
node _tails_T_35 = add(tails[io.enq[0].bits.virt_channel_id], UInt<1>(0h1))
node _tails_T_36 = tail(_tails_T_35, 1)
node _tails_T_37 = mux(_tails_T_17, _tails_WIRE_2, _tails_T_36)
connect tails[io.enq[0].bits.virt_channel_id], _tails_T_37
else :
node _T_2 = and(io.enq[0].valid, direct_to_q)
when _T_2 :
node _T_3 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0))
when _T_3 :
connect qs_0.io.enq.valid, UInt<1>(0h1)
connect qs_0.io.enq.bits.payload, flit.payload
connect qs_0.io.enq.bits.tail, flit.tail
connect qs_0.io.enq.bits.head, flit.head
node _T_4 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1))
when _T_4 :
connect qs_1.io.enq.valid, UInt<1>(0h1)
connect qs_1.io.enq.bits.payload, flit.payload
connect qs_1.io.enq.bits.tail, flit.tail
connect qs_1.io.enq.bits.head, flit.head
node _T_5 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2))
when _T_5 :
connect qs_2.io.enq.valid, UInt<1>(0h1)
connect qs_2.io.enq.bits.payload, flit.payload
connect qs_2.io.enq.bits.tail, flit.tail
connect qs_2.io.enq.bits.head, flit.head
node _T_6 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h3))
when _T_6 :
connect qs_3.io.enq.valid, UInt<1>(0h1)
connect qs_3.io.enq.bits.payload, flit.payload
connect qs_3.io.enq.bits.tail, flit.tail
connect qs_3.io.enq.bits.head, flit.head
node _T_7 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h4))
when _T_7 :
connect qs_4.io.enq.valid, UInt<1>(0h1)
connect qs_4.io.enq.bits.payload, flit.payload
connect qs_4.io.enq.bits.tail, flit.tail
connect qs_4.io.enq.bits.head, flit.head
node _T_8 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h5))
when _T_8 :
connect qs_5.io.enq.valid, UInt<1>(0h1)
connect qs_5.io.enq.bits.payload, flit.payload
connect qs_5.io.enq.bits.tail, flit.tail
connect qs_5.io.enq.bits.head, flit.head
node _can_to_q_T = eq(empty_0, UInt<1>(0h0))
node can_to_q_0 = and(_can_to_q_T, qs_0.io.enq.ready)
node _can_to_q_T_1 = eq(empty_1, UInt<1>(0h0))
node can_to_q_1 = and(_can_to_q_T_1, qs_1.io.enq.ready)
node _can_to_q_T_2 = eq(empty_2, UInt<1>(0h0))
node can_to_q_2 = and(_can_to_q_T_2, qs_2.io.enq.ready)
node _can_to_q_T_3 = eq(empty_3, UInt<1>(0h0))
node can_to_q_3 = and(_can_to_q_T_3, qs_3.io.enq.ready)
node _can_to_q_T_4 = eq(empty_4, UInt<1>(0h0))
node can_to_q_4 = and(_can_to_q_T_4, qs_4.io.enq.ready)
node _can_to_q_T_5 = eq(empty_5, UInt<1>(0h0))
node can_to_q_5 = and(_can_to_q_T_5, qs_5.io.enq.ready)
node _to_q_oh_enc_T = mux(can_to_q_5, UInt<6>(0h20), UInt<6>(0h0))
node _to_q_oh_enc_T_1 = mux(can_to_q_4, UInt<6>(0h10), _to_q_oh_enc_T)
node _to_q_oh_enc_T_2 = mux(can_to_q_3, UInt<6>(0h8), _to_q_oh_enc_T_1)
node _to_q_oh_enc_T_3 = mux(can_to_q_2, UInt<6>(0h4), _to_q_oh_enc_T_2)
node _to_q_oh_enc_T_4 = mux(can_to_q_1, UInt<6>(0h2), _to_q_oh_enc_T_3)
node to_q_oh_enc = mux(can_to_q_0, UInt<6>(0h1), _to_q_oh_enc_T_4)
node to_q_oh_0 = bits(to_q_oh_enc, 0, 0)
node to_q_oh_1 = bits(to_q_oh_enc, 1, 1)
node to_q_oh_2 = bits(to_q_oh_enc, 2, 2)
node to_q_oh_3 = bits(to_q_oh_enc, 3, 3)
node to_q_oh_4 = bits(to_q_oh_enc, 4, 4)
node to_q_oh_5 = bits(to_q_oh_enc, 5, 5)
node to_q_lo_hi = cat(to_q_oh_2, to_q_oh_1)
node to_q_lo = cat(to_q_lo_hi, to_q_oh_0)
node to_q_hi_hi = cat(to_q_oh_5, to_q_oh_4)
node to_q_hi = cat(to_q_hi_hi, to_q_oh_3)
node _to_q_T = cat(to_q_hi, to_q_lo)
node to_q_hi_1 = bits(_to_q_T, 5, 4)
node to_q_lo_1 = bits(_to_q_T, 3, 0)
node _to_q_T_1 = orr(to_q_hi_1)
node _to_q_T_2 = or(to_q_hi_1, to_q_lo_1)
node to_q_hi_2 = bits(_to_q_T_2, 3, 2)
node to_q_lo_2 = bits(_to_q_T_2, 1, 0)
node _to_q_T_3 = orr(to_q_hi_2)
node _to_q_T_4 = or(to_q_hi_2, to_q_lo_2)
node _to_q_T_5 = bits(_to_q_T_4, 1, 1)
node _to_q_T_6 = cat(_to_q_T_3, _to_q_T_5)
node to_q = cat(_to_q_T_1, _to_q_T_6)
node _T_9 = or(can_to_q_0, can_to_q_1)
node _T_10 = or(_T_9, can_to_q_2)
node _T_11 = or(_T_10, can_to_q_3)
node _T_12 = or(_T_11, can_to_q_4)
node _T_13 = or(_T_12, can_to_q_5)
when _T_13 :
node _head_T = mux(to_q_oh_0, heads[0], UInt<1>(0h0))
node _head_T_1 = mux(to_q_oh_1, heads[1], UInt<1>(0h0))
node _head_T_2 = mux(to_q_oh_2, heads[2], UInt<1>(0h0))
node _head_T_3 = mux(to_q_oh_3, heads[3], UInt<1>(0h0))
node _head_T_4 = mux(to_q_oh_4, heads[4], UInt<1>(0h0))
node _head_T_5 = mux(to_q_oh_5, heads[5], UInt<1>(0h0))
node _head_T_6 = or(_head_T, _head_T_1)
node _head_T_7 = or(_head_T_6, _head_T_2)
node _head_T_8 = or(_head_T_7, _head_T_3)
node _head_T_9 = or(_head_T_8, _head_T_4)
node _head_T_10 = or(_head_T_9, _head_T_5)
wire head : UInt<5>
connect head, _head_T_10
node _heads_T = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_1 = mux(to_q_oh_1, UInt<2>(0h3), UInt<1>(0h0))
node _heads_T_2 = mux(to_q_oh_2, UInt<3>(0h7), UInt<1>(0h0))
node _heads_T_3 = mux(to_q_oh_3, UInt<4>(0hb), UInt<1>(0h0))
node _heads_T_4 = mux(to_q_oh_4, UInt<4>(0hf), UInt<1>(0h0))
node _heads_T_5 = mux(to_q_oh_5, UInt<5>(0h13), UInt<1>(0h0))
node _heads_T_6 = or(_heads_T, _heads_T_1)
node _heads_T_7 = or(_heads_T_6, _heads_T_2)
node _heads_T_8 = or(_heads_T_7, _heads_T_3)
node _heads_T_9 = or(_heads_T_8, _heads_T_4)
node _heads_T_10 = or(_heads_T_9, _heads_T_5)
wire _heads_WIRE_1 : UInt<5>
connect _heads_WIRE_1, _heads_T_10
node _heads_T_11 = eq(head, _heads_WIRE_1)
node _heads_T_12 = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_13 = mux(to_q_oh_1, UInt<1>(0h0), UInt<1>(0h0))
node _heads_T_14 = mux(to_q_oh_2, UInt<3>(0h4), UInt<1>(0h0))
node _heads_T_15 = mux(to_q_oh_3, UInt<4>(0h8), UInt<1>(0h0))
node _heads_T_16 = mux(to_q_oh_4, UInt<4>(0hc), UInt<1>(0h0))
node _heads_T_17 = mux(to_q_oh_5, UInt<5>(0h10), UInt<1>(0h0))
node _heads_T_18 = or(_heads_T_12, _heads_T_13)
node _heads_T_19 = or(_heads_T_18, _heads_T_14)
node _heads_T_20 = or(_heads_T_19, _heads_T_15)
node _heads_T_21 = or(_heads_T_20, _heads_T_16)
node _heads_T_22 = or(_heads_T_21, _heads_T_17)
wire _heads_WIRE_2 : UInt<5>
connect _heads_WIRE_2, _heads_T_22
node _heads_T_23 = add(head, UInt<1>(0h1))
node _heads_T_24 = tail(_heads_T_23, 1)
node _heads_T_25 = mux(_heads_T_11, _heads_WIRE_2, _heads_T_24)
connect heads[to_q], _heads_T_25
when to_q_oh_0 :
connect qs_0.io.enq.valid, UInt<1>(0h1)
read mport qs_0_io_enq_bits_MPORT = mem[head], clock
connect qs_0.io.enq.bits.payload, qs_0_io_enq_bits_MPORT.payload
connect qs_0.io.enq.bits.tail, qs_0_io_enq_bits_MPORT.tail
connect qs_0.io.enq.bits.head, qs_0_io_enq_bits_MPORT.head
when to_q_oh_1 :
connect qs_1.io.enq.valid, UInt<1>(0h1)
read mport qs_1_io_enq_bits_MPORT = mem[head], clock
connect qs_1.io.enq.bits.payload, qs_1_io_enq_bits_MPORT.payload
connect qs_1.io.enq.bits.tail, qs_1_io_enq_bits_MPORT.tail
connect qs_1.io.enq.bits.head, qs_1_io_enq_bits_MPORT.head
when to_q_oh_2 :
connect qs_2.io.enq.valid, UInt<1>(0h1)
read mport qs_2_io_enq_bits_MPORT = mem[head], clock
connect qs_2.io.enq.bits.payload, qs_2_io_enq_bits_MPORT.payload
connect qs_2.io.enq.bits.tail, qs_2_io_enq_bits_MPORT.tail
connect qs_2.io.enq.bits.head, qs_2_io_enq_bits_MPORT.head
when to_q_oh_3 :
connect qs_3.io.enq.valid, UInt<1>(0h1)
read mport qs_3_io_enq_bits_MPORT = mem[head], clock
connect qs_3.io.enq.bits.payload, qs_3_io_enq_bits_MPORT.payload
connect qs_3.io.enq.bits.tail, qs_3_io_enq_bits_MPORT.tail
connect qs_3.io.enq.bits.head, qs_3_io_enq_bits_MPORT.head
when to_q_oh_4 :
connect qs_4.io.enq.valid, UInt<1>(0h1)
read mport qs_4_io_enq_bits_MPORT = mem[head], clock
connect qs_4.io.enq.bits.payload, qs_4_io_enq_bits_MPORT.payload
connect qs_4.io.enq.bits.tail, qs_4_io_enq_bits_MPORT.tail
connect qs_4.io.enq.bits.head, qs_4_io_enq_bits_MPORT.head
when to_q_oh_5 :
connect qs_5.io.enq.valid, UInt<1>(0h1)
read mport qs_5_io_enq_bits_MPORT = mem[head], clock
connect qs_5.io.enq.bits.payload, qs_5_io_enq_bits_MPORT.payload
connect qs_5.io.enq.bits.tail, qs_5_io_enq_bits_MPORT.tail
connect qs_5.io.enq.bits.head, qs_5_io_enq_bits_MPORT.head
connect io.deq[0].bits, qs_0.io.deq.bits
connect io.deq[0].valid, qs_0.io.deq.valid
connect qs_0.io.deq.ready, io.deq[0].ready
connect io.deq[1].bits, qs_1.io.deq.bits
connect io.deq[1].valid, qs_1.io.deq.valid
connect qs_1.io.deq.ready, io.deq[1].ready
connect io.deq[2].bits, qs_2.io.deq.bits
connect io.deq[2].valid, qs_2.io.deq.valid
connect qs_2.io.deq.ready, io.deq[2].ready
connect io.deq[3].bits, qs_3.io.deq.bits
connect io.deq[3].valid, qs_3.io.deq.valid
connect qs_3.io.deq.ready, io.deq[3].ready
connect io.deq[4].bits, qs_4.io.deq.bits
connect io.deq[4].valid, qs_4.io.deq.valid
connect qs_4.io.deq.ready, io.deq[4].ready
connect io.deq[5].bits, qs_5.io.deq.bits
connect io.deq[5].valid, qs_5.io.deq.valid
connect qs_5.io.deq.ready, io.deq[5].ready | module InputBuffer_9( // @[InputUnit.scala:49:7]
input clock, // @[InputUnit.scala:49:7]
input reset, // @[InputUnit.scala:49:7]
input io_enq_0_valid, // @[InputUnit.scala:51:14]
input io_enq_0_bits_head, // @[InputUnit.scala:51:14]
input io_enq_0_bits_tail, // @[InputUnit.scala:51:14]
input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14]
input [2:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14]
output io_deq_0_bits_head, // @[InputUnit.scala:51:14]
output io_deq_0_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_1_ready, // @[InputUnit.scala:51:14]
output io_deq_1_valid, // @[InputUnit.scala:51:14]
output io_deq_1_bits_head, // @[InputUnit.scala:51:14]
output io_deq_1_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_2_ready, // @[InputUnit.scala:51:14]
output io_deq_2_valid, // @[InputUnit.scala:51:14]
output io_deq_2_bits_head, // @[InputUnit.scala:51:14]
output io_deq_2_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_3_ready, // @[InputUnit.scala:51:14]
output io_deq_3_valid, // @[InputUnit.scala:51:14]
output io_deq_3_bits_head, // @[InputUnit.scala:51:14]
output io_deq_3_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_4_ready, // @[InputUnit.scala:51:14]
output io_deq_4_valid, // @[InputUnit.scala:51:14]
output io_deq_4_bits_head, // @[InputUnit.scala:51:14]
output io_deq_4_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_5_ready, // @[InputUnit.scala:51:14]
output io_deq_5_valid, // @[InputUnit.scala:51:14]
output io_deq_5_bits_head, // @[InputUnit.scala:51:14]
output io_deq_5_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_5_bits_payload // @[InputUnit.scala:51:14]
);
wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49]
wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18]
reg [4:0] heads_0; // @[InputUnit.scala:86:24]
reg [4:0] heads_1; // @[InputUnit.scala:86:24]
reg [4:0] heads_2; // @[InputUnit.scala:86:24]
reg [4:0] heads_3; // @[InputUnit.scala:86:24]
reg [4:0] heads_4; // @[InputUnit.scala:86:24]
reg [4:0] heads_5; // @[InputUnit.scala:86:24]
reg [4:0] tails_0; // @[InputUnit.scala:87:24]
reg [4:0] tails_1; // @[InputUnit.scala:87:24]
reg [4:0] tails_2; // @[InputUnit.scala:87:24]
reg [4:0] tails_3; // @[InputUnit.scala:87:24]
reg [4:0] tails_4; // @[InputUnit.scala:87:24]
reg [4:0] tails_5; // @[InputUnit.scala:87:24]
wire _tails_T_18 = io_enq_0_bits_virt_channel_id == 3'h0; // @[Mux.scala:32:36]
wire _tails_T_19 = io_enq_0_bits_virt_channel_id == 3'h1; // @[Mux.scala:32:36]
wire _tails_T_20 = io_enq_0_bits_virt_channel_id == 3'h2; // @[Mux.scala:32:36]
wire _tails_T_21 = io_enq_0_bits_virt_channel_id == 3'h3; // @[Mux.scala:32:36]
wire _tails_T_22 = io_enq_0_bits_virt_channel_id == 3'h4; // @[Mux.scala:32:36]
wire _tails_T_23 = io_enq_0_bits_virt_channel_id == 3'h5; // @[Mux.scala:32:36]
wire direct_to_q = (_tails_T_18 & _qs_0_io_enq_ready | _tails_T_19 & _qs_1_io_enq_ready | _tails_T_20 & _qs_2_io_enq_ready | _tails_T_21 & _qs_3_io_enq_ready | _tails_T_22 & _qs_4_io_enq_ready | _tails_T_23 & _qs_5_io_enq_ready) & (_tails_T_18 & heads_0 == tails_0 | _tails_T_19 & heads_1 == tails_1 | _tails_T_20 & heads_2 == tails_2 | _tails_T_21 & heads_3 == tails_3 | _tails_T_22 & heads_4 == tails_4 | _tails_T_23 & heads_5 == tails_5); // @[Mux.scala:30:73, :32:36]
wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}]
wire [7:0][4:0] _GEN = {{tails_0}, {tails_0}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16]
wire _GEN_0 = io_enq_0_bits_virt_channel_id == 3'h0; // @[InputUnit.scala:103:45]
wire _GEN_1 = io_enq_0_bits_virt_channel_id == 3'h1; // @[InputUnit.scala:103:45]
wire _GEN_2 = io_enq_0_bits_virt_channel_id == 3'h2; // @[InputUnit.scala:103:45]
wire _GEN_3 = io_enq_0_bits_virt_channel_id == 3'h3; // @[InputUnit.scala:103:45]
wire _GEN_4 = io_enq_0_bits_virt_channel_id == 3'h4; // @[InputUnit.scala:103:45]
wire _GEN_5 = io_enq_0_bits_virt_channel_id == 3'h5; // @[InputUnit.scala:103:45]
wire _GEN_6 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34]
wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire [5:0] to_q_oh_enc = can_to_q_0 ? 6'h1 : can_to_q_1 ? 6'h2 : can_to_q_2 ? 6'h4 : can_to_q_3 ? 6'h8 : can_to_q_4 ? 6'h10 : {can_to_q_5, 5'h0}; // @[Mux.scala:50:70]
wire _GEN_7 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3 | can_to_q_4 | can_to_q_5; // @[package.scala:81:59]
wire [4:0] head = (to_q_oh_enc[0] ? heads_0 : 5'h0) | (to_q_oh_enc[1] ? heads_1 : 5'h0) | (to_q_oh_enc[2] ? heads_2 : 5'h0) | (to_q_oh_enc[3] ? heads_3 : 5'h0) | (to_q_oh_enc[4] ? heads_4 : 5'h0) | (to_q_oh_enc[5] ? heads_5 : 5'h0); // @[OneHot.scala:83:30]
wire _GEN_8 = _GEN_7 & to_q_oh_enc[0]; // @[OneHot.scala:83:30]
wire _GEN_9 = _GEN_7 & to_q_oh_enc[1]; // @[OneHot.scala:83:30]
wire _GEN_10 = _GEN_7 & to_q_oh_enc[2]; // @[OneHot.scala:83:30]
wire _GEN_11 = _GEN_7 & to_q_oh_enc[3]; // @[OneHot.scala:83:30]
wire _GEN_12 = _GEN_7 & to_q_oh_enc[4]; // @[OneHot.scala:83:30]
wire _GEN_13 = _GEN_7 & to_q_oh_enc[5]; // @[OneHot.scala:83:30]
wire [4:0] _tails_T_37 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {2{_tails_T_19}}} | {3{_tails_T_20}}} | (_tails_T_21 ? 4'hB : 4'h0) | {4{_tails_T_22}}} | (_tails_T_23 ? 5'h13 : 5'h0)) ? {_tails_T_23, {_tails_T_21, _tails_T_20, 2'h0} | (_tails_T_22 ? 4'hC : 4'h0)} : _GEN[io_enq_0_bits_virt_channel_id] + 5'h1; // @[Mux.scala:30:73, :32:36]
wire [2:0] _to_q_T_2 = {2'h0, to_q_oh_enc[5]} | to_q_oh_enc[3:1]; // @[OneHot.scala:31:18, :32:28]
wire _to_q_T_4 = _to_q_T_2[2] | _to_q_T_2[0]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [2:0] to_q = {|(to_q_oh_enc[5:4]), |(_to_q_T_2[2:1]), _to_q_T_4}; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [4:0] _heads_T_25 = head == ({1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[1]}}} | {3{to_q_oh_enc[2]}}} | (to_q_oh_enc[3] ? 4'hB : 4'h0) | {4{to_q_oh_enc[4]}}} | (to_q_oh_enc[5] ? 5'h13 : 5'h0)) ? {to_q_oh_enc[5], {to_q_oh_enc[3:2], 2'h0} | (to_q_oh_enc[4] ? 4'hC : 4'h0)} : head + 5'h1; // @[OneHot.scala:83:30]
always @(posedge clock) begin // @[InputUnit.scala:49:7]
if (reset) begin // @[InputUnit.scala:49:7]
heads_0 <= 5'h0; // @[InputUnit.scala:86:24]
heads_1 <= 5'h0; // @[InputUnit.scala:86:24]
heads_2 <= 5'h4; // @[InputUnit.scala:86:24]
heads_3 <= 5'h8; // @[InputUnit.scala:86:24]
heads_4 <= 5'hC; // @[InputUnit.scala:86:24]
heads_5 <= 5'h10; // @[InputUnit.scala:86:24]
tails_0 <= 5'h0; // @[InputUnit.scala:87:24]
tails_1 <= 5'h0; // @[InputUnit.scala:87:24]
tails_2 <= 5'h4; // @[InputUnit.scala:87:24]
tails_3 <= 5'h8; // @[InputUnit.scala:87:24]
tails_4 <= 5'hC; // @[InputUnit.scala:87:24]
tails_5 <= 5'h10; // @[InputUnit.scala:87:24]
end
else begin // @[InputUnit.scala:49:7]
if (_GEN_7 & {to_q_oh_enc[5:4], |(_to_q_T_2[2:1]), _to_q_T_4} == 4'h0) // @[OneHot.scala:30:18, :32:{10,14,28}]
heads_0 <= _heads_T_25; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_7 & to_q == 3'h1) // @[OneHot.scala:32:10]
heads_1 <= _heads_T_25; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_7 & to_q == 3'h2) // @[OneHot.scala:32:10]
heads_2 <= _heads_T_25; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_7 & to_q == 3'h3) // @[OneHot.scala:32:10]
heads_3 <= _heads_T_25; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_7 & to_q == 3'h4) // @[OneHot.scala:32:10]
heads_4 <= _heads_T_25; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_7 & to_q == 3'h5) // @[OneHot.scala:32:10]
heads_5 <= _heads_T_25; // @[InputUnit.scala:86:24, :122:27]
if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_0 <= _tails_T_37; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_1 <= _tails_T_37; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_2 <= _tails_T_37; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_3 <= _tails_T_37; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_4 <= _tails_T_37; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_5 <= _tails_T_37; // @[InputUnit.scala:87:24, :103:51]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_24 :
input clock : Clock
input reset : Reset
output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `2` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `1` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `0` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}}
connect io.req.`0`.ready, UInt<1>(0h1)
node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id)
node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node)
node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id)
node _addr_T = cat(addr_hi, addr_lo)
node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T)
wire decoded_plaInput : UInt<14>
node decoded_invInputs = not(decoded_plaInput)
wire decoded_plaOutput : UInt<6>
node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_plaInput, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_plaInput, 12, 12)
node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9)
node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5, decoded_andMatrixOutputs_andMatrixInput_6)
node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_7)
node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo)
node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4)
node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1)
node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2)
node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo)
node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo)
node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T)
node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_plaInput, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_plaInput, 12, 12)
node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_8_1, decoded_andMatrixOutputs_andMatrixInput_9_1)
node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_5_1, decoded_andMatrixOutputs_andMatrixInput_6_1)
node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_7_1)
node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1)
node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1)
node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1)
node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1)
node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1)
node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2)
node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T)
node decoded_orMatrixOutputs_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, _decoded_orMatrixOutputs_T_1)
node decoded_orMatrixOutputs_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, UInt<1>(0h0))
node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo)
node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0)
node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1)
node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2)
node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3)
node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4)
node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5)
node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1)
node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, _decoded_invMatrixOutputs_T)
node decoded_invMatrixOutputs_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4)
node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, _decoded_invMatrixOutputs_T_3)
node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo)
connect decoded_plaOutput, decoded_invMatrixOutputs
connect decoded_plaInput, addr
node _decoded_T = bits(decoded_plaOutput, 3, 0)
node _decoded_T_1 = bits(_decoded_T, 1, 0)
node _decoded_T_2 = bits(_decoded_T_1, 0, 0)
node _decoded_T_3 = bits(_decoded_T_1, 1, 1)
node _decoded_T_4 = cat(_decoded_T_2, _decoded_T_3)
node _decoded_T_5 = bits(_decoded_T, 3, 2)
node _decoded_T_6 = bits(_decoded_T_5, 0, 0)
node _decoded_T_7 = bits(_decoded_T_5, 1, 1)
node _decoded_T_8 = cat(_decoded_T_6, _decoded_T_7)
node _decoded_T_9 = cat(_decoded_T_4, _decoded_T_8)
node _decoded_T_10 = bits(decoded_plaOutput, 5, 4)
node _decoded_T_11 = bits(_decoded_T_10, 0, 0)
node _decoded_T_12 = bits(_decoded_T_10, 1, 1)
node _decoded_T_13 = cat(_decoded_T_11, _decoded_T_12)
node decoded = cat(_decoded_T_9, _decoded_T_13)
node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0)
connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T
node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1)
connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T
node _io_resp_0_vc_sel_1_0_T = bits(decoded, 2, 2)
connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T
node _io_resp_0_vc_sel_1_1_T = bits(decoded, 3, 3)
connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T
node _io_resp_0_vc_sel_2_0_T = bits(decoded, 4, 4)
connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T
node _io_resp_0_vc_sel_2_1_T = bits(decoded, 5, 5)
connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T
connect io.resp.`0`.vc_sel.`3`[0], UInt<1>(0h0)
connect io.req.`1`.ready, UInt<1>(0h1)
node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id)
node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node)
node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id)
node _addr_T_1 = cat(addr_hi_1, addr_lo_1)
node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1)
wire decoded_plaInput_1 : UInt<14>
node decoded_invInputs_1 = not(decoded_plaInput_1)
wire decoded_plaOutput_1 : UInt<6>
node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_0_2_1 = andr(decoded_andMatrixOutputs_andMatrixInput_0_2)
node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_plaInput_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_plaInput_1, 12, 12)
node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2)
node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2)
node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2)
node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2)
node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2)
node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2)
node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2)
node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2)
node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_2)
node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_plaInput_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_plaInput_1, 12, 12)
node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3)
node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3)
node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3)
node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3)
node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3)
node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3)
node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3)
node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3)
node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_3)
node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_2_2)
node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2)
node _decoded_orMatrixOutputs_T_4 = orr(decoded_andMatrixOutputs_0_2_1)
node decoded_orMatrixOutputs_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, _decoded_orMatrixOutputs_T_3)
node decoded_orMatrixOutputs_hi_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_4)
node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, UInt<1>(0h0))
node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1)
node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 0, 0)
node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 1, 1)
node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs_1, 2, 2)
node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 3, 3)
node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 4, 4)
node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 5, 5)
node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7)
node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, _decoded_invMatrixOutputs_T_6)
node decoded_invMatrixOutputs_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10)
node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, _decoded_invMatrixOutputs_T_9)
node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1)
connect decoded_plaOutput_1, decoded_invMatrixOutputs_1
connect decoded_plaInput_1, addr_1
node _decoded_T_14 = bits(decoded_plaOutput_1, 3, 0)
node _decoded_T_15 = bits(_decoded_T_14, 1, 0)
node _decoded_T_16 = bits(_decoded_T_15, 0, 0)
node _decoded_T_17 = bits(_decoded_T_15, 1, 1)
node _decoded_T_18 = cat(_decoded_T_16, _decoded_T_17)
node _decoded_T_19 = bits(_decoded_T_14, 3, 2)
node _decoded_T_20 = bits(_decoded_T_19, 0, 0)
node _decoded_T_21 = bits(_decoded_T_19, 1, 1)
node _decoded_T_22 = cat(_decoded_T_20, _decoded_T_21)
node _decoded_T_23 = cat(_decoded_T_18, _decoded_T_22)
node _decoded_T_24 = bits(decoded_plaOutput_1, 5, 4)
node _decoded_T_25 = bits(_decoded_T_24, 0, 0)
node _decoded_T_26 = bits(_decoded_T_24, 1, 1)
node _decoded_T_27 = cat(_decoded_T_25, _decoded_T_26)
node decoded_1 = cat(_decoded_T_23, _decoded_T_27)
node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0)
connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T
node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1)
connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T
node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 2, 2)
connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T
node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 3, 3)
connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T
node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 4, 4)
connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T
node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 5, 5)
connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T
connect io.resp.`1`.vc_sel.`3`[0], UInt<1>(0h0)
connect io.req.`2`.ready, UInt<1>(0h1)
node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id)
node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node)
node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id)
node _addr_T_2 = cat(addr_hi_2, addr_lo_2)
node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2)
wire decoded_plaInput_2 : UInt<14>
node decoded_invInputs_2 = not(decoded_plaInput_2)
wire decoded_plaOutput_2 : UInt<6>
node _decoded_orMatrixOutputs_T_5 = orr(UInt<1>(0h1))
node decoded_orMatrixOutputs_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_2, _decoded_orMatrixOutputs_T_5)
node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2)
node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_2, 0, 0)
node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_2, 1, 1)
node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_2, 2, 2)
node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_2, 3, 3)
node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_2, 4, 4)
node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_2, 5, 5)
node decoded_invMatrixOutputs_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13)
node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, _decoded_invMatrixOutputs_T_12)
node decoded_invMatrixOutputs_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16)
node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, _decoded_invMatrixOutputs_T_15)
node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2)
connect decoded_plaOutput_2, decoded_invMatrixOutputs_2
connect decoded_plaInput_2, addr_2
node _decoded_T_28 = bits(decoded_plaOutput_2, 3, 0)
node _decoded_T_29 = bits(_decoded_T_28, 1, 0)
node _decoded_T_30 = bits(_decoded_T_29, 0, 0)
node _decoded_T_31 = bits(_decoded_T_29, 1, 1)
node _decoded_T_32 = cat(_decoded_T_30, _decoded_T_31)
node _decoded_T_33 = bits(_decoded_T_28, 3, 2)
node _decoded_T_34 = bits(_decoded_T_33, 0, 0)
node _decoded_T_35 = bits(_decoded_T_33, 1, 1)
node _decoded_T_36 = cat(_decoded_T_34, _decoded_T_35)
node _decoded_T_37 = cat(_decoded_T_32, _decoded_T_36)
node _decoded_T_38 = bits(decoded_plaOutput_2, 5, 4)
node _decoded_T_39 = bits(_decoded_T_38, 0, 0)
node _decoded_T_40 = bits(_decoded_T_38, 1, 1)
node _decoded_T_41 = cat(_decoded_T_39, _decoded_T_40)
node decoded_2 = cat(_decoded_T_37, _decoded_T_41)
node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0)
connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T
node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1)
connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T
node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 2, 2)
connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T
node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 3, 3)
connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T
node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 4, 4)
connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T
node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 5, 5)
connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T
connect io.resp.`2`.vc_sel.`3`[0], UInt<1>(0h0)
extmodule plusarg_reader_50 :
output out : UInt<20>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "noc_util_sample_rate=%d"
parameter WIDTH = 20 | module RouteComputer_24( // @[RouteComputer.scala:29:7]
input io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_1_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_0, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_1 // @[RouteComputer.scala:40:14]
);
wire [11:0] decoded_invInputs = ~{io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [10:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_ingress_node[2:0], io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21]
assign io_resp_1_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_2_1 = |{&{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[9], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_1 = decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29]
assign io_resp_0_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_2_1 = |{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[11], io_req_0_bits_flow_vnet_id}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[11], io_req_0_bits_flow_vnet_id}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_39 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}}
node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero)
node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf)
node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1)
node notNaN_isInfOut = or(io.a.isInf, io.b.isInf)
node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero)
node notNaN_signOut = xor(io.a.sign, io.b.sign)
node _common_sExpOut_T = add(io.a.sExp, io.b.sExp)
node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1)
node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1)
node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100)))
node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1)
node common_sExpOut = asSInt(_common_sExpOut_T_4)
node _common_sigOut_T = mul(io.a.sig, io.b.sig)
node common_sigOut = bits(_common_sigOut_T, 47, 0)
node _io_invalidExc_T = bits(io.a.sig, 22, 22)
node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0))
node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1)
node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22)
node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0))
node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4)
node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc)
connect io.invalidExc, _io_invalidExc_T_7
connect io.rawOut.isInf, notNaN_isInfOut
connect io.rawOut.isZero, notNaN_isZeroOut
connect io.rawOut.sExp, common_sExpOut
node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.sign, notNaN_signOut
connect io.rawOut.sig, common_sigOut | module MulFullRawFN_39( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_19 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
when _T_8 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_10 = or(_T_9, prs1_rebusys_2)
node _T_11 = or(_T_10, prs1_rebusys_3)
node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = or(_T_11, _T_13)
node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_16 = and(_T_14, _T_15)
when _T_16 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_18 = or(_T_17, prs2_wakeups_2)
node _T_19 = or(_T_18, prs2_wakeups_3)
when _T_19 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_21 = or(_T_20, prs2_rebusys_2)
node _T_22 = or(_T_21, prs2_rebusys_3)
node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_24 = neq(_T_23, UInt<1>(0h0))
node _T_25 = or(_T_22, _T_24)
node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_29 = or(_T_28, prs3_wakeups_2)
node _T_30 = or(_T_29, prs3_wakeups_3)
when _T_30 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_32 = and(io.pred_wakeup_port.valid, _T_31)
when _T_32 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h1))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h1))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_33 = eq(io.squash_grant, UInt<1>(0h0))
node _T_34 = and(io.grant, _T_33)
when _T_34 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_35 = and(slot_uop.fu_code[1], slot_uop.fu_code[2])
when _T_35 :
when agen_ready :
node _T_36 = eq(io.squash_grant, UInt<1>(0h0))
node _T_37 = and(io.grant, _T_36)
when _T_37 :
connect next_uop.iw_issued_partial_agen, UInt<1>(0h1)
connect io.iss_uop.fu_code[1], UInt<1>(0h1)
connect io.iss_uop.fu_code[2], UInt<1>(0h0)
else :
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h1)
connect io.iss_uop.fu_code[1], UInt<1>(0h0)
connect io.iss_uop.fu_code[2], UInt<1>(0h1)
connect io.iss_uop.imm_sel, UInt<3>(0h6)
connect io.iss_uop.prs1, slot_uop.prs2
connect io.iss_uop.lrs1_rtype, slot_uop.lrs2_rtype
connect io.iss_uop.iw_p1_bypass_hint, slot_uop.iw_p2_bypass_hint
else :
when slot_uop.fu_code[2] :
connect io.iss_uop.imm_sel, UInt<3>(0h6)
connect io.iss_uop.prs1, slot_uop.prs2
connect io.iss_uop.lrs1_rtype, slot_uop.lrs2_rtype
connect io.iss_uop.iw_p1_bypass_hint, slot_uop.iw_p2_bypass_hint
connect io.iss_uop.lrs2_rtype, UInt<2>(0h2)
connect io.iss_uop.prs2, io.iss_uop.prs1
node _T_40 = and(slot_valid, slot_uop.iw_issued)
when _T_40 :
connect next_valid, rebusied
when slot_uop.iw_issued_partial_agen :
connect next_valid, UInt<1>(0h1)
node _T_41 = eq(rebusied_prs1, UInt<1>(0h0))
when _T_41 :
connect next_uop.fu_code[1], UInt<1>(0h0)
connect next_uop.fu_code[2], UInt<1>(0h1)
else :
when slot_uop.iw_issued_partial_dgen :
connect next_valid, UInt<1>(0h1)
node _T_42 = eq(rebusied_prs2, UInt<1>(0h0))
when _T_42 :
connect next_uop.fu_code[1], UInt<1>(0h1)
connect next_uop.fu_code[2], UInt<1>(0h0) | module IssueSlot_19( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [1:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen_0 = io_in_uop_bits_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen_0 = io_in_uop_bits_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23]
reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_198 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_366
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_198( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_366 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_174 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_191
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_174( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_191 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e5_s11_2 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_2
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e5_s11_2( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_2 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_2 :
input clock : Clock
input reset : Reset
output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<40>, commit_coh : { state : UInt<2>}, lb_read : { offset : UInt<2>}, flip lb_resp : UInt<128>, lb_write : { valid : UInt<1>, bits : { offset : UInt<2>, data : UInt<128>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>}
regreset state : UInt<5>, clock, reset, UInt<5>(0h0)
reg req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 11, 6)
node req_tag = shr(req.addr, 12)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd)
node _T = and(io.mem_grant.ready, io.mem_grant.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 4)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 4)
node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0))
node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_3 = eq(state, UInt<5>(0h0))
node _sec_rdy_T_4 = eq(state, UInt<5>(0hd))
node _sec_rdy_T_5 = eq(state, UInt<5>(0he))
node _sec_rdy_T_6 = eq(state, UInt<5>(0hf))
node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4)
node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5)
node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6)
node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0))
node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10)
inst rpq of BranchKillableQueue_5
connect rpq.clock, clock
connect rpq.reset, reset
connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken
connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect rpq.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect rpq.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect rpq.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect rpq.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect rpq.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect rpq.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect rpq.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect rpq.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect rpq.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect rpq.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect rpq.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect rpq.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect rpq.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect rpq.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect rpq.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect rpq.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect rpq.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect rpq.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect rpq.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect rpq.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect rpq.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect rpq.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect rpq.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect rpq.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect rpq.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect rpq.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect rpq.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect rpq.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect rpq.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect rpq.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect rpq.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect rpq.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect rpq.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect rpq.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect rpq.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect rpq.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect rpq.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect rpq.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect rpq.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect rpq.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect rpq.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect rpq.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect rpq.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect rpq.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect rpq.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect rpq.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect rpq.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect rpq.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect rpq.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect rpq.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect rpq.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect rpq.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect rpq.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect rpq.io.flush, io.exception
node _T_1 = eq(state, UInt<5>(0h0))
node _T_2 = eq(rpq.io.empty, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req.sdq_id
connect rpq.io.enq.bits.way_en, io.req.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req.tag_match
connect rpq.io.enq.bits.is_hella, io.req.is_hella
connect rpq.io.enq.bits.data, io.req.data
connect rpq.io.enq.bits.addr, io.req.addr
connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc
connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc
connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if
connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if
connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if
connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if
connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if
connect rpq.io.enq.bits.uop.fp_typ, io.req.uop.fp_typ
connect rpq.io.enq.bits.uop.fp_rm, io.req.uop.fp_rm
connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val
connect rpq.io.enq.bits.uop.fcn_op, io.req.uop.fcn_op
connect rpq.io.enq.bits.uop.fcn_dw, io.req.uop.fcn_dw
connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en
connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype
connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype
connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype
connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3
connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2
connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1
connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst
connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1
connect rpq.io.enq.bits.uop.csr_cmd, io.req.uop.csr_cmd
connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit
connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique
connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq
connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq
connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed
connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size
connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd
connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause
connect rpq.io.enq.bits.uop.exception, io.req.uop.exception
connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst
connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy
connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy
connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy
connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy
connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred
connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3
connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2
connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1
connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst
connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx
connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx
connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx
connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx
connect rpq.io.enq.bits.uop.fp_ctrl.vec, io.req.uop.fp_ctrl.vec
connect rpq.io.enq.bits.uop.fp_ctrl.wflags, io.req.uop.fp_ctrl.wflags
connect rpq.io.enq.bits.uop.fp_ctrl.sqrt, io.req.uop.fp_ctrl.sqrt
connect rpq.io.enq.bits.uop.fp_ctrl.div, io.req.uop.fp_ctrl.div
connect rpq.io.enq.bits.uop.fp_ctrl.fma, io.req.uop.fp_ctrl.fma
connect rpq.io.enq.bits.uop.fp_ctrl.fastpipe, io.req.uop.fp_ctrl.fastpipe
connect rpq.io.enq.bits.uop.fp_ctrl.toint, io.req.uop.fp_ctrl.toint
connect rpq.io.enq.bits.uop.fp_ctrl.fromint, io.req.uop.fp_ctrl.fromint
connect rpq.io.enq.bits.uop.fp_ctrl.typeTagOut, io.req.uop.fp_ctrl.typeTagOut
connect rpq.io.enq.bits.uop.fp_ctrl.typeTagIn, io.req.uop.fp_ctrl.typeTagIn
connect rpq.io.enq.bits.uop.fp_ctrl.swap23, io.req.uop.fp_ctrl.swap23
connect rpq.io.enq.bits.uop.fp_ctrl.swap12, io.req.uop.fp_ctrl.swap12
connect rpq.io.enq.bits.uop.fp_ctrl.ren3, io.req.uop.fp_ctrl.ren3
connect rpq.io.enq.bits.uop.fp_ctrl.ren2, io.req.uop.fp_ctrl.ren2
connect rpq.io.enq.bits.uop.fp_ctrl.ren1, io.req.uop.fp_ctrl.ren1
connect rpq.io.enq.bits.uop.fp_ctrl.wen, io.req.uop.fp_ctrl.wen
connect rpq.io.enq.bits.uop.fp_ctrl.ldst, io.req.uop.fp_ctrl.ldst
connect rpq.io.enq.bits.uop.op2_sel, io.req.uop.op2_sel
connect rpq.io.enq.bits.uop.op1_sel, io.req.uop.op1_sel
connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed
connect rpq.io.enq.bits.uop.pimm, io.req.uop.pimm
connect rpq.io.enq.bits.uop.imm_sel, io.req.uop.imm_sel
connect rpq.io.enq.bits.uop.imm_rename, io.req.uop.imm_rename
connect rpq.io.enq.bits.uop.taken, io.req.uop.taken
connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob
connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst
connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx
connect rpq.io.enq.bits.uop.is_mov, io.req.uop.is_mov
connect rpq.io.enq.bits.uop.is_rocc, io.req.uop.is_rocc
connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc
connect rpq.io.enq.bits.uop.is_eret, io.req.uop.is_eret
connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo
connect rpq.io.enq.bits.uop.is_sfence, io.req.uop.is_sfence
connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei
connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence
connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb
connect rpq.io.enq.bits.uop.br_type, io.req.uop.br_type
connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag
connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask
connect rpq.io.enq.bits.uop.dis_col_sel, io.req.uop.dis_col_sel
connect rpq.io.enq.bits.uop.iw_p3_bypass_hint, io.req.uop.iw_p3_bypass_hint
connect rpq.io.enq.bits.uop.iw_p2_bypass_hint, io.req.uop.iw_p2_bypass_hint
connect rpq.io.enq.bits.uop.iw_p1_bypass_hint, io.req.uop.iw_p1_bypass_hint
connect rpq.io.enq.bits.uop.iw_p2_speculative_child, io.req.uop.iw_p2_speculative_child
connect rpq.io.enq.bits.uop.iw_p1_speculative_child, io.req.uop.iw_p1_speculative_child
connect rpq.io.enq.bits.uop.iw_issued_partial_dgen, io.req.uop.iw_issued_partial_dgen
connect rpq.io.enq.bits.uop.iw_issued_partial_agen, io.req.uop.iw_issued_partial_agen
connect rpq.io.enq.bits.uop.iw_issued, io.req.uop.iw_issued
connect rpq.io.enq.bits.uop.fu_code[0], io.req.uop.fu_code[0]
connect rpq.io.enq.bits.uop.fu_code[1], io.req.uop.fu_code[1]
connect rpq.io.enq.bits.uop.fu_code[2], io.req.uop.fu_code[2]
connect rpq.io.enq.bits.uop.fu_code[3], io.req.uop.fu_code[3]
connect rpq.io.enq.bits.uop.fu_code[4], io.req.uop.fu_code[4]
connect rpq.io.enq.bits.uop.fu_code[5], io.req.uop.fu_code[5]
connect rpq.io.enq.bits.uop.fu_code[6], io.req.uop.fu_code[6]
connect rpq.io.enq.bits.uop.fu_code[7], io.req.uop.fu_code[7]
connect rpq.io.enq.bits.uop.fu_code[8], io.req.uop.fu_code[8]
connect rpq.io.enq.bits.uop.fu_code[9], io.req.uop.fu_code[9]
connect rpq.io.enq.bits.uop.iq_type[0], io.req.uop.iq_type[0]
connect rpq.io.enq.bits.uop.iq_type[1], io.req.uop.iq_type[1]
connect rpq.io.enq.bits.uop.iq_type[2], io.req.uop.iq_type[2]
connect rpq.io.enq.bits.uop.iq_type[3], io.req.uop.iq_type[3]
connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc
connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc
connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst
connect rpq.io.enq.bits.uop.inst, io.req.uop.inst
connect rpq.io.deq.ready, UInt<1>(0h0)
reg grantack : { valid : UInt<1>, bits : { sink : UInt<4>}}, clock
reg refill_ctr : UInt<2>, clock
reg commit_line : UInt<1>, clock
reg grant_had_data : UInt<1>, clock
reg finish_to_prefetch : UInt<1>, clock
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_8 = neq(meta_hazard, UInt<1>(0h0))
when _T_8 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_9 = and(io.meta_write.ready, io.meta_write.valid)
when _T_9 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0))
node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1))
node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2))
node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3))
node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2)
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4)
node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4))
node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid)
node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_idx_valid_T = neq(state, UInt<5>(0h0))
connect io.idx.valid, _io_idx_valid_T
node _io_tag_valid_T = neq(state, UInt<5>(0h0))
connect io.tag.valid, _io_tag_valid_T
node _io_way_valid_T = eq(state, UInt<5>(0h0))
node _io_way_valid_T_1 = eq(state, UInt<5>(0h11))
node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1)
node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0))
connect io.way.valid, _io_way_valid_T_3
connect io.idx.bits, req_idx
connect io.tag.bits, req_tag
connect io.way.bits, req.way_en
connect io.meta_write.valid, UInt<1>(0h0)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, coh_on_clear
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
connect io.meta_write.bits.tag, req_tag
connect io.req_pri_rdy, UInt<1>(0h0)
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
connect io.mem_acquire.valid, UInt<1>(0h0)
node _io_mem_acquire_bits_T = cat(req_tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000))
node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6)
node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000)))
node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8)
node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000))
node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000)))
node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10)
node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15)
node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17)
node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19)
node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000))
node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21)
node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000)))
node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23)
node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26)
node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28)
node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30)
node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31)
node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, io.id
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 3, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4))
node io_mem_acquire_bits_a_mask_sub_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 3, 3)
node io_mem_acquire_bits_a_mask_sub_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 3, 3)
node io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_sub_4_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_4 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_4_2)
node io_mem_acquire_bits_a_mask_sub_4_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_4)
node io_mem_acquire_bits_a_mask_sub_5_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_5 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_5_2)
node io_mem_acquire_bits_a_mask_sub_5_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_5)
node io_mem_acquire_bits_a_mask_sub_6_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_6 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_6_2)
node io_mem_acquire_bits_a_mask_sub_6_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_6)
node io_mem_acquire_bits_a_mask_sub_7_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_7 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_7_2)
node io_mem_acquire_bits_a_mask_sub_7_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_7)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_eq_8 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_8 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_8)
node io_mem_acquire_bits_a_mask_acc_8 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_8)
node io_mem_acquire_bits_a_mask_eq_9 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_9 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_9)
node io_mem_acquire_bits_a_mask_acc_9 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_9)
node io_mem_acquire_bits_a_mask_eq_10 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_10 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_10)
node io_mem_acquire_bits_a_mask_acc_10 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_10)
node io_mem_acquire_bits_a_mask_eq_11 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_11 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_11)
node io_mem_acquire_bits_a_mask_acc_11 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_11)
node io_mem_acquire_bits_a_mask_eq_12 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_12 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_12)
node io_mem_acquire_bits_a_mask_acc_12 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_12)
node io_mem_acquire_bits_a_mask_eq_13 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_13 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_13)
node io_mem_acquire_bits_a_mask_acc_13 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_13)
node io_mem_acquire_bits_a_mask_eq_14 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_14 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_14)
node io_mem_acquire_bits_a_mask_acc_14 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_14)
node io_mem_acquire_bits_a_mask_eq_15 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_15 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_15)
node io_mem_acquire_bits_a_mask_acc_15 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_15)
node io_mem_acquire_bits_a_mask_lo_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_lo_lo_hi, io_mem_acquire_bits_a_mask_lo_lo_lo)
node io_mem_acquire_bits_a_mask_lo_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_lo_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_lo_hi_hi, io_mem_acquire_bits_a_mask_lo_hi_lo)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_9, io_mem_acquire_bits_a_mask_acc_8)
node io_mem_acquire_bits_a_mask_hi_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_11, io_mem_acquire_bits_a_mask_acc_10)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_hi_lo_hi, io_mem_acquire_bits_a_mask_hi_lo_lo)
node io_mem_acquire_bits_a_mask_hi_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_13, io_mem_acquire_bits_a_mask_acc_12)
node io_mem_acquire_bits_a_mask_hi_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_15, io_mem_acquire_bits_a_mask_acc_14)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_hi_hi_hi, io_mem_acquire_bits_a_mask_hi_hi_lo)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
connect io.refill.valid, UInt<1>(0h0)
node _io_refill_bits_addr_T = shl(refill_ctr, 4)
node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T)
connect io.refill.bits.addr, _io_refill_bits_addr_T_1
connect io.refill.bits.way_en, req.way_en
node _io_refill_bits_wmask_T = not(UInt<2>(0h0))
connect io.refill.bits.wmask, _io_refill_bits_wmask_T
connect io.refill.bits.data, io.lb_resp
connect io.replay.valid, UInt<1>(0h0)
connect io.replay.bits, rpq.io.deq.bits
connect io.wb_req.valid, UInt<1>(0h0)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.source, io.id
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
connect io.resp.valid, UInt<1>(0h0)
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
connect io.resp.bits.data, rpq.io.deq.bits.data
connect io.resp.bits.uop, rpq.io.deq.bits.uop
connect io.commit_val, UInt<1>(0h0)
connect io.commit_addr, req.addr
connect io.commit_coh, coh_on_grant
connect io.meta_read.valid, UInt<1>(0h0)
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
connect io.meta_read.bits.way_en, req.way_en
connect io.mem_finish.valid, UInt<1>(0h0)
connect io.mem_finish.bits, grantack.bits
connect io.lb_write.valid, UInt<1>(0h0)
node _io_lb_write_bits_offset_T = shr(refill_address_inc, 4)
connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T
connect io.lb_write.bits.data, io.mem_grant.bits.data
connect io.mem_grant.ready, UInt<1>(0h0)
node _io_lb_read_offset_T = shr(rpq.io.deq.bits.addr, 4)
connect io.lb_read.offset, _io_lb_read_offset_T
node _T_10 = and(io.req_sec_val, io.req_sec_rdy)
when _T_10 :
connect req.uop.mem_cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_11 = eq(state, UInt<5>(0h0))
when _T_11 :
connect io.req_pri_rdy, UInt<1>(0h1)
connect grant_had_data, UInt<1>(0h0)
node _T_12 = and(io.req_pri_val, io.req_pri_rdy)
when _T_12 :
wire state_new_state : UInt
connect state_new_state, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T = asUInt(reset)
node _state_T_1 = eq(_state_T, UInt<1>(0h0))
when _state_T_1 :
node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert
connect req, io.req
node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1)
node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3)
node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20)
node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21)
node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22)
node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24)
node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25)
node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26)
node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28)
node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29)
node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30)
node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32)
node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33)
node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34)
node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36)
node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37)
node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38)
node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40)
node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41)
node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42)
node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44)
node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45)
node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46)
node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48)
node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49)
node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50)
node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52)
node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53)
node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54)
node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56)
node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57)
node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58)
node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6)
node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60)
node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61)
node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62)
wire state_req_needs_wb_meta : { state : UInt<2>}
connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3
connect req_needs_wb, state_req_needs_wb_r_1
when io.req.tag_match :
node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1)
node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3)
node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6)
node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7)
node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8)
node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13)
node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14)
node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15)
node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16)
node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20)
node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21)
node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24)
node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26)
node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29)
node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30)
node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31)
node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36)
node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37)
node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38)
node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39)
node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43)
node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44)
node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46)
node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48)
node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49)
node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state)
node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3))
node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2))
node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1))
node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3))
node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2))
node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3))
node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2))
node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0))
node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1))
node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0))
node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1))
node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0))
node _state_r_T_25 = eq(_state_r_T_24, _state_r_T)
node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_28 = eq(_state_r_T_22, _state_r_T)
node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26)
node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27)
node _state_r_T_31 = eq(_state_r_T_20, _state_r_T)
node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29)
node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30)
node _state_r_T_34 = eq(_state_r_T_18, _state_r_T)
node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32)
node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33)
node _state_r_T_37 = eq(_state_r_T_16, _state_r_T)
node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35)
node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36)
node _state_r_T_40 = eq(_state_r_T_14, _state_r_T)
node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38)
node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39)
node _state_r_T_43 = eq(_state_r_T_12, _state_r_T)
node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41)
node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42)
node _state_r_T_46 = eq(_state_r_T_10, _state_r_T)
node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44)
node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45)
node _state_r_T_49 = eq(_state_r_T_8, _state_r_T)
node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47)
node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48)
node _state_r_T_52 = eq(_state_r_T_6, _state_r_T)
node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50)
node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51)
node _state_r_T_55 = eq(_state_r_T_4, _state_r_T)
node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53)
node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54)
node _state_r_T_58 = eq(_state_r_T_2, _state_r_T)
node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56)
node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57)
wire state_coh_on_hit : { state : UInt<2>}
connect state_coh_on_hit.state, state_r_2
when state_is_hit :
node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_5 = or(_state_T_3, _state_T_4)
node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_7 = or(_state_T_5, _state_T_6)
node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_12 = or(_state_T_8, _state_T_9)
node _state_T_13 = or(_state_T_12, _state_T_10)
node _state_T_14 = or(_state_T_13, _state_T_11)
node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_20 = or(_state_T_15, _state_T_16)
node _state_T_21 = or(_state_T_20, _state_T_17)
node _state_T_22 = or(_state_T_21, _state_T_18)
node _state_T_23 = or(_state_T_22, _state_T_19)
node _state_T_24 = or(_state_T_14, _state_T_23)
node _state_T_25 = or(_state_T_7, _state_T_24)
node _state_T_26 = asUInt(reset)
node _state_T_27 = eq(_state_T_26, UInt<1>(0h0))
when _state_T_27 :
node _state_T_28 = eq(_state_T_25, UInt<1>(0h0))
when _state_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1
assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1
connect new_coh, state_coh_on_hit
connect state_new_state, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state, UInt<5>(0h1)
else :
wire state_new_coh_meta : { state : UInt<2>}
connect state_new_coh_meta.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta
connect state_new_state, UInt<5>(0h1)
connect state, state_new_state
else :
node _T_13 = eq(state, UInt<5>(0h1))
when _T_13 :
connect io.mem_acquire.valid, UInt<1>(0h1)
node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_14 :
connect state, UInt<5>(0h2)
else :
node _T_15 = eq(state, UInt<5>(0h2))
when _T_15 :
connect io.mem_grant.ready, UInt<1>(0h1)
node opdata = bits(io.mem_grant.bits.opcode, 0, 0)
when opdata :
connect io.lb_write.valid, io.mem_grant.valid
else :
connect io.mem_grant.ready, UInt<1>(0h1)
node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid)
when _T_16 :
node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
connect grant_had_data, grant_had_data_opdata
when refill_done :
node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0))
node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2)
connect grantack.valid, _grantack_valid_T_3
wire grantack_bits_e : { sink : UInt<4>}
connect grantack_bits_e.sink, io.mem_grant.bits.sink
connect grantack.bits, grantack_bits_e
node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc))
connect state, _state_T_29
node _T_17 = eq(grant_had_data, UInt<1>(0h0))
node _T_18 = and(_T_17, req_needs_wb)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:261 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
connect commit_line, UInt<1>(0h0)
connect new_coh, coh_on_grant
else :
node _T_23 = eq(state, UInt<5>(0h3))
when _T_23 :
node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0))
node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10))
node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1)
node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2)
node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3)
node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8)
node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9)
node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10)
node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15)
node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16)
node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17)
node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18)
node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22)
node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23)
node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26)
node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28)
node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31)
node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32)
node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33)
node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38)
node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39)
node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40)
node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41)
node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45)
node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46)
node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0))
node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48)
node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node drain_load = and(_drain_load_T_49, _drain_load_T_50)
node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node rp_addr_hi = cat(req_tag, req_idx)
node rp_addr = cat(rp_addr_hi, _rp_addr_T)
node word_idx = bits(rp_addr, 3, 3)
node _data_word_T = cat(word_idx, UInt<6>(0h0))
node data_word = dshr(io.lb_resp, _data_word_T)
node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0)
node hi = cat(req_tag, req_idx)
node _T_25 = cat(hi, _T_24)
wire size : UInt<2>
connect size, rpq.io.deq.bits.uop.mem_size
node _rpq_io_deq_ready_T = and(io.resp.ready, drain_load)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T
node _io_lb_read_offset_T_1 = shr(rpq.io.deq.bits.addr, 4)
connect io.lb_read.offset, _io_lb_read_offset_T_1
node _io_resp_valid_T = and(rpq.io.deq.valid, drain_load)
connect io.resp.valid, _io_resp_valid_T
node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(data_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid)
when _T_26 :
connect commit_line, UInt<1>(0h1)
else :
node _T_27 = eq(commit_line, UInt<1>(0h0))
node _T_28 = and(rpq.io.empty, _T_27)
when _T_28 :
node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_31 = eq(drain_load, UInt<1>(0h0))
node _T_32 = and(rpq.io.deq.valid, _T_31)
node _T_33 = or(rpq.io.empty, _T_32)
when _T_33 :
connect io.commit_val, UInt<1>(0h1)
connect state, UInt<5>(0h4)
else :
node _T_34 = eq(state, UInt<5>(0h4))
when _T_34 :
node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1)
node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 11, 6)
node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx)
node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4)
connect io.meta_read.valid, _io_meta_read_valid_T_5
node _T_35 = and(io.meta_read.ready, io.meta_read.valid)
when _T_35 :
connect state, UInt<5>(0h5)
else :
node _T_36 = eq(state, UInt<5>(0h5))
when _T_36 :
connect state, UInt<5>(0h6)
else :
node _T_37 = eq(state, UInt<5>(0h6))
when _T_37 :
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0))
node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb))
node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31)
connect state, _state_T_32
else :
node _T_38 = eq(state, UInt<5>(0h7))
when _T_38 :
connect io.meta_write.valid, UInt<1>(0h1)
node _T_39 = and(io.meta_write.ready, io.meta_write.valid)
when _T_39 :
connect state, UInt<5>(0h9)
else :
node _T_40 = eq(state, UInt<5>(0h9))
when _T_40 :
connect io.wb_req.valid, UInt<1>(0h1)
node _T_41 = and(io.wb_req.ready, io.wb_req.valid)
when _T_41 :
connect state, UInt<5>(0ha)
else :
node _T_42 = eq(state, UInt<5>(0ha))
when _T_42 :
when io.wb_resp :
connect state, UInt<5>(0hb)
else :
node _T_43 = eq(state, UInt<5>(0hb))
when _T_43 :
connect io.lb_read.offset, refill_ctr
connect io.refill.valid, UInt<1>(0h1)
node _T_44 = and(io.refill.ready, io.refill.valid)
when _T_44 :
node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1))
node _refill_ctr_T_1 = tail(_refill_ctr_T, 1)
connect refill_ctr, _refill_ctr_T_1
node _T_45 = eq(refill_ctr, UInt<2>(0h3))
when _T_45 :
connect state, UInt<5>(0hc)
else :
node _T_46 = eq(state, UInt<5>(0hc))
when _T_46 :
connect io.replay.bits, rpq.io.deq.bits
connect io.replay.valid, rpq.io.deq.valid
connect rpq.io.deq.ready, io.replay.ready
connect io.replay.bits.way_en, req.way_en
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(req_tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
node _T_47 = and(io.replay.ready, io.replay.valid)
node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _T_52 = or(_T_50, _T_51)
node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _T_57 = or(_T_53, _T_54)
node _T_58 = or(_T_57, _T_55)
node _T_59 = or(_T_58, _T_56)
node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _T_65 = or(_T_60, _T_61)
node _T_66 = or(_T_65, _T_62)
node _T_67 = or(_T_66, _T_63)
node _T_68 = or(_T_67, _T_64)
node _T_69 = or(_T_59, _T_68)
node _T_70 = or(_T_52, _T_69)
node _T_71 = and(_T_47, _T_70)
when _T_71 :
node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, new_coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(is_hit, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:345 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2
assert(clock, is_hit, UInt<1>(0h1), "") : assert_2
connect new_coh, coh_on_hit
node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0))
node _T_76 = and(rpq.io.empty, _T_75)
when _T_76 :
connect state, UInt<5>(0hd)
else :
node _T_77 = eq(state, UInt<5>(0hd))
when _T_77 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, new_coh
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_78 = and(io.meta_write.ready, io.meta_write.valid)
when _T_78 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_79 = eq(state, UInt<5>(0he))
when _T_79 :
connect io.mem_finish.valid, grantack.valid
node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid)
node _T_81 = eq(grantack.valid, UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
when _T_82 :
connect grantack.valid, UInt<1>(0h0)
connect state, UInt<5>(0hf)
else :
node _T_83 = eq(state, UInt<5>(0hf))
when _T_83 :
node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0))
connect state, _state_T_33
else :
node _T_84 = eq(state, UInt<5>(0h11))
when _T_84 :
connect io.req_pri_rdy, UInt<1>(0h1)
node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0))
node _T_86 = and(io.req_sec_val, _T_85)
node _T_87 = or(_T_86, io.clear_prefetch)
when _T_87 :
connect state, UInt<5>(0h0)
else :
node _T_88 = and(io.req_sec_val, io.req_sec_rdy)
when _T_88 :
node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51)
node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53)
node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56)
node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57)
node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58)
node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63)
node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64)
node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65)
node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66)
node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70)
node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71)
node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74)
node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76)
node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79)
node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80)
node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81)
node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86)
node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87)
node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88)
node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89)
node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93)
node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94)
node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96)
node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98)
node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99)
node _r_T_123 = cat(r_c_1, new_coh.state)
node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_125 = cat(_r_T_124, UInt<2>(0h3))
node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_127 = cat(_r_T_126, UInt<2>(0h2))
node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_129 = cat(_r_T_128, UInt<2>(0h1))
node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_131 = cat(_r_T_130, UInt<2>(0h3))
node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_133 = cat(_r_T_132, UInt<2>(0h2))
node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_135 = cat(_r_T_134, UInt<2>(0h3))
node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_137 = cat(_r_T_136, UInt<2>(0h2))
node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_139 = cat(_r_T_138, UInt<2>(0h0))
node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_141 = cat(_r_T_140, UInt<2>(0h1))
node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_143 = cat(_r_T_142, UInt<2>(0h0))
node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_145 = cat(_r_T_144, UInt<2>(0h1))
node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_147 = cat(_r_T_146, UInt<2>(0h0))
node _r_T_148 = eq(_r_T_147, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_151 = eq(_r_T_145, _r_T_123)
node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149)
node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150)
node _r_T_154 = eq(_r_T_143, _r_T_123)
node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152)
node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153)
node _r_T_157 = eq(_r_T_141, _r_T_123)
node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155)
node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156)
node _r_T_160 = eq(_r_T_139, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158)
node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159)
node _r_T_163 = eq(_r_T_137, _r_T_123)
node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161)
node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162)
node _r_T_166 = eq(_r_T_135, _r_T_123)
node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164)
node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165)
node _r_T_169 = eq(_r_T_133, _r_T_123)
node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167)
node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168)
node _r_T_172 = eq(_r_T_131, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170)
node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171)
node _r_T_175 = eq(_r_T_129, _r_T_123)
node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173)
node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174)
node _r_T_178 = eq(_r_T_127, _r_T_123)
node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176)
node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177)
node _r_T_181 = eq(_r_T_125, _r_T_123)
node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179)
node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180)
wire coh_on_hit_1 : { state : UInt<2>}
connect coh_on_hit_1.state, r_2_2
when is_hit_1 :
connect new_coh, coh_on_hit_1
connect state, UInt<5>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
connect state, UInt<5>(0h1)
else :
node _T_89 = and(io.req_pri_val, io.req_pri_rdy)
when _T_89 :
connect grant_had_data, UInt<1>(0h0)
wire state_new_state_1 : UInt
connect state_new_state_1, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T_34 = asUInt(reset)
node _state_T_35 = eq(_state_T_34, UInt<1>(0h0))
when _state_T_35 :
node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf_2
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2
connect req, io.req
node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65)
node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67)
node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84)
node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85)
node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86)
node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88)
node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89)
node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90)
node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92)
node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93)
node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94)
node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96)
node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97)
node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98)
node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100)
node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101)
node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102)
node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104)
node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105)
node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106)
node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108)
node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109)
node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110)
node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112)
node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113)
node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114)
node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116)
node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117)
node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118)
node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120)
node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121)
node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122)
node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70)
node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124)
node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125)
node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126)
wire state_req_needs_wb_meta_1 : { state : UInt<2>}
connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1
connect req_needs_wb, state_req_needs_wb_r_1_1
when io.req.tag_match :
node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51)
node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53)
node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56)
node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57)
node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58)
node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63)
node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64)
node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65)
node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66)
node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70)
node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71)
node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74)
node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76)
node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79)
node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80)
node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81)
node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86)
node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87)
node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88)
node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89)
node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93)
node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94)
node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96)
node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98)
node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99)
node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state)
node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3))
node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2))
node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1))
node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3))
node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2))
node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3))
node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2))
node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0))
node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1))
node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0))
node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1))
node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0))
node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59)
node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59)
node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85)
node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86)
node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59)
node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88)
node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89)
node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59)
node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91)
node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92)
node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59)
node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94)
node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95)
node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59)
node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97)
node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98)
node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59)
node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100)
node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101)
node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59)
node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103)
node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104)
node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59)
node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106)
node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107)
node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59)
node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109)
node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110)
node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59)
node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112)
node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113)
node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59)
node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115)
node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116)
wire state_coh_on_hit_1 : { state : UInt<2>}
connect state_coh_on_hit_1.state, state_r_2_1
when state_is_hit_1 :
node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_39 = or(_state_T_37, _state_T_38)
node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_41 = or(_state_T_39, _state_T_40)
node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_46 = or(_state_T_42, _state_T_43)
node _state_T_47 = or(_state_T_46, _state_T_44)
node _state_T_48 = or(_state_T_47, _state_T_45)
node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_54 = or(_state_T_49, _state_T_50)
node _state_T_55 = or(_state_T_54, _state_T_51)
node _state_T_56 = or(_state_T_55, _state_T_52)
node _state_T_57 = or(_state_T_56, _state_T_53)
node _state_T_58 = or(_state_T_48, _state_T_57)
node _state_T_59 = or(_state_T_41, _state_T_58)
node _state_T_60 = asUInt(reset)
node _state_T_61 = eq(_state_T_60, UInt<1>(0h0))
when _state_T_61 :
node _state_T_62 = eq(_state_T_59, UInt<1>(0h0))
when _state_T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3
assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3
connect new_coh, state_coh_on_hit_1
connect state_new_state_1, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state_1, UInt<5>(0h1)
else :
wire state_new_coh_meta_1 : { state : UInt<2>}
connect state_new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta_1
connect state_new_state_1, UInt<5>(0h1)
connect state, state_new_state_1 | module BoomMSHR_2( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14]
input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iq_type_0, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iq_type_1, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iq_type_2, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iq_type_3, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_0, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_1, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_2, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_3, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_4, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_5, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_6, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_7, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_8, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fu_code_9, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_issued, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[mshrs.scala:39:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_sfence, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_eret, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_rocc, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_mov, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_imm_rename, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[mshrs.scala:39:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fcn_dw, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14]
input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14]
input io_brupdate_b2_taken, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14]
input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14]
input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14]
input io_exception, // @[mshrs.scala:39:14]
input [6:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [6:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input io_req_uop_iq_type_0, // @[mshrs.scala:39:14]
input io_req_uop_iq_type_1, // @[mshrs.scala:39:14]
input io_req_uop_iq_type_2, // @[mshrs.scala:39:14]
input io_req_uop_iq_type_3, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_0, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_1, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_2, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_3, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_4, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_5, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_6, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_7, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_8, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_9, // @[mshrs.scala:39:14]
input io_req_uop_iw_issued, // @[mshrs.scala:39:14]
input io_req_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14]
input io_req_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14]
input io_req_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_dis_col_sel, // @[mshrs.scala:39:14]
input [15:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_type, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_sfence, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_is_eret, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_rocc, // @[mshrs.scala:39:14]
input io_req_uop_is_mov, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input io_req_uop_imm_rename, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_pimm, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_op2_sel, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_wen, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_toint, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_fma, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_div, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_vec, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fcn_dw, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_fcn_op, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_fp_rm, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_fp_typ, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [39:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [7:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [5:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [7:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [27:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [7:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [127:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [19:0] io_meta_write_bits_tag, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [39:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
output [1:0] io_lb_read_offset, // @[mshrs.scala:39:14]
input [127:0] io_lb_resp, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [1:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [127:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iq_type_0, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iq_type_1, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iq_type_2, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iq_type_3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_0, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_1, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_2, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_4, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_5, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_6, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_7, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_8, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_9, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_issued, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_dis_col_sel, // @[mshrs.scala:39:14]
output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_type, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_eret, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rocc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_mov, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output io_replay_bits_uop_imm_rename, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_pimm, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_op2_sel, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fcn_dw, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_fcn_op, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_fp_rm, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_fp_typ, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [7:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_issued, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:39:14]
output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_eret, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rocc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_mov, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output io_resp_bits_uop_imm_rename, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :234:30, :241:40, :246:41, :266:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iq_type_0; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iq_type_1; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iq_type_2; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iq_type_3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_0; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_1; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_2; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_4; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_5; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_6; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_7; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_8; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_9; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_issued; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_dis_col_sel; // @[mshrs.scala:128:19]
wire [15:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_type; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_eret; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rocc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_mov; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_imm_rename; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_pimm; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_op2_sel; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_wen; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_toint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_fma; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_div; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_vec; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fcn_dw; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_fcn_op; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_fp_rm; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_fp_typ; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_data; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire [7:0] _rpq_io_deq_bits_way_en; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[mshrs.scala:36:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7]
wire io_exception_0 = io_exception; // @[mshrs.scala:36:7]
wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire io_req_uop_iq_type_0_0 = io_req_uop_iq_type_0; // @[mshrs.scala:36:7]
wire io_req_uop_iq_type_1_0 = io_req_uop_iq_type_1; // @[mshrs.scala:36:7]
wire io_req_uop_iq_type_2_0 = io_req_uop_iq_type_2; // @[mshrs.scala:36:7]
wire io_req_uop_iq_type_3_0 = io_req_uop_iq_type_3; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_0_0 = io_req_uop_fu_code_0; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_1_0 = io_req_uop_fu_code_1; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_2_0 = io_req_uop_fu_code_2; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_3_0 = io_req_uop_fu_code_3; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_4_0 = io_req_uop_fu_code_4; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_5_0 = io_req_uop_fu_code_5; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_6_0 = io_req_uop_fu_code_6; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_7_0 = io_req_uop_fu_code_7; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_8_0 = io_req_uop_fu_code_8; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_9_0 = io_req_uop_fu_code_9; // @[mshrs.scala:36:7]
wire io_req_uop_iw_issued_0 = io_req_uop_iw_issued; // @[mshrs.scala:36:7]
wire io_req_uop_iw_issued_partial_agen_0 = io_req_uop_iw_issued_partial_agen; // @[mshrs.scala:36:7]
wire io_req_uop_iw_issued_partial_dgen_0 = io_req_uop_iw_issued_partial_dgen; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iw_p1_speculative_child_0 = io_req_uop_iw_p1_speculative_child; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iw_p2_speculative_child_0 = io_req_uop_iw_p2_speculative_child; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_bypass_hint_0 = io_req_uop_iw_p1_bypass_hint; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_bypass_hint_0 = io_req_uop_iw_p2_bypass_hint; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p3_bypass_hint_0 = io_req_uop_iw_p3_bypass_hint; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_dis_col_sel_0 = io_req_uop_dis_col_sel; // @[mshrs.scala:36:7]
wire [15:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_type_0 = io_req_uop_br_type; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfence_0 = io_req_uop_is_sfence; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_is_eret_0 = io_req_uop_is_eret; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_rocc_0 = io_req_uop_is_rocc; // @[mshrs.scala:36:7]
wire io_req_uop_is_mov_0 = io_req_uop_is_mov; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire io_req_uop_imm_rename_0 = io_req_uop_imm_rename; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_imm_sel_0 = io_req_uop_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_pimm_0 = io_req_uop_pimm; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_op1_sel_0 = io_req_uop_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_op2_sel_0 = io_req_uop_op2_sel; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_ldst_0 = io_req_uop_fp_ctrl_ldst; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_wen_0 = io_req_uop_fp_ctrl_wen; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_ren1_0 = io_req_uop_fp_ctrl_ren1; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_ren2_0 = io_req_uop_fp_ctrl_ren2; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_ren3_0 = io_req_uop_fp_ctrl_ren3; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_swap12_0 = io_req_uop_fp_ctrl_swap12; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_swap23_0 = io_req_uop_fp_ctrl_swap23; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_fp_ctrl_typeTagIn_0 = io_req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_fp_ctrl_typeTagOut_0 = io_req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_fromint_0 = io_req_uop_fp_ctrl_fromint; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_toint_0 = io_req_uop_fp_ctrl_toint; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_fastpipe_0 = io_req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_fma_0 = io_req_uop_fp_ctrl_fma; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_div_0 = io_req_uop_fp_ctrl_div; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_sqrt_0 = io_req_uop_fp_ctrl_sqrt; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_wflags_0 = io_req_uop_fp_ctrl_wflags; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_vec_0 = io_req_uop_fp_ctrl_vec; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_csr_cmd_0 = io_req_uop_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fcn_dw_0 = io_req_uop_fcn_dw; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_fcn_op_0 = io_req_uop_fcn_op; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_fp_rm_0 = io_req_uop_fp_rm; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_fp_typ_0 = io_req_uop_fp_typ; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [7:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire [127:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:213:11]
wire _state_T_26 = reset; // @[mshrs.scala:220:15]
wire _state_T_34 = reset; // @[mshrs.scala:213:11]
wire _state_T_60 = reset; // @[mshrs.scala:220:15]
wire [1:0] io_id = 2'h2; // @[mshrs.scala:36:7]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [2:0] io_mem_acquire_bits_source = 3'h2; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_source = 3'h2; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_source = 3'h2; // @[Edges.scala:346:17]
wire [15:0] io_mem_acquire_bits_mask = 16'hFFFF; // @[mshrs.scala:36:7]
wire [15:0] io_mem_acquire_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17]
wire [15:0] _io_mem_acquire_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_mem_acquire_bits_data = 128'h0; // @[mshrs.scala:36:7]
wire [127:0] io_mem_acquire_bits_a_data = 128'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:36:7]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _io_refill_bits_wmask_T = 2'h3; // @[mshrs.scala:174:28]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] io_mem_acquire_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [7:0] io_mem_acquire_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] io_mem_acquire_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:163:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [5:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [27:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [3:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [127:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [127:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [7:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire [19:0] io_meta_write_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [1:0] io_lb_read_offset_0; // @[mshrs.scala:36:7]
wire [1:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_issued_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7]
wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_type_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_eret_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rocc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_mov_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_imm_rename_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_pimm_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_op2_sel_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_fcn_op_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_fp_rm_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_fp_typ_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7]
wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg req_uop_iq_type_0; // @[mshrs.scala:109:20]
reg req_uop_iq_type_1; // @[mshrs.scala:109:20]
reg req_uop_iq_type_2; // @[mshrs.scala:109:20]
reg req_uop_iq_type_3; // @[mshrs.scala:109:20]
reg req_uop_fu_code_0; // @[mshrs.scala:109:20]
reg req_uop_fu_code_1; // @[mshrs.scala:109:20]
reg req_uop_fu_code_2; // @[mshrs.scala:109:20]
reg req_uop_fu_code_3; // @[mshrs.scala:109:20]
reg req_uop_fu_code_4; // @[mshrs.scala:109:20]
reg req_uop_fu_code_5; // @[mshrs.scala:109:20]
reg req_uop_fu_code_6; // @[mshrs.scala:109:20]
reg req_uop_fu_code_7; // @[mshrs.scala:109:20]
reg req_uop_fu_code_8; // @[mshrs.scala:109:20]
reg req_uop_fu_code_9; // @[mshrs.scala:109:20]
reg req_uop_iw_issued; // @[mshrs.scala:109:20]
reg req_uop_iw_issued_partial_agen; // @[mshrs.scala:109:20]
reg req_uop_iw_issued_partial_dgen; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iw_p1_speculative_child; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iw_p2_speculative_child; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_bypass_hint; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_bypass_hint; // @[mshrs.scala:109:20]
reg req_uop_iw_p3_bypass_hint; // @[mshrs.scala:109:20]
reg [2:0] req_uop_dis_col_sel; // @[mshrs.scala:109:20]
reg [15:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_type; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_sfence; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_is_eret; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_rocc; // @[mshrs.scala:109:20]
reg req_uop_is_mov; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg req_uop_imm_rename; // @[mshrs.scala:109:20]
reg [2:0] req_uop_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_pimm; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [1:0] req_uop_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_op2_sel; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_ldst; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_wen; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_ren1; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_ren2; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_ren3; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_swap12; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_swap23; // @[mshrs.scala:109:20]
reg [1:0] req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:109:20]
reg [1:0] req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_fromint; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_toint; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_fma; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_div; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_sqrt; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_wflags; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_vec; // @[mshrs.scala:109:20]
reg [6:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [4:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg [2:0] req_uop_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fcn_dw; // @[mshrs.scala:109:20]
reg [4:0] req_uop_fcn_op; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg [2:0] req_uop_fp_rm; // @[mshrs.scala:109:20]
reg [1:0] req_uop_fp_typ; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [2:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [39:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [7:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34]
wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] r_counter; // @[Edges.scala:229:27]
wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [3:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [1:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign io_meta_write_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31]
assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31]
assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :163:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :163:37]
wire [33:0] _GEN_27 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :168:26]
wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:168:26]
assign _io_mem_acquire_bits_T = _GEN_27; // @[mshrs.scala:168:26]
wire [33:0] rp_addr_hi; // @[mshrs.scala:271:22]
assign rp_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :271:22]
wire [33:0] hi; // @[mshrs.scala:276:10]
assign hi = _GEN_27; // @[mshrs.scala:168:26, :276:10]
wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:341:31]
assign io_replay_bits_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :341:31]
wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:168:{26,45}]
wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42]
wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42]
wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42]
wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_bit = _io_mem_acquire_bits_T_1[3]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = io_mem_acquire_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_4_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_5_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_6_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_7_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_8 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_8 = io_mem_acquire_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_9 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_9 = io_mem_acquire_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_10 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_10 = io_mem_acquire_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_11 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_11 = io_mem_acquire_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_12 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_12 = io_mem_acquire_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_13 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_13 = io_mem_acquire_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_14 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_14 = io_mem_acquire_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_15 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_15 = io_mem_acquire_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 4'h0}; // @[mshrs.scala:139:24, :172:57]
wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :172:{43,57}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :172:{25,43}]
wire [7:0] _io_lb_write_bits_offset_T = refill_address_inc[11:4]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[1:0]; // @[mshrs.scala:36:7, :197:{27,49}]
wire [35:0] _io_lb_read_offset_T = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :200:45]
wire [35:0] _io_lb_read_offset_T_1 = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :200:45, :282:47]
wire [4:0] state_new_state; // @[mshrs.scala:210:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:213:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11]
wire [3:0] _GEN_28 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_28; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_28; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:220:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3; // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :260:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :269:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:267:59, :268:60, :269:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :271:61]
wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:271:{22,61}]
wire word_idx = rp_addr[3]; // @[mshrs.scala:271:22, :272:56]
wire [6:0] _data_word_T = {word_idx, 6'h0}; // @[mshrs.scala:272:56, :274:32]
wire [127:0] data_word = io_lb_resp_0 >> _data_word_T; // @[mshrs.scala:36:7, :274:{26,32}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & drain_load; // @[mshrs.scala:36:7, :268:60, :280:40]
wire _io_resp_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :268:60, :284:43]
wire _GEN_41 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_41 & _io_probe_rdy_T_4 & _io_resp_valid_T; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _GEN_41 | ~_io_probe_rdy_T_4 ? _rpq_io_deq_bits_data : _io_resp_bits_data_T_23; // @[package.scala:16:47]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :290:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :268:60, :296:{31,52,55}]
assign io_commit_val_0 = ~_GEN_41 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :303:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :303:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:303:{27,50,53}]
wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :303:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :303:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:303:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :307:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :309:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :311:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:311:{17,18}, :312:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :313:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :319:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :324:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :328:22]
wire _GEN_42 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :200:21, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:41]
assign io_lb_read_offset_0 = _GEN_41 ? _io_lb_read_offset_T[1:0] : _io_probe_rdy_T_4 ? _io_lb_read_offset_T_1[1:0] : _GEN_42 | ~_T_43 ? _io_lb_read_offset_T[1:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_43 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_42; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_43) & _T_43; // @[package.scala:16:47]
wire [2:0] _refill_ctr_T = {1'h0, refill_ctr} + 3'h1; // @[mshrs.scala:139:24, :333:32]
wire [1:0] _refill_ctr_T_1 = _refill_ctr_T[1:0]; // @[mshrs.scala:333:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :338:22]
wire _GEN_44 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :176:26, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:39]
wire _GEN_45 = _io_probe_rdy_T_4 | _GEN_44; // @[package.scala:16:47]
wire _GEN_46 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~_GEN_46 & _T_46 & _rpq_io_deq_valid; // @[mshrs.scala:36:7, :128:19, :176:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}, :339:15]
assign rpq_io_deq_ready = ~_GEN_41 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T : ~_GEN_44 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire _GEN_47 = _GEN_46 | ~_T_46; // @[mshrs.scala:176:26, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}]
assign io_replay_bits_way_en_0 = _GEN_47 ? _rpq_io_deq_bits_way_en : req_way_en; // @[mshrs.scala:36:7, :109:20, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :341:70]
wire [39:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:341:{31,70}]
assign io_replay_bits_addr_0 = _GEN_47 ? _rpq_io_deq_bits_addr : _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39, :341:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_48 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:{22,39}, :351:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_48 & _sec_rdy_T_4); // @[package.scala:16:47]
wire _GEN_49 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _GEN_48; // @[mshrs.scala:148:129, :156:26, :158:31, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:36, :324:37, :328:41, :338:39, :351:44]
assign io_meta_write_bits_data_coh_state_0 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_49 | ~_sec_rdy_T_4 ? coh_on_clear_state : new_coh_state; // @[package.scala:16:47]
wire _GEN_50 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_50) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :368:17]
wire _GEN_51 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_52 = _T_46 | _GEN_51; // @[mshrs.scala:162:26, :338:{22,39}, :351:44, :361:42, :367:42, :369:38]
wire _GEN_53 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_52; // @[package.scala:16:47]
wire _GEN_54 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_53; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_54 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :371:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:210:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:213:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:220:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to this FIRRTL code module FMADecoder_2 :
input clock : Clock
input reset : Reset
output io : { flip uopc : UInt<7>, cmd : UInt<2>}
wire decoder_decoded_plaInput : UInt<7>
node decoder_decoded_invInputs = not(decoder_decoded_plaInput)
wire decoder_decoded : UInt<2>
node decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoder_decoded_invInputs, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoder_decoded_invInputs, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoder_decoded_invInputs, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoder_decoded_plaInput, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoder_decoded_plaInput, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoder_decoded_invInputs, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5)
node decoder_decoded_andMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6)
node decoder_decoded_andMatrixOutputs_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3)
node decoder_decoded_andMatrixOutputs_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1)
node decoder_decoded_andMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo)
node _decoder_decoded_andMatrixOutputs_T = cat(decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo)
node decoder_decoded_andMatrixOutputs_6_2 = andr(_decoder_decoded_andMatrixOutputs_T)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoder_decoded_plaInput, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoder_decoded_plaInput, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoder_decoded_plaInput, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoder_decoded_invInputs, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_1, decoder_decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoder_decoded_andMatrixOutputs_lo_1 = cat(decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1)
node decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoder_decoded_andMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_1)
node _decoder_decoded_andMatrixOutputs_T_1 = cat(decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1)
node decoder_decoded_andMatrixOutputs_0_2 = andr(_decoder_decoded_andMatrixOutputs_T_1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoder_decoded_plaInput, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoder_decoded_plaInput, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoder_decoded_plaInput, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoder_decoded_invInputs, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2)
node decoder_decoded_andMatrixOutputs_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2)
node decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoder_decoded_andMatrixOutputs_hi_2 = cat(decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2)
node _decoder_decoded_andMatrixOutputs_T_2 = cat(decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2)
node decoder_decoded_andMatrixOutputs_1_2 = andr(_decoder_decoded_andMatrixOutputs_T_2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoder_decoded_plaInput, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoder_decoded_plaInput, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoder_decoded_plaInput, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoder_decoded_plaInput, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoder_decoded_invInputs, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3)
node decoder_decoded_andMatrixOutputs_lo_3 = cat(decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_1)
node decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3)
node decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoder_decoded_andMatrixOutputs_hi_3 = cat(decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_1)
node _decoder_decoded_andMatrixOutputs_T_3 = cat(decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3)
node decoder_decoded_andMatrixOutputs_2_2 = andr(_decoder_decoded_andMatrixOutputs_T_3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoder_decoded_invInputs, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoder_decoded_invInputs, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoder_decoded_invInputs, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoder_decoded_invInputs, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoder_decoded_plaInput, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4)
node decoder_decoded_andMatrixOutputs_lo_4 = cat(decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4)
node decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4)
node decoder_decoded_andMatrixOutputs_hi_4 = cat(decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4)
node _decoder_decoded_andMatrixOutputs_T_4 = cat(decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4)
node decoder_decoded_andMatrixOutputs_4_2 = andr(_decoder_decoded_andMatrixOutputs_T_4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoder_decoded_invInputs, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoder_decoded_invInputs, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoder_decoded_invInputs, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoder_decoded_plaInput, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5)
node decoder_decoded_andMatrixOutputs_lo_5 = cat(decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5)
node decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5)
node decoder_decoded_andMatrixOutputs_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5)
node _decoder_decoded_andMatrixOutputs_T_5 = cat(decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5)
node decoder_decoded_andMatrixOutputs_3_2 = andr(_decoder_decoded_andMatrixOutputs_T_5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoder_decoded_plaInput, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoder_decoded_invInputs, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoder_decoded_invInputs, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoder_decoded_invInputs, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoder_decoded_plaInput, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6)
node decoder_decoded_andMatrixOutputs_lo_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_2)
node decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, decoder_decoded_andMatrixOutputs_andMatrixInput_3_6)
node decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6)
node decoder_decoded_andMatrixOutputs_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_2)
node _decoder_decoded_andMatrixOutputs_T_6 = cat(decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6)
node decoder_decoded_andMatrixOutputs_5_2 = andr(_decoder_decoded_andMatrixOutputs_T_6)
node decoder_decoded_orMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_3_2)
node decoder_decoded_orMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_0_2)
node _decoder_decoded_orMatrixOutputs_T = cat(decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo)
node _decoder_decoded_orMatrixOutputs_T_1 = orr(_decoder_decoded_orMatrixOutputs_T)
node decoder_decoded_orMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_4_2)
node _decoder_decoded_orMatrixOutputs_T_2 = cat(decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_5_2)
node _decoder_decoded_orMatrixOutputs_T_3 = orr(_decoder_decoded_orMatrixOutputs_T_2)
node decoder_decoded_orMatrixOutputs = cat(_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_1)
node _decoder_decoded_invMatrixOutputs_T = bits(decoder_decoded_orMatrixOutputs, 0, 0)
node _decoder_decoded_invMatrixOutputs_T_1 = bits(decoder_decoded_orMatrixOutputs, 1, 1)
node decoder_decoded_invMatrixOutputs = cat(_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T)
connect decoder_decoded, decoder_decoded_invMatrixOutputs
connect decoder_decoded_plaInput, io.uopc
node decoder_0 = bits(decoder_decoded, 1, 0)
connect io.cmd, decoder_0 | module FMADecoder_2( // @[fpu.scala:123:7]
input clock, // @[fpu.scala:123:7]
input reset, // @[fpu.scala:123:7]
input [6:0] io_uopc, // @[fpu.scala:125:14]
output [1:0] io_cmd // @[fpu.scala:125:14]
);
wire [6:0] io_uopc_0 = io_uopc; // @[fpu.scala:123:7]
wire [6:0] decoder_decoded_plaInput = io_uopc_0; // @[pla.scala:77:22]
wire [1:0] decoder_0; // @[Decode.scala:50:77]
wire [1:0] io_cmd_0; // @[fpu.scala:123:7]
wire [6:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [1:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [1:0] decoder_decoded; // @[pla.scala:81:23]
assign decoder_0 = decoder_decoded; // @[pla.scala:81:23]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_6_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_1, decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:90:45, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:90:45, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_1_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_4 = {decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T_5 = {decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_5_2 = &_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _decoder_decoded_orMatrixOutputs_T = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_1 = |_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _decoder_decoded_orMatrixOutputs_T_2 = {decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19]
wire _decoder_decoded_orMatrixOutputs_T_3 = |_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs = {_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
assign decoder_decoded_invMatrixOutputs = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign io_cmd_0 = decoder_0; // @[Decode.scala:50:77]
assign io_cmd = io_cmd_0; // @[fpu.scala:123:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_132 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_132( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit :
input clock : Clock
input reset : Reset
output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<48>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], flip pc : UInt<48>, flip ea : UInt<48>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1]}
connect io.xcpt_if, UInt<1>(0h0)
connect io.xcpt_ld, UInt<1>(0h0)
connect io.xcpt_st, UInt<1>(0h0)
connect io.debug_if, UInt<1>(0h0)
connect io.debug_ld, UInt<1>(0h0)
connect io.debug_st, UInt<1>(0h0)
node _en_T = eq(io.status.debug, UInt<1>(0h0))
node en_lo = cat(io.bp[0].control.s, io.bp[0].control.u)
node en_hi = cat(io.bp[0].control.m, io.bp[0].control.h)
node _en_T_1 = cat(en_hi, en_lo)
node _en_T_2 = dshr(_en_T_1, io.status.prv)
node _en_T_3 = bits(_en_T_2, 0, 0)
node en = and(_en_T, _en_T_3)
node cx = and(UInt<1>(0h1), UInt<1>(0h1))
node _r_T = and(en, io.bp[0].control.r)
node _r_T_1 = bits(io.bp[0].control.tmatch, 1, 1)
node _r_T_2 = geq(io.ea, io.bp[0].address)
node _r_T_3 = bits(io.bp[0].control.tmatch, 0, 0)
node _r_T_4 = xor(_r_T_2, _r_T_3)
node _r_T_5 = not(io.ea)
node _r_T_6 = bits(io.bp[0].control.tmatch, 0, 0)
node _r_T_7 = bits(io.bp[0].address, 0, 0)
node _r_T_8 = and(_r_T_6, _r_T_7)
node _r_T_9 = bits(io.bp[0].address, 1, 1)
node _r_T_10 = and(_r_T_8, _r_T_9)
node _r_T_11 = bits(io.bp[0].address, 2, 2)
node _r_T_12 = and(_r_T_10, _r_T_11)
node r_lo = cat(_r_T_8, _r_T_6)
node r_hi = cat(_r_T_12, _r_T_10)
node _r_T_13 = cat(r_hi, r_lo)
node _r_T_14 = or(_r_T_5, _r_T_13)
node _r_T_15 = not(io.bp[0].address)
node _r_T_16 = bits(io.bp[0].control.tmatch, 0, 0)
node _r_T_17 = bits(io.bp[0].address, 0, 0)
node _r_T_18 = and(_r_T_16, _r_T_17)
node _r_T_19 = bits(io.bp[0].address, 1, 1)
node _r_T_20 = and(_r_T_18, _r_T_19)
node _r_T_21 = bits(io.bp[0].address, 2, 2)
node _r_T_22 = and(_r_T_20, _r_T_21)
node r_lo_1 = cat(_r_T_18, _r_T_16)
node r_hi_1 = cat(_r_T_22, _r_T_20)
node _r_T_23 = cat(r_hi_1, r_lo_1)
node _r_T_24 = or(_r_T_15, _r_T_23)
node _r_T_25 = eq(_r_T_14, _r_T_24)
node _r_T_26 = mux(_r_T_1, _r_T_4, _r_T_25)
node _r_T_27 = and(_r_T, _r_T_26)
node r = and(_r_T_27, cx)
node _w_T = and(en, io.bp[0].control.w)
node _w_T_1 = bits(io.bp[0].control.tmatch, 1, 1)
node _w_T_2 = geq(io.ea, io.bp[0].address)
node _w_T_3 = bits(io.bp[0].control.tmatch, 0, 0)
node _w_T_4 = xor(_w_T_2, _w_T_3)
node _w_T_5 = not(io.ea)
node _w_T_6 = bits(io.bp[0].control.tmatch, 0, 0)
node _w_T_7 = bits(io.bp[0].address, 0, 0)
node _w_T_8 = and(_w_T_6, _w_T_7)
node _w_T_9 = bits(io.bp[0].address, 1, 1)
node _w_T_10 = and(_w_T_8, _w_T_9)
node _w_T_11 = bits(io.bp[0].address, 2, 2)
node _w_T_12 = and(_w_T_10, _w_T_11)
node w_lo = cat(_w_T_8, _w_T_6)
node w_hi = cat(_w_T_12, _w_T_10)
node _w_T_13 = cat(w_hi, w_lo)
node _w_T_14 = or(_w_T_5, _w_T_13)
node _w_T_15 = not(io.bp[0].address)
node _w_T_16 = bits(io.bp[0].control.tmatch, 0, 0)
node _w_T_17 = bits(io.bp[0].address, 0, 0)
node _w_T_18 = and(_w_T_16, _w_T_17)
node _w_T_19 = bits(io.bp[0].address, 1, 1)
node _w_T_20 = and(_w_T_18, _w_T_19)
node _w_T_21 = bits(io.bp[0].address, 2, 2)
node _w_T_22 = and(_w_T_20, _w_T_21)
node w_lo_1 = cat(_w_T_18, _w_T_16)
node w_hi_1 = cat(_w_T_22, _w_T_20)
node _w_T_23 = cat(w_hi_1, w_lo_1)
node _w_T_24 = or(_w_T_15, _w_T_23)
node _w_T_25 = eq(_w_T_14, _w_T_24)
node _w_T_26 = mux(_w_T_1, _w_T_4, _w_T_25)
node _w_T_27 = and(_w_T, _w_T_26)
node w = and(_w_T_27, cx)
node _x_T = and(en, io.bp[0].control.x)
node _x_T_1 = bits(io.bp[0].control.tmatch, 1, 1)
node _x_T_2 = geq(io.pc, io.bp[0].address)
node _x_T_3 = bits(io.bp[0].control.tmatch, 0, 0)
node _x_T_4 = xor(_x_T_2, _x_T_3)
node _x_T_5 = not(io.pc)
node _x_T_6 = bits(io.bp[0].control.tmatch, 0, 0)
node _x_T_7 = bits(io.bp[0].address, 0, 0)
node _x_T_8 = and(_x_T_6, _x_T_7)
node _x_T_9 = bits(io.bp[0].address, 1, 1)
node _x_T_10 = and(_x_T_8, _x_T_9)
node _x_T_11 = bits(io.bp[0].address, 2, 2)
node _x_T_12 = and(_x_T_10, _x_T_11)
node x_lo = cat(_x_T_8, _x_T_6)
node x_hi = cat(_x_T_12, _x_T_10)
node _x_T_13 = cat(x_hi, x_lo)
node _x_T_14 = or(_x_T_5, _x_T_13)
node _x_T_15 = not(io.bp[0].address)
node _x_T_16 = bits(io.bp[0].control.tmatch, 0, 0)
node _x_T_17 = bits(io.bp[0].address, 0, 0)
node _x_T_18 = and(_x_T_16, _x_T_17)
node _x_T_19 = bits(io.bp[0].address, 1, 1)
node _x_T_20 = and(_x_T_18, _x_T_19)
node _x_T_21 = bits(io.bp[0].address, 2, 2)
node _x_T_22 = and(_x_T_20, _x_T_21)
node x_lo_1 = cat(_x_T_18, _x_T_16)
node x_hi_1 = cat(_x_T_22, _x_T_20)
node _x_T_23 = cat(x_hi_1, x_lo_1)
node _x_T_24 = or(_x_T_15, _x_T_23)
node _x_T_25 = eq(_x_T_14, _x_T_24)
node _x_T_26 = mux(_x_T_1, _x_T_4, _x_T_25)
node _x_T_27 = and(_x_T, _x_T_26)
node x = and(_x_T_27, cx)
node end = eq(io.bp[0].control.chain, UInt<1>(0h0))
connect io.bpwatch[0].action, io.bp[0].control.action
connect io.bpwatch[0].valid[0], UInt<1>(0h0)
connect io.bpwatch[0].rvalid[0], UInt<1>(0h0)
connect io.bpwatch[0].wvalid[0], UInt<1>(0h0)
connect io.bpwatch[0].ivalid[0], UInt<1>(0h0)
node _T = and(end, r)
node _T_1 = and(_T, UInt<1>(0h1))
when _T_1 :
node _io_xcpt_ld_T = eq(io.bp[0].control.action, UInt<1>(0h0))
connect io.xcpt_ld, _io_xcpt_ld_T
node _io_debug_ld_T = eq(io.bp[0].control.action, UInt<1>(0h1))
connect io.debug_ld, _io_debug_ld_T
connect io.bpwatch[0].valid[0], UInt<1>(0h1)
connect io.bpwatch[0].rvalid[0], UInt<1>(0h1)
node _T_2 = and(end, w)
node _T_3 = and(_T_2, UInt<1>(0h1))
when _T_3 :
node _io_xcpt_st_T = eq(io.bp[0].control.action, UInt<1>(0h0))
connect io.xcpt_st, _io_xcpt_st_T
node _io_debug_st_T = eq(io.bp[0].control.action, UInt<1>(0h1))
connect io.debug_st, _io_debug_st_T
connect io.bpwatch[0].valid[0], UInt<1>(0h1)
connect io.bpwatch[0].wvalid[0], UInt<1>(0h1)
node _T_4 = and(end, x)
node _T_5 = and(_T_4, UInt<1>(0h1))
when _T_5 :
node _io_xcpt_if_T = eq(io.bp[0].control.action, UInt<1>(0h0))
connect io.xcpt_if, _io_xcpt_if_T
node _io_debug_if_T = eq(io.bp[0].control.action, UInt<1>(0h1))
connect io.debug_if, _io_debug_if_T
connect io.bpwatch[0].valid[0], UInt<1>(0h1)
connect io.bpwatch[0].ivalid[0], UInt<1>(0h1)
node _T_6 = or(end, r)
node _T_7 = or(end, w)
node _T_8 = or(end, x) | module BreakpointUnit( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [31:0] io_status_isa, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input io_bp_0_control_dmode, // @[Breakpoint.scala:80:14]
input io_bp_0_control_action, // @[Breakpoint.scala:80:14]
input [1:0] io_bp_0_control_tmatch, // @[Breakpoint.scala:80:14]
input io_bp_0_control_m, // @[Breakpoint.scala:80:14]
input io_bp_0_control_s, // @[Breakpoint.scala:80:14]
input io_bp_0_control_u, // @[Breakpoint.scala:80:14]
input io_bp_0_control_x, // @[Breakpoint.scala:80:14]
input io_bp_0_control_w, // @[Breakpoint.scala:80:14]
input io_bp_0_control_r, // @[Breakpoint.scala:80:14]
input [47:0] io_bp_0_address, // @[Breakpoint.scala:80:14]
input [47:0] io_bp_0_textra_pad2, // @[Breakpoint.scala:80:14]
input io_bp_0_textra_pad1, // @[Breakpoint.scala:80:14]
input [47:0] io_pc, // @[Breakpoint.scala:80:14]
input [47:0] io_ea, // @[Breakpoint.scala:80:14]
output io_xcpt_if, // @[Breakpoint.scala:80:14]
output io_xcpt_ld, // @[Breakpoint.scala:80:14]
output io_xcpt_st, // @[Breakpoint.scala:80:14]
output io_debug_if, // @[Breakpoint.scala:80:14]
output io_debug_ld, // @[Breakpoint.scala:80:14]
output io_debug_st, // @[Breakpoint.scala:80:14]
output io_bpwatch_0_rvalid_0, // @[Breakpoint.scala:80:14]
output io_bpwatch_0_wvalid_0, // @[Breakpoint.scala:80:14]
output io_bpwatch_0_ivalid_0 // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [31:0] io_status_isa_0 = io_status_isa; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_dmode_0 = io_bp_0_control_dmode; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_action_0 = io_bp_0_control_action; // @[Breakpoint.scala:79:7]
wire [1:0] io_bp_0_control_tmatch_0 = io_bp_0_control_tmatch; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_m_0 = io_bp_0_control_m; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_s_0 = io_bp_0_control_s; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_u_0 = io_bp_0_control_u; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_x_0 = io_bp_0_control_x; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_w_0 = io_bp_0_control_w; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_r_0 = io_bp_0_control_r; // @[Breakpoint.scala:79:7]
wire [47:0] io_bp_0_address_0 = io_bp_0_address; // @[Breakpoint.scala:79:7]
wire [47:0] io_bp_0_textra_pad2_0 = io_bp_0_textra_pad2; // @[Breakpoint.scala:79:7]
wire io_bp_0_textra_pad1_0 = io_bp_0_textra_pad1; // @[Breakpoint.scala:79:7]
wire [47:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [47:0] io_ea_0 = io_ea; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire cx = 1'h1; // @[Breakpoint.scala:55:126]
wire end_0 = 1'h1; // @[Breakpoint.scala:109:15]
wire [39:0] io_bp_0_control_reserved = 40'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[Breakpoint.scala:79:7, :80:14]
wire [3:0] io_bp_0_control_ttype = 4'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_bp_0_control_zero = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_chain = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_h = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_textra_mselect = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_textra_sselect = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire _io_debug_ld_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:84]
wire _io_debug_st_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :119:84]
wire _io_debug_if_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :120:84]
wire r; // @[Breakpoint.scala:106:58]
wire w; // @[Breakpoint.scala:107:58]
wire x; // @[Breakpoint.scala:108:58]
wire io_bpwatch_0_valid_0; // @[Breakpoint.scala:79:7]
wire io_bpwatch_0_rvalid_0_0; // @[Breakpoint.scala:79:7]
wire io_bpwatch_0_wvalid_0_0; // @[Breakpoint.scala:79:7]
wire io_bpwatch_0_ivalid_0_0; // @[Breakpoint.scala:79:7]
wire [2:0] io_bpwatch_0_action; // @[Breakpoint.scala:79:7]
wire io_xcpt_if_0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld_0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st_0; // @[Breakpoint.scala:79:7]
wire io_debug_if_0; // @[Breakpoint.scala:79:7]
wire io_debug_ld_0; // @[Breakpoint.scala:79:7]
wire io_debug_st_0; // @[Breakpoint.scala:79:7]
wire _en_T = ~io_status_debug_0; // @[Breakpoint.scala:30:35, :79:7]
wire [1:0] en_lo = {io_bp_0_control_s_0, io_bp_0_control_u_0}; // @[Breakpoint.scala:30:56, :79:7]
wire [1:0] en_hi = {io_bp_0_control_m_0, 1'h0}; // @[Breakpoint.scala:30:56, :79:7]
wire [3:0] _en_T_1 = {en_hi, en_lo}; // @[Breakpoint.scala:30:56]
wire [3:0] _en_T_2 = _en_T_1 >> io_status_prv_0; // @[Breakpoint.scala:30:{56,68}, :79:7]
wire _en_T_3 = _en_T_2[0]; // @[Breakpoint.scala:30:68]
wire en = _en_T & _en_T_3; // @[Breakpoint.scala:30:{35,50,68}]
wire _r_T = en & io_bp_0_control_r_0; // @[Breakpoint.scala:30:50, :79:7, :106:16]
wire _r_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7]
wire _w_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7]
wire _x_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7]
wire _GEN = io_ea_0 >= io_bp_0_address_0; // @[Breakpoint.scala:65:8, :79:7]
wire _r_T_2; // @[Breakpoint.scala:65:8]
assign _r_T_2 = _GEN; // @[Breakpoint.scala:65:8]
wire _w_T_2; // @[Breakpoint.scala:65:8]
assign _w_T_2 = _GEN; // @[Breakpoint.scala:65:8]
wire _r_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7]
wire _r_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _r_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _w_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7]
wire _w_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _w_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _x_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7]
wire _x_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _x_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _r_T_4 = _r_T_2 ^ _r_T_3; // @[Breakpoint.scala:65:{8,20,36}]
wire [47:0] _r_T_5 = ~io_ea_0; // @[Breakpoint.scala:62:6, :79:7]
wire _r_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_8 = _r_T_6 & _r_T_7; // @[Breakpoint.scala:59:{56,73,83}]
wire _r_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_10 = _r_T_8 & _r_T_9; // @[Breakpoint.scala:59:{73,83}]
wire _r_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_12 = _r_T_10 & _r_T_11; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] r_lo = {_r_T_8, _r_T_6}; // @[package.scala:45:27]
wire [1:0] r_hi = {_r_T_12, _r_T_10}; // @[package.scala:45:27]
wire [3:0] _r_T_13 = {r_hi, r_lo}; // @[package.scala:45:27]
wire [47:0] _r_T_14 = {_r_T_5[47:4], _r_T_5[3:0] | _r_T_13}; // @[package.scala:45:27]
wire [47:0] _r_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7]
wire _r_T_18 = _r_T_16 & _r_T_17; // @[Breakpoint.scala:59:{56,73,83}]
wire _r_T_20 = _r_T_18 & _r_T_19; // @[Breakpoint.scala:59:{73,83}]
wire _r_T_22 = _r_T_20 & _r_T_21; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] r_lo_1 = {_r_T_18, _r_T_16}; // @[package.scala:45:27]
wire [1:0] r_hi_1 = {_r_T_22, _r_T_20}; // @[package.scala:45:27]
wire [3:0] _r_T_23 = {r_hi_1, r_lo_1}; // @[package.scala:45:27]
wire [47:0] _r_T_24 = {_r_T_15[47:4], _r_T_15[3:0] | _r_T_23}; // @[package.scala:45:27]
wire _r_T_25 = _r_T_14 == _r_T_24; // @[Breakpoint.scala:62:{9,19,33}]
wire _r_T_26 = _r_T_1 ? _r_T_4 : _r_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}]
wire _r_T_27 = _r_T & _r_T_26; // @[Breakpoint.scala:68:8, :106:{16,32}]
assign r = _r_T_27; // @[Breakpoint.scala:106:{32,58}]
assign io_bpwatch_0_rvalid_0_0 = r; // @[Breakpoint.scala:79:7, :106:58]
wire _w_T = en & io_bp_0_control_w_0; // @[Breakpoint.scala:30:50, :79:7, :107:16]
wire _w_T_4 = _w_T_2 ^ _w_T_3; // @[Breakpoint.scala:65:{8,20,36}]
wire [47:0] _w_T_5 = ~io_ea_0; // @[Breakpoint.scala:62:6, :79:7]
wire _w_T_8 = _w_T_6 & _w_T_7; // @[Breakpoint.scala:59:{56,73,83}]
wire _w_T_10 = _w_T_8 & _w_T_9; // @[Breakpoint.scala:59:{73,83}]
wire _w_T_12 = _w_T_10 & _w_T_11; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] w_lo = {_w_T_8, _w_T_6}; // @[package.scala:45:27]
wire [1:0] w_hi = {_w_T_12, _w_T_10}; // @[package.scala:45:27]
wire [3:0] _w_T_13 = {w_hi, w_lo}; // @[package.scala:45:27]
wire [47:0] _w_T_14 = {_w_T_5[47:4], _w_T_5[3:0] | _w_T_13}; // @[package.scala:45:27]
wire [47:0] _w_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7]
wire _w_T_18 = _w_T_16 & _w_T_17; // @[Breakpoint.scala:59:{56,73,83}]
wire _w_T_20 = _w_T_18 & _w_T_19; // @[Breakpoint.scala:59:{73,83}]
wire _w_T_22 = _w_T_20 & _w_T_21; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] w_lo_1 = {_w_T_18, _w_T_16}; // @[package.scala:45:27]
wire [1:0] w_hi_1 = {_w_T_22, _w_T_20}; // @[package.scala:45:27]
wire [3:0] _w_T_23 = {w_hi_1, w_lo_1}; // @[package.scala:45:27]
wire [47:0] _w_T_24 = {_w_T_15[47:4], _w_T_15[3:0] | _w_T_23}; // @[package.scala:45:27]
wire _w_T_25 = _w_T_14 == _w_T_24; // @[Breakpoint.scala:62:{9,19,33}]
wire _w_T_26 = _w_T_1 ? _w_T_4 : _w_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}]
wire _w_T_27 = _w_T & _w_T_26; // @[Breakpoint.scala:68:8, :107:{16,32}]
assign w = _w_T_27; // @[Breakpoint.scala:107:{32,58}]
assign io_bpwatch_0_wvalid_0_0 = w; // @[Breakpoint.scala:79:7, :107:58]
wire _x_T = en & io_bp_0_control_x_0; // @[Breakpoint.scala:30:50, :79:7, :108:16]
wire _x_T_2 = io_pc_0 >= io_bp_0_address_0; // @[Breakpoint.scala:65:8, :79:7]
wire _x_T_4 = _x_T_2 ^ _x_T_3; // @[Breakpoint.scala:65:{8,20,36}]
wire [47:0] _x_T_5 = ~io_pc_0; // @[Breakpoint.scala:62:6, :79:7]
wire _x_T_8 = _x_T_6 & _x_T_7; // @[Breakpoint.scala:59:{56,73,83}]
wire _x_T_10 = _x_T_8 & _x_T_9; // @[Breakpoint.scala:59:{73,83}]
wire _x_T_12 = _x_T_10 & _x_T_11; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] x_lo = {_x_T_8, _x_T_6}; // @[package.scala:45:27]
wire [1:0] x_hi = {_x_T_12, _x_T_10}; // @[package.scala:45:27]
wire [3:0] _x_T_13 = {x_hi, x_lo}; // @[package.scala:45:27]
wire [47:0] _x_T_14 = {_x_T_5[47:4], _x_T_5[3:0] | _x_T_13}; // @[package.scala:45:27]
wire [47:0] _x_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7]
wire _x_T_18 = _x_T_16 & _x_T_17; // @[Breakpoint.scala:59:{56,73,83}]
wire _x_T_20 = _x_T_18 & _x_T_19; // @[Breakpoint.scala:59:{73,83}]
wire _x_T_22 = _x_T_20 & _x_T_21; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] x_lo_1 = {_x_T_18, _x_T_16}; // @[package.scala:45:27]
wire [1:0] x_hi_1 = {_x_T_22, _x_T_20}; // @[package.scala:45:27]
wire [3:0] _x_T_23 = {x_hi_1, x_lo_1}; // @[package.scala:45:27]
wire [47:0] _x_T_24 = {_x_T_15[47:4], _x_T_15[3:0] | _x_T_23}; // @[package.scala:45:27]
wire _x_T_25 = _x_T_14 == _x_T_24; // @[Breakpoint.scala:62:{9,19,33}]
wire _x_T_26 = _x_T_1 ? _x_T_4 : _x_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}]
wire _x_T_27 = _x_T & _x_T_26; // @[Breakpoint.scala:68:8, :108:{16,32}]
assign x = _x_T_27; // @[Breakpoint.scala:108:{32,58}]
assign io_bpwatch_0_ivalid_0_0 = x; // @[Breakpoint.scala:79:7, :108:58]
assign io_bpwatch_0_action = {2'h0, io_bp_0_control_action_0}; // @[Breakpoint.scala:79:7, :80:14, :112:16]
wire _io_xcpt_ld_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51]
assign io_xcpt_ld_0 = r & _io_xcpt_ld_T; // @[Breakpoint.scala:79:7, :97:14, :106:58, :118:{27,40,51}]
assign io_debug_ld_0 = r & _io_debug_ld_T; // @[Breakpoint.scala:79:7, :100:15, :106:58, :118:{27,73,84}]
wire _io_xcpt_st_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51, :119:51]
assign io_xcpt_st_0 = w & _io_xcpt_st_T; // @[Breakpoint.scala:79:7, :98:14, :107:58, :119:{27,40,51}]
assign io_debug_st_0 = w & _io_debug_st_T; // @[Breakpoint.scala:79:7, :101:15, :107:58, :119:{27,73,84}]
wire _io_xcpt_if_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51, :120:51]
assign io_xcpt_if_0 = x & _io_xcpt_if_T; // @[Breakpoint.scala:79:7, :96:14, :108:58, :120:{27,40,51}]
assign io_debug_if_0 = x & _io_debug_if_T; // @[Breakpoint.scala:79:7, :99:15, :108:58, :120:{27,73,84}]
assign io_bpwatch_0_valid_0 = x | w | r; // @[Breakpoint.scala:79:7, :106:58, :107:58, :108:58, :118:27, :119:{27,107}, :120:{27,107}]
assign io_xcpt_if = io_xcpt_if_0; // @[Breakpoint.scala:79:7]
assign io_xcpt_ld = io_xcpt_ld_0; // @[Breakpoint.scala:79:7]
assign io_xcpt_st = io_xcpt_st_0; // @[Breakpoint.scala:79:7]
assign io_debug_if = io_debug_if_0; // @[Breakpoint.scala:79:7]
assign io_debug_ld = io_debug_ld_0; // @[Breakpoint.scala:79:7]
assign io_debug_st = io_debug_st_0; // @[Breakpoint.scala:79:7]
assign io_bpwatch_0_rvalid_0 = io_bpwatch_0_rvalid_0_0; // @[Breakpoint.scala:79:7]
assign io_bpwatch_0_wvalid_0 = io_bpwatch_0_wvalid_0_0; // @[Breakpoint.scala:79:7]
assign io_bpwatch_0_ivalid_0 = io_bpwatch_0_ivalid_0_0; // @[Breakpoint.scala:79:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_198 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_198( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_8 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_8( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_231 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_231( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DecoupledSerialPhy_1 :
output io : { flip outer_clock : Clock, flip outer_reset : UInt<1>, flip inner_clock : Clock, flip inner_reset : UInt<1>, outer_ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}}, flip inner_ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5]}
inst out_phits_out_async of AsyncQueue_10
connect out_phits_out_async.io.enq_clock, io.inner_clock
connect out_phits_out_async.io.enq_reset, io.inner_reset
connect out_phits_out_async.io.deq_clock, io.outer_clock
connect out_phits_out_async.io.deq_reset, io.outer_reset
inst out_phits_out_async_io_enq_q of Queue8_Flit_10
connect out_phits_out_async_io_enq_q.clock, io.inner_clock
connect out_phits_out_async_io_enq_q.reset, io.inner_reset
connect out_phits_out_async_io_enq_q.io.enq.valid, io.inner_ser[0].out.valid
connect out_phits_out_async_io_enq_q.io.enq.bits.flit, io.inner_ser[0].out.bits.flit
connect io.inner_ser[0].out.ready, out_phits_out_async_io_enq_q.io.enq.ready
inst out_phits_out_async_io_enq_flit2phit of FlitToPhit_f32_p32_5
connect out_phits_out_async_io_enq_flit2phit.clock, io.inner_clock
connect out_phits_out_async_io_enq_flit2phit.reset, io.inner_reset
connect out_phits_out_async_io_enq_flit2phit.io.in, out_phits_out_async_io_enq_q.io.deq
connect out_phits_out_async.io.enq, out_phits_out_async_io_enq_flit2phit.io.out
inst out_phits_out_async_1 of AsyncQueue_11
connect out_phits_out_async_1.io.enq_clock, io.inner_clock
connect out_phits_out_async_1.io.enq_reset, io.inner_reset
connect out_phits_out_async_1.io.deq_clock, io.outer_clock
connect out_phits_out_async_1.io.deq_reset, io.outer_reset
inst out_phits_out_async_io_enq_q_1 of Queue8_Flit_11
connect out_phits_out_async_io_enq_q_1.clock, io.inner_clock
connect out_phits_out_async_io_enq_q_1.reset, io.inner_reset
connect out_phits_out_async_io_enq_q_1.io.enq.valid, io.inner_ser[1].out.valid
connect out_phits_out_async_io_enq_q_1.io.enq.bits.flit, io.inner_ser[1].out.bits.flit
connect io.inner_ser[1].out.ready, out_phits_out_async_io_enq_q_1.io.enq.ready
inst out_phits_out_async_io_enq_flit2phit_1 of FlitToPhit_f32_p32_6
connect out_phits_out_async_io_enq_flit2phit_1.clock, io.inner_clock
connect out_phits_out_async_io_enq_flit2phit_1.reset, io.inner_reset
connect out_phits_out_async_io_enq_flit2phit_1.io.in, out_phits_out_async_io_enq_q_1.io.deq
connect out_phits_out_async_1.io.enq, out_phits_out_async_io_enq_flit2phit_1.io.out
inst out_phits_out_async_2 of AsyncQueue_12
connect out_phits_out_async_2.io.enq_clock, io.inner_clock
connect out_phits_out_async_2.io.enq_reset, io.inner_reset
connect out_phits_out_async_2.io.deq_clock, io.outer_clock
connect out_phits_out_async_2.io.deq_reset, io.outer_reset
inst out_phits_out_async_io_enq_q_2 of Queue8_Flit_12
connect out_phits_out_async_io_enq_q_2.clock, io.inner_clock
connect out_phits_out_async_io_enq_q_2.reset, io.inner_reset
connect out_phits_out_async_io_enq_q_2.io.enq.valid, io.inner_ser[2].out.valid
connect out_phits_out_async_io_enq_q_2.io.enq.bits.flit, io.inner_ser[2].out.bits.flit
connect io.inner_ser[2].out.ready, out_phits_out_async_io_enq_q_2.io.enq.ready
inst out_phits_out_async_io_enq_flit2phit_2 of FlitToPhit_f32_p32_7
connect out_phits_out_async_io_enq_flit2phit_2.clock, io.inner_clock
connect out_phits_out_async_io_enq_flit2phit_2.reset, io.inner_reset
connect out_phits_out_async_io_enq_flit2phit_2.io.in, out_phits_out_async_io_enq_q_2.io.deq
connect out_phits_out_async_2.io.enq, out_phits_out_async_io_enq_flit2phit_2.io.out
inst out_phits_out_async_3 of AsyncQueue_13
connect out_phits_out_async_3.io.enq_clock, io.inner_clock
connect out_phits_out_async_3.io.enq_reset, io.inner_reset
connect out_phits_out_async_3.io.deq_clock, io.outer_clock
connect out_phits_out_async_3.io.deq_reset, io.outer_reset
inst out_phits_out_async_io_enq_q_3 of Queue8_Flit_13
connect out_phits_out_async_io_enq_q_3.clock, io.inner_clock
connect out_phits_out_async_io_enq_q_3.reset, io.inner_reset
connect out_phits_out_async_io_enq_q_3.io.enq.valid, io.inner_ser[3].out.valid
connect out_phits_out_async_io_enq_q_3.io.enq.bits.flit, io.inner_ser[3].out.bits.flit
connect io.inner_ser[3].out.ready, out_phits_out_async_io_enq_q_3.io.enq.ready
inst out_phits_out_async_io_enq_flit2phit_3 of FlitToPhit_f32_p32_8
connect out_phits_out_async_io_enq_flit2phit_3.clock, io.inner_clock
connect out_phits_out_async_io_enq_flit2phit_3.reset, io.inner_reset
connect out_phits_out_async_io_enq_flit2phit_3.io.in, out_phits_out_async_io_enq_q_3.io.deq
connect out_phits_out_async_3.io.enq, out_phits_out_async_io_enq_flit2phit_3.io.out
inst out_phits_out_async_4 of AsyncQueue_14
connect out_phits_out_async_4.io.enq_clock, io.inner_clock
connect out_phits_out_async_4.io.enq_reset, io.inner_reset
connect out_phits_out_async_4.io.deq_clock, io.outer_clock
connect out_phits_out_async_4.io.deq_reset, io.outer_reset
inst out_phits_out_async_io_enq_q_4 of Queue8_Flit_14
connect out_phits_out_async_io_enq_q_4.clock, io.inner_clock
connect out_phits_out_async_io_enq_q_4.reset, io.inner_reset
connect out_phits_out_async_io_enq_q_4.io.enq.valid, io.inner_ser[4].out.valid
connect out_phits_out_async_io_enq_q_4.io.enq.bits.flit, io.inner_ser[4].out.bits.flit
connect io.inner_ser[4].out.ready, out_phits_out_async_io_enq_q_4.io.enq.ready
inst out_phits_out_async_io_enq_flit2phit_4 of FlitToPhit_f32_p32_9
connect out_phits_out_async_io_enq_flit2phit_4.clock, io.inner_clock
connect out_phits_out_async_io_enq_flit2phit_4.reset, io.inner_reset
connect out_phits_out_async_io_enq_flit2phit_4.io.in, out_phits_out_async_io_enq_q_4.io.deq
connect out_phits_out_async_4.io.enq, out_phits_out_async_io_enq_flit2phit_4.io.out
inst out_arb of PhitArbiter_p32_f32_n5_1
connect out_arb.clock, io.outer_clock
connect out_arb.reset, io.outer_reset
connect out_arb.io.in[0], out_phits_out_async.io.deq
connect out_arb.io.in[1], out_phits_out_async_1.io.deq
connect out_arb.io.in[2], out_phits_out_async_2.io.deq
connect out_arb.io.in[3], out_phits_out_async_3.io.deq
connect out_arb.io.in[4], out_phits_out_async_4.io.deq
connect io.outer_ser.out.bits, out_arb.io.out.bits
connect io.outer_ser.out.valid, out_arb.io.out.valid
connect out_arb.io.out.ready, io.outer_ser.out.ready
inst in_phits_in_async of AsyncQueue_15
connect in_phits_in_async.io.enq_clock, io.outer_clock
connect in_phits_in_async.io.enq_reset, io.outer_reset
connect in_phits_in_async.io.deq_clock, io.inner_clock
connect in_phits_in_async.io.deq_reset, io.inner_reset
inst in_phits_io_inner_ser_0_in_phit2flit of PhitToFlit_p32_f32_5
connect in_phits_io_inner_ser_0_in_phit2flit.clock, io.inner_clock
connect in_phits_io_inner_ser_0_in_phit2flit.reset, io.inner_reset
connect in_phits_io_inner_ser_0_in_phit2flit.io.in, in_phits_in_async.io.deq
inst in_phits_io_inner_ser_0_in_q of Queue8_Flit_15
connect in_phits_io_inner_ser_0_in_q.clock, io.inner_clock
connect in_phits_io_inner_ser_0_in_q.reset, io.inner_reset
connect in_phits_io_inner_ser_0_in_q.io.enq.valid, in_phits_io_inner_ser_0_in_phit2flit.io.out.valid
connect in_phits_io_inner_ser_0_in_q.io.enq.bits.flit, in_phits_io_inner_ser_0_in_phit2flit.io.out.bits.flit
connect in_phits_io_inner_ser_0_in_phit2flit.io.out.ready, in_phits_io_inner_ser_0_in_q.io.enq.ready
connect io.inner_ser[0].in.bits, in_phits_io_inner_ser_0_in_q.io.deq.bits
connect io.inner_ser[0].in.valid, in_phits_io_inner_ser_0_in_q.io.deq.valid
connect in_phits_io_inner_ser_0_in_q.io.deq.ready, io.inner_ser[0].in.ready
inst in_phits_in_async_1 of AsyncQueue_16
connect in_phits_in_async_1.io.enq_clock, io.outer_clock
connect in_phits_in_async_1.io.enq_reset, io.outer_reset
connect in_phits_in_async_1.io.deq_clock, io.inner_clock
connect in_phits_in_async_1.io.deq_reset, io.inner_reset
inst in_phits_io_inner_ser_1_in_phit2flit of PhitToFlit_p32_f32_6
connect in_phits_io_inner_ser_1_in_phit2flit.clock, io.inner_clock
connect in_phits_io_inner_ser_1_in_phit2flit.reset, io.inner_reset
connect in_phits_io_inner_ser_1_in_phit2flit.io.in, in_phits_in_async_1.io.deq
inst in_phits_io_inner_ser_1_in_q of Queue8_Flit_16
connect in_phits_io_inner_ser_1_in_q.clock, io.inner_clock
connect in_phits_io_inner_ser_1_in_q.reset, io.inner_reset
connect in_phits_io_inner_ser_1_in_q.io.enq.valid, in_phits_io_inner_ser_1_in_phit2flit.io.out.valid
connect in_phits_io_inner_ser_1_in_q.io.enq.bits.flit, in_phits_io_inner_ser_1_in_phit2flit.io.out.bits.flit
connect in_phits_io_inner_ser_1_in_phit2flit.io.out.ready, in_phits_io_inner_ser_1_in_q.io.enq.ready
connect io.inner_ser[1].in.bits, in_phits_io_inner_ser_1_in_q.io.deq.bits
connect io.inner_ser[1].in.valid, in_phits_io_inner_ser_1_in_q.io.deq.valid
connect in_phits_io_inner_ser_1_in_q.io.deq.ready, io.inner_ser[1].in.ready
inst in_phits_in_async_2 of AsyncQueue_17
connect in_phits_in_async_2.io.enq_clock, io.outer_clock
connect in_phits_in_async_2.io.enq_reset, io.outer_reset
connect in_phits_in_async_2.io.deq_clock, io.inner_clock
connect in_phits_in_async_2.io.deq_reset, io.inner_reset
inst in_phits_io_inner_ser_2_in_phit2flit of PhitToFlit_p32_f32_7
connect in_phits_io_inner_ser_2_in_phit2flit.clock, io.inner_clock
connect in_phits_io_inner_ser_2_in_phit2flit.reset, io.inner_reset
connect in_phits_io_inner_ser_2_in_phit2flit.io.in, in_phits_in_async_2.io.deq
inst in_phits_io_inner_ser_2_in_q of Queue8_Flit_17
connect in_phits_io_inner_ser_2_in_q.clock, io.inner_clock
connect in_phits_io_inner_ser_2_in_q.reset, io.inner_reset
connect in_phits_io_inner_ser_2_in_q.io.enq.valid, in_phits_io_inner_ser_2_in_phit2flit.io.out.valid
connect in_phits_io_inner_ser_2_in_q.io.enq.bits.flit, in_phits_io_inner_ser_2_in_phit2flit.io.out.bits.flit
connect in_phits_io_inner_ser_2_in_phit2flit.io.out.ready, in_phits_io_inner_ser_2_in_q.io.enq.ready
connect io.inner_ser[2].in.bits, in_phits_io_inner_ser_2_in_q.io.deq.bits
connect io.inner_ser[2].in.valid, in_phits_io_inner_ser_2_in_q.io.deq.valid
connect in_phits_io_inner_ser_2_in_q.io.deq.ready, io.inner_ser[2].in.ready
inst in_phits_in_async_3 of AsyncQueue_18
connect in_phits_in_async_3.io.enq_clock, io.outer_clock
connect in_phits_in_async_3.io.enq_reset, io.outer_reset
connect in_phits_in_async_3.io.deq_clock, io.inner_clock
connect in_phits_in_async_3.io.deq_reset, io.inner_reset
inst in_phits_io_inner_ser_3_in_phit2flit of PhitToFlit_p32_f32_8
connect in_phits_io_inner_ser_3_in_phit2flit.clock, io.inner_clock
connect in_phits_io_inner_ser_3_in_phit2flit.reset, io.inner_reset
connect in_phits_io_inner_ser_3_in_phit2flit.io.in, in_phits_in_async_3.io.deq
inst in_phits_io_inner_ser_3_in_q of Queue8_Flit_18
connect in_phits_io_inner_ser_3_in_q.clock, io.inner_clock
connect in_phits_io_inner_ser_3_in_q.reset, io.inner_reset
connect in_phits_io_inner_ser_3_in_q.io.enq.valid, in_phits_io_inner_ser_3_in_phit2flit.io.out.valid
connect in_phits_io_inner_ser_3_in_q.io.enq.bits.flit, in_phits_io_inner_ser_3_in_phit2flit.io.out.bits.flit
connect in_phits_io_inner_ser_3_in_phit2flit.io.out.ready, in_phits_io_inner_ser_3_in_q.io.enq.ready
connect io.inner_ser[3].in.bits, in_phits_io_inner_ser_3_in_q.io.deq.bits
connect io.inner_ser[3].in.valid, in_phits_io_inner_ser_3_in_q.io.deq.valid
connect in_phits_io_inner_ser_3_in_q.io.deq.ready, io.inner_ser[3].in.ready
inst in_phits_in_async_4 of AsyncQueue_19
connect in_phits_in_async_4.io.enq_clock, io.outer_clock
connect in_phits_in_async_4.io.enq_reset, io.outer_reset
connect in_phits_in_async_4.io.deq_clock, io.inner_clock
connect in_phits_in_async_4.io.deq_reset, io.inner_reset
inst in_phits_io_inner_ser_4_in_phit2flit of PhitToFlit_p32_f32_9
connect in_phits_io_inner_ser_4_in_phit2flit.clock, io.inner_clock
connect in_phits_io_inner_ser_4_in_phit2flit.reset, io.inner_reset
connect in_phits_io_inner_ser_4_in_phit2flit.io.in, in_phits_in_async_4.io.deq
inst in_phits_io_inner_ser_4_in_q of Queue8_Flit_19
connect in_phits_io_inner_ser_4_in_q.clock, io.inner_clock
connect in_phits_io_inner_ser_4_in_q.reset, io.inner_reset
connect in_phits_io_inner_ser_4_in_q.io.enq.valid, in_phits_io_inner_ser_4_in_phit2flit.io.out.valid
connect in_phits_io_inner_ser_4_in_q.io.enq.bits.flit, in_phits_io_inner_ser_4_in_phit2flit.io.out.bits.flit
connect in_phits_io_inner_ser_4_in_phit2flit.io.out.ready, in_phits_io_inner_ser_4_in_q.io.enq.ready
connect io.inner_ser[4].in.bits, in_phits_io_inner_ser_4_in_q.io.deq.bits
connect io.inner_ser[4].in.valid, in_phits_io_inner_ser_4_in_q.io.deq.valid
connect in_phits_io_inner_ser_4_in_q.io.deq.ready, io.inner_ser[4].in.ready
inst in_demux of PhitDemux_p32_f32_n5_1
connect in_demux.clock, io.outer_clock
connect in_demux.reset, io.outer_reset
connect in_demux.io.in, io.outer_ser.in
connect in_phits_in_async.io.enq, in_demux.io.out[0]
connect in_phits_in_async_1.io.enq, in_demux.io.out[1]
connect in_phits_in_async_2.io.enq, in_demux.io.out[2]
connect in_phits_in_async_3.io.enq, in_demux.io.out[3]
connect in_phits_in_async_4.io.enq, in_demux.io.out[4]
when io.outer_reset :
connect io.outer_ser.in.ready, UInt<1>(0h0)
connect io.outer_ser.out.valid, UInt<1>(0h0) | module DecoupledSerialPhy_1( // @[SerialPhy.scala:13:7]
input io_outer_clock, // @[SerialPhy.scala:14:14]
input io_outer_reset, // @[SerialPhy.scala:14:14]
input io_inner_clock, // @[SerialPhy.scala:14:14]
input io_inner_reset, // @[SerialPhy.scala:14:14]
output io_outer_ser_in_ready, // @[SerialPhy.scala:14:14]
input io_outer_ser_in_valid, // @[SerialPhy.scala:14:14]
input [31:0] io_outer_ser_in_bits_phit, // @[SerialPhy.scala:14:14]
input io_outer_ser_out_ready, // @[SerialPhy.scala:14:14]
output io_outer_ser_out_valid, // @[SerialPhy.scala:14:14]
output [31:0] io_outer_ser_out_bits_phit, // @[SerialPhy.scala:14:14]
input io_inner_ser_0_in_ready, // @[SerialPhy.scala:14:14]
output io_inner_ser_0_in_valid, // @[SerialPhy.scala:14:14]
output [31:0] io_inner_ser_0_in_bits_flit, // @[SerialPhy.scala:14:14]
output io_inner_ser_0_out_ready, // @[SerialPhy.scala:14:14]
input [31:0] io_inner_ser_0_out_bits_flit, // @[SerialPhy.scala:14:14]
input io_inner_ser_1_in_ready, // @[SerialPhy.scala:14:14]
output io_inner_ser_1_in_valid, // @[SerialPhy.scala:14:14]
output [31:0] io_inner_ser_1_in_bits_flit, // @[SerialPhy.scala:14:14]
input io_inner_ser_2_in_ready, // @[SerialPhy.scala:14:14]
output io_inner_ser_2_in_valid, // @[SerialPhy.scala:14:14]
output [31:0] io_inner_ser_2_in_bits_flit, // @[SerialPhy.scala:14:14]
output io_inner_ser_2_out_ready, // @[SerialPhy.scala:14:14]
input io_inner_ser_2_out_valid, // @[SerialPhy.scala:14:14]
input [31:0] io_inner_ser_2_out_bits_flit, // @[SerialPhy.scala:14:14]
input io_inner_ser_3_in_ready, // @[SerialPhy.scala:14:14]
output io_inner_ser_3_in_valid, // @[SerialPhy.scala:14:14]
output [31:0] io_inner_ser_3_in_bits_flit, // @[SerialPhy.scala:14:14]
input io_inner_ser_4_in_ready, // @[SerialPhy.scala:14:14]
output io_inner_ser_4_in_valid, // @[SerialPhy.scala:14:14]
output [31:0] io_inner_ser_4_in_bits_flit, // @[SerialPhy.scala:14:14]
output io_inner_ser_4_out_ready, // @[SerialPhy.scala:14:14]
input io_inner_ser_4_out_valid, // @[SerialPhy.scala:14:14]
input [31:0] io_inner_ser_4_out_bits_flit // @[SerialPhy.scala:14:14]
);
wire _in_demux_io_in_ready; // @[SerialPhy.scala:54:11]
wire _in_demux_io_out_0_valid; // @[SerialPhy.scala:54:11]
wire [31:0] _in_demux_io_out_0_bits_phit; // @[SerialPhy.scala:54:11]
wire _in_demux_io_out_1_valid; // @[SerialPhy.scala:54:11]
wire [31:0] _in_demux_io_out_1_bits_phit; // @[SerialPhy.scala:54:11]
wire _in_demux_io_out_2_valid; // @[SerialPhy.scala:54:11]
wire [31:0] _in_demux_io_out_2_bits_phit; // @[SerialPhy.scala:54:11]
wire _in_demux_io_out_3_valid; // @[SerialPhy.scala:54:11]
wire [31:0] _in_demux_io_out_3_bits_phit; // @[SerialPhy.scala:54:11]
wire _in_demux_io_out_4_valid; // @[SerialPhy.scala:54:11]
wire [31:0] _in_demux_io_out_4_bits_phit; // @[SerialPhy.scala:54:11]
wire _in_phits_io_inner_ser_4_in_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _in_phits_io_inner_ser_4_in_phit2flit_io_in_ready; // @[Serdes.scala:131:27]
wire _in_phits_io_inner_ser_4_in_phit2flit_io_out_valid; // @[Serdes.scala:131:27]
wire [31:0] _in_phits_io_inner_ser_4_in_phit2flit_io_out_bits_flit; // @[Serdes.scala:131:27]
wire _in_phits_in_async_4_io_enq_ready; // @[SerialPhy.scala:43:26]
wire _in_phits_in_async_4_io_deq_valid; // @[SerialPhy.scala:43:26]
wire [31:0] _in_phits_in_async_4_io_deq_bits_phit; // @[SerialPhy.scala:43:26]
wire _in_phits_io_inner_ser_3_in_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _in_phits_io_inner_ser_3_in_phit2flit_io_in_ready; // @[Serdes.scala:131:27]
wire _in_phits_io_inner_ser_3_in_phit2flit_io_out_valid; // @[Serdes.scala:131:27]
wire [31:0] _in_phits_io_inner_ser_3_in_phit2flit_io_out_bits_flit; // @[Serdes.scala:131:27]
wire _in_phits_in_async_3_io_enq_ready; // @[SerialPhy.scala:43:26]
wire _in_phits_in_async_3_io_deq_valid; // @[SerialPhy.scala:43:26]
wire [31:0] _in_phits_in_async_3_io_deq_bits_phit; // @[SerialPhy.scala:43:26]
wire _in_phits_io_inner_ser_2_in_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _in_phits_io_inner_ser_2_in_phit2flit_io_in_ready; // @[Serdes.scala:131:27]
wire _in_phits_io_inner_ser_2_in_phit2flit_io_out_valid; // @[Serdes.scala:131:27]
wire [31:0] _in_phits_io_inner_ser_2_in_phit2flit_io_out_bits_flit; // @[Serdes.scala:131:27]
wire _in_phits_in_async_2_io_enq_ready; // @[SerialPhy.scala:43:26]
wire _in_phits_in_async_2_io_deq_valid; // @[SerialPhy.scala:43:26]
wire [31:0] _in_phits_in_async_2_io_deq_bits_phit; // @[SerialPhy.scala:43:26]
wire _in_phits_io_inner_ser_1_in_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _in_phits_io_inner_ser_1_in_phit2flit_io_in_ready; // @[Serdes.scala:131:27]
wire _in_phits_io_inner_ser_1_in_phit2flit_io_out_valid; // @[Serdes.scala:131:27]
wire [31:0] _in_phits_io_inner_ser_1_in_phit2flit_io_out_bits_flit; // @[Serdes.scala:131:27]
wire _in_phits_in_async_1_io_enq_ready; // @[SerialPhy.scala:43:26]
wire _in_phits_in_async_1_io_deq_valid; // @[SerialPhy.scala:43:26]
wire [31:0] _in_phits_in_async_1_io_deq_bits_phit; // @[SerialPhy.scala:43:26]
wire _in_phits_io_inner_ser_0_in_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _in_phits_io_inner_ser_0_in_phit2flit_io_in_ready; // @[Serdes.scala:131:27]
wire _in_phits_io_inner_ser_0_in_phit2flit_io_out_valid; // @[Serdes.scala:131:27]
wire [31:0] _in_phits_io_inner_ser_0_in_phit2flit_io_out_bits_flit; // @[Serdes.scala:131:27]
wire _in_phits_in_async_io_enq_ready; // @[SerialPhy.scala:43:26]
wire _in_phits_in_async_io_deq_valid; // @[SerialPhy.scala:43:26]
wire [31:0] _in_phits_in_async_io_deq_bits_phit; // @[SerialPhy.scala:43:26]
wire _out_arb_io_in_0_ready; // @[SerialPhy.scala:37:11]
wire _out_arb_io_in_1_ready; // @[SerialPhy.scala:37:11]
wire _out_arb_io_in_2_ready; // @[SerialPhy.scala:37:11]
wire _out_arb_io_in_3_ready; // @[SerialPhy.scala:37:11]
wire _out_arb_io_in_4_ready; // @[SerialPhy.scala:37:11]
wire _out_arb_io_out_valid; // @[SerialPhy.scala:37:11]
wire _out_phits_out_async_io_enq_flit2phit_4_io_in_ready; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_flit2phit_4_io_out_valid; // @[Serdes.scala:97:27]
wire [31:0] _out_phits_out_async_io_enq_flit2phit_4_io_out_bits_phit; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_q_4_io_deq_valid; // @[Decoupled.scala:362:21]
wire [31:0] _out_phits_out_async_io_enq_q_4_io_deq_bits_flit; // @[Decoupled.scala:362:21]
wire _out_phits_out_async_4_io_enq_ready; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_4_io_deq_valid; // @[SerialPhy.scala:25:27]
wire [31:0] _out_phits_out_async_4_io_deq_bits_phit; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_io_enq_flit2phit_3_io_in_ready; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_flit2phit_3_io_out_valid; // @[Serdes.scala:97:27]
wire [31:0] _out_phits_out_async_io_enq_flit2phit_3_io_out_bits_phit; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_q_3_io_deq_valid; // @[Decoupled.scala:362:21]
wire [31:0] _out_phits_out_async_io_enq_q_3_io_deq_bits_flit; // @[Decoupled.scala:362:21]
wire _out_phits_out_async_3_io_enq_ready; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_3_io_deq_valid; // @[SerialPhy.scala:25:27]
wire [31:0] _out_phits_out_async_3_io_deq_bits_phit; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_io_enq_flit2phit_2_io_in_ready; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_flit2phit_2_io_out_valid; // @[Serdes.scala:97:27]
wire [31:0] _out_phits_out_async_io_enq_flit2phit_2_io_out_bits_phit; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_q_2_io_deq_valid; // @[Decoupled.scala:362:21]
wire [31:0] _out_phits_out_async_io_enq_q_2_io_deq_bits_flit; // @[Decoupled.scala:362:21]
wire _out_phits_out_async_2_io_enq_ready; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_2_io_deq_valid; // @[SerialPhy.scala:25:27]
wire [31:0] _out_phits_out_async_2_io_deq_bits_phit; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_io_enq_flit2phit_1_io_in_ready; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_flit2phit_1_io_out_valid; // @[Serdes.scala:97:27]
wire [31:0] _out_phits_out_async_io_enq_flit2phit_1_io_out_bits_phit; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_q_1_io_deq_valid; // @[Decoupled.scala:362:21]
wire [31:0] _out_phits_out_async_io_enq_q_1_io_deq_bits_flit; // @[Decoupled.scala:362:21]
wire _out_phits_out_async_1_io_enq_ready; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_1_io_deq_valid; // @[SerialPhy.scala:25:27]
wire [31:0] _out_phits_out_async_1_io_deq_bits_phit; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_io_enq_flit2phit_io_in_ready; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_flit2phit_io_out_valid; // @[Serdes.scala:97:27]
wire [31:0] _out_phits_out_async_io_enq_flit2phit_io_out_bits_phit; // @[Serdes.scala:97:27]
wire _out_phits_out_async_io_enq_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [31:0] _out_phits_out_async_io_enq_q_io_deq_bits_flit; // @[Decoupled.scala:362:21]
wire _out_phits_out_async_io_enq_ready; // @[SerialPhy.scala:25:27]
wire _out_phits_out_async_io_deq_valid; // @[SerialPhy.scala:25:27]
wire [31:0] _out_phits_out_async_io_deq_bits_phit; // @[SerialPhy.scala:25:27]
wire io_outer_clock_0 = io_outer_clock; // @[SerialPhy.scala:13:7]
wire io_outer_reset_0 = io_outer_reset; // @[SerialPhy.scala:13:7]
wire io_inner_clock_0 = io_inner_clock; // @[SerialPhy.scala:13:7]
wire io_inner_reset_0 = io_inner_reset; // @[SerialPhy.scala:13:7]
wire io_outer_ser_in_valid_0 = io_outer_ser_in_valid; // @[SerialPhy.scala:13:7]
wire [31:0] io_outer_ser_in_bits_phit_0 = io_outer_ser_in_bits_phit; // @[SerialPhy.scala:13:7]
wire io_outer_ser_out_ready_0 = io_outer_ser_out_ready; // @[SerialPhy.scala:13:7]
wire io_inner_ser_0_in_ready_0 = io_inner_ser_0_in_ready; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_0_out_bits_flit_0 = io_inner_ser_0_out_bits_flit; // @[SerialPhy.scala:13:7]
wire io_inner_ser_1_in_ready_0 = io_inner_ser_1_in_ready; // @[SerialPhy.scala:13:7]
wire io_inner_ser_2_in_ready_0 = io_inner_ser_2_in_ready; // @[SerialPhy.scala:13:7]
wire io_inner_ser_2_out_valid_0 = io_inner_ser_2_out_valid; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_2_out_bits_flit_0 = io_inner_ser_2_out_bits_flit; // @[SerialPhy.scala:13:7]
wire io_inner_ser_3_in_ready_0 = io_inner_ser_3_in_ready; // @[SerialPhy.scala:13:7]
wire io_inner_ser_4_in_ready_0 = io_inner_ser_4_in_ready; // @[SerialPhy.scala:13:7]
wire io_inner_ser_4_out_valid_0 = io_inner_ser_4_out_valid; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_4_out_bits_flit_0 = io_inner_ser_4_out_bits_flit; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_1_out_bits_flit = 32'h0; // @[Decoupled.scala:362:21]
wire [31:0] io_inner_ser_3_out_bits_flit = 32'h0; // @[Decoupled.scala:362:21]
wire io_inner_ser_1_out_ready = 1'h1; // @[SerialPhy.scala:13:7]
wire io_inner_ser_3_out_ready = 1'h1; // @[SerialPhy.scala:13:7]
wire io_inner_ser_0_out_valid = 1'h0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_1_out_valid = 1'h0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_3_out_valid = 1'h0; // @[SerialPhy.scala:13:7]
wire io_outer_ser_in_ready_0; // @[SerialPhy.scala:13:7]
wire [31:0] io_outer_ser_out_bits_phit_0; // @[SerialPhy.scala:13:7]
wire io_outer_ser_out_valid_0; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_0_in_bits_flit_0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_0_in_valid_0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_0_out_ready_0; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_1_in_bits_flit_0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_1_in_valid_0; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_2_in_bits_flit_0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_2_in_valid_0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_2_out_ready_0; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_3_in_bits_flit_0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_3_in_valid_0; // @[SerialPhy.scala:13:7]
wire [31:0] io_inner_ser_4_in_bits_flit_0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_4_in_valid_0; // @[SerialPhy.scala:13:7]
wire io_inner_ser_4_out_ready_0; // @[SerialPhy.scala:13:7]
assign io_outer_ser_in_ready_0 = ~io_outer_reset_0 & _in_demux_io_in_ready; // @[SerialPhy.scala:13:7, :54:11, :57:18, :61:25, :62:28]
assign io_outer_ser_out_valid_0 = ~io_outer_reset_0 & _out_arb_io_out_valid; // @[SerialPhy.scala:13:7, :37:11, :40:20, :57:18, :61:25, :62:28, :63:28]
AsyncQueue_10 out_phits_out_async ( // @[SerialPhy.scala:25:27]
.io_enq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_out_phits_out_async_io_enq_ready),
.io_enq_valid (_out_phits_out_async_io_enq_flit2phit_io_out_valid), // @[Serdes.scala:97:27]
.io_enq_bits_phit (_out_phits_out_async_io_enq_flit2phit_io_out_bits_phit), // @[Serdes.scala:97:27]
.io_deq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_arb_io_in_0_ready), // @[SerialPhy.scala:37:11]
.io_deq_valid (_out_phits_out_async_io_deq_valid),
.io_deq_bits_phit (_out_phits_out_async_io_deq_bits_phit)
); // @[SerialPhy.scala:25:27]
Queue8_Flit_10 out_phits_out_async_io_enq_q ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (io_inner_ser_0_out_ready_0),
.io_enq_bits_flit (io_inner_ser_0_out_bits_flit_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_phits_out_async_io_enq_flit2phit_io_in_ready), // @[Serdes.scala:97:27]
.io_deq_valid (_out_phits_out_async_io_enq_q_io_deq_valid),
.io_deq_bits_flit (_out_phits_out_async_io_enq_q_io_deq_bits_flit)
); // @[Decoupled.scala:362:21]
FlitToPhit_f32_p32_5 out_phits_out_async_io_enq_flit2phit ( // @[Serdes.scala:97:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_out_phits_out_async_io_enq_flit2phit_io_in_ready),
.io_in_valid (_out_phits_out_async_io_enq_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_bits_flit (_out_phits_out_async_io_enq_q_io_deq_bits_flit), // @[Decoupled.scala:362:21]
.io_out_ready (_out_phits_out_async_io_enq_ready), // @[SerialPhy.scala:25:27]
.io_out_valid (_out_phits_out_async_io_enq_flit2phit_io_out_valid),
.io_out_bits_phit (_out_phits_out_async_io_enq_flit2phit_io_out_bits_phit)
); // @[Serdes.scala:97:27]
AsyncQueue_11 out_phits_out_async_1 ( // @[SerialPhy.scala:25:27]
.io_enq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_out_phits_out_async_1_io_enq_ready),
.io_enq_valid (_out_phits_out_async_io_enq_flit2phit_1_io_out_valid), // @[Serdes.scala:97:27]
.io_enq_bits_phit (_out_phits_out_async_io_enq_flit2phit_1_io_out_bits_phit), // @[Serdes.scala:97:27]
.io_deq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_arb_io_in_1_ready), // @[SerialPhy.scala:37:11]
.io_deq_valid (_out_phits_out_async_1_io_deq_valid),
.io_deq_bits_phit (_out_phits_out_async_1_io_deq_bits_phit)
); // @[SerialPhy.scala:25:27]
Queue8_Flit_11 out_phits_out_async_io_enq_q_1 ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_phits_out_async_io_enq_flit2phit_1_io_in_ready), // @[Serdes.scala:97:27]
.io_deq_valid (_out_phits_out_async_io_enq_q_1_io_deq_valid),
.io_deq_bits_flit (_out_phits_out_async_io_enq_q_1_io_deq_bits_flit)
); // @[Decoupled.scala:362:21]
FlitToPhit_f32_p32_6 out_phits_out_async_io_enq_flit2phit_1 ( // @[Serdes.scala:97:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_out_phits_out_async_io_enq_flit2phit_1_io_in_ready),
.io_in_valid (_out_phits_out_async_io_enq_q_1_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_bits_flit (_out_phits_out_async_io_enq_q_1_io_deq_bits_flit), // @[Decoupled.scala:362:21]
.io_out_ready (_out_phits_out_async_1_io_enq_ready), // @[SerialPhy.scala:25:27]
.io_out_valid (_out_phits_out_async_io_enq_flit2phit_1_io_out_valid),
.io_out_bits_phit (_out_phits_out_async_io_enq_flit2phit_1_io_out_bits_phit)
); // @[Serdes.scala:97:27]
AsyncQueue_12 out_phits_out_async_2 ( // @[SerialPhy.scala:25:27]
.io_enq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_out_phits_out_async_2_io_enq_ready),
.io_enq_valid (_out_phits_out_async_io_enq_flit2phit_2_io_out_valid), // @[Serdes.scala:97:27]
.io_enq_bits_phit (_out_phits_out_async_io_enq_flit2phit_2_io_out_bits_phit), // @[Serdes.scala:97:27]
.io_deq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_arb_io_in_2_ready), // @[SerialPhy.scala:37:11]
.io_deq_valid (_out_phits_out_async_2_io_deq_valid),
.io_deq_bits_phit (_out_phits_out_async_2_io_deq_bits_phit)
); // @[SerialPhy.scala:25:27]
Queue8_Flit_12 out_phits_out_async_io_enq_q_2 ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (io_inner_ser_2_out_ready_0),
.io_enq_valid (io_inner_ser_2_out_valid_0), // @[SerialPhy.scala:13:7]
.io_enq_bits_flit (io_inner_ser_2_out_bits_flit_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_phits_out_async_io_enq_flit2phit_2_io_in_ready), // @[Serdes.scala:97:27]
.io_deq_valid (_out_phits_out_async_io_enq_q_2_io_deq_valid),
.io_deq_bits_flit (_out_phits_out_async_io_enq_q_2_io_deq_bits_flit)
); // @[Decoupled.scala:362:21]
FlitToPhit_f32_p32_7 out_phits_out_async_io_enq_flit2phit_2 ( // @[Serdes.scala:97:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_out_phits_out_async_io_enq_flit2phit_2_io_in_ready),
.io_in_valid (_out_phits_out_async_io_enq_q_2_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_bits_flit (_out_phits_out_async_io_enq_q_2_io_deq_bits_flit), // @[Decoupled.scala:362:21]
.io_out_ready (_out_phits_out_async_2_io_enq_ready), // @[SerialPhy.scala:25:27]
.io_out_valid (_out_phits_out_async_io_enq_flit2phit_2_io_out_valid),
.io_out_bits_phit (_out_phits_out_async_io_enq_flit2phit_2_io_out_bits_phit)
); // @[Serdes.scala:97:27]
AsyncQueue_13 out_phits_out_async_3 ( // @[SerialPhy.scala:25:27]
.io_enq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_out_phits_out_async_3_io_enq_ready),
.io_enq_valid (_out_phits_out_async_io_enq_flit2phit_3_io_out_valid), // @[Serdes.scala:97:27]
.io_enq_bits_phit (_out_phits_out_async_io_enq_flit2phit_3_io_out_bits_phit), // @[Serdes.scala:97:27]
.io_deq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_arb_io_in_3_ready), // @[SerialPhy.scala:37:11]
.io_deq_valid (_out_phits_out_async_3_io_deq_valid),
.io_deq_bits_phit (_out_phits_out_async_3_io_deq_bits_phit)
); // @[SerialPhy.scala:25:27]
Queue8_Flit_13 out_phits_out_async_io_enq_q_3 ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_phits_out_async_io_enq_flit2phit_3_io_in_ready), // @[Serdes.scala:97:27]
.io_deq_valid (_out_phits_out_async_io_enq_q_3_io_deq_valid),
.io_deq_bits_flit (_out_phits_out_async_io_enq_q_3_io_deq_bits_flit)
); // @[Decoupled.scala:362:21]
FlitToPhit_f32_p32_8 out_phits_out_async_io_enq_flit2phit_3 ( // @[Serdes.scala:97:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_out_phits_out_async_io_enq_flit2phit_3_io_in_ready),
.io_in_valid (_out_phits_out_async_io_enq_q_3_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_bits_flit (_out_phits_out_async_io_enq_q_3_io_deq_bits_flit), // @[Decoupled.scala:362:21]
.io_out_ready (_out_phits_out_async_3_io_enq_ready), // @[SerialPhy.scala:25:27]
.io_out_valid (_out_phits_out_async_io_enq_flit2phit_3_io_out_valid),
.io_out_bits_phit (_out_phits_out_async_io_enq_flit2phit_3_io_out_bits_phit)
); // @[Serdes.scala:97:27]
AsyncQueue_14 out_phits_out_async_4 ( // @[SerialPhy.scala:25:27]
.io_enq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_out_phits_out_async_4_io_enq_ready),
.io_enq_valid (_out_phits_out_async_io_enq_flit2phit_4_io_out_valid), // @[Serdes.scala:97:27]
.io_enq_bits_phit (_out_phits_out_async_io_enq_flit2phit_4_io_out_bits_phit), // @[Serdes.scala:97:27]
.io_deq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_arb_io_in_4_ready), // @[SerialPhy.scala:37:11]
.io_deq_valid (_out_phits_out_async_4_io_deq_valid),
.io_deq_bits_phit (_out_phits_out_async_4_io_deq_bits_phit)
); // @[SerialPhy.scala:25:27]
Queue8_Flit_14 out_phits_out_async_io_enq_q_4 ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (io_inner_ser_4_out_ready_0),
.io_enq_valid (io_inner_ser_4_out_valid_0), // @[SerialPhy.scala:13:7]
.io_enq_bits_flit (io_inner_ser_4_out_bits_flit_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_out_phits_out_async_io_enq_flit2phit_4_io_in_ready), // @[Serdes.scala:97:27]
.io_deq_valid (_out_phits_out_async_io_enq_q_4_io_deq_valid),
.io_deq_bits_flit (_out_phits_out_async_io_enq_q_4_io_deq_bits_flit)
); // @[Decoupled.scala:362:21]
FlitToPhit_f32_p32_9 out_phits_out_async_io_enq_flit2phit_4 ( // @[Serdes.scala:97:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_out_phits_out_async_io_enq_flit2phit_4_io_in_ready),
.io_in_valid (_out_phits_out_async_io_enq_q_4_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_bits_flit (_out_phits_out_async_io_enq_q_4_io_deq_bits_flit), // @[Decoupled.scala:362:21]
.io_out_ready (_out_phits_out_async_4_io_enq_ready), // @[SerialPhy.scala:25:27]
.io_out_valid (_out_phits_out_async_io_enq_flit2phit_4_io_out_valid),
.io_out_bits_phit (_out_phits_out_async_io_enq_flit2phit_4_io_out_bits_phit)
); // @[Serdes.scala:97:27]
PhitArbiter_p32_f32_n5_1 out_arb ( // @[SerialPhy.scala:37:11]
.clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_in_0_ready (_out_arb_io_in_0_ready),
.io_in_0_valid (_out_phits_out_async_io_deq_valid), // @[SerialPhy.scala:25:27]
.io_in_0_bits_phit (_out_phits_out_async_io_deq_bits_phit), // @[SerialPhy.scala:25:27]
.io_in_1_ready (_out_arb_io_in_1_ready),
.io_in_1_valid (_out_phits_out_async_1_io_deq_valid), // @[SerialPhy.scala:25:27]
.io_in_1_bits_phit (_out_phits_out_async_1_io_deq_bits_phit), // @[SerialPhy.scala:25:27]
.io_in_2_ready (_out_arb_io_in_2_ready),
.io_in_2_valid (_out_phits_out_async_2_io_deq_valid), // @[SerialPhy.scala:25:27]
.io_in_2_bits_phit (_out_phits_out_async_2_io_deq_bits_phit), // @[SerialPhy.scala:25:27]
.io_in_3_ready (_out_arb_io_in_3_ready),
.io_in_3_valid (_out_phits_out_async_3_io_deq_valid), // @[SerialPhy.scala:25:27]
.io_in_3_bits_phit (_out_phits_out_async_3_io_deq_bits_phit), // @[SerialPhy.scala:25:27]
.io_in_4_ready (_out_arb_io_in_4_ready),
.io_in_4_valid (_out_phits_out_async_4_io_deq_valid), // @[SerialPhy.scala:25:27]
.io_in_4_bits_phit (_out_phits_out_async_4_io_deq_bits_phit), // @[SerialPhy.scala:25:27]
.io_out_ready (io_outer_ser_out_ready_0), // @[SerialPhy.scala:13:7]
.io_out_valid (_out_arb_io_out_valid),
.io_out_bits_phit (io_outer_ser_out_bits_phit_0)
); // @[SerialPhy.scala:37:11]
AsyncQueue_15 in_phits_in_async ( // @[SerialPhy.scala:43:26]
.io_enq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_in_async_io_enq_ready),
.io_enq_valid (_in_demux_io_out_0_valid), // @[SerialPhy.scala:54:11]
.io_enq_bits_phit (_in_demux_io_out_0_bits_phit), // @[SerialPhy.scala:54:11]
.io_deq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_in_phits_io_inner_ser_0_in_phit2flit_io_in_ready), // @[Serdes.scala:131:27]
.io_deq_valid (_in_phits_in_async_io_deq_valid),
.io_deq_bits_phit (_in_phits_in_async_io_deq_bits_phit)
); // @[SerialPhy.scala:43:26]
PhitToFlit_p32_f32_5 in_phits_io_inner_ser_0_in_phit2flit ( // @[Serdes.scala:131:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_in_phits_io_inner_ser_0_in_phit2flit_io_in_ready),
.io_in_valid (_in_phits_in_async_io_deq_valid), // @[SerialPhy.scala:43:26]
.io_in_bits_phit (_in_phits_in_async_io_deq_bits_phit), // @[SerialPhy.scala:43:26]
.io_out_ready (_in_phits_io_inner_ser_0_in_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_out_valid (_in_phits_io_inner_ser_0_in_phit2flit_io_out_valid),
.io_out_bits_flit (_in_phits_io_inner_ser_0_in_phit2flit_io_out_bits_flit)
); // @[Serdes.scala:131:27]
Queue8_Flit_15 in_phits_io_inner_ser_0_in_q ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_io_inner_ser_0_in_q_io_enq_ready),
.io_enq_valid (_in_phits_io_inner_ser_0_in_phit2flit_io_out_valid), // @[Serdes.scala:131:27]
.io_enq_bits_flit (_in_phits_io_inner_ser_0_in_phit2flit_io_out_bits_flit), // @[Serdes.scala:131:27]
.io_deq_ready (io_inner_ser_0_in_ready_0), // @[SerialPhy.scala:13:7]
.io_deq_valid (io_inner_ser_0_in_valid_0),
.io_deq_bits_flit (io_inner_ser_0_in_bits_flit_0)
); // @[Decoupled.scala:362:21]
AsyncQueue_16 in_phits_in_async_1 ( // @[SerialPhy.scala:43:26]
.io_enq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_in_async_1_io_enq_ready),
.io_enq_valid (_in_demux_io_out_1_valid), // @[SerialPhy.scala:54:11]
.io_enq_bits_phit (_in_demux_io_out_1_bits_phit), // @[SerialPhy.scala:54:11]
.io_deq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_in_phits_io_inner_ser_1_in_phit2flit_io_in_ready), // @[Serdes.scala:131:27]
.io_deq_valid (_in_phits_in_async_1_io_deq_valid),
.io_deq_bits_phit (_in_phits_in_async_1_io_deq_bits_phit)
); // @[SerialPhy.scala:43:26]
PhitToFlit_p32_f32_6 in_phits_io_inner_ser_1_in_phit2flit ( // @[Serdes.scala:131:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_in_phits_io_inner_ser_1_in_phit2flit_io_in_ready),
.io_in_valid (_in_phits_in_async_1_io_deq_valid), // @[SerialPhy.scala:43:26]
.io_in_bits_phit (_in_phits_in_async_1_io_deq_bits_phit), // @[SerialPhy.scala:43:26]
.io_out_ready (_in_phits_io_inner_ser_1_in_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_out_valid (_in_phits_io_inner_ser_1_in_phit2flit_io_out_valid),
.io_out_bits_flit (_in_phits_io_inner_ser_1_in_phit2flit_io_out_bits_flit)
); // @[Serdes.scala:131:27]
Queue8_Flit_16 in_phits_io_inner_ser_1_in_q ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_io_inner_ser_1_in_q_io_enq_ready),
.io_enq_valid (_in_phits_io_inner_ser_1_in_phit2flit_io_out_valid), // @[Serdes.scala:131:27]
.io_enq_bits_flit (_in_phits_io_inner_ser_1_in_phit2flit_io_out_bits_flit), // @[Serdes.scala:131:27]
.io_deq_ready (io_inner_ser_1_in_ready_0), // @[SerialPhy.scala:13:7]
.io_deq_valid (io_inner_ser_1_in_valid_0),
.io_deq_bits_flit (io_inner_ser_1_in_bits_flit_0)
); // @[Decoupled.scala:362:21]
AsyncQueue_17 in_phits_in_async_2 ( // @[SerialPhy.scala:43:26]
.io_enq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_in_async_2_io_enq_ready),
.io_enq_valid (_in_demux_io_out_2_valid), // @[SerialPhy.scala:54:11]
.io_enq_bits_phit (_in_demux_io_out_2_bits_phit), // @[SerialPhy.scala:54:11]
.io_deq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_in_phits_io_inner_ser_2_in_phit2flit_io_in_ready), // @[Serdes.scala:131:27]
.io_deq_valid (_in_phits_in_async_2_io_deq_valid),
.io_deq_bits_phit (_in_phits_in_async_2_io_deq_bits_phit)
); // @[SerialPhy.scala:43:26]
PhitToFlit_p32_f32_7 in_phits_io_inner_ser_2_in_phit2flit ( // @[Serdes.scala:131:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_in_phits_io_inner_ser_2_in_phit2flit_io_in_ready),
.io_in_valid (_in_phits_in_async_2_io_deq_valid), // @[SerialPhy.scala:43:26]
.io_in_bits_phit (_in_phits_in_async_2_io_deq_bits_phit), // @[SerialPhy.scala:43:26]
.io_out_ready (_in_phits_io_inner_ser_2_in_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_out_valid (_in_phits_io_inner_ser_2_in_phit2flit_io_out_valid),
.io_out_bits_flit (_in_phits_io_inner_ser_2_in_phit2flit_io_out_bits_flit)
); // @[Serdes.scala:131:27]
Queue8_Flit_17 in_phits_io_inner_ser_2_in_q ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_io_inner_ser_2_in_q_io_enq_ready),
.io_enq_valid (_in_phits_io_inner_ser_2_in_phit2flit_io_out_valid), // @[Serdes.scala:131:27]
.io_enq_bits_flit (_in_phits_io_inner_ser_2_in_phit2flit_io_out_bits_flit), // @[Serdes.scala:131:27]
.io_deq_ready (io_inner_ser_2_in_ready_0), // @[SerialPhy.scala:13:7]
.io_deq_valid (io_inner_ser_2_in_valid_0),
.io_deq_bits_flit (io_inner_ser_2_in_bits_flit_0)
); // @[Decoupled.scala:362:21]
AsyncQueue_18 in_phits_in_async_3 ( // @[SerialPhy.scala:43:26]
.io_enq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_in_async_3_io_enq_ready),
.io_enq_valid (_in_demux_io_out_3_valid), // @[SerialPhy.scala:54:11]
.io_enq_bits_phit (_in_demux_io_out_3_bits_phit), // @[SerialPhy.scala:54:11]
.io_deq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_in_phits_io_inner_ser_3_in_phit2flit_io_in_ready), // @[Serdes.scala:131:27]
.io_deq_valid (_in_phits_in_async_3_io_deq_valid),
.io_deq_bits_phit (_in_phits_in_async_3_io_deq_bits_phit)
); // @[SerialPhy.scala:43:26]
PhitToFlit_p32_f32_8 in_phits_io_inner_ser_3_in_phit2flit ( // @[Serdes.scala:131:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_in_phits_io_inner_ser_3_in_phit2flit_io_in_ready),
.io_in_valid (_in_phits_in_async_3_io_deq_valid), // @[SerialPhy.scala:43:26]
.io_in_bits_phit (_in_phits_in_async_3_io_deq_bits_phit), // @[SerialPhy.scala:43:26]
.io_out_ready (_in_phits_io_inner_ser_3_in_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_out_valid (_in_phits_io_inner_ser_3_in_phit2flit_io_out_valid),
.io_out_bits_flit (_in_phits_io_inner_ser_3_in_phit2flit_io_out_bits_flit)
); // @[Serdes.scala:131:27]
Queue8_Flit_18 in_phits_io_inner_ser_3_in_q ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_io_inner_ser_3_in_q_io_enq_ready),
.io_enq_valid (_in_phits_io_inner_ser_3_in_phit2flit_io_out_valid), // @[Serdes.scala:131:27]
.io_enq_bits_flit (_in_phits_io_inner_ser_3_in_phit2flit_io_out_bits_flit), // @[Serdes.scala:131:27]
.io_deq_ready (io_inner_ser_3_in_ready_0), // @[SerialPhy.scala:13:7]
.io_deq_valid (io_inner_ser_3_in_valid_0),
.io_deq_bits_flit (io_inner_ser_3_in_bits_flit_0)
); // @[Decoupled.scala:362:21]
AsyncQueue_19 in_phits_in_async_4 ( // @[SerialPhy.scala:43:26]
.io_enq_clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.io_enq_reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_in_async_4_io_enq_ready),
.io_enq_valid (_in_demux_io_out_4_valid), // @[SerialPhy.scala:54:11]
.io_enq_bits_phit (_in_demux_io_out_4_bits_phit), // @[SerialPhy.scala:54:11]
.io_deq_clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.io_deq_reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_deq_ready (_in_phits_io_inner_ser_4_in_phit2flit_io_in_ready), // @[Serdes.scala:131:27]
.io_deq_valid (_in_phits_in_async_4_io_deq_valid),
.io_deq_bits_phit (_in_phits_in_async_4_io_deq_bits_phit)
); // @[SerialPhy.scala:43:26]
PhitToFlit_p32_f32_9 in_phits_io_inner_ser_4_in_phit2flit ( // @[Serdes.scala:131:27]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_in_phits_io_inner_ser_4_in_phit2flit_io_in_ready),
.io_in_valid (_in_phits_in_async_4_io_deq_valid), // @[SerialPhy.scala:43:26]
.io_in_bits_phit (_in_phits_in_async_4_io_deq_bits_phit), // @[SerialPhy.scala:43:26]
.io_out_ready (_in_phits_io_inner_ser_4_in_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_out_valid (_in_phits_io_inner_ser_4_in_phit2flit_io_out_valid),
.io_out_bits_flit (_in_phits_io_inner_ser_4_in_phit2flit_io_out_bits_flit)
); // @[Serdes.scala:131:27]
Queue8_Flit_19 in_phits_io_inner_ser_4_in_q ( // @[Decoupled.scala:362:21]
.clock (io_inner_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_inner_reset_0), // @[SerialPhy.scala:13:7]
.io_enq_ready (_in_phits_io_inner_ser_4_in_q_io_enq_ready),
.io_enq_valid (_in_phits_io_inner_ser_4_in_phit2flit_io_out_valid), // @[Serdes.scala:131:27]
.io_enq_bits_flit (_in_phits_io_inner_ser_4_in_phit2flit_io_out_bits_flit), // @[Serdes.scala:131:27]
.io_deq_ready (io_inner_ser_4_in_ready_0), // @[SerialPhy.scala:13:7]
.io_deq_valid (io_inner_ser_4_in_valid_0),
.io_deq_bits_flit (io_inner_ser_4_in_bits_flit_0)
); // @[Decoupled.scala:362:21]
PhitDemux_p32_f32_n5_1 in_demux ( // @[SerialPhy.scala:54:11]
.clock (io_outer_clock_0), // @[SerialPhy.scala:13:7]
.reset (io_outer_reset_0), // @[SerialPhy.scala:13:7]
.io_in_ready (_in_demux_io_in_ready),
.io_in_valid (io_outer_ser_in_valid_0), // @[SerialPhy.scala:13:7]
.io_in_bits_phit (io_outer_ser_in_bits_phit_0), // @[SerialPhy.scala:13:7]
.io_out_0_ready (_in_phits_in_async_io_enq_ready), // @[SerialPhy.scala:43:26]
.io_out_0_valid (_in_demux_io_out_0_valid),
.io_out_0_bits_phit (_in_demux_io_out_0_bits_phit),
.io_out_1_ready (_in_phits_in_async_1_io_enq_ready), // @[SerialPhy.scala:43:26]
.io_out_1_valid (_in_demux_io_out_1_valid),
.io_out_1_bits_phit (_in_demux_io_out_1_bits_phit),
.io_out_2_ready (_in_phits_in_async_2_io_enq_ready), // @[SerialPhy.scala:43:26]
.io_out_2_valid (_in_demux_io_out_2_valid),
.io_out_2_bits_phit (_in_demux_io_out_2_bits_phit),
.io_out_3_ready (_in_phits_in_async_3_io_enq_ready), // @[SerialPhy.scala:43:26]
.io_out_3_valid (_in_demux_io_out_3_valid),
.io_out_3_bits_phit (_in_demux_io_out_3_bits_phit),
.io_out_4_ready (_in_phits_in_async_4_io_enq_ready), // @[SerialPhy.scala:43:26]
.io_out_4_valid (_in_demux_io_out_4_valid),
.io_out_4_bits_phit (_in_demux_io_out_4_bits_phit)
); // @[SerialPhy.scala:54:11]
assign io_outer_ser_in_ready = io_outer_ser_in_ready_0; // @[SerialPhy.scala:13:7]
assign io_outer_ser_out_valid = io_outer_ser_out_valid_0; // @[SerialPhy.scala:13:7]
assign io_outer_ser_out_bits_phit = io_outer_ser_out_bits_phit_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_0_in_valid = io_inner_ser_0_in_valid_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_0_in_bits_flit = io_inner_ser_0_in_bits_flit_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_0_out_ready = io_inner_ser_0_out_ready_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_1_in_valid = io_inner_ser_1_in_valid_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_1_in_bits_flit = io_inner_ser_1_in_bits_flit_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_2_in_valid = io_inner_ser_2_in_valid_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_2_in_bits_flit = io_inner_ser_2_in_bits_flit_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_2_out_ready = io_inner_ser_2_out_ready_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_3_in_valid = io_inner_ser_3_in_valid_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_3_in_bits_flit = io_inner_ser_3_in_bits_flit_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_4_in_valid = io_inner_ser_4_in_valid_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_4_in_bits_flit = io_inner_ser_4_in_bits_flit_0; // @[SerialPhy.scala:13:7]
assign io_inner_ser_4_out_ready = io_inner_ser_4_out_ready_0; // @[SerialPhy.scala:13:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_425 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_425( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_SerialRAM :
input clock : Clock
input reset : Reset
output auto : { flip manager_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}}
wire managerNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate managerNodeIn.d.bits.corrupt
invalidate managerNodeIn.d.bits.data
invalidate managerNodeIn.d.bits.denied
invalidate managerNodeIn.d.bits.sink
invalidate managerNodeIn.d.bits.source
invalidate managerNodeIn.d.bits.size
invalidate managerNodeIn.d.bits.param
invalidate managerNodeIn.d.bits.opcode
invalidate managerNodeIn.d.valid
invalidate managerNodeIn.d.ready
invalidate managerNodeIn.a.bits.corrupt
invalidate managerNodeIn.a.bits.data
invalidate managerNodeIn.a.bits.mask
invalidate managerNodeIn.a.bits.address
invalidate managerNodeIn.a.bits.source
invalidate managerNodeIn.a.bits.size
invalidate managerNodeIn.a.bits.param
invalidate managerNodeIn.a.bits.opcode
invalidate managerNodeIn.a.valid
invalidate managerNodeIn.a.ready
inst monitor of TLMonitor_69
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, managerNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, managerNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, managerNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, managerNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, managerNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, managerNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, managerNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, managerNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, managerNodeIn.d.valid
connect monitor.io.in.d.ready, managerNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, managerNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, managerNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, managerNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, managerNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, managerNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, managerNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, managerNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, managerNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, managerNodeIn.a.valid
connect monitor.io.in.a.ready, managerNodeIn.a.ready
connect managerNodeIn, auto.manager_in
wire client_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}}
connect client_tl.e.bits.sink, UInt<8>(0h0)
connect client_tl.e.valid, UInt<1>(0h0)
connect client_tl.e.ready, UInt<1>(0h0)
connect client_tl.d.bits.corrupt, UInt<1>(0h0)
connect client_tl.d.bits.data, UInt<64>(0h0)
connect client_tl.d.bits.denied, UInt<1>(0h0)
connect client_tl.d.bits.sink, UInt<8>(0h0)
connect client_tl.d.bits.source, UInt<8>(0h0)
connect client_tl.d.bits.size, UInt<8>(0h0)
connect client_tl.d.bits.param, UInt<2>(0h0)
connect client_tl.d.bits.opcode, UInt<3>(0h0)
connect client_tl.d.valid, UInt<1>(0h0)
connect client_tl.d.ready, UInt<1>(0h0)
connect client_tl.c.bits.corrupt, UInt<1>(0h0)
connect client_tl.c.bits.data, UInt<64>(0h0)
connect client_tl.c.bits.address, UInt<64>(0h0)
connect client_tl.c.bits.source, UInt<8>(0h0)
connect client_tl.c.bits.size, UInt<8>(0h0)
connect client_tl.c.bits.param, UInt<3>(0h0)
connect client_tl.c.bits.opcode, UInt<3>(0h0)
connect client_tl.c.valid, UInt<1>(0h0)
connect client_tl.c.ready, UInt<1>(0h0)
connect client_tl.b.bits.corrupt, UInt<1>(0h0)
connect client_tl.b.bits.data, UInt<64>(0h0)
connect client_tl.b.bits.mask, UInt<8>(0h0)
connect client_tl.b.bits.address, UInt<64>(0h0)
connect client_tl.b.bits.source, UInt<8>(0h0)
connect client_tl.b.bits.size, UInt<8>(0h0)
connect client_tl.b.bits.param, UInt<2>(0h0)
connect client_tl.b.bits.opcode, UInt<3>(0h0)
connect client_tl.b.valid, UInt<1>(0h0)
connect client_tl.b.ready, UInt<1>(0h0)
connect client_tl.a.bits.corrupt, UInt<1>(0h0)
connect client_tl.a.bits.data, UInt<64>(0h0)
connect client_tl.a.bits.mask, UInt<8>(0h0)
connect client_tl.a.bits.address, UInt<64>(0h0)
connect client_tl.a.bits.source, UInt<8>(0h0)
connect client_tl.a.bits.size, UInt<8>(0h0)
connect client_tl.a.bits.param, UInt<3>(0h0)
connect client_tl.a.bits.opcode, UInt<3>(0h0)
connect client_tl.a.valid, UInt<1>(0h0)
connect client_tl.a.ready, UInt<1>(0h0)
wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _out_channels_WIRE.bits.sink, UInt<4>(0h0)
connect _out_channels_WIRE.valid, UInt<1>(0h0)
connect _out_channels_WIRE.ready, UInt<1>(0h0)
wire out_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect out_channels_0_1.bits, _out_channels_WIRE.bits
connect out_channels_0_1.valid, _out_channels_WIRE.valid
connect out_channels_0_1.ready, _out_channels_WIRE.ready
inst out_channels_0_2 of TLEToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_0_2.clock, clock
connect out_channels_0_2.reset, reset
wire _out_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _out_channels_WIRE_1.bits.corrupt, UInt<1>(0h0)
connect _out_channels_WIRE_1.bits.data, UInt<64>(0h0)
connect _out_channels_WIRE_1.bits.address, UInt<32>(0h0)
connect _out_channels_WIRE_1.bits.source, UInt<1>(0h0)
connect _out_channels_WIRE_1.bits.size, UInt<4>(0h0)
connect _out_channels_WIRE_1.bits.param, UInt<3>(0h0)
connect _out_channels_WIRE_1.bits.opcode, UInt<3>(0h0)
connect _out_channels_WIRE_1.valid, UInt<1>(0h0)
connect _out_channels_WIRE_1.ready, UInt<1>(0h0)
wire out_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect out_channels_2_1.bits, _out_channels_WIRE_1.bits
connect out_channels_2_1.valid, _out_channels_WIRE_1.valid
connect out_channels_2_1.ready, _out_channels_WIRE_1.ready
inst out_channels_2_2 of TLCToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_2_2.clock, clock
connect out_channels_2_2.reset, reset
inst out_channels_4_2 of TLAToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_4_2.clock, clock
connect out_channels_4_2.reset, reset
connect io.ser[0].out.valid, UInt<1>(0h0)
connect io.ser[1].out.valid, UInt<1>(0h0)
connect io.ser[2].out.valid, UInt<1>(0h0)
connect io.ser[3].out.valid, UInt<1>(0h0)
connect io.ser[4].out.valid, UInt<1>(0h0)
invalidate io.ser[0].out.bits.flit
invalidate io.ser[1].out.bits.flit
invalidate io.ser[2].out.bits.flit
invalidate io.ser[3].out.bits.flit
invalidate io.ser[4].out.bits.flit
connect out_channels_0_2.io.protocol, out_channels_0_1
inst ser_0 of GenericSerializer_TLBeatw10_f32
connect ser_0.clock, clock
connect ser_0.reset, reset
connect ser_0.io.in, out_channels_0_2.io.beat
connect io.ser[0].out.bits, ser_0.io.out.bits
connect io.ser[0].out.valid, ser_0.io.out.valid
connect ser_0.io.out.ready, io.ser[0].out.ready
connect out_channels_2_2.io.protocol, out_channels_2_1
inst ser_2 of GenericSerializer_TLBeatw88_f32
connect ser_2.clock, clock
connect ser_2.reset, reset
connect ser_2.io.in, out_channels_2_2.io.beat
connect io.ser[2].out.bits, ser_2.io.out.bits
connect io.ser[2].out.valid, ser_2.io.out.valid
connect ser_2.io.out.ready, io.ser[2].out.ready
connect out_channels_4_2.io.protocol, managerNodeIn.a
inst ser_4 of GenericSerializer_TLBeatw88_f32_1
connect ser_4.clock, clock
connect ser_4.reset, reset
connect ser_4.io.in, out_channels_4_2.io.beat
connect io.ser[4].out.bits, ser_4.io.out.bits
connect io.ser[4].out.valid, ser_4.io.out.valid
connect ser_4.io.out.ready, io.ser[4].out.ready
node _io_debug_ser_busy_T = or(ser_0.io.busy, ser_2.io.busy)
node _io_debug_ser_busy_T_1 = or(_io_debug_ser_busy_T, ser_4.io.busy)
connect io.debug.ser_busy, _io_debug_ser_busy_T_1
inst in_channels_0_2 of TLEFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_0_2.clock, clock
connect in_channels_0_2.reset, reset
inst in_channels_1_2 of TLDFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_1_2.clock, clock
connect in_channels_1_2.reset, reset
inst in_channels_2_2 of TLCFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_2_2.clock, clock
connect in_channels_2_2.reset, reset
wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _in_channels_WIRE.bits.corrupt, UInt<1>(0h0)
connect _in_channels_WIRE.bits.data, UInt<64>(0h0)
connect _in_channels_WIRE.bits.mask, UInt<8>(0h0)
connect _in_channels_WIRE.bits.address, UInt<32>(0h0)
connect _in_channels_WIRE.bits.source, UInt<1>(0h0)
connect _in_channels_WIRE.bits.size, UInt<4>(0h0)
connect _in_channels_WIRE.bits.param, UInt<2>(0h0)
connect _in_channels_WIRE.bits.opcode, UInt<3>(0h0)
connect _in_channels_WIRE.valid, UInt<1>(0h0)
connect _in_channels_WIRE.ready, UInt<1>(0h0)
wire in_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect in_channels_3_1.bits, _in_channels_WIRE.bits
connect in_channels_3_1.valid, _in_channels_WIRE.valid
connect in_channels_3_1.ready, _in_channels_WIRE.ready
inst in_channels_3_2 of TLBFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_3_2.clock, clock
connect in_channels_3_2.reset, reset
inst in_channels_4_2 of TLAFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_4_2.clock, clock
connect in_channels_4_2.reset, reset
connect client_tl.e.bits.sink, in_channels_0_2.io.protocol.bits.sink
connect client_tl.e.valid, in_channels_0_2.io.protocol.valid
connect in_channels_0_2.io.protocol.ready, client_tl.e.ready
inst des_0 of GenericDeserializer_TLBeatw10_f32_1
connect des_0.clock, clock
connect des_0.reset, reset
connect des_0.io.in, io.ser[0].in
connect in_channels_0_2.io.beat, des_0.io.out
connect managerNodeIn.d.bits, in_channels_1_2.io.protocol.bits
connect managerNodeIn.d.valid, in_channels_1_2.io.protocol.valid
connect in_channels_1_2.io.protocol.ready, managerNodeIn.d.ready
inst des_1 of GenericDeserializer_TLBeatw67_f32_1
connect des_1.clock, clock
connect des_1.reset, reset
connect des_1.io.in, io.ser[1].in
connect in_channels_1_2.io.beat, des_1.io.out
connect client_tl.c.bits.corrupt, in_channels_2_2.io.protocol.bits.corrupt
connect client_tl.c.bits.data, in_channels_2_2.io.protocol.bits.data
connect client_tl.c.bits.address, in_channels_2_2.io.protocol.bits.address
connect client_tl.c.bits.source, in_channels_2_2.io.protocol.bits.source
connect client_tl.c.bits.size, in_channels_2_2.io.protocol.bits.size
connect client_tl.c.bits.param, in_channels_2_2.io.protocol.bits.param
connect client_tl.c.bits.opcode, in_channels_2_2.io.protocol.bits.opcode
connect client_tl.c.valid, in_channels_2_2.io.protocol.valid
connect in_channels_2_2.io.protocol.ready, client_tl.c.ready
inst des_2 of GenericDeserializer_TLBeatw88_f32_2
connect des_2.clock, clock
connect des_2.reset, reset
connect des_2.io.in, io.ser[2].in
connect in_channels_2_2.io.beat, des_2.io.out
connect in_channels_3_1.bits, in_channels_3_2.io.protocol.bits
connect in_channels_3_1.valid, in_channels_3_2.io.protocol.valid
connect in_channels_3_2.io.protocol.ready, in_channels_3_1.ready
inst des_3 of GenericDeserializer_TLBeatw87_f32_1
connect des_3.clock, clock
connect des_3.reset, reset
connect des_3.io.in, io.ser[3].in
connect in_channels_3_2.io.beat, des_3.io.out
connect client_tl.a.bits.corrupt, in_channels_4_2.io.protocol.bits.corrupt
connect client_tl.a.bits.data, in_channels_4_2.io.protocol.bits.data
connect client_tl.a.bits.mask, in_channels_4_2.io.protocol.bits.mask
connect client_tl.a.bits.address, in_channels_4_2.io.protocol.bits.address
connect client_tl.a.bits.source, in_channels_4_2.io.protocol.bits.source
connect client_tl.a.bits.size, in_channels_4_2.io.protocol.bits.size
connect client_tl.a.bits.param, in_channels_4_2.io.protocol.bits.param
connect client_tl.a.bits.opcode, in_channels_4_2.io.protocol.bits.opcode
connect client_tl.a.valid, in_channels_4_2.io.protocol.valid
connect in_channels_4_2.io.protocol.ready, client_tl.a.ready
inst des_4 of GenericDeserializer_TLBeatw88_f32_3
connect des_4.clock, clock
connect des_4.reset, reset
connect des_4.io.in, io.ser[4].in
connect in_channels_4_2.io.beat, des_4.io.out
node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy)
node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy)
node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy)
node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy)
connect io.debug.des_busy, _io_debug_des_busy_T_3 | module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_0_out_ready, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_2_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_2_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_4_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_4_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_4_io_busy; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_busy; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28]
wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28]
wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_4_io_busy; // @[TLSerdes.scala:69:23]
wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23]
wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50]
wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50]
wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50]
wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50]
wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9]
wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9]
wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9]
wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9]
wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9]
wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9]
wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71]
wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71]
wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71]
wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [3:0] _out_channels_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74]
wire [3:0] out_channels_0_1_bits_sink = 4'h0; // @[Bundles.scala:267:61]
wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9]
wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9]
wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9]
wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9]
wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire _io_debug_ser_busy_T_1; // @[package.scala:81:59]
wire _io_debug_des_busy_T_3; // @[package.scala:81:59]
wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9]
wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_debug_ser_busy; // @[TLSerdes.scala:39:9]
wire io_debug_des_busy; // @[TLSerdes.scala:39:9]
assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9]
wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71]
wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71]
wire client_tl_a_valid; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71]
wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71]
wire client_tl_c_valid; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71]
wire client_tl_e_valid; // @[TLSerdes.scala:45:71]
wire _io_debug_ser_busy_T; // @[package.scala:81:59]
assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T | _ser_4_io_busy; // @[TLSerdes.scala:69:23]
assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9]
wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61]
wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61]
wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61]
wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61]
wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61]
wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61]
wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61]
wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61]
wire in_channels_3_1_valid; // @[Bundles.scala:264:61]
assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9]
assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9]
assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[3:0]; // @[TLSerdes.scala:79:28, :85:9]
assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9]
assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9]
assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9]
wire _io_debug_des_busy_T; // @[package.scala:81:59]
wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23]
assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23]
assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9]
TLMonitor_69 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_0_2_io_beat_bits_head)
); // @[TLSerdes.scala:59:50]
TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_2_2_io_beat_bits_head)
); // @[TLSerdes.scala:61:50]
TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (managerNodeIn_a_ready),
.io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_4_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_4_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail)
); // @[TLSerdes.scala:63:50]
GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_0_io_in_ready),
.io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50]
.io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_bits_flit (io_ser_0_out_bits_flit_0)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_2_io_in_ready),
.io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50]
.io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_2_out_valid_0),
.io_out_bits_flit (io_ser_2_out_bits_flit_0),
.io_busy (_io_debug_ser_busy_T)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_4_io_in_ready),
.io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50]
.io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50]
.io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50]
.io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50]
.io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_4_out_valid_0),
.io_out_bits_flit (io_ser_4_out_bits_flit_0),
.io_busy (_ser_4_io_busy)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_e_valid),
.io_protocol_bits_sink (client_tl_e_bits_sink),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_protocol_valid (managerNodeIn_d_valid),
.io_protocol_bits_opcode (managerNodeIn_d_bits_opcode),
.io_protocol_bits_param (managerNodeIn_d_bits_param),
.io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source),
.io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink),
.io_protocol_bits_denied (managerNodeIn_d_bits_denied),
.io_protocol_bits_data (managerNodeIn_d_bits_data),
.io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_c_valid),
.io_protocol_bits_opcode (client_tl_c_bits_opcode),
.io_protocol_bits_param (client_tl_c_bits_param),
.io_protocol_bits_size (client_tl_c_bits_size),
.io_protocol_bits_source (client_tl_c_bits_source),
.io_protocol_bits_address (client_tl_c_bits_address),
.io_protocol_bits_data (client_tl_c_bits_data),
.io_protocol_bits_corrupt (client_tl_c_bits_corrupt),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (in_channels_3_1_valid),
.io_protocol_bits_opcode (in_channels_3_1_bits_opcode),
.io_protocol_bits_param (in_channels_3_1_bits_param),
.io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address),
.io_protocol_bits_mask (in_channels_3_1_bits_mask),
.io_protocol_bits_data (in_channels_3_1_bits_data),
.io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_a_valid),
.io_protocol_bits_opcode (client_tl_a_bits_opcode),
.io_protocol_bits_param (client_tl_a_bits_param),
.io_protocol_bits_size (client_tl_a_bits_size),
.io_protocol_bits_source (client_tl_a_bits_source),
.io_protocol_bits_address (client_tl_a_bits_address),
.io_protocol_bits_mask (client_tl_a_bits_mask),
.io_protocol_bits_data (client_tl_a_bits_data),
.io_protocol_bits_corrupt (client_tl_a_bits_corrupt),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_0_in_ready_0),
.io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_payload (_des_0_io_out_bits_payload),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready_0),
.io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (_des_1_io_out_bits_payload),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail),
.io_busy (_io_debug_des_busy_T)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready_0),
.io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (_des_2_io_out_bits_payload),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail),
.io_busy (_des_2_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready_0),
.io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_payload (_des_3_io_out_bits_payload),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail),
.io_busy (_des_3_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready_0),
.io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (_des_4_io_out_bits_payload),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail),
.io_busy (_des_4_io_busy)
); // @[TLSerdes.scala:86:23]
assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d64s7k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a32d64s7k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [6:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [6:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [6:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [6:0] saved_source; // @[Repeater.scala:21:18]
reg [31:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_471 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_215
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_471( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_215 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24_6 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0h80)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node _adjustedSig_T = bits(io.in.sig, 64, 39)
node _adjustedSig_T_1 = bits(io.in.sig, 38, 0)
node _adjustedSig_T_2 = orr(_adjustedSig_T_1)
node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0))
node roundMask = cat(_roundMask_T, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1)
connect common_underflow, UInt<1>(0h0)
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24_6( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55]
wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41]
wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53]
wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28]
wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46]
wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32]
wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22]
wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire [9:0] _sAdjustedExp_T = {io_in_sExp_0[8], io_in_sExp_0} + 10'h80; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [25:0] _adjustedSig_T = io_in_sig_0[64:39]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23]
wire [38:0] _adjustedSig_T_1 = io_in_sig_0[38:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26]
wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}]
wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [25:0] _roundedSig_T_15 = {25'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61]
wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15]
wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ReservationBuffer :
input clock : Clock
input reset : Reset
output io : { flip alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, count : UInt<9>}}, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, data : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}}
inst buffer of BufferBRAM
connect buffer.clock, clock
connect buffer.reset, reset
regreset bufValid : UInt<379>, clock, reset, UInt<379>(0h0)
regreset head : UInt<9>, clock, reset, UInt<9>(0h0)
regreset tail : UInt<9>, clock, reset, UInt<9>(0h0)
regreset count : UInt<9>, clock, reset, UInt<9>(0h0)
node _full_T = add(count, io.alloc.bits.count)
node _full_T_1 = tail(_full_T, 1)
node full = gt(_full_T_1, UInt<9>(0h17b))
reg xactHeads : UInt<9>[8], clock
regreset occupied : UInt<1>, clock, reset, UInt<1>(0h0)
node _ren_T = eq(occupied, UInt<1>(0h0))
node _ren_T_1 = or(_ren_T, io.out.ready)
node _ren_T_2 = dshr(bufValid, tail)
node _ren_T_3 = bits(_ren_T_2, 0, 0)
node ren = and(_ren_T_1, _ren_T_3)
node _count_T = and(io.alloc.ready, io.alloc.valid)
node _count_T_1 = mux(_count_T, io.alloc.bits.count, UInt<1>(0h0))
node _count_T_2 = add(count, _count_T_1)
node _count_T_3 = tail(_count_T_2, 1)
node _count_T_4 = and(io.out.ready, io.out.valid)
node _count_T_5 = mux(_count_T_4, UInt<1>(0h1), UInt<1>(0h0))
node _count_T_6 = sub(_count_T_3, _count_T_5)
node _count_T_7 = tail(_count_T_6, 1)
connect count, _count_T_7
node _bufValid_T = and(io.in.ready, io.in.valid)
node _bufValid_T_1 = dshl(UInt<1>(0h1), xactHeads[io.in.bits.id])
node _bufValid_T_2 = mux(_bufValid_T, _bufValid_T_1, UInt<1>(0h0))
node _bufValid_T_3 = or(bufValid, _bufValid_T_2)
node _bufValid_T_4 = dshl(UInt<1>(0h1), tail)
node _bufValid_T_5 = mux(ren, _bufValid_T_4, UInt<1>(0h0))
node _bufValid_T_6 = not(_bufValid_T_5)
node _bufValid_T_7 = and(_bufValid_T_3, _bufValid_T_6)
connect bufValid, _bufValid_T_7
node _io_alloc_ready_T = eq(full, UInt<1>(0h0))
connect io.alloc.ready, _io_alloc_ready_T
connect io.in.ready, UInt<1>(0h1)
connect io.out.valid, occupied
connect io.out.bits, buffer.io.read.data
node _buffer_io_write_en_T = and(io.in.ready, io.in.valid)
connect buffer.io.write.en, _buffer_io_write_en_T
connect buffer.io.write.addr, xactHeads[io.in.bits.id]
connect buffer.io.write.data.last, io.in.bits.data.last
connect buffer.io.write.data.keep, io.in.bits.data.keep
connect buffer.io.write.data.data, io.in.bits.data.data
connect buffer.io.read.en, ren
connect buffer.io.read.addr, tail
node _T = and(io.alloc.ready, io.alloc.valid)
when _T :
connect xactHeads[io.alloc.bits.id], head
node head_unwrapped = add(head, io.alloc.bits.count)
node _head_T = geq(head_unwrapped, UInt<9>(0h17b))
node _head_T_1 = sub(head_unwrapped, UInt<9>(0h17b))
node _head_T_2 = tail(_head_T_1, 1)
node _head_T_3 = mux(_head_T, _head_T_2, head_unwrapped)
connect head, _head_T_3
node _T_1 = and(io.in.ready, io.in.valid)
when _T_1 :
node xactHeads_unwrapped = add(xactHeads[io.in.bits.id], UInt<1>(0h1))
node _xactHeads_T = geq(xactHeads_unwrapped, UInt<9>(0h17b))
node _xactHeads_T_1 = sub(xactHeads_unwrapped, UInt<9>(0h17b))
node _xactHeads_T_2 = tail(_xactHeads_T_1, 1)
node _xactHeads_T_3 = mux(_xactHeads_T, _xactHeads_T_2, xactHeads_unwrapped)
connect xactHeads[io.in.bits.id], _xactHeads_T_3
node _T_2 = and(io.out.ready, io.out.valid)
when _T_2 :
connect occupied, UInt<1>(0h0)
when ren :
connect occupied, UInt<1>(0h1)
node tail_unwrapped = add(tail, UInt<1>(0h1))
node _tail_T = geq(tail_unwrapped, UInt<9>(0h17b))
node _tail_T_1 = sub(tail_unwrapped, UInt<9>(0h17b))
node _tail_T_2 = tail(_tail_T_1, 1)
node _tail_T_3 = mux(_tail_T, _tail_T_2, tail_unwrapped)
connect tail, _tail_T_3 | module ReservationBuffer( // @[Buffer.scala:360:7]
input clock, // @[Buffer.scala:360:7]
input reset, // @[Buffer.scala:360:7]
output io_alloc_ready, // @[Buffer.scala:366:14]
input io_alloc_valid, // @[Buffer.scala:366:14]
input [2:0] io_alloc_bits_id, // @[Buffer.scala:366:14]
input [8:0] io_alloc_bits_count, // @[Buffer.scala:366:14]
input io_in_valid, // @[Buffer.scala:366:14]
input [2:0] io_in_bits_id, // @[Buffer.scala:366:14]
input [63:0] io_in_bits_data_data, // @[Buffer.scala:366:14]
input [7:0] io_in_bits_data_keep, // @[Buffer.scala:366:14]
input io_in_bits_data_last, // @[Buffer.scala:366:14]
input io_out_ready, // @[Buffer.scala:366:14]
output io_out_valid, // @[Buffer.scala:366:14]
output [63:0] io_out_bits_data, // @[Buffer.scala:366:14]
output [7:0] io_out_bits_keep, // @[Buffer.scala:366:14]
output io_out_bits_last // @[Buffer.scala:366:14]
);
wire io_alloc_valid_0 = io_alloc_valid; // @[Buffer.scala:360:7]
wire [2:0] io_alloc_bits_id_0 = io_alloc_bits_id; // @[Buffer.scala:360:7]
wire [8:0] io_alloc_bits_count_0 = io_alloc_bits_count; // @[Buffer.scala:360:7]
wire io_in_valid_0 = io_in_valid; // @[Buffer.scala:360:7]
wire [2:0] io_in_bits_id_0 = io_in_bits_id; // @[Buffer.scala:360:7]
wire [63:0] io_in_bits_data_data_0 = io_in_bits_data_data; // @[Buffer.scala:360:7]
wire [7:0] io_in_bits_data_keep_0 = io_in_bits_data_keep; // @[Buffer.scala:360:7]
wire io_in_bits_data_last_0 = io_in_bits_data_last; // @[Buffer.scala:360:7]
wire io_out_ready_0 = io_out_ready; // @[Buffer.scala:360:7]
wire io_in_ready = 1'h1; // @[Buffer.scala:360:7]
wire _io_alloc_ready_T; // @[Buffer.scala:397:21]
wire _bufValid_T = io_in_valid_0; // @[Decoupled.scala:51:35]
wire _buffer_io_write_en_T = io_in_valid_0; // @[Decoupled.scala:51:35]
wire io_alloc_ready_0; // @[Buffer.scala:360:7]
wire [63:0] io_out_bits_data_0; // @[Buffer.scala:360:7]
wire [7:0] io_out_bits_keep_0; // @[Buffer.scala:360:7]
wire io_out_bits_last_0; // @[Buffer.scala:360:7]
wire io_out_valid_0; // @[Buffer.scala:360:7]
reg [378:0] bufValid; // @[Buffer.scala:378:25]
reg [8:0] head; // @[Buffer.scala:380:21]
reg [8:0] tail; // @[Buffer.scala:381:21]
reg [8:0] count; // @[Buffer.scala:382:22]
wire [9:0] _GEN = {1'h0, count}; // @[Buffer.scala:382:22, :384:21]
wire [9:0] _GEN_0 = {1'h0, io_alloc_bits_count_0}; // @[Buffer.scala:360:7, :384:21]
wire [9:0] _full_T = _GEN + _GEN_0; // @[Buffer.scala:384:21]
wire [8:0] _full_T_1 = _full_T[8:0]; // @[Buffer.scala:384:21]
wire full = _full_T_1 > 9'h17B; // @[Buffer.scala:384:{21,44}]
reg [8:0] xactHeads_0; // @[Buffer.scala:385:22]
reg [8:0] xactHeads_1; // @[Buffer.scala:385:22]
reg [8:0] xactHeads_2; // @[Buffer.scala:385:22]
reg [8:0] xactHeads_3; // @[Buffer.scala:385:22]
reg [8:0] xactHeads_4; // @[Buffer.scala:385:22]
reg [8:0] xactHeads_5; // @[Buffer.scala:385:22]
reg [8:0] xactHeads_6; // @[Buffer.scala:385:22]
reg [8:0] xactHeads_7; // @[Buffer.scala:385:22]
reg occupied; // @[Buffer.scala:388:25]
assign io_out_valid_0 = occupied; // @[Buffer.scala:360:7, :388:25]
wire _ren_T = ~occupied; // @[Buffer.scala:388:25, :389:14]
wire _ren_T_1 = _ren_T | io_out_ready_0; // @[Buffer.scala:360:7, :389:{14,24}]
wire [378:0] _ren_T_2 = bufValid >> tail; // @[Buffer.scala:378:25, :381:21, :389:54]
wire _ren_T_3 = _ren_T_2[0]; // @[Buffer.scala:389:{54,62}]
wire ren = _ren_T_1 & _ren_T_3; // @[Buffer.scala:389:{24,41,62}]
wire _count_T = io_alloc_ready_0 & io_alloc_valid_0; // @[Decoupled.scala:51:35]
wire [8:0] _count_T_1 = _count_T ? io_alloc_bits_count_0 : 9'h0; // @[Decoupled.scala:51:35]
wire [9:0] _count_T_2 = _GEN + {1'h0, _count_T_1}; // @[Buffer.scala:384:21, :391:18, :392:18]
wire [8:0] _count_T_3 = _count_T_2[8:0]; // @[Buffer.scala:391:18]
wire _count_T_4 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35]
wire _count_T_5 = _count_T_4; // @[Decoupled.scala:51:35]
wire [9:0] _count_T_6 = {1'h0, _count_T_3} - {9'h0, _count_T_5}; // @[Buffer.scala:391:18, :392:60, :393:18]
wire [8:0] _count_T_7 = _count_T_6[8:0]; // @[Buffer.scala:392:60]
wire [7:0][8:0] _GEN_1 = {{xactHeads_7}, {xactHeads_6}, {xactHeads_5}, {xactHeads_4}, {xactHeads_3}, {xactHeads_2}, {xactHeads_1}, {xactHeads_0}}; // @[OneHot.scala:58:35]
wire [511:0] _bufValid_T_1 = 512'h1 << _GEN_1[io_in_bits_id_0]; // @[OneHot.scala:58:35]
wire [511:0] _bufValid_T_2 = _bufValid_T ? _bufValid_T_1 : 512'h0; // @[OneHot.scala:58:35]
wire [511:0] _bufValid_T_3 = {133'h0, bufValid} | _bufValid_T_2; // @[Buffer.scala:378:25, :394:{25,30}]
wire [511:0] _bufValid_T_4 = 512'h1 << tail; // @[OneHot.scala:58:35]
wire [511:0] _bufValid_T_5 = ren ? _bufValid_T_4 : 512'h0; // @[OneHot.scala:58:35]
wire [511:0] _bufValid_T_6 = ~_bufValid_T_5; // @[Buffer.scala:395:{26,30}]
wire [511:0] _bufValid_T_7 = _bufValid_T_3 & _bufValid_T_6; // @[Buffer.scala:394:{25,72}, :395:26]
assign _io_alloc_ready_T = ~full; // @[Buffer.scala:384:44, :397:21]
assign io_alloc_ready_0 = _io_alloc_ready_T; // @[Buffer.scala:360:7, :397:21]
wire [9:0] head_unwrapped = {1'h0, head} + _GEN_0; // @[Buffer.scala:373:25, :380:21, :384:21]
wire _head_T = head_unwrapped > 10'h17A; // @[Buffer.scala:373:25, :374:19]
wire [10:0] _head_T_1 = {1'h0, head_unwrapped} - 11'h17B; // @[Buffer.scala:373:25, :374:42]
wire [9:0] _head_T_2 = _head_T_1[9:0]; // @[Buffer.scala:374:42]
wire [9:0] _head_T_3 = _head_T ? _head_T_2 : head_unwrapped; // @[Buffer.scala:373:25, :374:{8,19,42}]
wire [9:0] xactHeads_unwrapped = {1'h0, _GEN_1[io_in_bits_id_0]} + 10'h1; // @[OneHot.scala:58:35]
wire _xactHeads_T = xactHeads_unwrapped > 10'h17A; // @[Buffer.scala:373:25, :374:19]
wire [10:0] _xactHeads_T_1 = {1'h0, xactHeads_unwrapped} - 11'h17B; // @[Buffer.scala:373:25, :374:42]
wire [9:0] _xactHeads_T_2 = _xactHeads_T_1[9:0]; // @[Buffer.scala:374:42]
wire [9:0] _xactHeads_T_3 = _xactHeads_T ? _xactHeads_T_2 : xactHeads_unwrapped; // @[Buffer.scala:373:25, :374:{8,19,42}]
wire [9:0] tail_unwrapped = {1'h0, tail} + 10'h1; // @[Buffer.scala:373:25, :381:21]
wire _tail_T = tail_unwrapped > 10'h17A; // @[Buffer.scala:373:25, :374:19]
wire [10:0] _tail_T_1 = {1'h0, tail_unwrapped} - 11'h17B; // @[Buffer.scala:373:25, :374:42]
wire [9:0] _tail_T_2 = _tail_T_1[9:0]; // @[Buffer.scala:374:42]
wire [9:0] _tail_T_3 = _tail_T ? _tail_T_2 : tail_unwrapped; // @[Buffer.scala:373:25, :374:{8,19,42}]
always @(posedge clock) begin // @[Buffer.scala:360:7]
if (reset) begin // @[Buffer.scala:360:7]
bufValid <= 379'h0; // @[Buffer.scala:378:25]
head <= 9'h0; // @[Buffer.scala:380:21]
tail <= 9'h0; // @[Buffer.scala:381:21]
count <= 9'h0; // @[Buffer.scala:382:22]
occupied <= 1'h0; // @[Buffer.scala:388:25]
end
else begin // @[Buffer.scala:360:7]
bufValid <= _bufValid_T_7[378:0]; // @[Buffer.scala:378:25, :394:{12,72}]
if (_count_T) // @[Decoupled.scala:51:35]
head <= _head_T_3[8:0]; // @[Buffer.scala:374:8, :380:21, :410:10]
if (ren) // @[Buffer.scala:389:41]
tail <= _tail_T_3[8:0]; // @[Buffer.scala:374:8, :381:21, :421:10]
count <= _count_T_7; // @[Buffer.scala:382:22, :392:60]
occupied <= ren | ~_count_T_4 & occupied; // @[Decoupled.scala:51:35]
end
if (io_in_valid_0 & io_in_bits_id_0 == 3'h0) // @[Buffer.scala:360:7, :408:24, :409:33, :413:21, :414:30]
xactHeads_0 <= _xactHeads_T_3[8:0]; // @[Buffer.scala:374:8, :385:22, :414:30]
else if (_count_T & io_alloc_bits_id_0 == 3'h0) // @[Decoupled.scala:51:35]
xactHeads_0 <= head; // @[Buffer.scala:380:21, :385:22]
if (io_in_valid_0 & io_in_bits_id_0 == 3'h1) // @[Buffer.scala:360:7, :408:24, :413:21, :414:30]
xactHeads_1 <= _xactHeads_T_3[8:0]; // @[Buffer.scala:374:8, :385:22, :414:30]
else if (_count_T & io_alloc_bits_id_0 == 3'h1) // @[Decoupled.scala:51:35]
xactHeads_1 <= head; // @[Buffer.scala:380:21, :385:22]
if (io_in_valid_0 & io_in_bits_id_0 == 3'h2) // @[Buffer.scala:360:7, :408:24, :413:21, :414:30]
xactHeads_2 <= _xactHeads_T_3[8:0]; // @[Buffer.scala:374:8, :385:22, :414:30]
else if (_count_T & io_alloc_bits_id_0 == 3'h2) // @[Decoupled.scala:51:35]
xactHeads_2 <= head; // @[Buffer.scala:380:21, :385:22]
if (io_in_valid_0 & io_in_bits_id_0 == 3'h3) // @[Buffer.scala:360:7, :408:24, :413:21, :414:30]
xactHeads_3 <= _xactHeads_T_3[8:0]; // @[Buffer.scala:374:8, :385:22, :414:30]
else if (_count_T & io_alloc_bits_id_0 == 3'h3) // @[Decoupled.scala:51:35]
xactHeads_3 <= head; // @[Buffer.scala:380:21, :385:22]
if (io_in_valid_0 & io_in_bits_id_0 == 3'h4) // @[Buffer.scala:360:7, :408:24, :413:21, :414:30]
xactHeads_4 <= _xactHeads_T_3[8:0]; // @[Buffer.scala:374:8, :385:22, :414:30]
else if (_count_T & io_alloc_bits_id_0 == 3'h4) // @[Decoupled.scala:51:35]
xactHeads_4 <= head; // @[Buffer.scala:380:21, :385:22]
if (io_in_valid_0 & io_in_bits_id_0 == 3'h5) // @[Buffer.scala:360:7, :408:24, :413:21, :414:30]
xactHeads_5 <= _xactHeads_T_3[8:0]; // @[Buffer.scala:374:8, :385:22, :414:30]
else if (_count_T & io_alloc_bits_id_0 == 3'h5) // @[Decoupled.scala:51:35]
xactHeads_5 <= head; // @[Buffer.scala:380:21, :385:22]
if (io_in_valid_0 & io_in_bits_id_0 == 3'h6) // @[Buffer.scala:360:7, :408:24, :413:21, :414:30]
xactHeads_6 <= _xactHeads_T_3[8:0]; // @[Buffer.scala:374:8, :385:22, :414:30]
else if (_count_T & io_alloc_bits_id_0 == 3'h6) // @[Decoupled.scala:51:35]
xactHeads_6 <= head; // @[Buffer.scala:380:21, :385:22]
if (io_in_valid_0 & (&io_in_bits_id_0)) // @[Buffer.scala:360:7, :408:24, :413:21, :414:30]
xactHeads_7 <= _xactHeads_T_3[8:0]; // @[Buffer.scala:374:8, :385:22, :414:30]
else if (_count_T & (&io_alloc_bits_id_0)) // @[Decoupled.scala:51:35]
xactHeads_7 <= head; // @[Buffer.scala:380:21, :385:22]
always @(posedge)
BufferBRAM buffer ( // @[Buffer.scala:377:22]
.clock (clock),
.reset (reset),
.io_read_en (ren), // @[Buffer.scala:389:41]
.io_read_addr (tail), // @[Buffer.scala:381:21]
.io_read_data_data (io_out_bits_data_0),
.io_read_data_keep (io_out_bits_keep_0),
.io_read_data_last (io_out_bits_last_0),
.io_write_en (_buffer_io_write_en_T), // @[Decoupled.scala:51:35]
.io_write_addr (_GEN_1[io_in_bits_id_0]), // @[OneHot.scala:58:35]
.io_write_data_data (io_in_bits_data_data_0), // @[Buffer.scala:360:7]
.io_write_data_keep (io_in_bits_data_keep_0), // @[Buffer.scala:360:7]
.io_write_data_last (io_in_bits_data_last_0) // @[Buffer.scala:360:7]
); // @[Buffer.scala:377:22]
assign io_alloc_ready = io_alloc_ready_0; // @[Buffer.scala:360:7]
assign io_out_valid = io_out_valid_0; // @[Buffer.scala:360:7]
assign io_out_bits_data = io_out_bits_data_0; // @[Buffer.scala:360:7]
assign io_out_bits_keep = io_out_bits_keep_0; // @[Buffer.scala:360:7]
assign io_out_bits_last = io_out_bits_last_0; // @[Buffer.scala:360:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NullIntSource_3 :
output auto : { int_out : UInt<1>[1]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire intnodeOut : UInt<1>[1]
invalidate intnodeOut[0]
connect auto.int_out, intnodeOut
connect intnodeOut[0], UInt<1>(0h0) | module NullIntSource_3(); // @[NullIntSource.scala:16:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire intnodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0)
node _source_ok_T = shr(io.in.a.bits.source, 12)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits = bits(_uncommonBits_T, 11, 0)
node _T_4 = shr(io.in.a.bits.source, 12)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<12>(0h80f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0)
node _T_24 = shr(io.in.a.bits.source, 12)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0)
node _T_86 = shr(io.in.a.bits.source, 12)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0)
node _T_152 = shr(io.in.a.bits.source, 12)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0)
node _T_199 = shr(io.in.a.bits.source, 12)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0)
node _T_240 = shr(io.in.a.bits.source, 12)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0)
node _T_283 = shr(io.in.a.bits.source, 12)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_292 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_293 = and(_T_291, _T_292)
node _T_294 = or(UInt<1>(0h0), _T_293)
node _T_295 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = and(_T_294, _T_299)
node _T_301 = or(UInt<1>(0h0), _T_300)
node _T_302 = and(_T_290, _T_301)
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_T_302, UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_302, UInt<1>(0h1), "") : assert_36
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(is_aligned, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_312 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_T_312, UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_312, UInt<1>(0h1), "") : assert_39
node _T_316 = eq(io.in.a.bits.mask, mask)
node _T_317 = asUInt(reset)
node _T_318 = eq(_T_317, UInt<1>(0h0))
when _T_318 :
node _T_319 = eq(_T_316, UInt<1>(0h0))
when _T_319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_316, UInt<1>(0h1), "") : assert_40
node _T_320 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_320 :
node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_322 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_323 = and(_T_321, _T_322)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0)
node _T_324 = shr(io.in.a.bits.source, 12)
node _T_325 = eq(_T_324, UInt<1>(0h0))
node _T_326 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_327 = and(_T_325, _T_326)
node _T_328 = leq(uncommonBits_7, UInt<12>(0h80f))
node _T_329 = and(_T_327, _T_328)
node _T_330 = and(_T_323, _T_329)
node _T_331 = or(UInt<1>(0h0), _T_330)
node _T_332 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_333 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = or(UInt<1>(0h0), _T_334)
node _T_336 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<13>(0h1000)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = and(_T_335, _T_340)
node _T_342 = or(UInt<1>(0h0), _T_341)
node _T_343 = and(_T_331, _T_342)
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(_T_343, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_343, UInt<1>(0h1), "") : assert_41
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(is_aligned, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_353 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(_T_353, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_353, UInt<1>(0h1), "") : assert_44
node _T_357 = eq(io.in.a.bits.mask, mask)
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_357, UInt<1>(0h1), "") : assert_45
node _T_361 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_361 :
node _T_362 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_363 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_364 = and(_T_362, _T_363)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0)
node _T_365 = shr(io.in.a.bits.source, 12)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_368 = and(_T_366, _T_367)
node _T_369 = leq(uncommonBits_8, UInt<12>(0h80f))
node _T_370 = and(_T_368, _T_369)
node _T_371 = and(_T_364, _T_370)
node _T_372 = or(UInt<1>(0h0), _T_371)
node _T_373 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_375 = cvt(_T_374)
node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000)))
node _T_377 = asSInt(_T_376)
node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0)))
node _T_379 = and(_T_373, _T_378)
node _T_380 = or(UInt<1>(0h0), _T_379)
node _T_381 = and(_T_372, _T_380)
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_381, UInt<1>(0h1), "") : assert_46
node _T_385 = asUInt(reset)
node _T_386 = eq(_T_385, UInt<1>(0h0))
when _T_386 :
node _T_387 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(is_aligned, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_391 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_391, UInt<1>(0h1), "") : assert_49
node _T_395 = eq(io.in.a.bits.mask, mask)
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_T_395, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_395, UInt<1>(0h1), "") : assert_50
node _T_399 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_399, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_403 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_403, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 12)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_407 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_407 :
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_411 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_411, UInt<1>(0h1), "") : assert_54
node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_415, UInt<1>(0h1), "") : assert_55
node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_419, UInt<1>(0h1), "") : assert_56
node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_424 = asUInt(reset)
node _T_425 = eq(_T_424, UInt<1>(0h0))
when _T_425 :
node _T_426 = eq(_T_423, UInt<1>(0h0))
when _T_426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_423, UInt<1>(0h1), "") : assert_57
node _T_427 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_427 :
node _T_428 = asUInt(reset)
node _T_429 = eq(_T_428, UInt<1>(0h0))
when _T_429 :
node _T_430 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(sink_ok, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_434 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_434, UInt<1>(0h1), "") : assert_60
node _T_438 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_T_438, UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_438, UInt<1>(0h1), "") : assert_61
node _T_442 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_442, UInt<1>(0h1), "") : assert_62
node _T_446 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_446, UInt<1>(0h1), "") : assert_63
node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_451 = or(UInt<1>(0h0), _T_450)
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(_T_451, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_451, UInt<1>(0h1), "") : assert_64
node _T_455 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_455 :
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(sink_ok, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_462 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_462, UInt<1>(0h1), "") : assert_67
node _T_466 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_466, UInt<1>(0h1), "") : assert_68
node _T_470 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_471 = asUInt(reset)
node _T_472 = eq(_T_471, UInt<1>(0h0))
when _T_472 :
node _T_473 = eq(_T_470, UInt<1>(0h0))
when _T_473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_470, UInt<1>(0h1), "") : assert_69
node _T_474 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_475 = or(_T_474, io.in.d.bits.corrupt)
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_475, UInt<1>(0h1), "") : assert_70
node _T_479 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_480 = or(UInt<1>(0h0), _T_479)
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_480, UInt<1>(0h1), "") : assert_71
node _T_484 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_484 :
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_488 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_488, UInt<1>(0h1), "") : assert_73
node _T_492 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_492, UInt<1>(0h1), "") : assert_74
node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_497 = or(UInt<1>(0h0), _T_496)
node _T_498 = asUInt(reset)
node _T_499 = eq(_T_498, UInt<1>(0h0))
when _T_499 :
node _T_500 = eq(_T_497, UInt<1>(0h0))
when _T_500 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_497, UInt<1>(0h1), "") : assert_75
node _T_501 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_501 :
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_505 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_505, UInt<1>(0h1), "") : assert_77
node _T_509 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_510 = or(_T_509, io.in.d.bits.corrupt)
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_510, UInt<1>(0h1), "") : assert_78
node _T_514 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_515 = or(UInt<1>(0h0), _T_514)
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(_T_515, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_515, UInt<1>(0h1), "") : assert_79
node _T_519 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_519 :
node _T_520 = asUInt(reset)
node _T_521 = eq(_T_520, UInt<1>(0h0))
when _T_521 :
node _T_522 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_523 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_523, UInt<1>(0h1), "") : assert_81
node _T_527 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_528 = asUInt(reset)
node _T_529 = eq(_T_528, UInt<1>(0h0))
when _T_529 :
node _T_530 = eq(_T_527, UInt<1>(0h0))
when _T_530 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_527, UInt<1>(0h1), "") : assert_82
node _T_531 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_532 = or(UInt<1>(0h0), _T_531)
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_532, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<12>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_536 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_537 = asUInt(reset)
node _T_538 = eq(_T_537, UInt<1>(0h0))
when _T_538 :
node _T_539 = eq(_T_536, UInt<1>(0h0))
when _T_539 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_536, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<12>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_540 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(_T_540, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_540, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_544 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_544, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_548 = eq(a_first, UInt<1>(0h0))
node _T_549 = and(io.in.a.valid, _T_548)
when _T_549 :
node _T_550 = eq(io.in.a.bits.opcode, opcode)
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_550, UInt<1>(0h1), "") : assert_87
node _T_554 = eq(io.in.a.bits.param, param)
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(_T_554, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_554, UInt<1>(0h1), "") : assert_88
node _T_558 = eq(io.in.a.bits.size, size)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_558, UInt<1>(0h1), "") : assert_89
node _T_562 = eq(io.in.a.bits.source, source)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_562, UInt<1>(0h1), "") : assert_90
node _T_566 = eq(io.in.a.bits.address, address)
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(_T_566, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_566, UInt<1>(0h1), "") : assert_91
node _T_570 = and(io.in.a.ready, io.in.a.valid)
node _T_571 = and(_T_570, a_first)
when _T_571 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_572 = eq(d_first, UInt<1>(0h0))
node _T_573 = and(io.in.d.valid, _T_572)
when _T_573 :
node _T_574 = eq(io.in.d.bits.opcode, opcode_1)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_574, UInt<1>(0h1), "") : assert_92
node _T_578 = eq(io.in.d.bits.param, param_1)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_578, UInt<1>(0h1), "") : assert_93
node _T_582 = eq(io.in.d.bits.size, size_1)
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_582, UInt<1>(0h1), "") : assert_94
node _T_586 = eq(io.in.d.bits.source, source_1)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_586, UInt<1>(0h1), "") : assert_95
node _T_590 = eq(io.in.d.bits.sink, sink)
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_590, UInt<1>(0h1), "") : assert_96
node _T_594 = eq(io.in.d.bits.denied, denied)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_594, UInt<1>(0h1), "") : assert_97
node _T_598 = and(io.in.d.ready, io.in.d.valid)
node _T_599 = and(_T_598, d_first)
when _T_599 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2064>
connect a_set, UInt<2064>(0h0)
wire a_set_wo_ready : UInt<2064>
connect a_set_wo_ready, UInt<2064>(0h0)
wire a_opcodes_set : UInt<8256>
connect a_opcodes_set, UInt<8256>(0h0)
wire a_sizes_set : UInt<8256>
connect a_sizes_set, UInt<8256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_600 = and(io.in.a.valid, a_first_1)
node _T_601 = and(_T_600, UInt<1>(0h1))
when _T_601 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_602 = and(io.in.a.ready, io.in.a.valid)
node _T_603 = and(_T_602, a_first_1)
node _T_604 = and(_T_603, UInt<1>(0h1))
when _T_604 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_605 = dshr(inflight, io.in.a.bits.source)
node _T_606 = bits(_T_605, 0, 0)
node _T_607 = eq(_T_606, UInt<1>(0h0))
node _T_608 = asUInt(reset)
node _T_609 = eq(_T_608, UInt<1>(0h0))
when _T_609 :
node _T_610 = eq(_T_607, UInt<1>(0h0))
when _T_610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_607, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<2064>
connect d_clr, UInt<2064>(0h0)
wire d_clr_wo_ready : UInt<2064>
connect d_clr_wo_ready, UInt<2064>(0h0)
wire d_opcodes_clr : UInt<8256>
connect d_opcodes_clr, UInt<8256>(0h0)
wire d_sizes_clr : UInt<8256>
connect d_sizes_clr, UInt<8256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_611 = and(io.in.d.valid, d_first_1)
node _T_612 = and(_T_611, UInt<1>(0h1))
node _T_613 = eq(d_release_ack, UInt<1>(0h0))
node _T_614 = and(_T_612, _T_613)
when _T_614 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_615 = and(io.in.d.ready, io.in.d.valid)
node _T_616 = and(_T_615, d_first_1)
node _T_617 = and(_T_616, UInt<1>(0h1))
node _T_618 = eq(d_release_ack, UInt<1>(0h0))
node _T_619 = and(_T_617, _T_618)
when _T_619 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_620 = and(io.in.d.valid, d_first_1)
node _T_621 = and(_T_620, UInt<1>(0h1))
node _T_622 = eq(d_release_ack, UInt<1>(0h0))
node _T_623 = and(_T_621, _T_622)
when _T_623 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_624 = dshr(inflight, io.in.d.bits.source)
node _T_625 = bits(_T_624, 0, 0)
node _T_626 = or(_T_625, same_cycle_resp)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_626, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_630 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_631 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_632 = or(_T_630, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_632, UInt<1>(0h1), "") : assert_100
node _T_636 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_636, UInt<1>(0h1), "") : assert_101
else :
node _T_640 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_641 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_642 = or(_T_640, _T_641)
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_642, UInt<1>(0h1), "") : assert_102
node _T_646 = eq(io.in.d.bits.size, a_size_lookup)
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_646, UInt<1>(0h1), "") : assert_103
node _T_650 = and(io.in.d.valid, d_first_1)
node _T_651 = and(_T_650, a_first_1)
node _T_652 = and(_T_651, io.in.a.valid)
node _T_653 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_654 = and(_T_652, _T_653)
node _T_655 = eq(d_release_ack, UInt<1>(0h0))
node _T_656 = and(_T_654, _T_655)
when _T_656 :
node _T_657 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_658 = or(_T_657, io.in.a.ready)
node _T_659 = asUInt(reset)
node _T_660 = eq(_T_659, UInt<1>(0h0))
when _T_660 :
node _T_661 = eq(_T_658, UInt<1>(0h0))
when _T_661 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_658, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_124
node _T_662 = orr(inflight)
node _T_663 = eq(_T_662, UInt<1>(0h0))
node _T_664 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_665 = or(_T_663, _T_664)
node _T_666 = lt(watchdog, plusarg_reader.out)
node _T_667 = or(_T_665, _T_666)
node _T_668 = asUInt(reset)
node _T_669 = eq(_T_668, UInt<1>(0h0))
when _T_669 :
node _T_670 = eq(_T_667, UInt<1>(0h0))
when _T_670 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_667, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_671 = and(io.in.a.ready, io.in.a.valid)
node _T_672 = and(io.in.d.ready, io.in.d.valid)
node _T_673 = or(_T_671, _T_672)
when _T_673 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<12>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2064>
connect c_set, UInt<2064>(0h0)
wire c_set_wo_ready : UInt<2064>
connect c_set_wo_ready, UInt<2064>(0h0)
wire c_opcodes_set : UInt<8256>
connect c_opcodes_set, UInt<8256>(0h0)
wire c_sizes_set : UInt<8256>
connect c_sizes_set, UInt<8256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<12>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_674 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<12>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_675 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<12>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_679 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_680 = and(_T_679, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<12>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_681 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_682 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_683 = and(_T_681, _T_682)
node _T_684 = and(_T_680, _T_683)
when _T_684 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<12>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_685 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_686 = bits(_T_685, 0, 0)
node _T_687 = eq(_T_686, UInt<1>(0h0))
node _T_688 = asUInt(reset)
node _T_689 = eq(_T_688, UInt<1>(0h0))
when _T_689 :
node _T_690 = eq(_T_687, UInt<1>(0h0))
when _T_690 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_687, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2064>
connect d_clr_1, UInt<2064>(0h0)
wire d_clr_wo_ready_1 : UInt<2064>
connect d_clr_wo_ready_1, UInt<2064>(0h0)
wire d_opcodes_clr_1 : UInt<8256>
connect d_opcodes_clr_1, UInt<8256>(0h0)
wire d_sizes_clr_1 : UInt<8256>
connect d_sizes_clr_1, UInt<8256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_691 = and(io.in.d.valid, d_first_2)
node _T_692 = and(_T_691, UInt<1>(0h1))
node _T_693 = and(_T_692, d_release_ack_1)
when _T_693 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_694 = and(io.in.d.ready, io.in.d.valid)
node _T_695 = and(_T_694, d_first_2)
node _T_696 = and(_T_695, UInt<1>(0h1))
node _T_697 = and(_T_696, d_release_ack_1)
when _T_697 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_698 = and(io.in.d.valid, d_first_2)
node _T_699 = and(_T_698, UInt<1>(0h1))
node _T_700 = and(_T_699, d_release_ack_1)
when _T_700 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_701 = dshr(inflight_1, io.in.d.bits.source)
node _T_702 = bits(_T_701, 0, 0)
node _T_703 = or(_T_702, same_cycle_resp_1)
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_703, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<12>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_707 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_707, UInt<1>(0h1), "") : assert_108
else :
node _T_711 = eq(io.in.d.bits.size, c_size_lookup)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_711, UInt<1>(0h1), "") : assert_109
node _T_715 = and(io.in.d.valid, d_first_2)
node _T_716 = and(_T_715, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<12>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_717 = and(_T_716, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<12>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_718 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_719 = and(_T_717, _T_718)
node _T_720 = and(_T_719, d_release_ack_1)
node _T_721 = eq(c_probe_ack, UInt<1>(0h0))
node _T_722 = and(_T_720, _T_721)
when _T_722 :
node _T_723 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<12>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_724 = or(_T_723, _WIRE_23.ready)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_724, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_125
node _T_728 = orr(inflight_1)
node _T_729 = eq(_T_728, UInt<1>(0h0))
node _T_730 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_731 = or(_T_729, _T_730)
node _T_732 = lt(watchdog_1, plusarg_reader_1.out)
node _T_733 = or(_T_731, _T_732)
node _T_734 = asUInt(reset)
node _T_735 = eq(_T_734, UInt<1>(0h0))
when _T_735 :
node _T_736 = eq(_T_733, UInt<1>(0h0))
when _T_736 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/icenet/src/main/scala/NIC.scala:443:38)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_733, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<12>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_737 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_738 = and(io.in.d.ready, io.in.d.valid)
node _T_739 = or(_T_737, _T_738)
when _T_739 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_61( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52]
wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79]
wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77]
wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35]
wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35]
wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34]
wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34]
wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34]
wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_671 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_671; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_671; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [11:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_739 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_739; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_739; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_739; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [11:0] source_1; // @[Monitor.scala:541:22]
reg denied; // @[Monitor.scala:543:22]
reg [2063:0] inflight; // @[Monitor.scala:614:27]
reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [2063:0] a_set; // @[Monitor.scala:626:34]
wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [4095:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_604 = _T_671 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_604 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_604 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_604 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_604 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_604 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [2063:0] d_clr; // @[Monitor.scala:664:34]
wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_650 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_650 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_619 = _T_739 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_619 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_619 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_619 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [2063:0] inflight_1; // @[Monitor.scala:726:35]
wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [2063:0] d_clr_1; // @[Monitor.scala:774:34]
wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_715 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_715 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_697 = _T_739 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_697 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_697 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_697 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113]
wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset // @[Crossing.scala:41:9]
);
wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9]
wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9]
wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
AsyncResetRegVec_w1_i0 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset)
); // @[AsyncResetReg.scala:86:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T = shr(io.in.a.bits.source, 3)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h7))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 3)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<3>(0h7))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_4 = shr(io.in.a.bits.source, 3)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<3>(0h7))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_17 = shr(io.in.a.bits.source, 3)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<3>(0h7))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _T_30 = and(_T_16, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_30, UInt<1>(0h1), "") : assert_1
node _T_34 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_34 :
node _T_35 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_36 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_37 = and(_T_35, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0)
node _T_38 = shr(io.in.a.bits.source, 3)
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<3>(0h7))
node _T_43 = and(_T_41, _T_42)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0)
node _T_44 = shr(io.in.a.bits.source, 3)
node _T_45 = eq(_T_44, UInt<1>(0h1))
node _T_46 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_47 = and(_T_45, _T_46)
node _T_48 = leq(uncommonBits_3, UInt<3>(0h7))
node _T_49 = and(_T_47, _T_48)
node _T_50 = or(_T_43, _T_49)
node _T_51 = and(_T_37, _T_50)
node _T_52 = or(UInt<1>(0h0), _T_51)
node _T_53 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_54 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<14>(0h2000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<18>(0h2f000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<17>(0h10000)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<27>(0h4000000)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<13>(0h1000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<30>(0h20000000)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_95 = cvt(_T_94)
node _T_96 = and(_T_95, asSInt(UInt<15>(0h4000)))
node _T_97 = asSInt(_T_96)
node _T_98 = eq(_T_97, asSInt(UInt<1>(0h0)))
node _T_99 = or(_T_58, _T_63)
node _T_100 = or(_T_99, _T_68)
node _T_101 = or(_T_100, _T_73)
node _T_102 = or(_T_101, _T_78)
node _T_103 = or(_T_102, _T_83)
node _T_104 = or(_T_103, _T_88)
node _T_105 = or(_T_104, _T_93)
node _T_106 = or(_T_105, _T_98)
node _T_107 = and(_T_53, _T_106)
node _T_108 = or(UInt<1>(0h0), _T_107)
node _T_109 = and(_T_52, _T_108)
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_109, UInt<1>(0h1), "") : assert_2
node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_115 = and(_T_113, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<14>(0h2000)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<13>(0h1000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<18>(0h2f000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<27>(0h4000000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<13>(0h1000)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_153 = cvt(_T_152)
node _T_154 = and(_T_153, asSInt(UInt<30>(0h20000000)))
node _T_155 = asSInt(_T_154)
node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_158 = cvt(_T_157)
node _T_159 = and(_T_158, asSInt(UInt<15>(0h4000)))
node _T_160 = asSInt(_T_159)
node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0)))
node _T_162 = or(_T_121, _T_126)
node _T_163 = or(_T_162, _T_131)
node _T_164 = or(_T_163, _T_136)
node _T_165 = or(_T_164, _T_141)
node _T_166 = or(_T_165, _T_146)
node _T_167 = or(_T_166, _T_151)
node _T_168 = or(_T_167, _T_156)
node _T_169 = or(_T_168, _T_161)
node _T_170 = and(_T_116, _T_169)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = and(UInt<1>(0h0), _T_171)
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(_T_172, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_172, UInt<1>(0h1), "") : assert_3
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(source_ok, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_179 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_179, UInt<1>(0h1), "") : assert_5
node _T_183 = asUInt(reset)
node _T_184 = eq(_T_183, UInt<1>(0h0))
when _T_184 :
node _T_185 = eq(is_aligned, UInt<1>(0h0))
when _T_185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_186 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_187 = asUInt(reset)
node _T_188 = eq(_T_187, UInt<1>(0h0))
when _T_188 :
node _T_189 = eq(_T_186, UInt<1>(0h0))
when _T_189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_186, UInt<1>(0h1), "") : assert_7
node _T_190 = not(io.in.a.bits.mask)
node _T_191 = eq(_T_190, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_191, UInt<1>(0h1), "") : assert_8
node _T_195 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_196 = asUInt(reset)
node _T_197 = eq(_T_196, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(_T_195, UInt<1>(0h0))
when _T_198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_195, UInt<1>(0h1), "") : assert_9
node _T_199 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_199 :
node _T_200 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_201 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_202 = and(_T_200, _T_201)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_203 = shr(io.in.a.bits.source, 3)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_206 = and(_T_204, _T_205)
node _T_207 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_208 = and(_T_206, _T_207)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_209 = shr(io.in.a.bits.source, 3)
node _T_210 = eq(_T_209, UInt<1>(0h1))
node _T_211 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_212 = and(_T_210, _T_211)
node _T_213 = leq(uncommonBits_5, UInt<3>(0h7))
node _T_214 = and(_T_212, _T_213)
node _T_215 = or(_T_208, _T_214)
node _T_216 = and(_T_202, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_219 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_220 = cvt(_T_219)
node _T_221 = and(_T_220, asSInt(UInt<14>(0h2000)))
node _T_222 = asSInt(_T_221)
node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0)))
node _T_224 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_225 = cvt(_T_224)
node _T_226 = and(_T_225, asSInt(UInt<13>(0h1000)))
node _T_227 = asSInt(_T_226)
node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_230 = cvt(_T_229)
node _T_231 = and(_T_230, asSInt(UInt<17>(0h10000)))
node _T_232 = asSInt(_T_231)
node _T_233 = eq(_T_232, asSInt(UInt<1>(0h0)))
node _T_234 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<18>(0h2f000)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_240 = cvt(_T_239)
node _T_241 = and(_T_240, asSInt(UInt<17>(0h10000)))
node _T_242 = asSInt(_T_241)
node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0)))
node _T_244 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_245 = cvt(_T_244)
node _T_246 = and(_T_245, asSInt(UInt<27>(0h4000000)))
node _T_247 = asSInt(_T_246)
node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0)))
node _T_249 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<13>(0h1000)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<30>(0h20000000)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<15>(0h4000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = or(_T_223, _T_228)
node _T_265 = or(_T_264, _T_233)
node _T_266 = or(_T_265, _T_238)
node _T_267 = or(_T_266, _T_243)
node _T_268 = or(_T_267, _T_248)
node _T_269 = or(_T_268, _T_253)
node _T_270 = or(_T_269, _T_258)
node _T_271 = or(_T_270, _T_263)
node _T_272 = and(_T_218, _T_271)
node _T_273 = or(UInt<1>(0h0), _T_272)
node _T_274 = and(_T_217, _T_273)
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_274, UInt<1>(0h1), "") : assert_10
node _T_278 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_279 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_280 = and(_T_278, _T_279)
node _T_281 = or(UInt<1>(0h0), _T_280)
node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_283 = cvt(_T_282)
node _T_284 = and(_T_283, asSInt(UInt<14>(0h2000)))
node _T_285 = asSInt(_T_284)
node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0)))
node _T_287 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_288 = cvt(_T_287)
node _T_289 = and(_T_288, asSInt(UInt<13>(0h1000)))
node _T_290 = asSInt(_T_289)
node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0)))
node _T_292 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_298 = cvt(_T_297)
node _T_299 = and(_T_298, asSInt(UInt<18>(0h2f000)))
node _T_300 = asSInt(_T_299)
node _T_301 = eq(_T_300, asSInt(UInt<1>(0h0)))
node _T_302 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_303 = cvt(_T_302)
node _T_304 = and(_T_303, asSInt(UInt<17>(0h10000)))
node _T_305 = asSInt(_T_304)
node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0)))
node _T_307 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<27>(0h4000000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<30>(0h20000000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<15>(0h4000)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = or(_T_286, _T_291)
node _T_328 = or(_T_327, _T_296)
node _T_329 = or(_T_328, _T_301)
node _T_330 = or(_T_329, _T_306)
node _T_331 = or(_T_330, _T_311)
node _T_332 = or(_T_331, _T_316)
node _T_333 = or(_T_332, _T_321)
node _T_334 = or(_T_333, _T_326)
node _T_335 = and(_T_281, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(UInt<1>(0h0), _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_337, UInt<1>(0h1), "") : assert_11
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(source_ok, UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_344 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_345 = asUInt(reset)
node _T_346 = eq(_T_345, UInt<1>(0h0))
when _T_346 :
node _T_347 = eq(_T_344, UInt<1>(0h0))
when _T_347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_344, UInt<1>(0h1), "") : assert_13
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(is_aligned, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_351 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_351, UInt<1>(0h1), "") : assert_15
node _T_355 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_355, UInt<1>(0h1), "") : assert_16
node _T_359 = not(io.in.a.bits.mask)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = asUInt(reset)
node _T_362 = eq(_T_361, UInt<1>(0h0))
when _T_362 :
node _T_363 = eq(_T_360, UInt<1>(0h0))
when _T_363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_360, UInt<1>(0h1), "") : assert_17
node _T_364 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_365 = asUInt(reset)
node _T_366 = eq(_T_365, UInt<1>(0h0))
when _T_366 :
node _T_367 = eq(_T_364, UInt<1>(0h0))
when _T_367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_364, UInt<1>(0h1), "") : assert_18
node _T_368 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_368 :
node _T_369 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_370 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_371 = and(_T_369, _T_370)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_372 = shr(io.in.a.bits.source, 3)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_375 = and(_T_373, _T_374)
node _T_376 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_377 = and(_T_375, _T_376)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_378 = shr(io.in.a.bits.source, 3)
node _T_379 = eq(_T_378, UInt<1>(0h1))
node _T_380 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_381 = and(_T_379, _T_380)
node _T_382 = leq(uncommonBits_7, UInt<3>(0h7))
node _T_383 = and(_T_381, _T_382)
node _T_384 = or(_T_377, _T_383)
node _T_385 = and(_T_371, _T_384)
node _T_386 = or(UInt<1>(0h0), _T_385)
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_386, UInt<1>(0h1), "") : assert_19
node _T_390 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_391 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_392 = and(_T_390, _T_391)
node _T_393 = or(UInt<1>(0h0), _T_392)
node _T_394 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<13>(0h1000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = and(_T_393, _T_398)
node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_401 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_402 = and(_T_400, _T_401)
node _T_403 = or(UInt<1>(0h0), _T_402)
node _T_404 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<14>(0h2000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<17>(0h10000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<18>(0h2f000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<17>(0h10000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<27>(0h4000000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<13>(0h1000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<30>(0h20000000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<15>(0h4000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = or(_T_408, _T_413)
node _T_445 = or(_T_444, _T_418)
node _T_446 = or(_T_445, _T_423)
node _T_447 = or(_T_446, _T_428)
node _T_448 = or(_T_447, _T_433)
node _T_449 = or(_T_448, _T_438)
node _T_450 = or(_T_449, _T_443)
node _T_451 = and(_T_403, _T_450)
node _T_452 = or(UInt<1>(0h0), _T_399)
node _T_453 = or(_T_452, _T_451)
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_453, UInt<1>(0h1), "") : assert_20
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(source_ok, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(is_aligned, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_463 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_463, UInt<1>(0h1), "") : assert_23
node _T_467 = eq(io.in.a.bits.mask, mask)
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_467, UInt<1>(0h1), "") : assert_24
node _T_471 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_471, UInt<1>(0h1), "") : assert_25
node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_475 :
node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_478 = and(_T_476, _T_477)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0)
node _T_479 = shr(io.in.a.bits.source, 3)
node _T_480 = eq(_T_479, UInt<1>(0h0))
node _T_481 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_482 = and(_T_480, _T_481)
node _T_483 = leq(uncommonBits_8, UInt<3>(0h7))
node _T_484 = and(_T_482, _T_483)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0)
node _T_485 = shr(io.in.a.bits.source, 3)
node _T_486 = eq(_T_485, UInt<1>(0h1))
node _T_487 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_488 = and(_T_486, _T_487)
node _T_489 = leq(uncommonBits_9, UInt<3>(0h7))
node _T_490 = and(_T_488, _T_489)
node _T_491 = or(_T_484, _T_490)
node _T_492 = and(_T_478, _T_491)
node _T_493 = or(UInt<1>(0h0), _T_492)
node _T_494 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_495 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_496 = and(_T_494, _T_495)
node _T_497 = or(UInt<1>(0h0), _T_496)
node _T_498 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_499 = cvt(_T_498)
node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000)))
node _T_501 = asSInt(_T_500)
node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0)))
node _T_503 = and(_T_497, _T_502)
node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_505 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_506 = and(_T_504, _T_505)
node _T_507 = or(UInt<1>(0h0), _T_506)
node _T_508 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_509 = cvt(_T_508)
node _T_510 = and(_T_509, asSInt(UInt<14>(0h2000)))
node _T_511 = asSInt(_T_510)
node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0)))
node _T_513 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_514 = cvt(_T_513)
node _T_515 = and(_T_514, asSInt(UInt<18>(0h2f000)))
node _T_516 = asSInt(_T_515)
node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0)))
node _T_518 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_519 = cvt(_T_518)
node _T_520 = and(_T_519, asSInt(UInt<17>(0h10000)))
node _T_521 = asSInt(_T_520)
node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0)))
node _T_523 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_524 = cvt(_T_523)
node _T_525 = and(_T_524, asSInt(UInt<27>(0h4000000)))
node _T_526 = asSInt(_T_525)
node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0)))
node _T_528 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_529 = cvt(_T_528)
node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000)))
node _T_531 = asSInt(_T_530)
node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0)))
node _T_533 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_534 = cvt(_T_533)
node _T_535 = and(_T_534, asSInt(UInt<15>(0h4000)))
node _T_536 = asSInt(_T_535)
node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0)))
node _T_538 = or(_T_512, _T_517)
node _T_539 = or(_T_538, _T_522)
node _T_540 = or(_T_539, _T_527)
node _T_541 = or(_T_540, _T_532)
node _T_542 = or(_T_541, _T_537)
node _T_543 = and(_T_507, _T_542)
node _T_544 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_545 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_546 = cvt(_T_545)
node _T_547 = and(_T_546, asSInt(UInt<17>(0h10000)))
node _T_548 = asSInt(_T_547)
node _T_549 = eq(_T_548, asSInt(UInt<1>(0h0)))
node _T_550 = and(_T_544, _T_549)
node _T_551 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_552 = leq(io.in.a.bits.size, UInt<4>(0h8))
node _T_553 = and(_T_551, _T_552)
node _T_554 = or(UInt<1>(0h0), _T_553)
node _T_555 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_556 = cvt(_T_555)
node _T_557 = and(_T_556, asSInt(UInt<30>(0h20000000)))
node _T_558 = asSInt(_T_557)
node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0)))
node _T_560 = and(_T_554, _T_559)
node _T_561 = or(UInt<1>(0h0), _T_503)
node _T_562 = or(_T_561, _T_543)
node _T_563 = or(_T_562, _T_550)
node _T_564 = or(_T_563, _T_560)
node _T_565 = and(_T_493, _T_564)
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(_T_565, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_565, UInt<1>(0h1), "") : assert_26
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(source_ok, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(is_aligned, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_575 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_576 = asUInt(reset)
node _T_577 = eq(_T_576, UInt<1>(0h0))
when _T_577 :
node _T_578 = eq(_T_575, UInt<1>(0h0))
when _T_578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_575, UInt<1>(0h1), "") : assert_29
node _T_579 = eq(io.in.a.bits.mask, mask)
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_579, UInt<1>(0h1), "") : assert_30
node _T_583 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_583 :
node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_585 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0)
node _T_587 = shr(io.in.a.bits.source, 3)
node _T_588 = eq(_T_587, UInt<1>(0h0))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_10, UInt<3>(0h7))
node _T_592 = and(_T_590, _T_591)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_593 = shr(io.in.a.bits.source, 3)
node _T_594 = eq(_T_593, UInt<1>(0h1))
node _T_595 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_596 = and(_T_594, _T_595)
node _T_597 = leq(uncommonBits_11, UInt<3>(0h7))
node _T_598 = and(_T_596, _T_597)
node _T_599 = or(_T_592, _T_598)
node _T_600 = and(_T_586, _T_599)
node _T_601 = or(UInt<1>(0h0), _T_600)
node _T_602 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_603 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_604 = and(_T_602, _T_603)
node _T_605 = or(UInt<1>(0h0), _T_604)
node _T_606 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_607 = cvt(_T_606)
node _T_608 = and(_T_607, asSInt(UInt<13>(0h1000)))
node _T_609 = asSInt(_T_608)
node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0)))
node _T_611 = and(_T_605, _T_610)
node _T_612 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_613 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_614 = and(_T_612, _T_613)
node _T_615 = or(UInt<1>(0h0), _T_614)
node _T_616 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_617 = cvt(_T_616)
node _T_618 = and(_T_617, asSInt(UInt<14>(0h2000)))
node _T_619 = asSInt(_T_618)
node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0)))
node _T_621 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_622 = cvt(_T_621)
node _T_623 = and(_T_622, asSInt(UInt<18>(0h2f000)))
node _T_624 = asSInt(_T_623)
node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0)))
node _T_626 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_627 = cvt(_T_626)
node _T_628 = and(_T_627, asSInt(UInt<17>(0h10000)))
node _T_629 = asSInt(_T_628)
node _T_630 = eq(_T_629, asSInt(UInt<1>(0h0)))
node _T_631 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_632 = cvt(_T_631)
node _T_633 = and(_T_632, asSInt(UInt<27>(0h4000000)))
node _T_634 = asSInt(_T_633)
node _T_635 = eq(_T_634, asSInt(UInt<1>(0h0)))
node _T_636 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_637 = cvt(_T_636)
node _T_638 = and(_T_637, asSInt(UInt<13>(0h1000)))
node _T_639 = asSInt(_T_638)
node _T_640 = eq(_T_639, asSInt(UInt<1>(0h0)))
node _T_641 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_642 = cvt(_T_641)
node _T_643 = and(_T_642, asSInt(UInt<15>(0h4000)))
node _T_644 = asSInt(_T_643)
node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0)))
node _T_646 = or(_T_620, _T_625)
node _T_647 = or(_T_646, _T_630)
node _T_648 = or(_T_647, _T_635)
node _T_649 = or(_T_648, _T_640)
node _T_650 = or(_T_649, _T_645)
node _T_651 = and(_T_615, _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<4>(0h8))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<30>(0h20000000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = and(_T_662, _T_667)
node _T_669 = or(UInt<1>(0h0), _T_611)
node _T_670 = or(_T_669, _T_651)
node _T_671 = or(_T_670, _T_658)
node _T_672 = or(_T_671, _T_668)
node _T_673 = and(_T_601, _T_672)
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_673, UInt<1>(0h1), "") : assert_31
node _T_677 = asUInt(reset)
node _T_678 = eq(_T_677, UInt<1>(0h0))
when _T_678 :
node _T_679 = eq(source_ok, UInt<1>(0h0))
when _T_679 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(is_aligned, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_683 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_684 = asUInt(reset)
node _T_685 = eq(_T_684, UInt<1>(0h0))
when _T_685 :
node _T_686 = eq(_T_683, UInt<1>(0h0))
when _T_686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_683, UInt<1>(0h1), "") : assert_34
node _T_687 = not(mask)
node _T_688 = and(io.in.a.bits.mask, _T_687)
node _T_689 = eq(_T_688, UInt<1>(0h0))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_689, UInt<1>(0h1), "") : assert_35
node _T_693 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_693 :
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_696 = and(_T_694, _T_695)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_697 = shr(io.in.a.bits.source, 3)
node _T_698 = eq(_T_697, UInt<1>(0h0))
node _T_699 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_700 = and(_T_698, _T_699)
node _T_701 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_702 = and(_T_700, _T_701)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_703 = shr(io.in.a.bits.source, 3)
node _T_704 = eq(_T_703, UInt<1>(0h1))
node _T_705 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_706 = and(_T_704, _T_705)
node _T_707 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_708 = and(_T_706, _T_707)
node _T_709 = or(_T_702, _T_708)
node _T_710 = and(_T_696, _T_709)
node _T_711 = or(UInt<1>(0h0), _T_710)
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_714 = and(_T_712, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<14>(0h2000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<13>(0h1000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<18>(0h2f000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<17>(0h10000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<27>(0h4000000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<15>(0h4000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = or(_T_720, _T_725)
node _T_752 = or(_T_751, _T_730)
node _T_753 = or(_T_752, _T_735)
node _T_754 = or(_T_753, _T_740)
node _T_755 = or(_T_754, _T_745)
node _T_756 = or(_T_755, _T_750)
node _T_757 = and(_T_715, _T_756)
node _T_758 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_759 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_765 = cvt(_T_764)
node _T_766 = and(_T_765, asSInt(UInt<30>(0h20000000)))
node _T_767 = asSInt(_T_766)
node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0)))
node _T_769 = or(_T_763, _T_768)
node _T_770 = and(_T_758, _T_769)
node _T_771 = or(UInt<1>(0h0), _T_757)
node _T_772 = or(_T_771, _T_770)
node _T_773 = and(_T_711, _T_772)
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_773, UInt<1>(0h1), "") : assert_36
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(source_ok, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_780 = asUInt(reset)
node _T_781 = eq(_T_780, UInt<1>(0h0))
when _T_781 :
node _T_782 = eq(is_aligned, UInt<1>(0h0))
when _T_782 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_783 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_784 = asUInt(reset)
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(_T_783, UInt<1>(0h0))
when _T_786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_783, UInt<1>(0h1), "") : assert_39
node _T_787 = eq(io.in.a.bits.mask, mask)
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_T_787, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_787, UInt<1>(0h1), "") : assert_40
node _T_791 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_791 :
node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_793 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_794 = and(_T_792, _T_793)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0)
node _T_795 = shr(io.in.a.bits.source, 3)
node _T_796 = eq(_T_795, UInt<1>(0h0))
node _T_797 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_798 = and(_T_796, _T_797)
node _T_799 = leq(uncommonBits_14, UInt<3>(0h7))
node _T_800 = and(_T_798, _T_799)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0)
node _T_801 = shr(io.in.a.bits.source, 3)
node _T_802 = eq(_T_801, UInt<1>(0h1))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_15, UInt<3>(0h7))
node _T_806 = and(_T_804, _T_805)
node _T_807 = or(_T_800, _T_806)
node _T_808 = and(_T_794, _T_807)
node _T_809 = or(UInt<1>(0h0), _T_808)
node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_811 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_812 = and(_T_810, _T_811)
node _T_813 = or(UInt<1>(0h0), _T_812)
node _T_814 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_815 = cvt(_T_814)
node _T_816 = and(_T_815, asSInt(UInt<14>(0h2000)))
node _T_817 = asSInt(_T_816)
node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0)))
node _T_819 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_820 = cvt(_T_819)
node _T_821 = and(_T_820, asSInt(UInt<13>(0h1000)))
node _T_822 = asSInt(_T_821)
node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0)))
node _T_824 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_825 = cvt(_T_824)
node _T_826 = and(_T_825, asSInt(UInt<18>(0h2f000)))
node _T_827 = asSInt(_T_826)
node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0)))
node _T_829 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<17>(0h10000)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<27>(0h4000000)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<15>(0h4000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = or(_T_818, _T_823)
node _T_850 = or(_T_849, _T_828)
node _T_851 = or(_T_850, _T_833)
node _T_852 = or(_T_851, _T_838)
node _T_853 = or(_T_852, _T_843)
node _T_854 = or(_T_853, _T_848)
node _T_855 = and(_T_813, _T_854)
node _T_856 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_857 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<17>(0h10000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_863 = cvt(_T_862)
node _T_864 = and(_T_863, asSInt(UInt<30>(0h20000000)))
node _T_865 = asSInt(_T_864)
node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0)))
node _T_867 = or(_T_861, _T_866)
node _T_868 = and(_T_856, _T_867)
node _T_869 = or(UInt<1>(0h0), _T_855)
node _T_870 = or(_T_869, _T_868)
node _T_871 = and(_T_809, _T_870)
node _T_872 = asUInt(reset)
node _T_873 = eq(_T_872, UInt<1>(0h0))
when _T_873 :
node _T_874 = eq(_T_871, UInt<1>(0h0))
when _T_874 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_871, UInt<1>(0h1), "") : assert_41
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(source_ok, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(is_aligned, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_881 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_881, UInt<1>(0h1), "") : assert_44
node _T_885 = eq(io.in.a.bits.mask, mask)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_885, UInt<1>(0h1), "") : assert_45
node _T_889 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_889 :
node _T_890 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_891 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_892 = and(_T_890, _T_891)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0)
node _T_893 = shr(io.in.a.bits.source, 3)
node _T_894 = eq(_T_893, UInt<1>(0h0))
node _T_895 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_896 = and(_T_894, _T_895)
node _T_897 = leq(uncommonBits_16, UInt<3>(0h7))
node _T_898 = and(_T_896, _T_897)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0)
node _T_899 = shr(io.in.a.bits.source, 3)
node _T_900 = eq(_T_899, UInt<1>(0h1))
node _T_901 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_902 = and(_T_900, _T_901)
node _T_903 = leq(uncommonBits_17, UInt<3>(0h7))
node _T_904 = and(_T_902, _T_903)
node _T_905 = or(_T_898, _T_904)
node _T_906 = and(_T_892, _T_905)
node _T_907 = or(UInt<1>(0h0), _T_906)
node _T_908 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_909 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_910 = and(_T_908, _T_909)
node _T_911 = or(UInt<1>(0h0), _T_910)
node _T_912 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_913 = cvt(_T_912)
node _T_914 = and(_T_913, asSInt(UInt<13>(0h1000)))
node _T_915 = asSInt(_T_914)
node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0)))
node _T_917 = and(_T_911, _T_916)
node _T_918 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_919 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<14>(0h2000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<18>(0h2f000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_935 = cvt(_T_934)
node _T_936 = and(_T_935, asSInt(UInt<17>(0h10000)))
node _T_937 = asSInt(_T_936)
node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0)))
node _T_939 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<27>(0h4000000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_945 = cvt(_T_944)
node _T_946 = and(_T_945, asSInt(UInt<13>(0h1000)))
node _T_947 = asSInt(_T_946)
node _T_948 = eq(_T_947, asSInt(UInt<1>(0h0)))
node _T_949 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_950 = cvt(_T_949)
node _T_951 = and(_T_950, asSInt(UInt<30>(0h20000000)))
node _T_952 = asSInt(_T_951)
node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0)))
node _T_954 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_955 = cvt(_T_954)
node _T_956 = and(_T_955, asSInt(UInt<15>(0h4000)))
node _T_957 = asSInt(_T_956)
node _T_958 = eq(_T_957, asSInt(UInt<1>(0h0)))
node _T_959 = or(_T_923, _T_928)
node _T_960 = or(_T_959, _T_933)
node _T_961 = or(_T_960, _T_938)
node _T_962 = or(_T_961, _T_943)
node _T_963 = or(_T_962, _T_948)
node _T_964 = or(_T_963, _T_953)
node _T_965 = or(_T_964, _T_958)
node _T_966 = and(_T_918, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_917)
node _T_968 = or(_T_967, _T_966)
node _T_969 = and(_T_907, _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_969, UInt<1>(0h1), "") : assert_46
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(source_ok, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(is_aligned, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_979 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(_T_979, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_979, UInt<1>(0h1), "") : assert_49
node _T_983 = eq(io.in.a.bits.mask, mask)
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_983, UInt<1>(0h1), "") : assert_50
node _T_987 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_988 = asUInt(reset)
node _T_989 = eq(_T_988, UInt<1>(0h0))
when _T_989 :
node _T_990 = eq(_T_987, UInt<1>(0h0))
when _T_990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_987, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_991 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_991, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0)
node _source_ok_T_12 = shr(io.in.d.bits.source, 3)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<3>(0h7))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 2, 0)
node _source_ok_T_18 = shr(io.in.d.bits.source, 3)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h1))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<3>(0h7))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_17
connect _source_ok_WIRE_1[1], _source_ok_T_23
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_995 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_995 :
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(source_ok_1, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_999 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_999, UInt<1>(0h1), "") : assert_54
node _T_1003 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_55
node _T_1007 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_56
node _T_1011 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(_T_1011, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1011, UInt<1>(0h1), "") : assert_57
node _T_1015 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1015 :
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(source_ok_1, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(sink_ok, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1022 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_60
node _T_1026 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_61
node _T_1030 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_62
node _T_1034 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_T_1034, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1034, UInt<1>(0h1), "") : assert_63
node _T_1038 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1039 = or(UInt<1>(0h1), _T_1038)
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_64
node _T_1043 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1043 :
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(source_ok_1, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(sink_ok, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1050 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_67
node _T_1054 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_68
node _T_1058 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_69
node _T_1062 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1063 = or(_T_1062, io.in.d.bits.corrupt)
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_T_1063, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1063, UInt<1>(0h1), "") : assert_70
node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1068 = or(UInt<1>(0h1), _T_1067)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_71
node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(source_ok_1, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_73
node _T_1080 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_74
node _T_1084 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1085 = or(UInt<1>(0h1), _T_1084)
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_75
node _T_1089 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1089 :
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(source_ok_1, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1093 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_77
node _T_1097 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1098 = or(_T_1097, io.in.d.bits.corrupt)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_78
node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1103 = or(UInt<1>(0h1), _T_1102)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_79
node _T_1107 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1107 :
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(source_ok_1, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1111 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_81
node _T_1115 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_82
node _T_1119 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1120 = or(UInt<1>(0h1), _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1124 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1128 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1132 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1136 = eq(a_first, UInt<1>(0h0))
node _T_1137 = and(io.in.a.valid, _T_1136)
when _T_1137 :
node _T_1138 = eq(io.in.a.bits.opcode, opcode)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_87
node _T_1142 = eq(io.in.a.bits.param, param)
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_88
node _T_1146 = eq(io.in.a.bits.size, size)
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_89
node _T_1150 = eq(io.in.a.bits.source, source)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_90
node _T_1154 = eq(io.in.a.bits.address, address)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_91
node _T_1158 = and(io.in.a.ready, io.in.a.valid)
node _T_1159 = and(_T_1158, a_first)
when _T_1159 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1160 = eq(d_first, UInt<1>(0h0))
node _T_1161 = and(io.in.d.valid, _T_1160)
when _T_1161 :
node _T_1162 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_92
node _T_1166 = eq(io.in.d.bits.param, param_1)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_93
node _T_1170 = eq(io.in.d.bits.size, size_1)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_94
node _T_1174 = eq(io.in.d.bits.source, source_1)
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_95
node _T_1178 = eq(io.in.d.bits.sink, sink)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_96
node _T_1182 = eq(io.in.d.bits.denied, denied)
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_97
node _T_1186 = and(io.in.d.ready, io.in.d.valid)
node _T_1187 = and(_T_1186, d_first)
when _T_1187 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1188 = and(io.in.a.valid, a_first_1)
node _T_1189 = and(_T_1188, UInt<1>(0h1))
when _T_1189 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1190 = and(io.in.a.ready, io.in.a.valid)
node _T_1191 = and(_T_1190, a_first_1)
node _T_1192 = and(_T_1191, UInt<1>(0h1))
when _T_1192 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1193 = dshr(inflight, io.in.a.bits.source)
node _T_1194 = bits(_T_1193, 0, 0)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1199 = and(io.in.d.valid, d_first_1)
node _T_1200 = and(_T_1199, UInt<1>(0h1))
node _T_1201 = eq(d_release_ack, UInt<1>(0h0))
node _T_1202 = and(_T_1200, _T_1201)
when _T_1202 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1203 = and(io.in.d.ready, io.in.d.valid)
node _T_1204 = and(_T_1203, d_first_1)
node _T_1205 = and(_T_1204, UInt<1>(0h1))
node _T_1206 = eq(d_release_ack, UInt<1>(0h0))
node _T_1207 = and(_T_1205, _T_1206)
when _T_1207 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1208 = and(io.in.d.valid, d_first_1)
node _T_1209 = and(_T_1208, UInt<1>(0h1))
node _T_1210 = eq(d_release_ack, UInt<1>(0h0))
node _T_1211 = and(_T_1209, _T_1210)
when _T_1211 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1212 = dshr(inflight, io.in.d.bits.source)
node _T_1213 = bits(_T_1212, 0, 0)
node _T_1214 = or(_T_1213, same_cycle_resp)
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1218 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1219 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1220 = or(_T_1218, _T_1219)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_100
node _T_1224 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_101
else :
node _T_1228 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1229 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1230 = or(_T_1228, _T_1229)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_102
node _T_1234 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(_T_1234, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1234, UInt<1>(0h1), "") : assert_103
node _T_1238 = and(io.in.d.valid, d_first_1)
node _T_1239 = and(_T_1238, a_first_1)
node _T_1240 = and(_T_1239, io.in.a.valid)
node _T_1241 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1242 = and(_T_1240, _T_1241)
node _T_1243 = eq(d_release_ack, UInt<1>(0h0))
node _T_1244 = and(_T_1242, _T_1243)
when _T_1244 :
node _T_1245 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1246 = or(_T_1245, io.in.a.ready)
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_104
node _T_1250 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1251 = orr(a_set_wo_ready)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
node _T_1253 = or(_T_1250, _T_1252)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_38
node _T_1257 = orr(inflight)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
node _T_1259 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1260 = or(_T_1258, _T_1259)
node _T_1261 = lt(watchdog, plusarg_reader.out)
node _T_1262 = or(_T_1260, _T_1261)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1266 = and(io.in.a.ready, io.in.a.valid)
node _T_1267 = and(io.in.d.ready, io.in.d.valid)
node _T_1268 = or(_T_1266, _T_1267)
when _T_1268 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1269 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1270 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1271 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1272 = and(_T_1270, _T_1271)
node _T_1273 = and(_T_1269, _T_1272)
when _T_1273 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1274 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1275 = and(_T_1274, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1276 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1277 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1278 = and(_T_1276, _T_1277)
node _T_1279 = and(_T_1275, _T_1278)
when _T_1279 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1280 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1281 = bits(_T_1280, 0, 0)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
node _T_1283 = asUInt(reset)
node _T_1284 = eq(_T_1283, UInt<1>(0h0))
when _T_1284 :
node _T_1285 = eq(_T_1282, UInt<1>(0h0))
when _T_1285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1282, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1286 = and(io.in.d.valid, d_first_2)
node _T_1287 = and(_T_1286, UInt<1>(0h1))
node _T_1288 = and(_T_1287, d_release_ack_1)
when _T_1288 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1289 = and(io.in.d.ready, io.in.d.valid)
node _T_1290 = and(_T_1289, d_first_2)
node _T_1291 = and(_T_1290, UInt<1>(0h1))
node _T_1292 = and(_T_1291, d_release_ack_1)
when _T_1292 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1293 = and(io.in.d.valid, d_first_2)
node _T_1294 = and(_T_1293, UInt<1>(0h1))
node _T_1295 = and(_T_1294, d_release_ack_1)
when _T_1295 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1296 = dshr(inflight_1, io.in.d.bits.source)
node _T_1297 = bits(_T_1296, 0, 0)
node _T_1298 = or(_T_1297, same_cycle_resp_1)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1302 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_109
else :
node _T_1306 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_110
node _T_1310 = and(io.in.d.valid, d_first_2)
node _T_1311 = and(_T_1310, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1312 = and(_T_1311, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1313 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1314 = and(_T_1312, _T_1313)
node _T_1315 = and(_T_1314, d_release_ack_1)
node _T_1316 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1317 = and(_T_1315, _T_1316)
when _T_1317 :
node _T_1318 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1319 = or(_T_1318, _WIRE_23.ready)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_111
node _T_1323 = orr(c_set_wo_ready)
when _T_1323 :
node _T_1324 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_39
node _T_1328 = orr(inflight_1)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
node _T_1330 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1333 = or(_T_1331, _T_1332)
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:174:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1337 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1338 = and(io.in.d.ready, io.in.d.valid)
node _T_1339 = or(_T_1337, _T_1338)
when _T_1339 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_19( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_bufferable, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_modifiable, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_readalloc, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_writealloc, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_privileged, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_secure, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_fetch, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_bufferable_0 = io_in_a_bits_user_amba_prot_bufferable; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_modifiable_0 = io_in_a_bits_user_amba_prot_modifiable; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_readalloc_0 = io_in_a_bits_user_amba_prot_readalloc; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_writealloc_0 = io_in_a_bits_user_amba_prot_writealloc; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_privileged_0 = io_in_a_bits_user_amba_prot_privileged; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_secure_0 = io_in_a_bits_user_amba_prot_secure; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_fetch_0 = io_in_a_bits_user_amba_prot_fetch; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7]
wire _source_ok_T_6 = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_12 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7]
wire _source_ok_T_18 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7]
wire _source_ok_T_13 = ~_source_ok_T_12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1339 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1339; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1339; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1339; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1192 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1192 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1192 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1192 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1192 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1192 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1238 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1238 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1207 = _T_1339 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1207 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1207 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1207 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1292 = _T_1339 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1292 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_285 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_285( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_129 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_143
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_129( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_143 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ChipyardPRCICtrlClockSinkDomain :
output auto : { flip reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, resetSynchronizer_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip xbar_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst xbar of TLXbar_prcibus_i1_o2_a21d64s7k1z3u
connect xbar.clock, childClock
connect xbar.reset, childReset
inst resetSynchronizer of ClockGroupResetSynchronizer
inst clock_gater of TileClockGater
connect clock_gater.clock, childClock
connect clock_gater.reset, childReset
inst fragmenter of TLFragmenter_TileClockGater
connect fragmenter.clock, childClock
connect fragmenter.reset, childReset
inst reset_setter of TileResetSetter
connect reset_setter.clock, childClock
connect reset_setter.reset, childReset
inst fragmenter_1 of TLFragmenter_TileResetSetter
connect fragmenter_1.clock, childClock
connect fragmenter_1.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect fragmenter.auto.anon_in, xbar.auto.anon_out_0
connect fragmenter_1.auto.anon_in, xbar.auto.anon_out_1
connect resetSynchronizer.auto.in, clock_gater.auto.clock_gater_out
connect clock_gater.auto.clock_gater_in_1, fragmenter.auto.anon_out
connect clock_gater.auto.clock_gater_in_0, reset_setter.auto.clock_out
connect reset_setter.auto.tl_in, fragmenter_1.auto.anon_out
connect clockNodeIn, auto.clock_in
connect xbar.auto.anon_in, auto.xbar_anon_in
connect auto.resetSynchronizer_out, resetSynchronizer.auto.out
connect reset_setter.auto.clock_in, auto.reset_setter_clock_in
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module ChipyardPRCICtrlClockSinkDomain( // @[ClockDomain.scala:14:9]
input auto_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_resetSynchronizer_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_resetSynchronizer_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _fragmenter_1_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_1_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_1_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_1_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [6:0] _fragmenter_1_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire _fragmenter_1_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_1_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_1_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_1_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [10:0] _fragmenter_1_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [20:0] _fragmenter_1_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_1_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_1_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_1_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_1_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _reset_setter_auto_clock_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:78:34]
wire _reset_setter_auto_clock_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:78:34]
wire _reset_setter_auto_tl_in_a_ready; // @[HasChipyardPRCI.scala:78:34]
wire _reset_setter_auto_tl_in_d_valid; // @[HasChipyardPRCI.scala:78:34]
wire [2:0] _reset_setter_auto_tl_in_d_bits_opcode; // @[HasChipyardPRCI.scala:78:34]
wire [1:0] _reset_setter_auto_tl_in_d_bits_size; // @[HasChipyardPRCI.scala:78:34]
wire [10:0] _reset_setter_auto_tl_in_d_bits_source; // @[HasChipyardPRCI.scala:78:34]
wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [6:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [10:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [20:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _clock_gater_auto_clock_gater_in_1_a_ready; // @[HasChipyardPRCI.scala:73:33]
wire _clock_gater_auto_clock_gater_in_1_d_valid; // @[HasChipyardPRCI.scala:73:33]
wire [2:0] _clock_gater_auto_clock_gater_in_1_d_bits_opcode; // @[HasChipyardPRCI.scala:73:33]
wire [1:0] _clock_gater_auto_clock_gater_in_1_d_bits_size; // @[HasChipyardPRCI.scala:73:33]
wire [10:0] _clock_gater_auto_clock_gater_in_1_d_bits_source; // @[HasChipyardPRCI.scala:73:33]
wire [63:0] _clock_gater_auto_clock_gater_in_1_d_bits_data; // @[HasChipyardPRCI.scala:73:33]
wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:73:33]
wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:73:33]
wire _xbar_auto_anon_out_1_a_valid; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_1_a_bits_opcode; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_1_a_bits_param; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_1_a_bits_size; // @[Xbar.scala:346:26]
wire [6:0] _xbar_auto_anon_out_1_a_bits_source; // @[Xbar.scala:346:26]
wire [20:0] _xbar_auto_anon_out_1_a_bits_address; // @[Xbar.scala:346:26]
wire [7:0] _xbar_auto_anon_out_1_a_bits_mask; // @[Xbar.scala:346:26]
wire [63:0] _xbar_auto_anon_out_1_a_bits_data; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_1_a_bits_corrupt; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_1_d_ready; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_0_a_valid; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_0_a_bits_opcode; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_0_a_bits_param; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_0_a_bits_size; // @[Xbar.scala:346:26]
wire [6:0] _xbar_auto_anon_out_0_a_bits_source; // @[Xbar.scala:346:26]
wire [20:0] _xbar_auto_anon_out_0_a_bits_address; // @[Xbar.scala:346:26]
wire [7:0] _xbar_auto_anon_out_0_a_bits_mask; // @[Xbar.scala:346:26]
wire [63:0] _xbar_auto_anon_out_0_a_bits_data; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_0_a_bits_corrupt; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_0_d_ready; // @[Xbar.scala:346:26]
wire auto_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_reset_setter_clock_in_member_allClocks_uncore_clock; // @[ClockDomain.scala:14:9]
wire auto_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_reset_setter_clock_in_member_allClocks_uncore_reset; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [20:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [1:0] auto_xbar_anon_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9]
wire auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLXbar_prcibus_i1_o2_a21d64s7k1z3u xbar ( // @[Xbar.scala:346:26]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (auto_xbar_anon_in_a_ready_0),
.auto_anon_in_a_valid (auto_xbar_anon_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_opcode (auto_xbar_anon_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_param (auto_xbar_anon_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_size (auto_xbar_anon_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_source (auto_xbar_anon_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_address (auto_xbar_anon_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_mask (auto_xbar_anon_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_data (auto_xbar_anon_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_corrupt (auto_xbar_anon_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_d_ready (auto_xbar_anon_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_d_valid (auto_xbar_anon_in_d_valid_0),
.auto_anon_in_d_bits_opcode (auto_xbar_anon_in_d_bits_opcode_0),
.auto_anon_in_d_bits_size (auto_xbar_anon_in_d_bits_size_0),
.auto_anon_in_d_bits_source (auto_xbar_anon_in_d_bits_source_0),
.auto_anon_in_d_bits_data (auto_xbar_anon_in_d_bits_data_0),
.auto_anon_out_1_a_ready (_fragmenter_1_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_anon_out_1_a_valid (_xbar_auto_anon_out_1_a_valid),
.auto_anon_out_1_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode),
.auto_anon_out_1_a_bits_param (_xbar_auto_anon_out_1_a_bits_param),
.auto_anon_out_1_a_bits_size (_xbar_auto_anon_out_1_a_bits_size),
.auto_anon_out_1_a_bits_source (_xbar_auto_anon_out_1_a_bits_source),
.auto_anon_out_1_a_bits_address (_xbar_auto_anon_out_1_a_bits_address),
.auto_anon_out_1_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask),
.auto_anon_out_1_a_bits_data (_xbar_auto_anon_out_1_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt),
.auto_anon_out_1_d_ready (_xbar_auto_anon_out_1_d_ready),
.auto_anon_out_1_d_valid (_fragmenter_1_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_anon_out_1_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_anon_out_1_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_anon_out_1_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_a_valid (_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34]
); // @[Xbar.scala:346:26]
ClockGroupResetSynchronizer resetSynchronizer ( // @[ResetSynchronizer.scala:46:69]
.auto_in_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:73:33]
.auto_in_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:73:33]
.auto_out_member_allClocks_uncore_clock (auto_resetSynchronizer_out_member_allClocks_uncore_clock_0),
.auto_out_member_allClocks_uncore_reset (auto_resetSynchronizer_out_member_allClocks_uncore_reset_0)
); // @[ResetSynchronizer.scala:46:69]
TileClockGater clock_gater ( // @[HasChipyardPRCI.scala:73:33]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_clock_gater_in_1_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready),
.auto_clock_gater_in_1_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid),
.auto_clock_gater_in_1_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode),
.auto_clock_gater_in_1_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size),
.auto_clock_gater_in_1_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source),
.auto_clock_gater_in_1_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data),
.auto_clock_gater_in_0_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:78:34]
.auto_clock_gater_in_0_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:78:34]
.auto_clock_gater_out_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock),
.auto_clock_gater_out_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset)
); // @[HasChipyardPRCI.scala:73:33]
TLFragmenter_TileClockGater fragmenter ( // @[Fragmenter.scala:345:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_xbar_auto_anon_out_0_a_valid), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), // @[Xbar.scala:346:26]
.auto_anon_in_d_ready (_xbar_auto_anon_out_0_d_ready), // @[Xbar.scala:346:26]
.auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data),
.auto_anon_out_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data) // @[HasChipyardPRCI.scala:73:33]
); // @[Fragmenter.scala:345:34]
TileResetSetter reset_setter ( // @[HasChipyardPRCI.scala:78:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_clock_in_member_allClocks_uncore_clock (auto_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[ClockDomain.scala:14:9]
.auto_clock_in_member_allClocks_uncore_reset (auto_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[ClockDomain.scala:14:9]
.auto_clock_out_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock),
.auto_clock_out_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset),
.auto_tl_in_a_ready (_reset_setter_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_fragmenter_1_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_tl_in_d_ready (_fragmenter_1_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_tl_in_d_valid (_reset_setter_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_reset_setter_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_reset_setter_auto_tl_in_d_bits_source)
); // @[HasChipyardPRCI.scala:78:34]
TLFragmenter_TileResetSetter fragmenter_1 ( // @[Fragmenter.scala:345:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_fragmenter_1_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_xbar_auto_anon_out_1_a_valid), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), // @[Xbar.scala:346:26]
.auto_anon_in_d_ready (_xbar_auto_anon_out_1_d_ready), // @[Xbar.scala:346:26]
.auto_anon_in_d_valid (_fragmenter_1_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source),
.auto_anon_out_a_ready (_reset_setter_auto_tl_in_a_ready), // @[HasChipyardPRCI.scala:78:34]
.auto_anon_out_a_valid (_fragmenter_1_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_1_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_reset_setter_auto_tl_in_d_valid), // @[HasChipyardPRCI.scala:78:34]
.auto_anon_out_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode), // @[HasChipyardPRCI.scala:78:34]
.auto_anon_out_d_bits_size (_reset_setter_auto_tl_in_d_bits_size), // @[HasChipyardPRCI.scala:78:34]
.auto_anon_out_d_bits_source (_reset_setter_auto_tl_in_d_bits_source) // @[HasChipyardPRCI.scala:78:34]
); // @[Fragmenter.scala:345:34]
assign auto_resetSynchronizer_out_member_allClocks_uncore_clock = auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9]
assign auto_resetSynchronizer_out_member_allClocks_uncore_reset = auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule |
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